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Posted to commits@nuttx.apache.org by gn...@apache.org on 2020/05/13 12:52:07 UTC
[incubator-nuttx] branch master updated (63e3054 -> 4967352)
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 63e3054 Don't need monitor IOB buffer empty event for POLLOUT implementation
new 2ef5714 arch/arm/src/stm32h7/stm32_allocateheap.c: Fix compilation when CONFIG_MM_REGIONS == 1
new d618dad arch/arm/src/stm32h7/Make.defs: arm_mpu.c was added twice
new db492ca arch/arm/src/stm32h7/stm32_ethernet.c: Break long lines to pass style checks
new 4967352 arch/arm/src/stm32h7/stm32_ethernet.c: Comment and debug assertion fixes
The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/stm32h7/Make.defs | 5 --
arch/arm/src/stm32h7/stm32_allocateheap.c | 2 +
arch/arm/src/stm32h7/stm32_ethernet.c | 126 +++++++++++++++++++-----------
3 files changed, 83 insertions(+), 50 deletions(-)
[incubator-nuttx] 04/04: arch/arm/src/stm32h7/stm32_ethernet.c:
Comment and debug assertion fixes
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 4967352c3388e7b09d0b6a4c3f659eb38ec12a3d
Author: Jukka Laitinen <ju...@intel.com>
AuthorDate: Wed Nov 27 08:28:36 2019 +0200
arch/arm/src/stm32h7/stm32_ethernet.c: Comment and debug assertion fixes
Modify some comments and debug assertions, which inherit from previous versions
and make no sense. Also add a few nerr printouts to make it easier to debug
running out of buffers
Signed-off-by: Jukka Laitinen <ju...@intel.com>
---
arch/arm/src/stm32h7/stm32_ethernet.c | 26 +++++++++++++++++---------
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c
index 8c52e2c..cd3bfda 100644
--- a/arch/arm/src/stm32h7/stm32_ethernet.c
+++ b/arch/arm/src/stm32h7/stm32_ethernet.c
@@ -1102,7 +1102,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
ninfo("d_len: %d d_buf: %p txhead: %p tdes3: %08x\n",
priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->des3);
- DEBUGASSERT(txdesc && (txdesc->des3 & ETH_TDES3_RD_OWN) == 0);
+ DEBUGASSERT(txdesc);
/* Flush the contents of the TX buffer into physical memory */
@@ -1133,8 +1133,6 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
for (i = 0; i < bufcount; i++)
{
- /* This could be a normal event but the design does not handle it */
-
DEBUGASSERT((txdesc->des3 & ETH_TDES3_RD_OWN) == 0);
/* Set the Buffer1 address pointer */
@@ -1170,7 +1168,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
/* The size of the transfer is the whole buffer */
- txdesc->des2 = ALIGNED_BUFSIZE | ETH_TDES2_RD_IOC;
+ txdesc->des2 = ALIGNED_BUFSIZE;
buffer += ALIGNED_BUFSIZE;
}
@@ -1193,6 +1191,8 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
else
#endif
{
+ DEBUGASSERT((txdesc->des3 & ETH_TDES3_RD_OWN) == 0);
+
/* Set the Buffer1 address pointer */
txdesc->des0 = (uint32_t)priv->dev.d_buf;
@@ -1266,8 +1266,6 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
stm32_disableint(priv, ETH_DMACIER_RIE);
}
- /* Check if the TX Buffer unavailable flag is set */
-
MEMORY_SYNC();
/* Enable TX interrupts */
@@ -1367,6 +1365,8 @@ static int stm32_txpoll(struct net_driver_s *dev)
* available for another transfer.
*/
+ nerr("No tx descriptors available");
+
return -EBUSY;
}
@@ -1382,6 +1382,8 @@ static int stm32_txpoll(struct net_driver_s *dev)
{
/* Terminate the poll. */
+ nerr("No tx buffer available");
+
return -ENOMEM;
}
}
@@ -1457,6 +1459,14 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv)
dev->d_buf = NULL;
}
}
+ else
+ {
+ nerr("No tx buffers");
+ }
+ }
+ else
+ {
+ nerr("No tx descriptors\n");
}
}
@@ -1602,9 +1612,7 @@ static void stm32_freesegment(struct stm32_ethmac_s *priv,
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct eth_desc_s));
- /* Get the next RX descriptor in the chain (cache coherency should not
- * be an issue because the link address is constant.
- */
+ /* Get the next RX descriptor in the chain */
rxdesc = stm32_get_next_rxdesc(priv, rxdesc);
[incubator-nuttx] 03/04: arch/arm/src/stm32h7/stm32_ethernet.c:
Break long lines to pass style checks
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit db492ca03b2318a94142bf982fd8e59a57f9807e
Author: Jukka Laitinen <ju...@intel.com>
AuthorDate: Wed May 13 14:15:03 2020 +0300
arch/arm/src/stm32h7/stm32_ethernet.c: Break long lines to pass style checks
Signed-off-by: Jukka Laitinen <ju...@intel.com>
---
arch/arm/src/stm32h7/stm32_ethernet.c | 100 ++++++++++++++++++++++------------
1 file changed, 64 insertions(+), 36 deletions(-)
diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c
index fdb3867..8c52e2c 100644
--- a/arch/arm/src/stm32h7/stm32_ethernet.c
+++ b/arch/arm/src/stm32h7/stm32_ethernet.c
@@ -333,7 +333,8 @@
* ETH_MACCR_BL Back-off limit 0 (10)
* ETH_MACCR_ACS Automatic pad/CRC stripping 0 (disabled)
* ETH_MACCR_DR Retry disable 1 (disabled)
- * ETH_MACCR_IPC IPv4 checksum offload Depends on CONFIG_STM32H7_ETH_HWCHECKSUM
+ * ETH_MACCR_IPC IPv4 checksum offload
+ * Depends on CONFIG_STM32H7_ETH_HWCHECKSUM
* ETH_MACCR_LM Loopback mode 0 (disabled)
* ETH_MACCR_DO Receive own disable 0 (enabled)
* ETH_MACCR_DCRS Carrier sense disable 0 (enabled)
@@ -356,9 +357,9 @@
(ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPG(96))
#endif
-/* Clear the MACPFR bits that will be setup during MAC initialization (or that
- * are cleared unconditionally). Per the reference manual, all reserved bits
- * must be retained at their reset value.
+/* Clear the MACPFR bits that will be setup during MAC initialization (or
+ * that are cleared unconditionally). Per the reference manual, all reserved
+ * bits must be retained at their reset value.
*
* ETH_MACPFR_PR Bit 0: Promiscuous mode
* ETH_MACPFR_HUC Bit 1: Hash unicast
@@ -385,15 +386,20 @@
/* The following bits are set or left zero unconditionally in all modes.
*
* ETH_MACPFR_PR Promiscuous mode 0 (disabled)
- * ETH_MACPFR_HUC Hash unicast 0 (perfect dest filtering)
- * ETH_MACPFR_HMC Hash multicast 0 (perfect dest filtering)
+ * ETH_MACPFR_HUC Hash unicast 0 (perfect
+ * dest filtering)
+ * ETH_MACPFR_HMC Hash multicast 0 (perfect
+ * dest filtering)
* ETH_MACPFR_DAIF Destination address inverse filtering 0 (normal)
- * ETH_MACPFR_PM Pass all multicast 0 (Depends on HMC bit)
+ * ETH_MACPFR_PM Pass all multicast 0 (Depends on HMC
+ * bit)
* ETH_MACPFR_DBF Broadcast frames disable 0 (enabled)
- * ETH_MACPFR_PCF Pass control frames 1 (block all but PAUSE)
+ * ETH_MACPFR_PCF Pass control frames 1 (block all but
+ * PAUSE)
* ETH_MACPFR_SAIF Source address inverse filtering 0 (not used)
* ETH_MACPFR_SAF Source address filter 0 (disabled)
- * ETH_MACPFR_HPF Hash or perfect filter 0 (Only matching frames passed)
+ * ETH_MACPFR_HPF Hash or perfect filter 0 (Only matching
+ * frames passed)
* ETH_MACPFR_RA Receive all 0 (disabled)
*/
@@ -423,21 +429,27 @@
/* The following bits are set or left zero unconditionally in all modes.
*
- * ETH_MACQTXFCR_FCB_BPA Flow control busy/back pressure activate 0 (no pause control frame)
- * ETH_MACQTXFCR_TFE Transmit flow control enable 0 (disabled)
- * ETH_MACQTXFCR_PLT Pause low threshold 0 (pause time - 4)
- * ETH_MACQTXFCR_DZPQ Zero-quanta pause disable 1 (disabled)
+ * ETH_MACQTXFCR_FCB_BPA Flow control busy/back pressure activate 0
+ * (no pause control frame)
+ * ETH_MACQTXFCR_TFE Transmit flow control enable 0
+ * (disabled)
+ * ETH_MACQTXFCR_PLT Pause low threshold 0
+ * (pause time - 4)
+ * ETH_MACQTXFCR_DZPQ Zero-quanta pause disable 1
+ * (disabled)
* ETH_MACQTXFCR_PT Pause time 0
- * ETH_MACRXFCR_RFE Receive flow control enable 0 (disabled)
- * ETH_MACRXFCR_UP Unicast pause frame detect 0 (disabled)
+ * ETH_MACRXFCR_RFE Receive flow control enable 0
+ * (disabled)
+ * ETH_MACRXFCR_UP Unicast pause frame detect 0
+ * (disabled)
*/
#define MACQTXFCR_SET_MASK (ETH_MACQTXFCR_PLT_M4 | ETH_MACQTXFCR_DZPQ)
#define MACRXFCR_SET_MASK (0)
-/* Clear the MTLTXQOMR bits that will be setup during MAC initialization (or that
- * are cleared unconditionally). Per the reference manual, all reserved bits
- * must be retained at their reset value.
+/* Clear the MTLTXQOMR bits that will be setup during MAC initialization
+ * (or that are cleared unconditionally). Per the reference manual, all
+ * reserved bits must be retained at their reset value.
* ETH_MTLTXQOMR_FTQ Bit 0: Flush Transmit Queue
* ETH_MTLTXQOMR_TSF Bit 1: Transmit Store and Forward
* ETH_MTLTXQOMR_TXQEN Bits 2-3: Transmit Queue Enable
@@ -450,18 +462,20 @@
ETH_MTLTXQOMR_TXQEN_MASK | ETH_MTLTXQOMR_TTC_MASK | \
ETH_MTLTXQOMR_TQS_MASK)
-/* Clear the MTLRXQOMR bits that will be setup during MAC initialization (or that
- * are cleared unconditionally). Per the reference manual, all reserved bits
- * must be retained at their reset value.
+/* Clear the MTLRXQOMR bits that will be setup during MAC initialization
+ * (or that are cleared unconditionally). Per the reference manual, all
+ * reserved bits must be retained at their reset value.
*
* ETH_MTLRXQOMR_RTC_MASK Bits 0-1: Receive Queue Threshold Control
* ETH_MTLRXQOMR_FUP Bit 3: Forward Undersized Good Packets
* ETH_MTLRXQOMR_FEP Bit 4: Forward Error Packets
* ETH_MTLRXQOMR_RSF Bit 5: Receive Queue Store and Forward
- * ETH_MTLRXQOMR_DIS_TCP_EF Bit 6: Disable Dropping of TCP/IP Checksum Error Packets
+ * ETH_MTLRXQOMR_DIS_TCP_EF Bit 6: Disable Dropping of TCP/IP Checksum Error
+ * Packets
* ETH_MTLRXQOMR_EHFC Bit 7: Enable Hardware Flow Control
* ETH_MTLRXQOMR_RFA_MASK Bits 8-10: Threshold for Activating Flow Control
- * ETH_MTLRXQOMR_RFD_MASK Bits 14-16: Threshold for Deactivating Flow Control
+ * ETH_MTLRXQOMR_RFD_MASK Bits 14-16: Threshold for Deactivating Flow
+ * Control
* ETH_MTLRXQOMR_RQS_MASK Bits 20-22: Receive Queue Size
*/
@@ -1767,7 +1781,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
*/
up_clean_dcache((uintptr_t)rxcurr,
- (uintptr_t)rxdesc + sizeof(struct eth_desc_s));
+ (uintptr_t)rxdesc +
+ sizeof(struct eth_desc_s));
/* Remember where we should re-start scanning and reset the
* segment scanning logic
@@ -1862,7 +1877,9 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
while (stm32_recvframe(priv) == OK)
{
#ifdef CONFIG_NET_PKT
- /* When packet sockets are enabled, feed the frame into the packet tap */
+ /* When packet sockets are enabled, feed the frame into the packet
+ * tap
+ */
pkt_input(&priv->dev);
#endif
@@ -2110,7 +2127,8 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
/* Force re-reading of the TX descriptor for physical memory */
up_invalidate_dcache((uintptr_t)txdesc,
- (uintptr_t)txdesc + sizeof(struct eth_desc_s));
+ (uintptr_t)txdesc +
+ sizeof(struct eth_desc_s));
}
/* We get here if (1) there are still frames "in-flight". Remember
@@ -3171,7 +3189,9 @@ static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr,
volatile uint32_t timeout;
uint32_t regval;
- /* Configure the MACMDIOAR register, preserving CSR Clock Range CR[3:0] bits */
+ /* Configure the MACMDIOAR register, preserving CSR Clock Range CR[3:0]
+ * bits
+ */
regval = stm32_getreg(STM32_ETH_MACMDIOAR);
regval &= ETH_MACMDIOAR_CR_MASK;
@@ -3230,7 +3250,9 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr,
uint32_t regval;
uint16_t value;
- /* Configure the MACMDIOAR register, preserving CSR Clock Range CR[3:0] bits */
+ /* Configure the MACMDIOAR register, preserving CSR Clock Range CR[3:0]
+ * bits
+ */
regval = stm32_getreg(STM32_ETH_MACMDIOAR);
regval &= ETH_MACMDIOAR_CR_MASK;
@@ -3279,8 +3301,8 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr,
}
}
- ninfo("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
- phydevaddr, phyregaddr, value);
+ ninfo("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: "
+ "%04x\n", phydevaddr, phyregaddr, value);
return -ETIMEDOUT;
}
@@ -3320,7 +3342,9 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
return ret;
}
- /* If we failed to read the PHY ID1 register, the reset the MCU to recover */
+ /* If we failed to read the PHY ID1 register, the reset the MCU to
+ * recover
+ */
else if (phyval == 0xffff)
{
@@ -3329,7 +3353,9 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
ninfo("PHY ID1: 0x%04X\n", phyval);
- /* Now check the "DAVICOM Specified Configuration Register (DSCR)", Register 16 */
+ /* Now check the "DAVICOM Specified Configuration Register (DSCR)",
+ * Register 16
+ */
ret = stm32_phyread(CONFIG_STM32H7_PHYADDR, 16, &phyval);
if (ret < 0)
@@ -3418,7 +3444,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
priv->mbps100 = 0;
priv->fduplex = 0;
- /* Setup up PHY clocking by setting the CR field in the MACMDIOAR register */
+ /* Setup up PHY clocking by setting the CR field in the MACMDIOAR reg */
regval = stm32_getreg(STM32_ETH_MACMDIOAR);
regval &= ~ETH_MACMDIOAR_CR_MASK;
@@ -3580,7 +3606,8 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
*/
#else
- if ((phyval & CONFIG_STM32H7_PHYSR_MODE) == CONFIG_STM32H7_PHYSR_FULLDUPLEX)
+ if ((phyval & CONFIG_STM32H7_PHYSR_MODE) ==
+ CONFIG_STM32H7_PHYSR_FULLDUPLEX)
{
priv->fduplex = 1;
}
@@ -4342,7 +4369,8 @@ static inline int stm32_ethinitialize(int intf)
#ifdef CONFIG_NETDEV_PHY_IOCTL
priv->dev.d_ioctl = stm32_ioctl; /* Support PHY ioctl() calls */
#endif
- priv->dev.d_private = (void *)g_stm32ethmac; /* Used to recover private state from dev */
+ priv->dev.d_private =
+ (void *)g_stm32ethmac; /* Used to recover private state */
priv->intf = intf; /* Remember the interface number */
/* Create a watchdog for timing polling for and timing of transmissions */
@@ -4389,7 +4417,7 @@ static inline int stm32_ethinitialize(int intf)
*
* Description:
* This is the "standard" network initialization logic called from the
- * low-level initialization logic in arm_initialize.c. If STM32H7_NETHERNET
+ * low-level initialization logic in arm_initialize.c. If STM32H7_NETHERNET
* greater than one, then board specific logic will have to supply a
* version of arm_netinitialize() that calls stm32_ethinitialize() with
* the appropriate interface number.
[incubator-nuttx] 01/04: arch/arm/src/stm32h7/stm32_allocateheap.c:
Fix compilation when CONFIG_MM_REGIONS == 1
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 2ef571453a116458430e582ec28f0b7fbb7f9cc2
Author: Jukka Laitinen <ju...@intel.com>
AuthorDate: Fri Apr 17 13:12:05 2020 +0300
arch/arm/src/stm32h7/stm32_allocateheap.c: Fix compilation when CONFIG_MM_REGIONS == 1
Signed-off-by: Jukka Laitinen <ju...@intel.com>
---
arch/arm/src/stm32h7/stm32_allocateheap.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c
index f65db6d..376738b 100644
--- a/arch/arm/src/stm32h7/stm32_allocateheap.c
+++ b/arch/arm/src/stm32h7/stm32_allocateheap.c
@@ -300,6 +300,7 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
}
#endif
+#if (CONFIG_MM_REGIONS > 1)
/****************************************************************************
* Name: addregion
*
@@ -389,3 +390,4 @@ void arm_addregion(void)
}
#endif
}
+#endif
[incubator-nuttx] 02/04: arch/arm/src/stm32h7/Make.defs: arm_mpu.c
was added twice
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d618dad296d3017488a4ca71b7188fb4333babf1
Author: Jukka Laitinen <ju...@intel.com>
AuthorDate: Mon Apr 20 10:45:47 2020 +0300
arch/arm/src/stm32h7/Make.defs: arm_mpu.c was added twice
Signed-off-by: Jukka Laitinen <ju...@intel.com>
---
arch/arm/src/stm32h7/Make.defs | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs
index 2951768..46cbc73 100644
--- a/arch/arm/src/stm32h7/Make.defs
+++ b/arch/arm/src/stm32h7/Make.defs
@@ -137,11 +137,6 @@ CHIP_CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_STM32H7_BBSRAM),y)
-ifeq ($(CONFIG_ARMV7M_DCACHE),y)
-ifeq ($(CONFIG_ARM_MPU),y)
-CMN_CSRCS += arm_mpu.c
-endif
-endif
CHIP_CSRCS += stm32_bbsram.c
endif