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Posted to commits@nuttx.apache.org by gn...@apache.org on 2020/04/07 12:23:24 UTC
[incubator-nuttx] branch master updated (81b286d -> 9029e4d)
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 81b286d Fix some long single line comments.
new 3cc336d Remove type casting to wdentry_t (sched/)
new 776e469 Remove type casting to wdentry_t (drivers/)
new 2ca9681 Remove type casting to wdentry_t (boards/)
new e264484 Remove type casting to wdentry_t (arch/)
new 9029e4d Fix nxstyle issues
The 5 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/cxd56xx/cxd56_rtc.c | 150 ++++++++--------
arch/arm/src/cxd56xx/cxd56_sdhci.c | 6 +-
arch/arm/src/imxrt/imxrt_usdhc.c | 6 +-
arch/arm/src/kinetis/kinetis_sdhc.c | 6 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c | 6 +-
arch/arm/src/lpc43xx/lpc43_sdmmc.c | 6 +-
arch/arm/src/lpc54xx/lpc54_sdmmc.c | 6 +-
arch/arm/src/sam34/sam_hsmci.c | 6 +-
arch/arm/src/sam34/sam_spi.c | 12 +-
arch/arm/src/sama5/sam_hsmci.c | 6 +-
arch/arm/src/sama5/sam_spi.c | 16 +-
arch/arm/src/sama5/sam_ssc.c | 32 ++--
arch/arm/src/samv7/sam_hsmci.c | 6 +-
arch/arm/src/samv7/sam_qspi.c | 82 +++++----
arch/arm/src/samv7/sam_spi.c | 18 +-
arch/arm/src/samv7/sam_ssc.c | 32 ++--
arch/arm/src/stm32/stm32_i2s.c | 33 ++--
arch/arm/src/stm32/stm32_sdio.c | 6 +-
arch/arm/src/stm32f7/stm32_qspi.c | 73 +++++---
arch/arm/src/stm32f7/stm32_sai.c | 82 +++++----
arch/arm/src/stm32f7/stm32_sdmmc.c | 6 +-
arch/arm/src/stm32h7/stm32_qspi.c | 24 ++-
arch/arm/src/stm32h7/stm32_sdmmc.c | 6 +-
arch/arm/src/stm32l4/stm32l4_qspi.c | 232 ++++++++++++++-----------
arch/arm/src/stm32l4/stm32l4_sai.c | 8 +-
arch/arm/src/stm32l4/stm32l4_sdmmc.c | 6 +-
arch/arm/src/xmc4/xmc4_spi.c | 4 +-
arch/mips/src/pic32mz/pic32mz-spi.c | 16 +-
arch/sim/src/sim/up_ioexpander.c | 25 +--
boards/arm/samv7/samv71-xult/src/sam_ili9488.c | 10 +-
boards/sim/sim/sim/src/sim_gpio.c | 2 +-
drivers/ioexpander/pcf8574.c | 12 +-
drivers/ioexpander/tca64xx.c | 12 +-
sched/mqueue/mq_timedreceive.c | 5 +-
sched/mqueue/mq_timedsend.c | 5 +-
sched/pthread/pthread_condtimedwait.c | 93 +++++-----
sched/semaphore/sem_tickwait.c | 3 +-
sched/semaphore/sem_timedwait.c | 3 +-
sched/semaphore/sem_timeout.c | 2 +-
sched/semaphore/semaphore.h | 2 +-
sched/signal/sig_timedwait.c | 4 +-
sched/timer/timer_settime.c | 12 +-
42 files changed, 634 insertions(+), 448 deletions(-)
[incubator-nuttx] 02/05: Remove type casting to wdentry_t (drivers/)
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 776e469b027e1cf168e31d50359709e1a7096dd6
Author: Nakamura, Yuuichi <Yu...@sony.com>
AuthorDate: Mon Apr 6 22:55:08 2020 +0900
Remove type casting to wdentry_t (drivers/)
---
drivers/ioexpander/pcf8574.c | 4 ++--
drivers/ioexpander/tca64xx.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ioexpander/pcf8574.c b/drivers/ioexpander/pcf8574.c
index e6bfdd3..8fca41c 100644
--- a/drivers/ioexpander/pcf8574.c
+++ b/drivers/ioexpander/pcf8574.c
@@ -984,7 +984,7 @@ static void pcf8574_irqworker(void *arg)
sched_lock();
ret = wd_start(priv->wdog, PCF8574_POLLDELAY,
- (wdentry_t)pcf8574_poll_expiry,
+ pcf8574_poll_expiry,
1, (wdparm_t)priv);
if (ret < 0)
{
@@ -1155,7 +1155,7 @@ FAR struct ioexpander_dev_s *pcf8574_initialize(FAR struct i2c_master_s *i2c,
DEBUGASSERT(priv->wdog != NULL);
ret = wd_start(priv->wdog, PCF8574_POLLDELAY,
- (wdentry_t)pcf8574_poll_expiry,
+ pcf8574_poll_expiry,
1, (wdparm_t)priv);
if (ret < 0)
{
diff --git a/drivers/ioexpander/tca64xx.c b/drivers/ioexpander/tca64xx.c
index 9f35927..87d058a 100644
--- a/drivers/ioexpander/tca64xx.c
+++ b/drivers/ioexpander/tca64xx.c
@@ -1257,7 +1257,7 @@ errout_with_restart:
/* Re-start the poll timer */
sched_lock();
- ret = wd_start(priv->wdog, TCA64XX_POLLDELAY, (wdentry_t)tca64_poll_expiry,
+ ret = wd_start(priv->wdog, TCA64XX_POLLDELAY, tca64_poll_expiry,
1, (wdparm_t)priv);
if (ret < 0)
{
@@ -1426,7 +1426,7 @@ FAR struct ioexpander_dev_s *tca64_initialize(FAR struct i2c_master_s *i2c,
priv->wdog = wd_create();
DEBUGASSERT(priv->wdog != NULL);
- ret = wd_start(priv->wdog, TCA64XX_POLLDELAY, (wdentry_t)tca64_poll_expiry,
+ ret = wd_start(priv->wdog, TCA64XX_POLLDELAY, tca64_poll_expiry,
1, (wdparm_t)priv);
if (ret < 0)
{
[incubator-nuttx] 01/05: Remove type casting to wdentry_t (sched/)
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 3cc336dddd48e17ae15a457807eb89fdcdc906ab
Author: Nakamura, Yuuichi <Yu...@sony.com>
AuthorDate: Fri Mar 13 15:44:16 2020 +0900
Remove type casting to wdentry_t (sched/)
---
sched/mqueue/mq_timedreceive.c | 5 +-
sched/mqueue/mq_timedsend.c | 5 +-
sched/pthread/pthread_condtimedwait.c | 93 ++++++++++++++++++++---------------
sched/semaphore/sem_tickwait.c | 3 +-
sched/semaphore/sem_timedwait.c | 3 +-
sched/semaphore/sem_timeout.c | 2 +-
sched/semaphore/semaphore.h | 2 +-
sched/signal/sig_timedwait.c | 4 +-
sched/timer/timer_settime.c | 8 +--
9 files changed, 67 insertions(+), 58 deletions(-)
diff --git a/sched/mqueue/mq_timedreceive.c b/sched/mqueue/mq_timedreceive.c
index 8500472..a7dbcf5 100644
--- a/sched/mqueue/mq_timedreceive.c
+++ b/sched/mqueue/mq_timedreceive.c
@@ -64,7 +64,7 @@
*
****************************************************************************/
-static void nxmq_rcvtimeout(int argc, wdparm_t pid)
+static void nxmq_rcvtimeout(int argc, wdparm_t pid, ...)
{
FAR struct tcb_s *wtcb;
irqstate_t flags;
@@ -224,8 +224,7 @@ ssize_t nxmq_timedreceive(mqd_t mqdes, FAR char *msg, size_t msglen,
/* Start the watchdog */
- wd_start(rtcb->waitdog, ticks, (wdentry_t)nxmq_rcvtimeout,
- 1, getpid());
+ wd_start(rtcb->waitdog, ticks, nxmq_rcvtimeout, 1, getpid());
}
/* Get the message from the message queue */
diff --git a/sched/mqueue/mq_timedsend.c b/sched/mqueue/mq_timedsend.c
index 7a46d5d..821a066 100644
--- a/sched/mqueue/mq_timedsend.c
+++ b/sched/mqueue/mq_timedsend.c
@@ -63,7 +63,7 @@
*
****************************************************************************/
-static void nxmq_sndtimeout(int argc, wdparm_t pid)
+static void nxmq_sndtimeout(int argc, wdparm_t pid, ...)
{
FAR struct tcb_s *wtcb;
irqstate_t flags;
@@ -256,8 +256,7 @@ int nxmq_timedsend(mqd_t mqdes, FAR const char *msg, size_t msglen,
/* Start the watchdog and begin the wait for MQ not full */
- wd_start(rtcb->waitdog, ticks, (wdentry_t)nxmq_sndtimeout,
- 1, getpid());
+ wd_start(rtcb->waitdog, ticks, nxmq_sndtimeout, 1, getpid());
/* And wait for the message queue to be non-empty */
diff --git a/sched/pthread/pthread_condtimedwait.c b/sched/pthread/pthread_condtimedwait.c
index 2bc81bd..6f14009 100644
--- a/sched/pthread/pthread_condtimedwait.c
+++ b/sched/pthread/pthread_condtimedwait.c
@@ -26,6 +26,7 @@
#include <nuttx/compiler.h>
#include <stdint.h>
+#include <stdarg.h>
#include <unistd.h>
#include <pthread.h>
#include <signal.h>
@@ -67,61 +68,73 @@
*
****************************************************************************/
-static void pthread_condtimedout(int argc, uint32_t pid, uint32_t signo)
+static void pthread_condtimedout(int argc, wdparm_t arg1, ...)
{
-#ifdef HAVE_GROUP_MEMBERS
+ pid_t pid = (pid_t)arg1;
+ int signo;
+ va_list ap;
- FAR struct tcb_s *tcb;
- siginfo_t info;
+ /* Retrieve the variadic argument */
- /* The logic below if equivalent to nxsig_queue(), but uses
- * nxsig_tcbdispatch() instead of nxsig_dispatch(). This avoids the group
- * signal deliver logic and assures, instead, that the signal is delivered
- * specifically to this thread that is known to be waiting on the signal.
- */
+ va_start(ap, arg1);
+ signo = (int)va_arg(ap, wdparm_t);
+ va_end(ap);
- /* Get the waiting TCB. sched_gettcb() might return NULL if the task has
- * exited for some reason.
- */
-
- tcb = sched_gettcb((pid_t)pid);
- if (tcb)
+#ifdef HAVE_GROUP_MEMBERS
{
- /* Create the siginfo structure */
+ FAR struct tcb_s *tcb;
+ siginfo_t info;
+
+ /* The logic below if equivalent to nxsig_queue(), but uses
+ * nxsig_tcbdispatch() instead of nxsig_dispatch(). This avoids the
+ * group signal deliver logic and assures, instead, that the signal is
+ * delivered specifically to this thread that is known to be waiting on
+ * the signal.
+ */
+
+ /* Get the waiting TCB. sched_gettcb() might return NULL if the task
+ * has exited for some reason.
+ */
+
+ tcb = sched_gettcb(pid);
+ if (tcb)
+ {
+ /* Create the siginfo structure */
- info.si_signo = signo;
- info.si_code = SI_QUEUE;
- info.si_errno = ETIMEDOUT;
- info.si_value.sival_ptr = NULL;
+ info.si_signo = signo;
+ info.si_code = SI_QUEUE;
+ info.si_errno = ETIMEDOUT;
+ info.si_value.sival_ptr = NULL;
#ifdef CONFIG_SCHED_HAVE_PARENT
- info.si_pid = (pid_t)pid;
- info.si_status = OK;
+ info.si_pid = pid;
+ info.si_status = OK;
#endif
- /* Process the receipt of the signal. The scheduler is not locked as
- * is normally the case when this function is called because we are in
- * a watchdog timer interrupt handler.
- */
+ /* Process the receipt of the signal. The scheduler is not locked
+ * as is normally the case when this function is called because we
+ * are in a watchdog timer interrupt handler.
+ */
- nxsig_tcbdispatch(tcb, &info);
+ nxsig_tcbdispatch(tcb, &info);
+ }
}
-
#else /* HAVE_GROUP_MEMBERS */
-
- /* Things are a little easier if there are not group members. We can just
- * use nxsig_queue().
- */
+ {
+ /* Things are a little easier if there are not group members. We can
+ * just use nxsig_queue().
+ */
#ifdef CONFIG_CAN_PASS_STRUCTS
- union sigval value;
+ union sigval value;
- /* Send the specified signal to the specified task. */
+ /* Send the specified signal to the specified task. */
- value.sival_ptr = NULL;
- nxsig_queue((int)pid, (int)signo, value);
+ value.sival_ptr = NULL;
+ nxsig_queue((int)pid, signo, value);
#else
- nxsig_queue((int)pid, (int)signo, NULL);
+ nxsig_queue((int)pid, signo, NULL);
#endif
+ }
#endif /* HAVE_GROUP_MEMBERS */
}
@@ -276,9 +289,9 @@ int pthread_cond_timedwait(FAR pthread_cond_t *cond,
/* Start the watchdog */
wd_start(rtcb->waitdog, ticks,
- (wdentry_t)pthread_condtimedout,
- 2, (uint32_t)mypid,
- (uint32_t)SIGCONDTIMEDOUT);
+ pthread_condtimedout,
+ 2, (wdparm_t)mypid,
+ (wdparm_t)SIGCONDTIMEDOUT);
/* Take the condition semaphore. Do not restore
* interrupts until we return from the wait. This is
diff --git a/sched/semaphore/sem_tickwait.c b/sched/semaphore/sem_tickwait.c
index e41c038..0bbfbf0 100644
--- a/sched/semaphore/sem_tickwait.c
+++ b/sched/semaphore/sem_tickwait.c
@@ -132,8 +132,7 @@ int nxsem_tickwait(FAR sem_t *sem, clock_t start, uint32_t delay)
/* Start the watchdog with interrupts still disabled */
- wd_start(rtcb->waitdog, delay, (wdentry_t)nxsem_timeout,
- 1, getpid());
+ wd_start(rtcb->waitdog, delay, nxsem_timeout, 1, getpid());
/* Now perform the blocking wait */
diff --git a/sched/semaphore/sem_timedwait.c b/sched/semaphore/sem_timedwait.c
index e12d074..da7294f 100644
--- a/sched/semaphore/sem_timedwait.c
+++ b/sched/semaphore/sem_timedwait.c
@@ -175,8 +175,7 @@ int nxsem_timedwait(FAR sem_t *sem, FAR const struct timespec *abstime)
/* Start the watchdog */
- wd_start(rtcb->waitdog, ticks, (wdentry_t)nxsem_timeout,
- 1, getpid());
+ wd_start(rtcb->waitdog, ticks, nxsem_timeout, 1, getpid());
/* Now perform the blocking wait. If nxsem_wait() fails, the
* negated errno value will be returned below.
diff --git a/sched/semaphore/sem_timeout.c b/sched/semaphore/sem_timeout.c
index b0cca95..b248ae9 100644
--- a/sched/semaphore/sem_timeout.c
+++ b/sched/semaphore/sem_timeout.c
@@ -71,7 +71,7 @@
*
****************************************************************************/
-void nxsem_timeout(int argc, wdparm_t pid)
+void nxsem_timeout(int argc, wdparm_t pid, ...)
{
FAR struct tcb_s *wtcb;
irqstate_t flags;
diff --git a/sched/semaphore/semaphore.h b/sched/semaphore/semaphore.h
index 7008db8..77cf8a8 100644
--- a/sched/semaphore/semaphore.h
+++ b/sched/semaphore/semaphore.h
@@ -75,7 +75,7 @@ void nxsem_wait_irq(FAR struct tcb_s *wtcb, int errcode);
/* Handle semaphore timer expiration */
-void nxsem_timeout(int argc, wdparm_t pid);
+void nxsem_timeout(int argc, wdparm_t pid, ...);
/* Recover semaphore resources with a task or thread is destroyed */
diff --git a/sched/signal/sig_timedwait.c b/sched/signal/sig_timedwait.c
index 4ccc5e9..ad75792 100644
--- a/sched/signal/sig_timedwait.c
+++ b/sched/signal/sig_timedwait.c
@@ -87,7 +87,7 @@
*
****************************************************************************/
-static void nxsig_timeout(int argc, wdparm_t itcb)
+static void nxsig_timeout(int argc, wdparm_t itcb, ...)
{
#ifdef CONFIG_SMP
irqstate_t flags;
@@ -358,7 +358,7 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info,
/* Start the watchdog */
wd_start(rtcb->waitdog, waitticks,
- (wdentry_t)nxsig_timeout, 1, wdparm.pvarg);
+ nxsig_timeout, 1, wdparm.pvarg);
/* Now wait for either the signal or the watchdog, but
* first, make sure this is not the idle task,
diff --git a/sched/timer/timer_settime.c b/sched/timer/timer_settime.c
index 33c8bce..92201d7 100644
--- a/sched/timer/timer_settime.c
+++ b/sched/timer/timer_settime.c
@@ -43,7 +43,7 @@
static inline void timer_signotify(FAR struct posix_timer_s *timer);
static inline void timer_restart(FAR struct posix_timer_s *timer,
wdparm_t itimer);
-static void timer_timeout(int argc, wdparm_t itimer);
+static void timer_timeout(int argc, wdparm_t itimer, ...);
/****************************************************************************
* Private Functions
@@ -99,7 +99,7 @@ static inline void timer_restart(FAR struct posix_timer_s *timer,
{
timer->pt_last = timer->pt_delay;
wd_start(timer->pt_wdog, timer->pt_delay,
- (wdentry_t)timer_timeout, 1, itimer);
+ timer_timeout, 1, itimer);
}
}
@@ -123,7 +123,7 @@ static inline void timer_restart(FAR struct posix_timer_s *timer,
*
****************************************************************************/
-static void timer_timeout(int argc, wdparm_t itimer)
+static void timer_timeout(int argc, wdparm_t itimer, ...)
{
#ifndef CONFIG_CAN_PASS_STRUCTS
/* On many small machines, pointers are encoded and cannot be simply cast
@@ -355,7 +355,7 @@ int timer_settime(timer_t timerid, int flags,
*/
timer->pt_last = delay;
- ret = wd_start(timer->pt_wdog, delay, (wdentry_t)timer_timeout,
+ ret = wd_start(timer->pt_wdog, delay, timer_timeout,
1, (wdparm_t)timer);
if (ret < 0)
{
[incubator-nuttx] 05/05: Fix nxstyle issues
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 9029e4daee6457560f93f7031612383814c584d0
Author: Nakamura, Yuuichi <Yu...@sony.com>
AuthorDate: Tue Apr 7 14:42:58 2020 +0900
Fix nxstyle issues
---
arch/arm/src/cxd56xx/cxd56_rtc.c | 148 ++++++++--------
arch/arm/src/sam34/sam_spi.c | 8 +-
arch/arm/src/sama5/sam_spi.c | 12 +-
arch/arm/src/sama5/sam_ssc.c | 20 ++-
arch/arm/src/samv7/sam_qspi.c | 78 +++++----
arch/arm/src/samv7/sam_spi.c | 14 +-
arch/arm/src/samv7/sam_ssc.c | 20 ++-
arch/arm/src/stm32/stm32_i2s.c | 21 ++-
arch/arm/src/stm32f7/stm32_qspi.c | 69 +++++---
arch/arm/src/stm32f7/stm32_sai.c | 78 +++++----
arch/arm/src/stm32h7/stm32_qspi.c | 20 ++-
arch/arm/src/stm32l4/stm32l4_qspi.c | 228 ++++++++++++++-----------
arch/arm/src/stm32l4/stm32l4_sai.c | 4 +-
arch/mips/src/pic32mz/pic32mz-spi.c | 10 +-
arch/sim/src/sim/up_ioexpander.c | 21 ++-
boards/arm/samv7/samv71-xult/src/sam_ili9488.c | 4 +-
drivers/ioexpander/pcf8574.c | 8 +-
drivers/ioexpander/tca64xx.c | 8 +-
sched/timer/timer_settime.c | 4 +-
19 files changed, 476 insertions(+), 299 deletions(-)
diff --git a/arch/arm/src/cxd56xx/cxd56_rtc.c b/arch/arm/src/cxd56xx/cxd56_rtc.c
index c0fd245..83e9753 100644
--- a/arch/arm/src/cxd56xx/cxd56_rtc.c
+++ b/arch/arm/src/cxd56xx/cxd56_rtc.c
@@ -33,9 +33,9 @@
*
****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
@@ -60,10 +60,11 @@
#include "hardware/cxd5602_backupmem.h"
#include "hardware/cxd56_rtc.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
-/* Configuration ********************************************************************/
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
#ifdef CONFIG_RTC_HIRES
# ifndef CONFIG_RTC_FREQUENCY
@@ -97,9 +98,9 @@
#define RTC_CLOCK_CHECK_INTERVAL (200) /* milliseconds */
#define RTC_CLOCK_CHECK_MAX_RETRY (15)
-/************************************************************************************
+/****************************************************************************
* Private Types
- ************************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_RTC_ALARM
struct alm_cbinfo_s
@@ -117,9 +118,9 @@ struct rtc_backup_s
int64_t reserved1;
};
-/************************************************************************************
+/****************************************************************************
* Private Data
- ************************************************************************************/
+ ****************************************************************************/
/* Callback to use when the alarm expires */
@@ -131,17 +132,17 @@ static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST];
static struct rtc_backup_s *g_rtc_save;
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
volatile bool g_rtc_enabled = false;
-/************************************************************************************
+/****************************************************************************
* Private Functions
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Name: rtc_dumptime
*
* Description:
@@ -153,7 +154,7 @@ volatile bool g_rtc_enabled = false;
* Returned Value:
* None
*
- ************************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_DEBUG_RTC
static void rtc_dumptime(FAR const struct timespec *tp, FAR const char *msg)
@@ -172,7 +173,7 @@ static void rtc_dumptime(FAR const struct timespec *tp, FAR const char *msg)
# define rtc_dumptime(tp, msg)
#endif
-/************************************************************************************
+/****************************************************************************
* Name: cxd56_rtc_interrupt
*
* Description:
@@ -185,7 +186,7 @@ static void rtc_dumptime(FAR const struct timespec *tp, FAR const char *msg)
* Returned Value:
* Zero (OK) on success; A negated errno value on failure.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int cxd56_rtc_interrupt(int irq, FAR void *context, FAR void *arg)
@@ -193,7 +194,8 @@ static int cxd56_rtc_interrupt(int irq, FAR void *context, FAR void *arg)
FAR struct alm_cbinfo_s *cbinfo;
alm_callback_t cb;
FAR void *cb_arg;
- uint32_t source, clear;
+ uint32_t source;
+ uint32_t clear;
int id;
int ret = OK;
@@ -221,6 +223,7 @@ static int cxd56_rtc_interrupt(int irq, FAR void *context, FAR void *arg)
rtcerr("ERROR: Invalid ALARM\n");
return ret;
}
+
putreg32(clear, CXD56_RTC0_ALMCLR);
putreg32(0, CXD56_RTC0_ALMOUTEN(id));
@@ -231,7 +234,7 @@ static int cxd56_rtc_interrupt(int irq, FAR void *context, FAR void *arg)
/* Alarm callback */
cb = cbinfo->ac_cb;
- cb_arg = (FAR void*)cbinfo->ac_arg;
+ cb_arg = (FAR void *)cbinfo->ac_arg;
cbinfo->ac_cb = NULL;
cbinfo->ac_arg = NULL;
@@ -243,18 +246,18 @@ static int cxd56_rtc_interrupt(int irq, FAR void *context, FAR void *arg)
}
#endif
-
-/************************************************************************************
+/****************************************************************************
* Name: cxd56_rtc_initialize
*
* Description:
* Actually initialize the hardware RTC. This function is called in the
- * initialization sequence, thereafter may be called when wdog timer is expired.
+ * initialization sequence, thereafter may be called when wdog timer is
+ * expired.
*
* Input Parameters:
* arg: Not used
*
- ************************************************************************************/
+ ****************************************************************************/
static void cxd56_rtc_initialize(int argc, uint32_t arg, ...)
{
@@ -268,30 +271,30 @@ static void cxd56_rtc_initialize(int argc, uint32_t arg, ...)
s_wdog = wd_create();
}
- /* Check whether RTC clock source selects the external RTC and the synchronization
- * from the external RTC is completed.
+ /* Check whether RTC clock source selects the external RTC and the
+ * synchronization from the external RTC is completed.
*/
- g_rtc_save = (struct rtc_backup_s*)BKUP->rtc_saved_data;
+ g_rtc_save = (struct rtc_backup_s *)BKUP->rtc_saved_data;
- if (((getreg32(CXD56_TOPREG_CKSEL_ROOT) & STATUS_RTC_MASK) != STATUS_RTC_SEL) ||
+ if (((getreg32(CXD56_TOPREG_CKSEL_ROOT) & STATUS_RTC_MASK)
+ != STATUS_RTC_SEL) ||
(g_rtc_save->magic != MAGIC_RTC_SAVE))
{
-
/* Retry until RTC clock is stable */
- if (s_retry++ < RTC_CLOCK_CHECK_MAX_RETRY) {
-
- rtcinfo("retry count: %d\n", s_retry);
+ if (s_retry++ < RTC_CLOCK_CHECK_MAX_RETRY)
+ {
+ rtcinfo("retry count: %d\n", s_retry);
- if (OK == wd_start(s_wdog, MSEC2TICK(RTC_CLOCK_CHECK_INTERVAL),
- cxd56_rtc_initialize, 1, (wdparm_t)NULL))
- {
- /* Again, this function is called recursively */
+ if (OK == wd_start(s_wdog, MSEC2TICK(RTC_CLOCK_CHECK_INTERVAL),
+ cxd56_rtc_initialize, 1, (wdparm_t)NULL))
+ {
+ /* Again, this function is called recursively */
- return;
- }
- }
+ return;
+ }
+ }
rtcerr("ERROR: Use inaccurate RCRTC instead of RTC\n");
}
@@ -337,7 +340,8 @@ static void cxd56_rtc_initialize(int argc, uint32_t arg, ...)
{
/* Reflect the system operating time to RTC offset data. */
- g_rtc_save->offset = SEC_TO_CNT(ts.tv_sec) | NSEC_TO_PRECNT(ts.tv_nsec);
+ g_rtc_save->offset = SEC_TO_CNT(ts.tv_sec) |
+ NSEC_TO_PRECNT(ts.tv_nsec);
}
/* Make it possible to use the RTC timer functions */
@@ -347,16 +351,16 @@ static void cxd56_rtc_initialize(int argc, uint32_t arg, ...)
return;
}
-/************************************************************************************
+/****************************************************************************
* Public Functions
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Name: up_rtc_initialize
*
* Description:
- * Initialize the hardware RTC per the selected configuration. This function is
- * called once during the OS initialization sequence
+ * Initialize the hardware RTC per the selected configuration. This
+ * function is called once during the OS initialization sequence
*
* Input Parameters:
* None
@@ -364,7 +368,7 @@ static void cxd56_rtc_initialize(int argc, uint32_t arg, ...)
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
- ************************************************************************************/
+ ****************************************************************************/
int up_rtc_initialize(void)
{
@@ -372,15 +376,15 @@ int up_rtc_initialize(void)
return OK;
}
-/************************************************************************************
+/****************************************************************************
* Name: up_rtc_time
*
* Description:
* Get the current time in seconds. This is similar to the standard time()
- * function. This interface is only required if the low-resolution RTC/counter
- * hardware implementation selected. It is only used by the RTOS during
- * initialization to set up the system time when CONFIG_RTC is set but neither
- * CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
+ * function. This interface is only required if the low-resolution
+ * RTC/counter hardware implementation selected. It is only used by the
+ * RTOS during initialization to set up the system time when CONFIG_RTC is
+ * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
*
* Input Parameters:
* None
@@ -388,7 +392,7 @@ int up_rtc_initialize(void)
* Returned Value:
* The current time in seconds
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef CONFIG_RTC_HIRES
time_t up_rtc_time(void)
@@ -399,17 +403,17 @@ time_t up_rtc_time(void)
count += g_rtc_save->offset;
count >>= 15; /* convert to 1sec resolution */
- return (time_t)count/CONFIG_RTC_FREQUENCY;
+ return (time_t)count / CONFIG_RTC_FREQUENCY;
}
#endif
-/************************************************************************************
+/****************************************************************************
* Name: up_rtc_gettime
*
* Description:
- * Get the current time from the high resolution RTC clock/counter. This interface
- * is only supported by the high-resolution RTC/counter hardware implementation.
- * It is used to replace the system timer.
+ * Get the current time from the high resolution RTC clock/counter. This
+ * interface is only supported by the high-resolution RTC/counter hardware
+ * implementation. It is used to replace the system timer.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
@@ -417,7 +421,7 @@ time_t up_rtc_time(void)
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
- ************************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_RTC_HIRES
int up_rtc_gettime(FAR struct timespec *tp)
@@ -430,7 +434,8 @@ int up_rtc_gettime(FAR struct timespec *tp)
/* Then we can save the time in seconds and fractional seconds. */
tp->tv_sec = count / CONFIG_RTC_FREQUENCY;
- tp->tv_nsec = (count % CONFIG_RTC_FREQUENCY)*(NSEC_PER_SEC/CONFIG_RTC_FREQUENCY);
+ tp->tv_nsec = (count % CONFIG_RTC_FREQUENCY) *
+ (NSEC_PER_SEC / CONFIG_RTC_FREQUENCY);
rtc_dumptime(tp, "Getting time");
@@ -438,12 +443,12 @@ int up_rtc_gettime(FAR struct timespec *tp)
}
#endif
-/************************************************************************************
+/****************************************************************************
* Name: up_rtc_settime
*
* Description:
- * Set the RTC to the provided time. All RTC implementations must be able to
- * set their time based on a standard timespec.
+ * Set the RTC to the provided time. All RTC implementations must be able
+ * to set their time based on a standard timespec.
*
* Input Parameters:
* tp - the time to use
@@ -451,7 +456,7 @@ int up_rtc_gettime(FAR struct timespec *tp)
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
- ************************************************************************************/
+ ****************************************************************************/
int up_rtc_settime(FAR const struct timespec *tp)
{
@@ -488,7 +493,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
return OK;
}
-/************************************************************************************
+/****************************************************************************
* Name: cxd56_rtc_count
*
* Description:
@@ -497,15 +502,14 @@ int up_rtc_settime(FAR const struct timespec *tp)
* Returned Value:
* 64bit counter value running at 32kHz
*
- ************************************************************************************/
+ ****************************************************************************/
uint64_t cxd56_rtc_count(void)
{
uint64_t val;
irqstate_t flags;
- /*
- * The pre register is latched with reading the post rtcounter register,
+ /* The pre register is latched with reading the post rtcounter register,
* so these registers always have to been read in the below order,
* 1st post -> 2nd pre, and should be operated in atomic.
*/
@@ -520,7 +524,7 @@ uint64_t cxd56_rtc_count(void)
return val;
}
-/************************************************************************************
+/****************************************************************************
* Name: cxd56_rtc_almcount
*
* Description:
@@ -529,7 +533,7 @@ uint64_t cxd56_rtc_count(void)
* Returned Value:
* 64bit alarm counter value running at 32kHz
*
- ************************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_RTC_ALARM
uint64_t cxd56_rtc_almcount(void)
@@ -548,7 +552,7 @@ uint64_t cxd56_rtc_almcount(void)
}
#endif
-/************************************************************************************
+/****************************************************************************
* Name: cxd56_rtc_setalarm
*
* Description:
@@ -560,7 +564,7 @@ uint64_t cxd56_rtc_almcount(void)
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
- ************************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int cxd56_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
@@ -617,7 +621,7 @@ int cxd56_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
}
#endif
-/************************************************************************************
+/****************************************************************************
* Name: cxd56_rtc_cancelalarm
*
* Description:
@@ -629,7 +633,7 @@ int cxd56_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
- ************************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int cxd56_rtc_cancelalarm(enum alm_id_e alarmid)
diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c
index 52d3fa5..f062d32 100644
--- a/arch/arm/src/sam34/sam_spi.c
+++ b/arch/arm/src/sam34/sam_spi.c
@@ -792,7 +792,9 @@ static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result)
if (spics->result == -EBUSY)
{
- /* Save the result of the transfer if no error was previously reported */
+ /* Save the result of the transfer if no error was previously
+ * reported
+ */
spics->result = result;
}
@@ -984,7 +986,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
spiinfo("cs=%d frequency=%d\n", spics->cs, frequency);
- /* Check if the requested frequency is the same as the frequency selection */
+ /* Check if the requested frequency is the same as the frequency
+ * selection
+ */
if (spics->frequency == frequency)
{
diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c
index 2f80d99..13942a6 100644
--- a/arch/arm/src/sama5/sam_spi.c
+++ b/arch/arm/src/sama5/sam_spi.c
@@ -780,7 +780,9 @@ static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result)
if (spics->result == -EBUSY)
{
- /* Save the result of the transfer if no error was previously reported */
+ /* Save the result of the transfer if no error was previously
+ * reported
+ */
spics->result = result;
}
@@ -972,7 +974,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
spiinfo("cs=%d frequency=%d\n", spics->cs, frequency);
- /* Check if the requested frequency is the same as the frequency selection */
+ /* Check if the requested frequency is the same as the frequency
+ * selection
+ */
if (spics->frequency == frequency)
{
@@ -1171,7 +1175,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so the subsequence re-configurations will be
+ * faster
+ */
spics->nbits = nbits;
}
diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c
index 962bb2f..7568980 100644
--- a/arch/arm/src/sama5/sam_ssc.c
+++ b/arch/arm/src/sama5/sam_ssc.c
@@ -418,7 +418,9 @@ struct sam_buffer_s
int result; /* The result of the transfer */
};
-/* This structure describes the state of one receiver or transmitter transport */
+/* This structure describes the state of one receiver or transmitter
+ * transport
+ */
struct sam_transport_s
{
@@ -1271,7 +1273,9 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
do
{
- /* Remove the pending RX transfer at the head of the RX pending queue. */
+ /* Remove the pending RX transfer at the head of the RX pending
+ * queue.
+ */
bfcontainer = (struct sam_buffer_s *)sq_remfirst(&priv->rx.pend);
DEBUGASSERT(bfcontainer && bfcontainer->apb);
@@ -1522,7 +1526,9 @@ static void ssc_rx_schedule(struct sam_ssc_s *priv, int result)
bfcontainer->result = result;
- /* Add the completed buffer container to the tail of the rx.done queue */
+ /* Add the completed buffer container to the tail of the rx.done
+ * queue
+ */
sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.done);
}
@@ -1685,7 +1691,9 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
do
{
- /* Remove the pending TX transfer at the head of the TX pending queue. */
+ /* Remove the pending TX transfer at the head of the TX pending
+ * queue.
+ */
bfcontainer = (struct sam_buffer_s *)sq_remfirst(&priv->tx.pend);
DEBUGASSERT(bfcontainer && bfcontainer->apb);
@@ -1922,7 +1930,9 @@ static void ssc_tx_schedule(struct sam_ssc_s *priv, int result)
bfcontainer->result = result;
- /* Add the completed buffer container to the tail of the tx.done queue */
+ /* Add the completed buffer container to the tail of the tx.done
+ * queue
+ */
sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.done);
}
diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c
index ca2bb14..4f10c52 100644
--- a/arch/arm/src/samv7/sam_qspi.c
+++ b/arch/arm/src/samv7/sam_qspi.c
@@ -75,6 +75,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Configuration ************************************************************/
#ifndef CONFIG_SAMV7_QSPI_DLYBS
@@ -115,6 +116,7 @@
#undef QSPI_USE_INTERRUPTS
/* Clocking *****************************************************************/
+
/* The QSPI Baud rate clock is generated by dividing the peripheral clock by
* a value between 1 and 255
*/
@@ -141,7 +143,8 @@
#define ALIGN_UP(n) (((n)+ALIGN_MASK) & ~ALIGN_MASK)
#define IS_ALIGNED(n) (((uint32_t)(n) & ALIGN_MASK) == 0)
-/* Debug *******************************************************************/
+/* Debug ********************************************************************/
+
/* Check if QSPI debug is enabled */
#ifndef CONFIG_DEBUG_DMA
@@ -201,10 +204,10 @@ struct sam_qspidev_s
#endif
#ifdef CONFIG_SAMV7_QSPI_REGDEBUG
- bool wrlast; /* Last was a write */
- uint32_t addresslast; /* Last address */
- uint32_t valuelast; /* Last value */
- int ntimes; /* Number of times */
+ bool wrlast; /* Last was a write */
+ uint32_t addresslast; /* Last address */
+ uint32_t valuelast; /* Last value */
+ int ntimes; /* Number of times */
#endif
};
@@ -276,7 +279,8 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg);
/* QSPI methods */
static int qspi_lock(struct qspi_dev_s *dev, bool lock);
-static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency);
+static uint32_t qspi_setfrequency(struct qspi_dev_s *dev,
+ uint32_t frequency);
static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode);
static void qspi_setbits(struct qspi_dev_s *dev, int nbits);
static int qspi_command(struct qspi_dev_s *dev,
@@ -358,8 +362,8 @@ static struct sam_qspidev_s g_qspi0dev =
****************************************************************************/
#ifdef CONFIG_SAMV7_QSPI_REGDEBUG
-static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr, uint32_t value,
- uint32_t address)
+static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr,
+ uint32_t value, uint32_t address)
{
if (wr == priv->wrlast && /* Same kind of access? */
value == priv->valuelast && /* Same value? */
@@ -526,6 +530,7 @@ static void qspi_dma_sampledone(struct sam_qspidev_s *priv)
sam_dmasample(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER]);
/* Then dump the sampled DMA registers */
+
/* Initial register values */
sam_dmadump(priv->dmach, &priv->dmaregs[DMA_INITIAL],
@@ -636,13 +641,15 @@ static void qspi_dma_callback(DMA_HANDLE handle, void *arg, int result)
qspi_dma_sample(priv, DMA_CALLBACK);
- /* Report the result of the transfer only if the TX callback has not already
- * reported an error.
+ /* Report the result of the transfer only if the TX callback has not
+ * already reported an error.
*/
if (priv->result == -EBUSY)
{
- /* Save the result of the transfer if no error was previously reported */
+ /* Save the result of the transfer if no error was previously
+ * reported
+ */
priv->result = result;
}
@@ -730,7 +737,8 @@ static int qspi_memory_enable(struct sam_qspidev_s *priv,
/* Write Instruction Frame Register:
*
- * QSPI_IFR_WIDTH_? Instruction=single bit/Data depends on meminfo->flags
+ * QSPI_IFR_WIDTH_? Instruction=single bit/Data depends on
+ * meminfo->flags
* QSPI_IFR_INSTEN=1 Instruction Enable
* QSPI_IFR_ADDREN=1 Address Enable
* QSPI_IFR_OPTEN=0 Option Disable
@@ -1098,7 +1106,9 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
spiinfo("frequency=%d\n", frequency);
DEBUGASSERT(priv);
- /* Check if the requested frequency is the same as the frequency selection */
+ /* Check if the requested frequency is the same as the frequency
+ * selection
+ */
if (priv->frequency == frequency)
{
@@ -1136,10 +1146,10 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
regval &= ~(QSPI_SCR_SCBR_MASK | QSPI_SCR_DLYBS_MASK);
regval |= (scbr - 1) << QSPI_SCR_SCBR_SHIFT;
- /* DLYBS: Delay Before QSCK. This field defines the delay from NPCS valid to the
- * first valid QSCK transition. When DLYBS equals zero, the NPCS valid to QSCK
- * transition is 1/2 the QSCK clock period. Otherwise, the following equations
- * determine the delay:
+ /* DLYBS: Delay Before QSCK. This field defines the delay from NPCS valid
+ * to the first valid QSCK transition. When DLYBS equals zero, the NPCS
+ * valid to QSCK transition is 1/2 the QSCK clock period. Otherwise, the
+ * following equations determine the delay:
*
* Delay Before QSCK = DLYBS / QSPI_CLK
*
@@ -1156,10 +1166,10 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
qspi_putreg(priv, regval, SAM_QSPI_SCR_OFFSET);
- /* DLYBCT: Delay Between Consecutive Transfers. This field defines the delay
- * between two consecutive transfers with the same peripheral without removing
- * the chip select. The delay is always inserted after each transfer and
- * before removing the chip select if needed.
+ /* DLYBCT: Delay Between Consecutive Transfers. This field defines the
+ * delay between two consecutive transfers with the same peripheral without
+ * removing the chip select. The delay is always inserted after each
+ * transfer and before removing the chip select if needed.
*
* Delay Between Consecutive Transfers = (32 x DLYBCT) / QSPI_CLK
*
@@ -1173,7 +1183,8 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
regval &= ~QSPI_MR_DLYBCT_MASK;
#if CONFIG_SAMV7_QSPI_DLYBCT > 0
- dlybct = ((CONFIG_SAMV7_QSPI_DLYBCT * (SAM_QSPI_CLOCK /1000000)) / 1000 / 32);
+ dlybct = ((CONFIG_SAMV7_QSPI_DLYBCT * (SAM_QSPI_CLOCK / 1000000))
+ / 1000 / 32);
regval |= dlybct << QSPI_MR_DLYBCT_SHIFT;
#endif
@@ -1300,7 +1311,9 @@ static void qspi_setbits(struct qspi_dev_s *dev, int nbits)
spiinfo("MR=%08x\n", regval);
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so the subsequence re-configurations will be
+ * faster
+ */
priv->nbits = nbits;
}
@@ -1343,8 +1356,10 @@ static int qspi_command(struct qspi_dev_s *dev,
if (QSPICMD_ISDATA(cmdinfo->flags))
{
- spiinfo(" %s Data:\n", QSPICMD_ISWRITE(cmdinfo->flags) ? "Write" : "Read");
- spiinfo(" buffer/length: %p/%d\n", cmdinfo->buffer, cmdinfo->buflen);
+ spiinfo(" %s Data:\n",
+ QSPICMD_ISWRITE(cmdinfo->flags) ? "Write" : "Read");
+ spiinfo(" buffer/length: %p/%d\n",
+ cmdinfo->buffer, cmdinfo->buflen);
}
#endif
@@ -1474,7 +1489,8 @@ static int qspi_command(struct qspi_dev_s *dev,
* registers are empty.
*/
- while ((qspi_getreg(priv, SAM_QSPI_SR_OFFSET) & QSPI_INT_TXEMPTY) == 0);
+ while ((qspi_getreg(priv, SAM_QSPI_SR_OFFSET) & QSPI_INT_TXEMPTY)
+ == 0);
qspi_putreg(priv, QSPI_CR_LASTXFER, SAM_QSPI_CR_OFFSET);
@@ -1544,7 +1560,8 @@ static int qspi_memory(struct qspi_dev_s *dev,
spiinfo(" cmd: %04x\n", meminfo->cmd);
spiinfo(" address/length: %08lx/%d\n",
(unsigned long)meminfo->addr, meminfo->addrlen);
- spiinfo(" %s Data:\n", QSPIMEM_ISWRITE(meminfo->flags) ? "Write" : "Read");
+ spiinfo(" %s Data:\n",
+ QSPIMEM_ISWRITE(meminfo->flags) ? "Write" : "Read");
spiinfo(" buffer/length: %p/%d\n", meminfo->buffer, meminfo->buflen);
#ifdef CONFIG_SAMV7_QSPI_DMA
@@ -1582,9 +1599,9 @@ static int qspi_memory(struct qspi_dev_s *dev,
static FAR void *qspi_alloc(FAR struct qspi_dev_s *dev, size_t buflen)
{
- /* Here we exploit the internal knowledge the kmm_malloc() will return memory
- * aligned to 64-bit addresses. The buffer length must be large enough to
- * hold the rested buflen in units a 32-bits.
+ /* Here we exploit the internal knowledge the kmm_malloc() will return
+ * memory aligned to 64-bit addresses. The buffer length must be large
+ * enough to hold the rested buflen in units a 32-bits.
*/
return kmm_malloc(ALIGN_UP(buflen));
@@ -1754,6 +1771,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
if (!priv->initialized)
{
/* No perform one time initialization */
+
/* Initialize the QSPI semaphore that enforces mutually exclusive
* access to the QSPI registers.
*/
diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c
index 1e06f0e..606f397 100644
--- a/arch/arm/src/samv7/sam_spi.c
+++ b/arch/arm/src/samv7/sam_spi.c
@@ -295,7 +295,9 @@ static void spi_recvblock(struct spi_dev_s *dev, void *buffer,
* Private Data
****************************************************************************/
-/* This array maps chip select numbers (0-3 or 1-15) to CSR register offsets */
+/* This array maps chip select numbers (0-3 or 1-15) to CSR register
+ * offsets
+ */
#if defined(CONFIG_SAMV7_SPI_CS_DECODING)
static const uint8_t g_csroffset[16] =
@@ -819,7 +821,9 @@ static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result)
if (spics->result == -EBUSY)
{
- /* Save the result of the transfer if no error was previously reported */
+ /* Save the result of the transfer if no error was previously
+ * reported
+ */
spics->result = result;
}
@@ -1022,7 +1026,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
spiinfo("cs=%d frequency=%d\n", spics->cs, frequency);
- /* Check if the requested frequency is the same as the frequency selection */
+ /* Check if the requested frequency is the same as the frequency
+ * selection
+ */
if (spics->frequency == frequency)
{
@@ -1259,7 +1265,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features)
offset = (unsigned int)g_csroffset[spics->cs];
regval = spi_getreg(spi, offset);
regval &= ~SPI_CSR_CSNAAT; /* Chip Select Not Active After Transfer */
- regval |= SPI_CSR_CSAAT; /* Chip Select Active After Transfer */
+ regval |= SPI_CSR_CSAAT ; /* Chip Select Active After Transfer */
spi_putreg(spi, regval, offset);
}
else
diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c
index a9b01ba..4bf9947 100644
--- a/arch/arm/src/samv7/sam_ssc.c
+++ b/arch/arm/src/samv7/sam_ssc.c
@@ -393,7 +393,9 @@ struct sam_buffer_s
int result; /* The result of the transfer */
};
-/* This structure describes the state of one receiver or transmitter transport */
+/* This structure describes the state of one receiver or transmitter
+ * transport
+ */
struct sam_transport_s
{
@@ -1246,7 +1248,9 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
do
{
- /* Remove the pending RX transfer at the head of the RX pending queue. */
+ /* Remove the pending RX transfer at the head of the RX pending
+ * queue.
+ */
bfcontainer = (struct sam_buffer_s *)sq_remfirst(&priv->rx.pend);
DEBUGASSERT(bfcontainer && bfcontainer->apb);
@@ -1499,7 +1503,9 @@ static void ssc_rx_schedule(struct sam_ssc_s *priv, int result)
bfcontainer->result = result;
- /* Add the completed buffer container to the tail of the rx.done queue */
+ /* Add the completed buffer container to the tail of the rx.done
+ * queue
+ */
sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.done);
}
@@ -1662,7 +1668,9 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
do
{
- /* Remove the pending TX transfer at the head of the TX pending queue. */
+ /* Remove the pending TX transfer at the head of the TX pending
+ * queue.
+ */
bfcontainer = (struct sam_buffer_s *)sq_remfirst(&priv->tx.pend);
DEBUGASSERT(bfcontainer && bfcontainer->apb);
@@ -1903,7 +1911,9 @@ static void ssc_tx_schedule(struct sam_ssc_s *priv, int result)
bfcontainer->result = result;
- /* Add the completed buffer container to the tail of the tx.done queue */
+ /* Add the completed buffer container to the tail of the tx.done
+ * queue
+ */
sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.done);
}
diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/stm32/stm32_i2s.c
index 71f9350..ec0adc5 100644
--- a/arch/arm/src/stm32/stm32_i2s.c
+++ b/arch/arm/src/stm32/stm32_i2s.c
@@ -1036,7 +1036,9 @@ static int i2s_rxdma_setup(struct stm32_i2s_s *priv)
do
{
- /* Remove the pending RX transfer at the head of the RX pending queue. */
+ /* Remove the pending RX transfer at the head of the RX pending
+ * queue.
+ */
bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->rx.pend);
DEBUGASSERT(bfcontainer && bfcontainer->apb);
@@ -1271,7 +1273,9 @@ static void i2s_rx_schedule(struct stm32_i2s_s *priv, int result)
bfcontainer->result = result;
- /* Add the completed buffer container to the tail of the rx.done queue */
+ /* Add the completed buffer container to the tail of the rx.done
+ * queue
+ */
sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.done);
}
@@ -1433,7 +1437,9 @@ static int i2s_txdma_setup(struct stm32_i2s_s *priv)
do
{
- /* Remove the pending TX transfer at the head of the TX pending queue. */
+ /* Remove the pending TX transfer at the head of the TX pending
+ * queue.
+ */
bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->tx.pend);
DEBUGASSERT(bfcontainer && bfcontainer->apb);
@@ -1654,7 +1660,9 @@ static void i2s_tx_schedule(struct stm32_i2s_s *priv, int result)
bfcontainer->result = result;
- /* Add the completed buffer container to the tail of the tx.done queue */
+ /* Add the completed buffer container to the tail of the tx.done
+ * queue
+ */
sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.done);
}
@@ -2278,7 +2286,10 @@ static uint32_t i2s_mckdivider(struct stm32_i2s_s *priv)
i2s_putreg(priv, STM32_SPI_I2SCFGR_OFFSET,
SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SCFG_MTX | SPI_I2SCFGR_I2SE);
- /* putreg32((getreg32(STM32_DMA1_HIFCR) | DMA_HIFCR_CTCIF7), STM32_DMA1_HIFCR); */
+#if 0
+ putreg32((getreg32(STM32_DMA1_HIFCR) | DMA_HIFCR_CTCIF7),
+ STM32_DMA1_HIFCR);
+#endif
putreg32((getreg32(STM32_DMA1_HIFCR) | 0x80000000), STM32_DMA1_HIFCR);
diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c
index 5e42fa7..2994c3d 100644
--- a/arch/arm/src/stm32f7/stm32_qspi.c
+++ b/arch/arm/src/stm32f7/stm32_qspi.c
@@ -268,8 +268,8 @@ static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr,
static inline uint32_t qspi_getreg(struct stm32f7_qspidev_s *priv,
unsigned int offset);
-static inline void qspi_putreg(struct stm32f7_qspidev_s *priv, uint32_t value,
- unsigned int offset);
+static inline void qspi_putreg(struct stm32f7_qspidev_s *priv,
+ uint32_t value, unsigned int offset);
#ifdef CONFIG_DEBUG_SPI_INFO
static void qspi_dumpregs(struct stm32f7_qspidev_s *priv,
@@ -314,7 +314,8 @@ static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv);
/* QSPI methods */
static int qspi_lock(struct qspi_dev_s *dev, bool lock);
-static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency);
+static uint32_t qspi_setfrequency(struct qspi_dev_s *dev,
+ uint32_t frequency);
static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode);
static void qspi_setbits(struct qspi_dev_s *dev, int nbits);
static int qspi_command(struct qspi_dev_s *dev,
@@ -455,8 +456,8 @@ static inline uint32_t qspi_getreg(struct stm32f7_qspidev_s *priv,
*
****************************************************************************/
-static inline void qspi_putreg(struct stm32f7_qspidev_s *priv, uint32_t value,
- unsigned int offset)
+static inline void qspi_putreg(struct stm32f7_qspidev_s *priv,
+ uint32_t value, unsigned int offset)
{
uint32_t address = priv->base + offset;
@@ -493,7 +494,8 @@ static void qspi_dumpregs(struct stm32f7_qspidev_s *priv, const char *msg)
#if 0
/* this extra verbose output may be helpful in some cases; you'll need
- * to make sure your syslog is large enough to accommodate the extra output.
+ * to make sure your syslog is large enough to accommodate the extra
+ * output.
*/
regval = getreg32(priv->base + STM32_QUADSPI_CR_OFFSET); /* Control Register */
@@ -881,7 +883,8 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn,
spiinfo(" cmd: %04x\n", meminfo->cmd);
spiinfo(" address/length: %08lx/%d\n",
(unsigned long)meminfo->addr, meminfo->addrlen);
- spiinfo(" %s Data:\n", QSPIMEM_ISWRITE(meminfo->flags) ? "Write" : "Read");
+ spiinfo(" %s Data:\n",
+ QSPIMEM_ISWRITE(meminfo->flags) ? "Write" : "Read");
spiinfo(" buffer/length: %p/%d\n", meminfo->buffer, meminfo->buflen);
#endif
@@ -1008,7 +1011,8 @@ static void qspi_waitstatusflags(struct stm32f7_qspidev_s *priv,
if (polarity)
{
- while (!((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET)) & mask));
+ while (!((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET))
+ & mask));
}
else
{
@@ -1137,13 +1141,15 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
{
/* Write data until we have no more or have no place to put it */
- while (((regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_SR_OFFSET)) &
+ while (((regval = qspi_getreg(&g_qspi0dev,
+ STM32_QUADSPI_SR_OFFSET)) &
QSPI_SR_FTF) != 0)
{
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
{
*(volatile uint8_t *)datareg =
- ((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow];
+ ((uint8_t *)g_qspi0dev.xctn->buffer)
+ [g_qspi0dev.xctn->idxnow];
++g_qspi0dev.xctn->idxnow;
}
else
@@ -1158,12 +1164,14 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
{
/* Read data until we have no more or have no place to put it */
- while (((regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_SR_OFFSET)) &
+ while (((regval = qspi_getreg(&g_qspi0dev,
+ STM32_QUADSPI_SR_OFFSET)) &
QSPI_SR_FTF) != 0)
{
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
{
- ((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow] =
+ ((uint8_t *)g_qspi0dev.xctn->buffer)
+ [g_qspi0dev.xctn->idxnow] =
*(volatile uint8_t *)datareg;
++g_qspi0dev.xctn->idxnow;
}
@@ -1202,12 +1210,14 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
/* Read any remaining data */
- while (((regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_SR_OFFSET)) &
+ while (((regval = qspi_getreg(&g_qspi0dev,
+ STM32_QUADSPI_SR_OFFSET)) &
QSPI_SR_FLEVEL_MASK) != 0)
{
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
{
- ((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow] =
+ ((uint8_t *)g_qspi0dev.xctn->buffer)
+ [g_qspi0dev.xctn->idxnow] =
*(volatile uint8_t *)datareg;
++g_qspi0dev.xctn->idxnow;
}
@@ -1261,7 +1271,9 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
}
else
{
- /* XXX if it's NOT auto stop; something needs to happen here; a callback? */
+ /* XXX if it's NOT auto stop; something needs to happen here;
+ * a callback?
+ */
}
}
@@ -1392,7 +1404,9 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
if (priv->result == -EBUSY)
{
- /* Save the result of the transfer if no error was previously reported */
+ /* Save the result of the transfer if no error was previously
+ * reported
+ */
if (isr & DMA_STREAM_TCIF_BIT)
{
@@ -1646,7 +1660,9 @@ static int qspi_receive_blocking(struct stm32f7_qspidev_s *priv,
qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR_OFFSET);
- /* Use Abort to clear the busy flag, and ditch any extra bytes in fifo */
+ /* Use Abort to clear the busy flag, and ditch any extra bytes in
+ * fifo
+ */
qspi_abort(priv);
}
@@ -1800,7 +1816,9 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
qspi_abort(priv);
qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0);
- /* Check if the requested frequency is the same as the frequency selection */
+ /* Check if the requested frequency is the same as the frequency
+ * selection
+ */
if (priv->frequency == frequency)
{
@@ -2030,8 +2048,8 @@ static int qspi_command(struct qspi_dev_s *dev,
qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDWR);
- /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete'
- * interrupts.
+ /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer
+ * Complete' interrupts.
*/
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
@@ -2055,8 +2073,8 @@ static int qspi_command(struct qspi_dev_s *dev,
qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET);
- /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete'
- * interrupts
+ /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer
+ * Complete' interrupts
*/
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
@@ -2266,7 +2284,9 @@ static int qspi_memory(struct qspi_dev_s *dev,
{
/* polling mode */
- /* Set up the Communications Configuration Register as per command info */
+ /* Set up the Communications Configuration Register as per command
+ * info
+ */
qspi_ccrconfig(priv, &xctn,
QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR :
@@ -2425,7 +2445,8 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv)
/* Configure QSPI FIFO Threshold */
regval &= ~(QSPI_CR_FTHRES_MASK);
- regval |= ((CONFIG_STM32F7_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT);
+ regval |= ((CONFIG_STM32F7_QSPI_FIFO_THESHOLD - 1)
+ << QSPI_CR_FTHRES_SHIFT);
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
/* Wait till BUSY flag reset */
diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c
index 05e60fc..eec9f25 100644
--- a/arch/arm/src/stm32f7/stm32_sai.c
+++ b/arch/arm/src/stm32f7/stm32_sai.c
@@ -443,7 +443,7 @@ static inline void sai_putreg(struct stm32f7_sai_s *priv, uint8_t offset,
putreg32(value, priv->base + offset);
}
-/************************************************************************************
+/****************************************************************************
* Name: sai_modifyreg
*
* Description:
@@ -458,7 +458,7 @@ static inline void sai_putreg(struct stm32f7_sai_s *priv, uint8_t offset,
* Returned Value:
* None
*
- ************************************************************************************/
+ ****************************************************************************/
static void sai_modifyreg(struct stm32f7_sai_s *priv, uint8_t offset,
uint32_t clrbits, uint32_t setbits)
@@ -503,7 +503,7 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
sai_getreg(priv, STM32F7_SAI_SR_OFFSET),
sai_getreg(priv, STM32F7_SAI_CLRFR_OFFSET));
#else
- /*********************GCR*********************/
+ /* GCR */
#ifdef CONFIG_STM32F7_SAI1
uint32_t gcr = getreg32(STM32F7_SAI1_GCR);
@@ -513,7 +513,7 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
i2sinfo("GCR: *%08x = %08x\n", STM32F7_SAI2_GCR, gcr);
#endif
- /********************* CR1 *******************/
+ /* CR1 */
uint32_t cr1 = sai_getreg(priv, STM32F7_SAI_CR1_OFFSET);
i2sinfo("CR1: *%08x = %08x\n", STM32F7_SAI_CR1_OFFSET, cr1);
@@ -553,8 +553,9 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
i2sinfo("\t\tCR1: DS[7:5] = %s\n", ds_string[ds]);
uint32_t lsbfirst = cr1 & SAI_CR1_LSBFIRST;
- i2sinfo("\t\tCR1: LSBFIRST[8] = %s\n", lsbfirst ? "Data are transferred with LSB first"
- : "Data are transferred with MSB first");
+ i2sinfo("\t\tCR1: LSBFIRST[8] = %s\n",
+ lsbfirst ? "Data are transferred with LSB first"
+ : "Data are transferred with MSB first");
uint32_t ckstr = cr1 & SAI_CR1_CKSTR;
i2sinfo("\t\tCR1: CKSTR[9] = %s\n", ckstr ? "SCK falling edge"
: "SCK rising edge");
@@ -562,8 +563,10 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
uint32_t syncen = (cr1 & SAI_CR1_SYNCEN_MASK) >> SAI_CR1_SYNCEN_SHIFT;
const char *syncen_string[] =
{ "audio sub-block in asynchronous mode",
- "audio sub-block in asynchronous with the other internal audio sub-block",
- "audio sub-block in synchronous with an external SAI embedded peripheral",
+ "audio sub-block in asynchronous with the other internal audio "
+ "sub-block",
+ "audio sub-block in synchronous with an external SAI embedded "
+ "peripheral",
"Reserved"
};
@@ -575,7 +578,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
: "Stereo mode");
uint32_t outdriv = cr1 & SAI_CR1_OUTDRIV;
i2sinfo("\t\tCR1: OUTDRIV[13] = %s\n",
- outdriv ? "Audio block output driven immediately after the setting of this bit"
+ outdriv ? "Audio block output driven immediately after "
+ "the setting of this bit"
: "Audio block output driven when SAIEN is set");
uint32_t saien = cr1 & SAI_CR1_SAIEN;
i2sinfo("\t\tCR1: SAIEN[16] = %s\n",
@@ -592,7 +596,7 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
uint32_t mckdiv = (cr1 & SAI_CR1_MCKDIV_MASK) >> SAI_CR1_MCKDIV_SHIFT;
i2sinfo("\t\tCR1: MCKDIV[23:20] = %d\n", mckdiv);
- /*************************CR2**************************/
+ /* CR2 */
uint32_t cr2 = sai_getreg(priv, STM32F7_SAI_CR2_OFFSET);
i2sinfo("CR2: *%08x = %08x\n", STM32F7_SAI_CR2_OFFSET, cr2);
@@ -616,8 +620,9 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
uint32_t tris = cr2 & SAI_CR2_TRIS;
i2sinfo("\t\tCR2: TRIS[4] = %s\n",
- tris ? "SD output line is release (HI-Z)"
- : "SD output line is still driven by the SAI when a slot is inactive");
+ tris ? "SD output line is release (HI-Z)" :
+ "SD output line is still driven by the SAI when a slot is "
+ "inactive");
uint32_t mute = cr2 & SAI_CR2_MUTE;
i2sinfo("\t\tCR2: MUTE[5] = %s\n",
mute ? "Mute mode enabled"
@@ -645,7 +650,7 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
i2sinfo("\t\tCR2: COMP[15:14] = %s\n", comp_string[comp]);
- /**********************FRCR*****************************/
+ /* FRCR */
uint32_t frcr = sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET);
i2sinfo("FRCR: *%08x = %08x\n", STM32F7_SAI_FRCR_OFFSET, frcr);
@@ -669,7 +674,7 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
fsoff ? "FS one bit before first bit of slot 0"
: "FS on first bit of slot 0");
- /*******************SLOTR****************************/
+ /* SLOTR */
uint32_t slotr = sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET);
i2sinfo("SLOTR: *%08x = %08x\n", STM32F7_SAI_SLOTR_OFFSET, slotr);
@@ -677,7 +682,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
uint32_t fboff = (slotr & SAI_SLOTR_FBOFF_MASK) >> SAI_SLOTR_FBOFF_SHIFT;
i2sinfo("\t\tSLOTR: FBOFF[4:0] = %d\n", fboff);
- uint32_t slotsz = (slotr & SAI_SLOTR_SLOTSZ_MASK) >> SAI_SLOTR_SLOTSZ_SHIFT;
+ uint32_t slotsz = (slotr & SAI_SLOTR_SLOTSZ_MASK) >>
+ SAI_SLOTR_SLOTSZ_SHIFT;
const char *slotsz_string[] =
{ "Same as data size",
"16-bit",
@@ -687,10 +693,12 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg)
i2sinfo("\t\tSLOTR: SLOTSZ[7:6] = %s\n", slotsz_string[slotsz]);
- uint32_t nbslot = (slotr & SAI_SLOTR_NBSLOT_MASK) >> SAI_SLOTR_NBSLOT_SHIFT;
+ uint32_t nbslot = (slotr & SAI_SLOTR_NBSLOT_MASK) >>
+ SAI_SLOTR_NBSLOT_SHIFT;
i2sinfo("\t\tSLOTR: NBSLOT[11:8] = %d\n", nbslot + 1);
- uint32_t sloten = (slotr & SAI_SLOTR_SLOTEN_MASK) >> SAI_SLOTR_SLOTEN_SHIFT;
+ uint32_t sloten = (slotr & SAI_SLOTR_SLOTEN_MASK) >>
+ SAI_SLOTR_SLOTEN_SHIFT;
i2sinfo("\t\tSLOTR: SLOTEN[31:16] = %08x\n", sloten + 1);
#endif
}
@@ -719,7 +727,7 @@ static void rcc_dump_regs(const char *msg)
}
#if 0
- /**************RCC_PLLSAICFGR******************/
+ /* RCC_PLLSAICFGR */
uint32_t pll_sai_cfgr = getreg32(STM32_RCC_PLLSAICFGR);
i2sinfo("PLLSAICFGR = %08x\n", pll_sai_cfgr);
@@ -776,8 +784,8 @@ static void sai_exclsem_take(struct stm32f7_sai_s *priv)
* Name: sai_mckdivider
*
* Description:
- * Setup the master clock divider based on the currently selected data width
- * and the sample rate
+ * Setup the master clock divider based on the currently selected data
+ * width and the sample rate
*
* Input Parameters:
* priv - SAI device structure (only the sample rate and frequency are
@@ -846,7 +854,9 @@ static void sai_timeout(int argc, uint32_t arg, ...)
stm32_dmastop(priv->dma);
#endif
- /* Then schedule completion of the transfer to occur on the worker thread. */
+ /* Then schedule completion of the transfer to occur on the worker
+ * thread.
+ */
sai_schedule(priv, -ETIMEDOUT);
}
@@ -1334,8 +1344,8 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
flags = enter_critical_section();
sq_addlast((sq_entry_t *)bfcontainer, &priv->pend);
- /* Then start the next transfer. If there is already a transfer in progress,
- * then this will do nothing.
+ /* Then start the next transfer. If there is already a transfer in
+ * progress, then this will do nothing.
*/
#ifdef CONFIG_STM32F7_SAI_DMA
@@ -1434,8 +1444,8 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
flags = enter_critical_section();
sq_addlast((sq_entry_t *)bfcontainer, &priv->pend);
- /* Then start the next transfer. If there is already a transfer in progress,
- * then this will do nothing.
+ /* Then start the next transfer. If there is already a transfer in
+ * progress, then this will do nothing.
*/
#ifdef CONFIG_STM32F7_SAI_DMA
@@ -1545,7 +1555,8 @@ static struct sai_buffer_s *sai_buf_allocate(struct stm32f7_sai_s *priv)
*
****************************************************************************/
-static void sai_buf_free(struct stm32f7_sai_s *priv, struct sai_buffer_s *bfcontainer)
+static void sai_buf_free(struct stm32f7_sai_s *priv,
+ struct sai_buffer_s *bfcontainer)
{
irqstate_t flags;
@@ -1628,7 +1639,8 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv)
/* Configure the data width */
- sai_datawidth((struct i2s_dev_s *)priv, CONFIG_STM32F7_SAI_DEFAULT_DATALEN);
+ sai_datawidth((struct i2s_dev_s *)priv,
+ CONFIG_STM32F7_SAI_DEFAULT_DATALEN);
#ifdef CONFIG_STM32F7_SAI_DMA
/* Get DMA channel */
@@ -1639,19 +1651,23 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv)
sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN);
#endif
- sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen);
+ sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK,
+ priv->syncen);
sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV);
- sai_modifyreg(priv, STM32F7_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF);
+ sai_modifyreg(priv, STM32F7_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK,
+ SAI_CR2_FTH_1QF);
sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET,
SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF,
- SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB);
+ SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW |
+ SAI_FRCR_FSOFF_BFB);
sai_modifyreg(priv, STM32F7_SAI_SLOTR_OFFSET,
SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK,
- SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1);
+ SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 |
+ SAI_SLOTR_SLOTEN_1);
sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN);
sai_dump_regs(priv, "After initialization");
diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c
index 96d08e9..da6cd64 100644
--- a/arch/arm/src/stm32h7/stm32_qspi.c
+++ b/arch/arm/src/stm32h7/stm32_qspi.c
@@ -1315,7 +1315,9 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
}
else
{
- /* XXX if it's NOT auto stop; something needs to happen here; a callback? */
+ /* XXX if it's NOT auto stop; something needs to happen here;
+ * a callback?
+ */
}
}
@@ -1446,7 +1448,9 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
if (priv->result == -EBUSY)
{
- /* Save the result of the transfer if no error was previously reported */
+ /* Save the result of the transfer if no error was previously
+ * reported
+ */
if (isr & DMA_STREAM_TCIF_BIT)
{
@@ -1707,7 +1711,9 @@ static int qspi_receive_blocking(struct stm32h7_qspidev_s *priv,
qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR_OFFSET);
- /* Use Abort to clear the busy flag, and ditch any extra bytes in fifo */
+ /* Use Abort to clear the busy flag, and ditch any extra bytes in
+ * fifo
+ */
qspi_abort(priv);
}
@@ -1873,7 +1879,9 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
qspi_abort(priv);
qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0);
- /* Check if the requested frequency is the same as the frequency selection */
+ /* Check if the requested frequency is the same as the frequency
+ * selection
+ */
if (priv->frequency == frequency)
{
@@ -2339,7 +2347,9 @@ static int qspi_memory(struct qspi_dev_s *dev,
{
/* polling mode */
- /* Set up the Communications Configuration Register as per command info */
+ /* Set up the Communications Configuration Register as per command
+ * info
+ */
qspi_ccrconfig(priv, &xctn,
QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR :
diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c
index 3c6937f..168c97c 100644
--- a/arch/arm/src/stm32l4/stm32l4_qspi.c
+++ b/arch/arm/src/stm32l4/stm32l4_qspi.c
@@ -74,7 +74,7 @@
* Pre-processor Definitions
****************************************************************************/
- /* QSPI memory synchronization */
+/* QSPI memory synchronization */
#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0)
@@ -207,17 +207,17 @@ struct stm32l4_qspidev_s
#endif
#ifdef CONFIG_STM32L4_QSPI_REGDEBUG
- bool wrlast; /* Last was a write */
- uint32_t addresslast; /* Last address */
- uint32_t valuelast; /* Last value */
- int ntimes; /* Number of times */
+ bool wrlast; /* Last was a write */
+ uint32_t addresslast; /* Last address */
+ uint32_t valuelast; /* Last value */
+ int ntimes; /* Number of times */
#endif
};
/* The QSPI transaction specification
*
- * This is mostly the values of the CCR and DLR, AR, ABR, broken out into a C struct
- * since these fields need to be considered at various phases of the
+ * This is mostly the values of the CCR and DLR, AR, ABR, broken out into a C
+ * struct since these fields need to be considered at various phases of the
* transaction processing activity.
*/
@@ -265,11 +265,12 @@ static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr,
static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv,
unsigned int offset);
-static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, uint32_t value,
- unsigned int offset);
+static inline void qspi_putreg(struct stm32l4_qspidev_s *priv,
+ uint32_t value, unsigned int offset);
#ifdef CONFIG_DEBUG_SPI_INFO
-static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg);
+static void qspi_dumpregs(struct stm32l4_qspidev_s *priv,
+ const char *msg);
#else
# define qspi_dumpregs(priv,msg)
#endif
@@ -310,7 +311,8 @@ static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv);
/* QSPI methods */
static int qspi_lock(struct qspi_dev_s *dev, bool lock);
-static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency);
+static uint32_t qspi_setfrequency(struct qspi_dev_s *dev,
+ uint32_t frequency);
static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode);
static void qspi_setbits(struct qspi_dev_s *dev, int nbits);
static int qspi_command(struct qspi_dev_s *dev,
@@ -382,8 +384,8 @@ static struct stm32l4_qspidev_s g_qspi0dev =
****************************************************************************/
#ifdef CONFIG_STM32L4_QSPI_REGDEBUG
-static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, uint32_t value,
- uint32_t address)
+static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr,
+ uint32_t value, uint32_t address)
{
if (wr == priv->wrlast && /* Same kind of access? */
value == priv->valuelast && /* Same value? */
@@ -451,8 +453,8 @@ static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv,
*
****************************************************************************/
-static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, uint32_t value,
- unsigned int offset)
+static inline void qspi_putreg(struct stm32l4_qspidev_s *priv,
+ uint32_t value, unsigned int offset)
{
uint32_t address = priv->base + offset;
@@ -489,7 +491,8 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg)
#if 0
/* This extra verbose output may be helpful in some cases; you'll need
- * to make sure your syslog is large enough to accommodate the extra output.
+ * to make sure your syslog is large enough to accommodate the extra
+ * output.
*/
regval = getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET); /* Control Register */
@@ -612,7 +615,8 @@ static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv)
{
/* Put contents of register samples into a known state */
- memset(priv->dmaregs, 0xff, DMA_NSAMPLES * sizeof(struct stm32l4_dmaregs_s));
+ memset(priv->dmaregs, 0xff,
+ DMA_NSAMPLES * sizeof(struct stm32l4_dmaregs_s));
/* Then get the initial samples */
@@ -713,8 +717,10 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn,
if (QSPICMD_ISDATA(cmdinfo->flags))
{
- spiinfo(" %s Data:\n", QSPICMD_ISWRITE(cmdinfo->flags) ? "Write" : "Read");
- spiinfo(" buffer/length: %p/%d\n", cmdinfo->buffer, cmdinfo->buflen);
+ spiinfo(" %s Data:\n",
+ QSPICMD_ISWRITE(cmdinfo->flags) ? "Write" : "Read");
+ spiinfo(" buffer/length: %p/%d\n",
+ cmdinfo->buffer, cmdinfo->buflen);
}
#endif
@@ -797,7 +803,8 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn,
}
#if defined(STM32L4_QSPI_INTERRUPTS)
- xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD;
+ xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR
+ : CCR_FMODE_INDRD;
xctn->disposition = - EIO;
xctn->idxnow = 0;
#endif
@@ -831,7 +838,8 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn,
spiinfo(" cmd: %04x\n", meminfo->cmd);
spiinfo(" address/length: %08lx/%d\n",
(unsigned long)meminfo->addr, meminfo->addrlen);
- spiinfo(" %s Data:\n", QSPIMEM_ISWRITE(meminfo->flags) ? "Write" : "Read");
+ spiinfo(" %s Data:\n",
+ QSPIMEM_ISWRITE(meminfo->flags) ? "Write" : "Read");
spiinfo(" buffer/length: %p/%d\n", meminfo->buffer, meminfo->buflen);
#endif
@@ -926,7 +934,8 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn,
xctn->isddr = 0;
#if defined(STM32L4_QSPI_INTERRUPTS)
- xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD;
+ xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR
+ : CCR_FMODE_INDRD;
xctn->disposition = - EIO;
xctn->idxnow = 0;
#endif
@@ -957,11 +966,13 @@ static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv,
if (polarity)
{
- while (!((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) & mask));
+ while (!((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET))
+ & mask));
}
else
{
- while (((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) & mask));
+ while (((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET))
+ & mask));
}
}
@@ -1014,7 +1025,7 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv,
if (CCR_DMODE_NONE != xctn->datamode && CCR_FMODE_MEMMAP != fctn)
{
- qspi_putreg(priv, xctn->datasize-1, STM32L4_QUADSPI_DLR_OFFSET);
+ qspi_putreg(priv, xctn->datasize - 1, STM32L4_QUADSPI_DLR_OFFSET);
}
/* If we have alternate bytes, stick them in now */
@@ -1086,7 +1097,9 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
{
/* Write data until we have no more or have no place to put it */
- while ((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF)
+ while ((regval = qspi_getreg(&g_qspi0dev,
+ STM32L4_QUADSPI_SR_OFFSET))
+ & QSPI_SR_FTF)
{
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
{
@@ -1106,11 +1119,14 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
{
/* Read data until we have no more or have no place to put it */
- while ((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF)
+ while ((regval = qspi_getreg(&g_qspi0dev,
+ STM32L4_QUADSPI_SR_OFFSET))
+ & QSPI_SR_FTF)
{
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
{
- ((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow] =
+ ((uint8_t *)g_qspi0dev.xctn->buffer)
+ [g_qspi0dev.xctn->idxnow] =
*(volatile uint8_t *)datareg;
++g_qspi0dev.xctn->idxnow;
}
@@ -1127,56 +1143,60 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
/* Is it 'Transfer Complete'? */
if ((status & QSPI_SR_TCF) && (cr & QSPI_CR_TCIE))
- {
- /* Acknowledge interrupt */
+ {
+ /* Acknowledge interrupt */
- qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR);
+ qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR);
- /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
+ /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer
+ * complete Interrupts
+ */
- regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET);
- regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE);
- qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
+ regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET);
+ regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE);
+ qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
- /* Do the last bit of read if needed */
+ /* Do the last bit of read if needed */
- if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD)
- {
- volatile uint32_t *datareg = (volatile uint32_t *)
- (g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
+ if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD)
+ {
+ volatile uint32_t *datareg = (volatile uint32_t *)
+ (g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
- /* Read any remaining data */
+ /* Read any remaining data */
- while (((regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET)) &
- QSPI_SR_FLEVEL_MASK) != 0)
- {
- if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
- {
- ((uint8_t *)g_qspi0dev.xctn->buffer)[g_qspi0dev.xctn->idxnow] =
- *(volatile uint8_t *)datareg;
- ++g_qspi0dev.xctn->idxnow;
- }
- else
- {
- /* No room at the inn */
+ while (((regval = qspi_getreg(&g_qspi0dev,
+ STM32L4_QUADSPI_SR_OFFSET)) &
+ QSPI_SR_FLEVEL_MASK) != 0)
+ {
+ if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
+ {
+ ((uint8_t *)g_qspi0dev.xctn->buffer)
+ [g_qspi0dev.xctn->idxnow] =
+ *(volatile uint8_t *)datareg;
+ ++g_qspi0dev.xctn->idxnow;
+ }
+ else
+ {
+ /* No room at the inn */
- break;
- }
- }
- }
+ break;
+ }
+ }
+ }
- /* Use 'abort' to ditch any stray fifo contents and clear BUSY flag */
+ /* Use 'abort' to ditch any stray fifo contents and clear BUSY flag */
- qspi_abort(&g_qspi0dev);
+ qspi_abort(&g_qspi0dev);
- /* Set success status */
+ /* Set success status */
- g_qspi0dev.xctn->disposition = OK;
+ g_qspi0dev.xctn->disposition = OK;
- /* Signal complete */
+ /* Signal complete */
- nxsem_post(&g_qspi0dev.op_sem);
- }
+ nxsem_post(&g_qspi0dev.op_sem);
+ }
/* Is it 'Status Match'? */
@@ -1206,7 +1226,9 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
}
else
{
- /* XXX if it's NOT auto stop; something needs to happen here; a callback? */
+ /* XXX if it's NOT auto stop; something needs to happen here;
+ * a callback?
+ */
}
}
@@ -1221,7 +1243,8 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
/* Disable all the QSPI Interrupts */
regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET);
- regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE);
+ regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE |
+ QSPI_CR_TOIE);
qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
/* Set error status; 'transfer error' means that, in 'indirect mode',
@@ -1336,7 +1359,9 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
if (priv->result == -EBUSY)
{
- /* Save the result of the transfer if no error was previously reported */
+ /* Save the result of the transfer if no error was previously
+ * reported
+ */
if (isr & DMA_CHAN_TCIF_BIT)
{
@@ -1416,7 +1441,8 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
DMA_CCR_MINC);
}
- stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv, STM32L4_QUADSPI_DR_OFFSET),
+ stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv,
+ STM32L4_QUADSPI_DR_OFFSET),
(uint32_t)meminfo->buffer, meminfo->buflen, dmaflags);
qspi_dma_sample(priv, DMA_AFTER_SETUP);
@@ -1581,7 +1607,9 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv,
qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR);
- /* Use Abort to clear the busy flag, and ditch any extra bytes in fifo */
+ /* Use Abort to clear the busy flag, and ditch any extra bytes in
+ * fifo
+ */
qspi_abort(priv);
}
@@ -1735,7 +1763,9 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
qspi_abort(priv);
qspi_waitstatusflags(priv, QSPI_SR_BUSY, 0);
- /* Check if the requested frequency is the same as the frequency selection */
+ /* Check if the requested frequency is the same as the frequency
+ * selection
+ */
if (priv->frequency == frequency)
{
@@ -1750,8 +1780,8 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
* QSCK frequency = STL32L4_QSPI_CLOCK / prescaler, or
* prescaler = STL32L4_QSPI_CLOCK / frequency
*
- * Where prescaler can have the range 1 to 256 and the STM32L4_QUADSPI_CR_OFFSET
- * register field holds prescaler - 1.
+ * Where prescaler can have the range 1 to 256 and the
+ * STM32L4_QUADSPI_CR_OFFSET register field holds prescaler - 1.
* NOTE that a "ceiling" type of calculation is performed.
* 'frequency' is treated as a not-to-exceed value.
*/
@@ -1928,9 +1958,9 @@ static int qspi_command(struct qspi_dev_s *dev,
ret = qspi_setupxctnfromcmd(&xctn, cmdinfo);
if (OK != ret)
- {
- return ret;
- }
+ {
+ return ret;
+ }
/* Prepare for transaction */
@@ -1965,8 +1995,8 @@ static int qspi_command(struct qspi_dev_s *dev,
qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDWR);
- /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete'
- * interrupts.
+ /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer
+ * Complete' interrupts.
*/
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
@@ -1990,8 +2020,8 @@ static int qspi_command(struct qspi_dev_s *dev,
qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET);
- /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete'
- * interrupts
+ /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer
+ * Complete' interrupts
*/
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
@@ -2038,7 +2068,8 @@ static int qspi_command(struct qspi_dev_s *dev,
/* Set up the Communications Configuration Register as per command info */
qspi_ccrconfig(priv, &xctn,
- QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD);
+ QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR
+ : CCR_FMODE_INDRD);
/* That may be it, unless there is also data to transfer */
@@ -2109,9 +2140,9 @@ static int qspi_memory(struct qspi_dev_s *dev,
ret = qspi_setupxctnfrommem(&xctn, meminfo);
if (OK != ret)
- {
- return ret;
- }
+ {
+ return ret;
+ }
/* Prepare for transaction */
@@ -2201,10 +2232,13 @@ static int qspi_memory(struct qspi_dev_s *dev,
{
/* polling mode */
- /* Set up the Communications Configuration Register as per command info */
+ /* Set up the Communications Configuration Register as per command
+ * info
+ */
qspi_ccrconfig(priv, &xctn,
- QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD);
+ QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR
+ : CCR_FMODE_INDRD);
/* Transfer data */
@@ -2234,7 +2268,8 @@ static int qspi_memory(struct qspi_dev_s *dev,
/* Set up the Communications Configuration Register as per command info */
qspi_ccrconfig(priv, &xctn,
- QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD);
+ QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR
+ : CCR_FMODE_INDRD);
/* Transfer data */
@@ -2344,12 +2379,14 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv)
/* Disable all interrupt sources for starters */
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
- regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE);
+ regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE |
+ QSPI_CR_TOIE);
/* Configure QSPI FIFO Threshold */
regval &= ~(QSPI_CR_FTHRES_MASK);
- regval |= ((CONFIG_STM32L4_QSPI_FIFO_THESHOLD-1) << QSPI_CR_FTHRES_SHIFT);
+ regval |= ((CONFIG_STM32L4_QSPI_FIFO_THESHOLD - 1) <<
+ QSPI_CR_FTHRES_SHIFT);
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
/* Wait till BUSY flag reset */
@@ -2369,17 +2406,18 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv)
regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR_OFFSET);
regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK);
regval |= (0x00);
- regval |= ((CONFIG_STM32L4_QSPI_CSHT-1) << QSPI_DCR_CSHT_SHIFT);
+ regval |= ((CONFIG_STM32L4_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT);
if (0 != CONFIG_STM32L4_QSPI_FLASH_SIZE)
{
- unsigned int nSize = CONFIG_STM32L4_QSPI_FLASH_SIZE;
- int nLog2Size = 31;
- while (!(nSize & 0x80000000))
+ unsigned int nsize = CONFIG_STM32L4_QSPI_FLASH_SIZE;
+ int nlog2size = 31;
+ while (!(nsize & 0x80000000))
{
- --nLog2Size;
- nSize <<= 1;
+ --nlog2size;
+ nsize <<= 1;
}
- regval |= ((nLog2Size-1) << QSPI_DCR_FSIZE_SHIFT);
+
+ regval |= ((nlog2size - 1) << QSPI_DCR_FSIZE_SHIFT);
}
qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR_OFFSET);
diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c
index 878c463..83911a4 100644
--- a/arch/arm/src/stm32l4/stm32l4_sai.c
+++ b/arch/arm/src/stm32l4/stm32l4_sai.c
@@ -523,7 +523,9 @@ static void sai_timeout(int argc, uint32_t arg, ...)
stm32l4_dmastop(priv->dma);
#endif
- /* Then schedule completion of the transfer to occur on the worker thread. */
+ /* Then schedule completion of the transfer to occur on the worker
+ * thread.
+ */
sai_schedule(priv, -ETIMEDOUT);
}
diff --git a/arch/mips/src/pic32mz/pic32mz-spi.c b/arch/mips/src/pic32mz/pic32mz-spi.c
index 7955ed5..f0e9e63 100644
--- a/arch/mips/src/pic32mz/pic32mz-spi.c
+++ b/arch/mips/src/pic32mz/pic32mz-spi.c
@@ -1226,7 +1226,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t actual;
uint32_t regval;
- /* Check if the requested frequency is the same as the frequency selection */
+ /* Check if the requested frequency is the same as the frequency
+ * selection
+ */
if (priv->frequency == frequency)
{
@@ -1575,7 +1577,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
if (priv->nbits > 8)
{
- /* 16-bit transfer (2 bytes)*/
+ /* 16-bit transfer (2 bytes) */
width = 2;
}
@@ -1999,7 +2001,9 @@ FAR struct spi_dev_s *pic32mz_spibus_initialize(int port)
up_disable_irq(priv->config->txirq);
#endif
- /* Stop and reset the SPI module by clearing the ON bit in the CON register. */
+ /* Stop and reset the SPI module by clearing the ON bit in the CON
+ * register.
+ */
spi_putreg(priv, PIC32MZ_SPI_CON_OFFSET, 0);
diff --git a/arch/sim/src/sim/up_ioexpander.c b/arch/sim/src/sim/up_ioexpander.c
index d505b4f..0371c89 100644
--- a/arch/sim/src/sim/up_ioexpander.c
+++ b/arch/sim/src/sim/up_ioexpander.c
@@ -382,14 +382,15 @@ static int sim_writepin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
* Name: sim_readpin
*
* Description:
- * Read the actual PIN level. This can be different from the last value written
- * to this pin. Required.
+ * Read the actual PIN level. This can be different from the last value
+ * written to this pin. Required.
*
* Input Parameters:
* dev - Device-specific state data
* pin - The index of the pin
* valptr - Pointer to a buffer where the pin level is stored. Usually TRUE
- * if the pin is high, except if OPTION_INVERT has been set on this pin.
+ * if the pin is high, except if OPTION_INVERT has been set on
+ * this pin.
*
* Returned Value:
* 0 on success, else a negative error code
@@ -403,7 +404,8 @@ static int sim_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin,
ioe_pinset_t inval;
bool retval;
- DEBUGASSERT(priv != NULL && pin < CONFIG_IOEXPANDER_NPINS && value != NULL);
+ DEBUGASSERT(priv != NULL && pin < CONFIG_IOEXPANDER_NPINS &&
+ value != NULL);
gpioinfo("pin=%u\n", pin);
@@ -607,7 +609,8 @@ static int sim_detach(FAR struct ioexpander_dev_s *dev, FAR void *handle)
DEBUGASSERT(priv != NULL && cb != NULL);
DEBUGASSERT((uintptr_t)cb >= (uintptr_t)&priv->cb[0] &&
- (uintptr_t)cb <= (uintptr_t)&priv->cb[CONFIG_SIM_INT_NCALLBACKS - 1]);
+ (uintptr_t)cb <= (uintptr_t)&priv->cb[
+ CONFIG_SIM_INT_NCALLBACKS - 1]);
UNUSED(priv);
cb->pinset = 0;
@@ -806,7 +809,9 @@ static void sim_interrupt(int argc, wdparm_t arg1, ...)
if (work_available(&priv->work))
{
- /* Schedule interrupt related work on the high priority worker thread. */
+ /* Schedule interrupt related work on the high priority worker
+ * thread.
+ */
work_queue(HPWORK, &priv->work, sim_interrupt_work,
(FAR void *)priv, 0);
@@ -821,8 +826,8 @@ static void sim_interrupt(int argc, wdparm_t arg1, ...)
* Name: sim_ioexpander_initialize
*
* Description:
- * Instantiate and configure the I/O Expander device driver to use the provided
- * I2C device instance.
+ * Instantiate and configure the I/O Expander device driver to use the
+ * provided I2C device instance.
*
* Input Parameters:
* i2c - An I2C driver instance
diff --git a/boards/arm/samv7/samv71-xult/src/sam_ili9488.c b/boards/arm/samv7/samv71-xult/src/sam_ili9488.c
index 7480fec..fb14b9f 100644
--- a/boards/arm/samv7/samv71-xult/src/sam_ili9488.c
+++ b/boards/arm/samv7/samv71-xult/src/sam_ili9488.c
@@ -603,7 +603,9 @@ static int sam_lcd_get(FAR struct sam_dev_s *priv, uint8_t cmd,
ret = sam_sendcmd(priv, cmd);
- /* If the command was sent successfully, then receive any accompanying data */
+ /* If the command was sent successfully, then receive any accompanying
+ * data
+ */
if (ret == OK && buflen > 0)
{
diff --git a/drivers/ioexpander/pcf8574.c b/drivers/ioexpander/pcf8574.c
index 8fca41c..4824f50 100644
--- a/drivers/ioexpander/pcf8574.c
+++ b/drivers/ioexpander/pcf8574.c
@@ -1040,7 +1040,9 @@ static void pcf8574_interrupt(FAR void *arg)
priv->config->enable(priv->config, false);
- /* Schedule interrupt related work on the high priority worker thread. */
+ /* Schedule interrupt related work on the high priority worker
+ * thread.
+ */
work_queue(HPWORK, &priv->work, pcf8574_irqworker,
(FAR void *)priv, 0);
@@ -1084,7 +1086,9 @@ static void pcf8574_poll_expiry(int argc, wdparm_t arg1, ...)
priv->config->enable(priv->config, false);
- /* Schedule interrupt related work on the high priority worker thread. */
+ /* Schedule interrupt related work on the high priority worker
+ * thread.
+ */
work_queue(HPWORK, &priv->work, pcf8574_irqworker,
(FAR void *)priv, 0);
diff --git a/drivers/ioexpander/tca64xx.c b/drivers/ioexpander/tca64xx.c
index 87d058a..5de8763 100644
--- a/drivers/ioexpander/tca64xx.c
+++ b/drivers/ioexpander/tca64xx.c
@@ -1313,7 +1313,9 @@ static void tca64_interrupt(FAR void *arg)
priv->config->enable(priv->config, false);
- /* Schedule interrupt related work on the high priority worker thread. */
+ /* Schedule interrupt related work on the high priority worker
+ * thread.
+ */
work_queue(HPWORK, &priv->work, tca64_irqworker,
(FAR void *)priv, 0);
@@ -1357,7 +1359,9 @@ static void tca64_poll_expiry(int argc, wdparm_t arg1, ...)
priv->config->enable(priv->config, false);
- /* Schedule interrupt related work on the high priority worker thread. */
+ /* Schedule interrupt related work on the high priority worker
+ * thread.
+ */
work_queue(HPWORK, &priv->work, tca64_irqworker,
(FAR void *)priv, 0);
diff --git a/sched/timer/timer_settime.c b/sched/timer/timer_settime.c
index 92201d7..b9669e3 100644
--- a/sched/timer/timer_settime.c
+++ b/sched/timer/timer_settime.c
@@ -288,7 +288,9 @@ int timer_settime(timer_t timerid, int flags,
nxsig_cancel_notification(&timer->pt_work);
- /* If the it_value member of value is zero, the timer will not be re-armed */
+ /* If the it_value member of value is zero, the timer will not be
+ * re-armed
+ */
if (value->it_value.tv_sec <= 0 && value->it_value.tv_nsec <= 0)
{
[incubator-nuttx] 03/05: Remove type casting to wdentry_t (boards/)
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 2ca9681b00d509b0f95884504f8504297863b859
Author: Nakamura, Yuuichi <Yu...@sony.com>
AuthorDate: Mon Apr 6 23:01:51 2020 +0900
Remove type casting to wdentry_t (boards/)
---
boards/arm/samv7/samv71-xult/src/sam_ili9488.c | 6 +++---
boards/sim/sim/sim/src/sim_gpio.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/boards/arm/samv7/samv71-xult/src/sam_ili9488.c b/boards/arm/samv7/samv71-xult/src/sam_ili9488.c
index be0009e..7480fec 100644
--- a/boards/arm/samv7/samv71-xult/src/sam_ili9488.c
+++ b/boards/arm/samv7/samv71-xult/src/sam_ili9488.c
@@ -382,7 +382,7 @@ static void sam_lcd_dump(struct sam_dev_s *priv);
#endif
static void sam_lcd_endwait(struct sam_dev_s *priv, int result);
-static void sam_lcd_dmatimeout(int argc, uint32_t arg);
+static void sam_lcd_dmatimeout(int argc, uint32_t arg, ...);
static int sam_lcd_dmawait(FAR struct sam_dev_s *priv, uint32_t timeout);
static void sam_lcd_dmacallback(DMA_HANDLE handle, void *arg, int result);
static int sam_lcd_txtransfer(FAR struct sam_dev_s *priv,
@@ -939,7 +939,7 @@ static void sam_lcd_endwait(struct sam_dev_s *priv, int result)
*
****************************************************************************/
-static void sam_lcd_dmatimeout(int argc, uint32_t arg)
+static void sam_lcd_dmatimeout(int argc, uint32_t arg, ...)
{
struct sam_dev_s *priv = (struct sam_dev_s *)arg;
@@ -981,7 +981,7 @@ static int sam_lcd_dmawait(FAR struct sam_dev_s *priv, uint32_t timeout)
/* Started ... setup the timeout */
- ret = wd_start(priv->dmadog, timeout, (wdentry_t)sam_lcd_dmatimeout,
+ ret = wd_start(priv->dmadog, timeout, sam_lcd_dmatimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/boards/sim/sim/sim/src/sim_gpio.c b/boards/sim/sim/sim/src/sim_gpio.c
index b6ba6d8..8ebe213 100644
--- a/boards/sim/sim/sim/src/sim_gpio.c
+++ b/boards/sim/sim/sim/src/sim_gpio.c
@@ -202,7 +202,7 @@ static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable)
{
gpioinfo("Start 1 second timer\n");
wd_start(simgpint->wdog, SEC2TICK(1),
- (wdentry_t)sim_interrupt, 1, (wdparm_t)dev);
+ sim_interrupt, 1, (wdparm_t)dev);
}
}
else
[incubator-nuttx] 04/05: Remove type casting to wdentry_t (arch/)
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit e264484c163287d12ba8e6d48e2209312d5cf9a1
Author: Nakamura, Yuuichi <Yu...@sony.com>
AuthorDate: Tue Apr 7 00:10:56 2020 +0900
Remove type casting to wdentry_t (arch/)
---
arch/arm/src/cxd56xx/cxd56_rtc.c | 4 ++--
arch/arm/src/cxd56xx/cxd56_sdhci.c | 6 +++---
arch/arm/src/imxrt/imxrt_usdhc.c | 6 +++---
arch/arm/src/kinetis/kinetis_sdhc.c | 6 +++---
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c | 6 +++---
arch/arm/src/lpc43xx/lpc43_sdmmc.c | 6 +++---
arch/arm/src/lpc54xx/lpc54_sdmmc.c | 6 +++---
arch/arm/src/sam34/sam_hsmci.c | 6 +++---
arch/arm/src/sam34/sam_spi.c | 4 ++--
arch/arm/src/sama5/sam_hsmci.c | 6 +++---
arch/arm/src/sama5/sam_spi.c | 4 ++--
arch/arm/src/sama5/sam_ssc.c | 12 ++++++------
arch/arm/src/samv7/sam_hsmci.c | 6 +++---
arch/arm/src/samv7/sam_qspi.c | 4 ++--
arch/arm/src/samv7/sam_spi.c | 4 ++--
arch/arm/src/samv7/sam_ssc.c | 12 ++++++------
arch/arm/src/stm32/stm32_i2s.c | 12 ++++++------
arch/arm/src/stm32/stm32_sdio.c | 6 +++---
arch/arm/src/stm32f7/stm32_qspi.c | 4 ++--
arch/arm/src/stm32f7/stm32_sai.c | 4 ++--
arch/arm/src/stm32f7/stm32_sdmmc.c | 6 +++---
arch/arm/src/stm32h7/stm32_qspi.c | 4 ++--
arch/arm/src/stm32h7/stm32_sdmmc.c | 6 +++---
arch/arm/src/stm32l4/stm32l4_qspi.c | 4 ++--
arch/arm/src/stm32l4/stm32l4_sai.c | 4 ++--
arch/arm/src/stm32l4/stm32l4_sdmmc.c | 6 +++---
arch/arm/src/xmc4/xmc4_spi.c | 4 ++--
arch/mips/src/pic32mz/pic32mz-spi.c | 6 +++---
arch/sim/src/sim/up_ioexpander.c | 4 ++--
29 files changed, 84 insertions(+), 84 deletions(-)
diff --git a/arch/arm/src/cxd56xx/cxd56_rtc.c b/arch/arm/src/cxd56xx/cxd56_rtc.c
index 3339d57..c0fd245 100644
--- a/arch/arm/src/cxd56xx/cxd56_rtc.c
+++ b/arch/arm/src/cxd56xx/cxd56_rtc.c
@@ -256,7 +256,7 @@ static int cxd56_rtc_interrupt(int irq, FAR void *context, FAR void *arg)
*
************************************************************************************/
-static void cxd56_rtc_initialize(int argc, uint32_t arg)
+static void cxd56_rtc_initialize(int argc, uint32_t arg, ...)
{
struct timespec ts;
#ifdef CONFIG_CXD56_RTC_LATEINIT
@@ -285,7 +285,7 @@ static void cxd56_rtc_initialize(int argc, uint32_t arg)
rtcinfo("retry count: %d\n", s_retry);
if (OK == wd_start(s_wdog, MSEC2TICK(RTC_CLOCK_CHECK_INTERVAL),
- (wdentry_t)cxd56_rtc_initialize, 1, (wdparm_t)NULL))
+ cxd56_rtc_initialize, 1, (wdparm_t)NULL))
{
/* Again, this function is called recursively */
diff --git a/arch/arm/src/cxd56xx/cxd56_sdhci.c b/arch/arm/src/cxd56xx/cxd56_sdhci.c
index 07dbdf7..6c60c08 100644
--- a/arch/arm/src/cxd56xx/cxd56_sdhci.c
+++ b/arch/arm/src/cxd56xx/cxd56_sdhci.c
@@ -392,7 +392,7 @@ static void cxd56_dataconfig(struct cxd56_sdiodev_s *priv, bool bwrite,
static void cxd56_datadisable(void);
static void cxd56_transmit(struct cxd56_sdiodev_s *priv);
static void cxd56_receive(struct cxd56_sdiodev_s *priv);
-static void cxd56_eventtimeout(int argc, uint32_t arg);
+static void cxd56_eventtimeout(int argc, uint32_t arg, ...);
static void cxd56_endwait(struct cxd56_sdiodev_s *priv,
sdio_eventset_t wkupevent);
static void cxd56_endtransfer(struct cxd56_sdiodev_s *priv,
@@ -1021,7 +1021,7 @@ static void cxd56_receive(struct cxd56_sdiodev_s *priv)
*
****************************************************************************/
-static void cxd56_eventtimeout(int argc, uint32_t arg)
+static void cxd56_eventtimeout(int argc, uint32_t arg, ...)
{
struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)arg;
@@ -2651,7 +2651,7 @@ static sdio_eventset_t cxd56_sdio_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t)cxd56_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, cxd56_eventtimeout,
1, (uint32_t)priv);
if (ret != OK)
{
diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c
index 7d3889d..a799ef2 100644
--- a/arch/arm/src/imxrt/imxrt_usdhc.c
+++ b/arch/arm/src/imxrt/imxrt_usdhc.c
@@ -288,7 +288,7 @@ static void imxrt_transmit(struct imxrt_dev_s *priv);
static void imxrt_receive(struct imxrt_dev_s *priv);
#endif
-static void imxrt_eventtimeout(int argc, uint32_t arg);
+static void imxrt_eventtimeout(int argc, uint32_t arg, ...);
static void imxrt_endwait(struct imxrt_dev_s *priv,
sdio_eventset_t wkupevent);
static void imxrt_endtransfer(struct imxrt_dev_s *priv,
@@ -1017,7 +1017,7 @@ static void imxrt_receive(struct imxrt_dev_s *priv)
*
****************************************************************************/
-static void imxrt_eventtimeout(int argc, uint32_t arg)
+static void imxrt_eventtimeout(int argc, uint32_t arg, ...)
{
struct imxrt_dev_s *priv = (struct imxrt_dev_s *)arg;
@@ -2708,7 +2708,7 @@ static sdio_eventset_t imxrt_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t) imxrt_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, imxrt_eventtimeout,
1, (uint32_t) priv);
if (ret < 0)
diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c
index f2d1cfe..7bfec1a 100644
--- a/arch/arm/src/kinetis/kinetis_sdhc.c
+++ b/arch/arm/src/kinetis/kinetis_sdhc.c
@@ -264,7 +264,7 @@ static void kinetis_datadisable(void);
static void kinetis_transmit(struct kinetis_dev_s *priv);
static void kinetis_receive(struct kinetis_dev_s *priv);
#endif
-static void kinetis_eventtimeout(int argc, uint32_t arg);
+static void kinetis_eventtimeout(int argc, uint32_t arg, ...);
static void kinetis_endwait(struct kinetis_dev_s *priv,
sdio_eventset_t wkupevent);
static void kinetis_endtransfer(struct kinetis_dev_s *priv,
@@ -934,7 +934,7 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
*
****************************************************************************/
-static void kinetis_eventtimeout(int argc, uint32_t arg)
+static void kinetis_eventtimeout(int argc, uint32_t arg, ...)
{
struct kinetis_dev_s *priv = (struct kinetis_dev_s *)arg;
@@ -2507,7 +2507,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
- (wdentry_t)kinetis_eventtimeout,
+ kinetis_eventtimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
index 17f02b0..9cff4e0 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
@@ -347,7 +347,7 @@ static void lpc17_40_dataconfig(uint32_t timeout, uint32_t dlen,
static void lpc17_40_datadisable(void);
static void lpc17_40_sendfifo(struct lpc17_40_dev_s *priv);
static void lpc17_40_recvfifo(struct lpc17_40_dev_s *priv);
-static void lpc17_40_eventtimeout(int argc, uint32_t arg);
+static void lpc17_40_eventtimeout(int argc, uint32_t arg, ...);
static void lpc17_40_endwait(struct lpc17_40_dev_s *priv,
sdio_eventset_t wkupevent);
static void lpc17_40_endtransfer(struct lpc17_40_dev_s *priv,
@@ -1088,7 +1088,7 @@ static void lpc17_40_recvfifo(struct lpc17_40_dev_s *priv)
*
****************************************************************************/
-static void lpc17_40_eventtimeout(int argc, uint32_t arg)
+static void lpc17_40_eventtimeout(int argc, uint32_t arg, ...)
{
struct lpc17_40_dev_s *priv = (struct lpc17_40_dev_s *)arg;
@@ -2345,7 +2345,7 @@ static sdio_eventset_t lpc17_40_eventwait(FAR struct sdio_dev_s *dev,
delay = MSEC2TICK(timeout);
ret = wd_start(priv->waitwdog, delay,
- (wdentry_t) lpc17_40_eventtimeout,
+ lpc17_40_eventtimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.c b/arch/arm/src/lpc43xx/lpc43_sdmmc.c
index 5517e50..bb1c7ff 100644
--- a/arch/arm/src/lpc43xx/lpc43_sdmmc.c
+++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.c
@@ -291,7 +291,7 @@ static void lpc43_config_dmaints(struct lpc43_dev_s *priv, uint32_t xfrmask,
/* Data Transfer Helpers ****************************************************/
-static void lpc43_eventtimeout(int argc, uint32_t arg);
+static void lpc43_eventtimeout(int argc, uint32_t arg, ...);
static void lpc43_endwait(struct lpc43_dev_s *priv,
sdio_eventset_t wkupevent);
static void lpc43_endtransfer(struct lpc43_dev_s *priv,
@@ -838,7 +838,7 @@ static void lpc43_config_dmaints(struct lpc43_dev_s *priv, uint32_t xfrmask,
*
****************************************************************************/
-static void lpc43_eventtimeout(int argc, uint32_t arg)
+static void lpc43_eventtimeout(int argc, uint32_t arg, ...)
{
struct lpc43_dev_s *priv = (struct lpc43_dev_s *)arg;
@@ -2313,7 +2313,7 @@ static sdio_eventset_t lpc43_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t)lpc43_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, lpc43_eventtimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.c b/arch/arm/src/lpc54xx/lpc54_sdmmc.c
index d072c4c..a1eb178 100644
--- a/arch/arm/src/lpc54xx/lpc54_sdmmc.c
+++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.c
@@ -295,7 +295,7 @@ static void lpc54_config_dmaints(struct lpc54_dev_s *priv, uint32_t xfrmask,
/* Data Transfer Helpers ****************************************************/
-static void lpc54_eventtimeout(int argc, uint32_t arg);
+static void lpc54_eventtimeout(int argc, uint32_t arg, ...);
static void lpc54_endwait(struct lpc54_dev_s *priv,
sdio_eventset_t wkupevent);
static void lpc54_endtransfer(struct lpc54_dev_s *priv,
@@ -838,7 +838,7 @@ static void lpc54_config_dmaints(struct lpc54_dev_s *priv, uint32_t xfrmask,
*
****************************************************************************/
-static void lpc54_eventtimeout(int argc, uint32_t arg)
+static void lpc54_eventtimeout(int argc, uint32_t arg, ...)
{
struct lpc54_dev_s *priv = (struct lpc54_dev_s *)arg;
@@ -2313,7 +2313,7 @@ static sdio_eventset_t lpc54_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t)lpc54_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, lpc54_eventtimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c
index 624f208..411d6f0 100644
--- a/arch/arm/src/sam34/sam_hsmci.c
+++ b/arch/arm/src/sam34/sam_hsmci.c
@@ -448,7 +448,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result);
/* Data Transfer Helpers ****************************************************/
-static void sam_eventtimeout(int argc, uint32_t arg);
+static void sam_eventtimeout(int argc, uint32_t arg, ...);
static void sam_endwait(struct sam_dev_s *priv, sdio_eventset_t wkupevent);
static void sam_endtransfer(struct sam_dev_s *priv,
sdio_eventset_t wkupevent);
@@ -1088,7 +1088,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result)
*
****************************************************************************/
-static void sam_eventtimeout(int argc, uint32_t arg)
+static void sam_eventtimeout(int argc, uint32_t arg, ...)
{
struct sam_dev_s *priv = (struct sam_dev_s *)arg;
@@ -2328,7 +2328,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t)sam_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, sam_eventtimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c
index bcc9e61..52d3fa5 100644
--- a/arch/arm/src/sam34/sam_spi.c
+++ b/arch/arm/src/sam34/sam_spi.c
@@ -735,7 +735,7 @@ static void spi_dma_sampledone(struct sam_spics_s *spics)
****************************************************************************/
#ifdef CONFIG_SAM34_SPI_DMA
-static void spi_dmatimeout(int argc, uint32_t arg)
+static void spi_dmatimeout(int argc, uint32_t arg, ...)
{
struct sam_spics_s *spics = (struct sam_spics_s *)arg;
DEBUGASSERT(spics != NULL);
@@ -1585,7 +1585,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Start (or re-start) the watchdog timeout */
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
- (wdentry_t)spi_dmatimeout, 1, (uint32_t)spics);
+ spi_dmatimeout, 1, (uint32_t)spics);
if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c
index c5df899..42d356a 100644
--- a/arch/arm/src/sama5/sam_hsmci.c
+++ b/arch/arm/src/sama5/sam_hsmci.c
@@ -527,7 +527,7 @@ static inline uintptr_t hsmci_physregaddr(struct sam_dev_s *priv,
/* Data Transfer Helpers ****************************************************/
-static void sam_eventtimeout(int argc, uint32_t arg);
+static void sam_eventtimeout(int argc, uint32_t arg, ...);
static void sam_endwait(struct sam_dev_s *priv, sdio_eventset_t wkupevent);
static void sam_endtransfer(struct sam_dev_s *priv,
sdio_eventset_t wkupevent);
@@ -1310,7 +1310,7 @@ static inline uintptr_t hsmci_physregaddr(struct sam_dev_s *priv,
*
****************************************************************************/
-static void sam_eventtimeout(int argc, uint32_t arg)
+static void sam_eventtimeout(int argc, uint32_t arg, ...)
{
struct sam_dev_s *priv = (struct sam_dev_s *)arg;
@@ -2755,7 +2755,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
}
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t)sam_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, sam_eventtimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c
index 33fbdbe..2f80d99 100644
--- a/arch/arm/src/sama5/sam_spi.c
+++ b/arch/arm/src/sama5/sam_spi.c
@@ -723,7 +723,7 @@ static void spi_dma_sampledone(struct sam_spics_s *spics)
****************************************************************************/
#ifdef CONFIG_SAMA5_SPI_DMA
-static void spi_dmatimeout(int argc, uint32_t arg)
+static void spi_dmatimeout(int argc, uint32_t arg, ...)
{
struct sam_spics_s *spics = (struct sam_spics_s *)arg;
DEBUGASSERT(spics != NULL);
@@ -1511,7 +1511,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Start (or re-start) the watchdog timeout */
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
- (wdentry_t)spi_dmatimeout, 1, (uint32_t)spics);
+ spi_dmatimeout, 1, (uint32_t)spics);
if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c
index 96e1f0f..962bb2f 100644
--- a/arch/arm/src/sama5/sam_ssc.c
+++ b/arch/arm/src/sama5/sam_ssc.c
@@ -578,14 +578,14 @@ static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result);
#endif
#ifdef SSC_HAVE_RX
-static void ssc_rxdma_timeout(int argc, uint32_t arg);
+static void ssc_rxdma_timeout(int argc, uint32_t arg, ...);
static int ssc_rxdma_setup(struct sam_ssc_s *priv);
static void ssc_rx_worker(void *arg);
static void ssc_rx_schedule(struct sam_ssc_s *priv, int result);
static void ssc_rxdma_callback(DMA_HANDLE handle, void *arg, int result);
#endif
#ifdef SSC_HAVE_TX
-static void ssc_txdma_timeout(int argc, uint32_t arg);
+static void ssc_txdma_timeout(int argc, uint32_t arg, ...);
static int ssc_txdma_setup(struct sam_ssc_s *priv);
static void ssc_tx_worker(void *arg);
static void ssc_tx_schedule(struct sam_ssc_s *priv, int result);
@@ -1193,7 +1193,7 @@ static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result)
****************************************************************************/
#ifdef SSC_HAVE_RX
-static void ssc_rxdma_timeout(int argc, uint32_t arg)
+static void ssc_rxdma_timeout(int argc, uint32_t arg, ...)
{
struct sam_ssc_s *priv = (struct sam_ssc_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -1340,7 +1340,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
if (!notimeout)
{
- ret = wd_start(priv->rx.dog, timeout, (wdentry_t)ssc_rxdma_timeout,
+ ret = wd_start(priv->rx.dog, timeout, ssc_rxdma_timeout,
1, (uint32_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@@ -1605,7 +1605,7 @@ static void ssc_rxdma_callback(DMA_HANDLE handle, void *arg, int result)
****************************************************************************/
#ifdef SSC_HAVE_TX
-static void ssc_txdma_timeout(int argc, uint32_t arg)
+static void ssc_txdma_timeout(int argc, uint32_t arg, ...)
{
struct sam_ssc_s *priv = (struct sam_ssc_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -1753,7 +1753,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
if (!notimeout)
{
- ret = wd_start(priv->tx.dog, timeout, (wdentry_t)ssc_txdma_timeout,
+ ret = wd_start(priv->tx.dog, timeout, ssc_txdma_timeout,
1, (uint32_t)priv);
/* Check if we have successfully started the watchdog timer. Note
diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c
index e2322ea..efdfbb5 100644
--- a/arch/arm/src/samv7/sam_hsmci.c
+++ b/arch/arm/src/samv7/sam_hsmci.c
@@ -462,7 +462,7 @@ static inline uintptr_t hsmci_regaddr(struct sam_dev_s *priv,
/* Data Transfer Helpers ****************************************************/
-static void sam_eventtimeout(int argc, uint32_t arg);
+static void sam_eventtimeout(int argc, uint32_t arg, ...);
static void sam_endwait(struct sam_dev_s *priv, sdio_eventset_t wkupevent);
static void sam_endtransfer(struct sam_dev_s *priv,
sdio_eventset_t wkupevent);
@@ -1246,7 +1246,7 @@ static inline uintptr_t hsmci_regaddr(struct sam_dev_s *priv,
*
****************************************************************************/
-static void sam_eventtimeout(int argc, uint32_t arg)
+static void sam_eventtimeout(int argc, uint32_t arg, ...)
{
struct sam_dev_s *priv = (struct sam_dev_s *)arg;
@@ -2803,7 +2803,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
}
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t)sam_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, sam_eventtimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c
index 6819190..ca2bb14 100644
--- a/arch/arm/src/samv7/sam_qspi.c
+++ b/arch/arm/src/samv7/sam_qspi.c
@@ -585,7 +585,7 @@ static void qspi_dma_sampledone(struct sam_qspidev_s *priv)
****************************************************************************/
#ifdef CONFIG_SAMV7_QSPI_DMA
-static void qspi_dma_timeout(int argc, uint32_t arg)
+static void qspi_dma_timeout(int argc, uint32_t arg, ...)
{
struct sam_qspidev_s *priv = (struct sam_qspidev_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -883,7 +883,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
/* Start (or re-start) the watchdog timeout */
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
- (wdentry_t)qspi_dma_timeout, 1, (uint32_t)priv);
+ qspi_dma_timeout, 1, (uint32_t)priv);
if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c
index 57cef53..1e06f0e 100644
--- a/arch/arm/src/samv7/sam_spi.c
+++ b/arch/arm/src/samv7/sam_spi.c
@@ -762,7 +762,7 @@ static void spi_dma_sampledone(struct sam_spics_s *spics)
****************************************************************************/
#ifdef CONFIG_SAMV7_SPI_DMA
-static void spi_dmatimeout(int argc, uint32_t arg)
+static void spi_dmatimeout(int argc, uint32_t arg, ...)
{
struct sam_spics_s *spics = (struct sam_spics_s *)arg;
DEBUGASSERT(spics != NULL);
@@ -1858,7 +1858,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Start (or re-start) the watchdog timeout */
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
- (wdentry_t)spi_dmatimeout, 1, (uint32_t)spics);
+ spi_dmatimeout, 1, (uint32_t)spics);
if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c
index ce9c255..a9b01ba 100644
--- a/arch/arm/src/samv7/sam_ssc.c
+++ b/arch/arm/src/samv7/sam_ssc.c
@@ -553,14 +553,14 @@ static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result);
#endif
#ifdef SSC_HAVE_RX
-static void ssc_rxdma_timeout(int argc, uint32_t arg);
+static void ssc_rxdma_timeout(int argc, uint32_t arg, ...);
static int ssc_rxdma_setup(struct sam_ssc_s *priv);
static void ssc_rx_worker(void *arg);
static void ssc_rx_schedule(struct sam_ssc_s *priv, int result);
static void ssc_rxdma_callback(DMA_HANDLE handle, void *arg, int result);
#endif
#ifdef SSC_HAVE_TX
-static void ssc_txdma_timeout(int argc, uint32_t arg);
+static void ssc_txdma_timeout(int argc, uint32_t arg, ...);
static int ssc_txdma_setup(struct sam_ssc_s *priv);
static void ssc_tx_worker(void *arg);
static void ssc_tx_schedule(struct sam_ssc_s *priv, int result);
@@ -1168,7 +1168,7 @@ static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result)
****************************************************************************/
#ifdef SSC_HAVE_RX
-static void ssc_rxdma_timeout(int argc, uint32_t arg)
+static void ssc_rxdma_timeout(int argc, uint32_t arg, ...)
{
struct sam_ssc_s *priv = (struct sam_ssc_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -1317,7 +1317,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
if (!notimeout)
{
- ret = wd_start(priv->rx.dog, timeout, (wdentry_t)ssc_rxdma_timeout,
+ ret = wd_start(priv->rx.dog, timeout, ssc_rxdma_timeout,
1, (uint32_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@@ -1582,7 +1582,7 @@ static void ssc_rxdma_callback(DMA_HANDLE handle, void *arg, int result)
****************************************************************************/
#ifdef SSC_HAVE_TX
-static void ssc_txdma_timeout(int argc, uint32_t arg)
+static void ssc_txdma_timeout(int argc, uint32_t arg, ...)
{
struct sam_ssc_s *priv = (struct sam_ssc_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -1734,7 +1734,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
if (!notimeout)
{
- ret = wd_start(priv->tx.dog, timeout, (wdentry_t)ssc_txdma_timeout,
+ ret = wd_start(priv->tx.dog, timeout, ssc_txdma_timeout,
1, (uint32_t)priv);
/* Check if we have successfully started the watchdog timer. Note
diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/stm32/stm32_i2s.c
index b4d2f01..71f9350 100644
--- a/arch/arm/src/stm32/stm32_i2s.c
+++ b/arch/arm/src/stm32/stm32_i2s.c
@@ -411,7 +411,7 @@ static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result);
#endif
#ifdef I2S_HAVE_RX
-static void i2s_rxdma_timeout(int argc, uint32_t arg);
+static void i2s_rxdma_timeout(int argc, uint32_t arg, ...);
static int i2s_rxdma_setup(struct stm32_i2s_s *priv);
static void i2s_rx_worker(void *arg);
static void i2s_rx_schedule(struct stm32_i2s_s *priv, int result);
@@ -419,7 +419,7 @@ static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result,
void *arg);
#endif
#ifdef I2S_HAVE_TX
-static void i2s_txdma_timeout(int argc, uint32_t arg);
+static void i2s_txdma_timeout(int argc, uint32_t arg, ...);
static int i2s_txdma_setup(struct stm32_i2s_s *priv);
static void i2s_tx_worker(void *arg);
static void i2s_tx_schedule(struct stm32_i2s_s *priv, int result);
@@ -959,7 +959,7 @@ static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result)
****************************************************************************/
#ifdef I2S_HAVE_RX
-static void i2s_rxdma_timeout(int argc, uint32_t arg)
+static void i2s_rxdma_timeout(int argc, uint32_t arg, ...)
{
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -1095,7 +1095,7 @@ static int i2s_rxdma_setup(struct stm32_i2s_s *priv)
if (!notimeout)
{
- ret = wd_start(priv->rx.dog, timeout, (wdentry_t)i2s_rxdma_timeout,
+ ret = wd_start(priv->rx.dog, timeout, i2s_rxdma_timeout,
1, (uint32_t)priv);
/* Check if we have successfully started the watchdog timer. Note
@@ -1355,7 +1355,7 @@ static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result, void *arg)
****************************************************************************/
#ifdef I2S_HAVE_TX
-static void i2s_txdma_timeout(int argc, uint32_t arg)
+static void i2s_txdma_timeout(int argc, uint32_t arg, ...)
{
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -1491,7 +1491,7 @@ static int i2s_txdma_setup(struct stm32_i2s_s *priv)
if (!notimeout)
{
- ret = wd_start(priv->tx.dog, timeout, (wdentry_t)i2s_txdma_timeout,
+ ret = wd_start(priv->tx.dog, timeout, i2s_txdma_timeout,
1, (uint32_t)priv);
/* Check if we have successfully started the watchdog timer. Note
diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c
index 343a58d..f25df1d 100644
--- a/arch/arm/src/stm32/stm32_sdio.c
+++ b/arch/arm/src/stm32/stm32_sdio.c
@@ -416,7 +416,7 @@ static void stm32_dataconfig(uint32_t timeout, uint32_t dlen,
static void stm32_datadisable(void);
static void stm32_sendfifo(struct stm32_dev_s *priv);
static void stm32_recvfifo(struct stm32_dev_s *priv);
-static void stm32_eventtimeout(int argc, uint32_t arg);
+static void stm32_eventtimeout(int argc, uint32_t arg, ...);
static void stm32_endwait(struct stm32_dev_s *priv,
sdio_eventset_t wkupevent);
static void stm32_endtransfer(struct stm32_dev_s *priv,
@@ -1201,7 +1201,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv)
*
****************************************************************************/
-static void stm32_eventtimeout(int argc, uint32_t arg)
+static void stm32_eventtimeout(int argc, uint32_t arg, ...)
{
struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
@@ -2545,7 +2545,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t)stm32_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, stm32_eventtimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c
index 62460ab..5e42fa7 100644
--- a/arch/arm/src/stm32f7/stm32_qspi.c
+++ b/arch/arm/src/stm32f7/stm32_qspi.c
@@ -1337,7 +1337,7 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
*
****************************************************************************/
-static void qspi_dma_timeout(int argc, uint32_t arg)
+static void qspi_dma_timeout(int argc, uint32_t arg, ...)
{
struct stm32f7_qspidev_s *priv = (struct stm32f7_qspidev_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -1511,7 +1511,7 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv,
/* Start (or re-start) the watchdog timeout */
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
- (wdentry_t)qspi_dma_timeout, 1, (uint32_t)priv);
+ qspi_dma_timeout, 1, (uint32_t)priv);
if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c
index c75264b..05e60fc 100644
--- a/arch/arm/src/stm32f7/stm32_sai.c
+++ b/arch/arm/src/stm32f7/stm32_sai.c
@@ -835,7 +835,7 @@ static void sai_mckdivider(struct stm32f7_sai_s *priv)
*
****************************************************************************/
-static void sai_timeout(int argc, uint32_t arg)
+static void sai_timeout(int argc, uint32_t arg, ...)
{
struct stm32f7_sai_s *priv = (struct stm32f7_sai_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -978,7 +978,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv)
if (bfcontainer->timeout > 0)
{
- ret = wd_start(priv->dog, bfcontainer->timeout, (wdentry_t)sai_timeout,
+ ret = wd_start(priv->dog, bfcontainer->timeout, sai_timeout,
1, (uint32_t)priv);
/* Check if we have successfully started the watchdog timer. Note
diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c
index a053f61..42afca7 100644
--- a/arch/arm/src/stm32f7/stm32_sdmmc.c
+++ b/arch/arm/src/stm32f7/stm32_sdmmc.c
@@ -509,7 +509,7 @@ static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout,
static void stm32_datadisable(struct stm32_dev_s *priv);
static void stm32_sendfifo(struct stm32_dev_s *priv);
static void stm32_recvfifo(struct stm32_dev_s *priv);
-static void stm32_eventtimeout(int argc, uint32_t arg);
+static void stm32_eventtimeout(int argc, uint32_t arg, ...);
static void stm32_endwait(struct stm32_dev_s *priv,
sdio_eventset_t wkupevent);
static void stm32_endtransfer(struct stm32_dev_s *priv,
@@ -1452,7 +1452,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv)
*
****************************************************************************/
-static void stm32_eventtimeout(int argc, uint32_t arg)
+static void stm32_eventtimeout(int argc, uint32_t arg, ...)
{
struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
@@ -2827,7 +2827,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t)stm32_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, stm32_eventtimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c
index 05c1be5..96d08e9 100644
--- a/arch/arm/src/stm32h7/stm32_qspi.c
+++ b/arch/arm/src/stm32h7/stm32_qspi.c
@@ -1391,7 +1391,7 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
*
****************************************************************************/
-static void qspi_dma_timeout(int argc, uint32_t arg)
+static void qspi_dma_timeout(int argc, uint32_t arg, ...)
{
struct stm32h7_qspidev_s *priv = (struct stm32h7_qspidev_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -1565,7 +1565,7 @@ static int qspi_memory_dma(struct stm32h7_qspidev_s *priv,
/* Start (or re-start) the watchdog timeout */
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
- (wdentry_t)qspi_dma_timeout, 1, (uint32_t)priv);
+ qspi_dma_timeout, 1, (uint32_t)priv);
if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c
index dcaab8b..65a24f7 100644
--- a/arch/arm/src/stm32h7/stm32_sdmmc.c
+++ b/arch/arm/src/stm32h7/stm32_sdmmc.c
@@ -430,7 +430,7 @@ static void stm32_datadisable(struct stm32_dev_s *priv);
static void stm32_sendfifo(struct stm32_dev_s *priv);
static void stm32_recvfifo(struct stm32_dev_s *priv);
#endif
-static void stm32_eventtimeout(int argc, uint32_t arg);
+static void stm32_eventtimeout(int argc, uint32_t arg, ...);
static void stm32_endwait(struct stm32_dev_s *priv,
sdio_eventset_t wkupevent);
static void stm32_endtransfer(struct stm32_dev_s *priv,
@@ -1275,7 +1275,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv)
*
****************************************************************************/
-static void stm32_eventtimeout(int argc, uint32_t arg)
+static void stm32_eventtimeout(int argc, uint32_t arg, ...)
{
struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
@@ -2729,7 +2729,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t)stm32_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, stm32_eventtimeout,
1, (uint32_t)priv);
if (ret < OK)
{
diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c
index e9775d6..3c6937f 100644
--- a/arch/arm/src/stm32l4/stm32l4_qspi.c
+++ b/arch/arm/src/stm32l4/stm32l4_qspi.c
@@ -1281,7 +1281,7 @@ static int qspi0_interrupt(int irq, void *context, FAR void *arg)
*
****************************************************************************/
-static void qspi_dma_timeout(int argc, uint32_t arg)
+static void qspi_dma_timeout(int argc, uint32_t arg, ...)
{
struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -1452,7 +1452,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
/* Start (or re-start) the watchdog timeout */
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
- (wdentry_t)qspi_dma_timeout, 1, (uint32_t)priv);
+ qspi_dma_timeout, 1, (uint32_t)priv);
if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c
index b99190a..878c463 100644
--- a/arch/arm/src/stm32l4/stm32l4_sai.c
+++ b/arch/arm/src/stm32l4/stm32l4_sai.c
@@ -512,7 +512,7 @@ static void sai_mckdivider(struct stm32l4_sai_s *priv)
*
****************************************************************************/
-static void sai_timeout(int argc, uint32_t arg)
+static void sai_timeout(int argc, uint32_t arg, ...)
{
struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -655,7 +655,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv)
if (bfcontainer->timeout > 0)
{
- ret = wd_start(priv->dog, bfcontainer->timeout, (wdentry_t)sai_timeout,
+ ret = wd_start(priv->dog, bfcontainer->timeout, sai_timeout,
1, (uint32_t)priv);
/* Check if we have successfully started the watchdog timer. Note
diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c
index a382df5..ada401e 100644
--- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c
+++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c
@@ -446,7 +446,7 @@ static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout,
static void stm32_datadisable(struct stm32_dev_s *priv);
static void stm32_sendfifo(struct stm32_dev_s *priv);
static void stm32_recvfifo(struct stm32_dev_s *priv);
-static void stm32_eventtimeout(int argc, uint32_t arg);
+static void stm32_eventtimeout(int argc, uint32_t arg, ...);
static void stm32_endwait(struct stm32_dev_s *priv,
sdio_eventset_t wkupevent);
static void stm32_endtransfer(struct stm32_dev_s *priv,
@@ -1332,7 +1332,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv)
*
****************************************************************************/
-static void stm32_eventtimeout(int argc, uint32_t arg)
+static void stm32_eventtimeout(int argc, uint32_t arg, ...)
{
struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
@@ -2631,7 +2631,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
/* Start the watchdog timer */
delay = MSEC2TICK(timeout);
- ret = wd_start(priv->waitwdog, delay, (wdentry_t)stm32_eventtimeout,
+ ret = wd_start(priv->waitwdog, delay, stm32_eventtimeout,
1, (uint32_t)priv);
if (ret < 0)
{
diff --git a/arch/arm/src/xmc4/xmc4_spi.c b/arch/arm/src/xmc4/xmc4_spi.c
index b0a6c38..95b5cba 100644
--- a/arch/arm/src/xmc4/xmc4_spi.c
+++ b/arch/arm/src/xmc4/xmc4_spi.c
@@ -911,7 +911,7 @@ static void spi_dma_sampledone(struct xmc4_spics_s *spics)
****************************************************************************/
#ifdef CONFIG_XMC4_SPI_DMA
-static void spi_dmatimeout(int argc, uint32_t arg)
+static void spi_dmatimeout(int argc, uint32_t arg, ...)
{
struct xmc4_spics_s *spics = (struct xmc4_spics_s *)arg;
@@ -1661,7 +1661,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Start (or re-start) the watchdog timeout */
ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS,
- (wdentry_t)spi_dmatimeout, 1, (uint32_t)spics);
+ spi_dmatimeout, 1, (uint32_t)spics);
if (ret != OK)
{
spierr("ERROR: wd_start failed: %d\n", ret);
diff --git a/arch/mips/src/pic32mz/pic32mz-spi.c b/arch/mips/src/pic32mz/pic32mz-spi.c
index f1dc419..7955ed5 100644
--- a/arch/mips/src/pic32mz/pic32mz-spi.c
+++ b/arch/mips/src/pic32mz/pic32mz-spi.c
@@ -218,7 +218,7 @@ static void spi_dma_sampledone(FAR struct pic32mz_dev_s *priv);
# endif
static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg);
static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t status, void *arg);
-static void spi_dmatimeout(int argc, uint32_t arg);
+static void spi_dmatimeout(int argc, uint32_t arg, ...);
#endif
/* SPI methods */
@@ -995,7 +995,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t status, void *arg)
****************************************************************************/
#ifdef CONFIG_PIC32MZ_SPI_DMA
-static void spi_dmatimeout(int argc, uint32_t arg)
+static void spi_dmatimeout(int argc, uint32_t arg, ...)
{
struct pic32mz_dev_s *priv = (struct pic32mz_dev_s *)arg;
DEBUGASSERT(priv != NULL);
@@ -1773,7 +1773,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
/* Start (or re-start) the watchdog timeout */
ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS,
- (wdentry_t)spi_dmatimeout, 1, (uint32_t)priv);
+ spi_dmatimeout, 1, (uint32_t)priv);
if (ret < 0)
{
spierr("ERROR: wd_start failed: %d\n", ret);
diff --git a/arch/sim/src/sim/up_ioexpander.c b/arch/sim/src/sim/up_ioexpander.c
index e7fd40b..d505b4f 100644
--- a/arch/sim/src/sim/up_ioexpander.c
+++ b/arch/sim/src/sim/up_ioexpander.c
@@ -767,7 +767,7 @@ static void sim_interrupt_work(void *arg)
/* Re-start the poll timer */
- ret = wd_start(priv->wdog, SIM_POLLDELAY, (wdentry_t)sim_interrupt,
+ ret = wd_start(priv->wdog, SIM_POLLDELAY, sim_interrupt,
1, (wdparm_t)priv);
if (ret < 0)
{
@@ -854,7 +854,7 @@ FAR struct ioexpander_dev_s *sim_ioexpander_initialize(void)
priv->wdog = wd_create();
DEBUGASSERT(priv->wdog != NULL);
- ret = wd_start(priv->wdog, SIM_POLLDELAY, (wdentry_t)sim_interrupt,
+ ret = wd_start(priv->wdog, SIM_POLLDELAY, sim_interrupt,
1, (wdparm_t)priv);
if (ret < 0)
{