You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by xi...@apache.org on 2024/10/01 04:10:15 UTC
(nuttx) 03/03: arm64: fix use arch-timer in SMP
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit c039ea77baf03ffc14b7a3bf053f88fa25fbb3b9
Author: hujun5 <hu...@xiaomi.com>
AuthorDate: Sun Sep 8 14:08:16 2024 +0800
arm64: fix use arch-timer in SMP
reason:
only one timer will be effective at a time.
Signed-off-by: hujun5 <hu...@xiaomi.com>
---
arch/arm64/src/common/arm64_arch_timer.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/src/common/arm64_arch_timer.c b/arch/arm64/src/common/arm64_arch_timer.c
index 9f72decc2e..8e0a606e68 100644
--- a/arch/arm64/src/common/arm64_arch_timer.c
+++ b/arch/arm64/src/common/arm64_arch_timer.c
@@ -70,8 +70,11 @@ struct arm64_oneshot_lowerhalf_s
void *arg; /* Argument that is passed to the handler */
uint64_t cycle_per_tick; /* cycle per tick */
oneshot_callback_t callback; /* Internal handler that receives callback */
- bool running; /* True: timer is running */
bool init[CONFIG_SMP_NCPUS]; /* True: timer is init */
+
+ /* which cpu timer is running, -1 indicate timer stoppd */
+
+ int running;
};
/****************************************************************************
@@ -157,7 +160,7 @@ static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
arm64_arch_timer_set_irq_mask(true);
- if (priv->callback && priv->running)
+ if (priv->callback && priv->running == this_cpu())
{
/* Then perform the callback */
@@ -228,7 +231,7 @@ static int arm64_tick_cancel(struct oneshot_lowerhalf_s *lower,
/* Disable int */
- priv->running = false;
+ priv->running = -1;
arm64_arch_timer_set_irq_mask(true);
return OK;
@@ -281,7 +284,7 @@ static int arm64_tick_start(struct oneshot_lowerhalf_s *lower,
priv->init[this_cpu()] = true;
}
- priv->running = true;
+ priv->running = this_cpu();
next_cycle =
arm64_arch_timer_count() / priv->cycle_per_tick * priv->cycle_per_tick +
@@ -374,6 +377,7 @@ struct oneshot_lowerhalf_s *arm64_oneshot_initialize(void)
/* Initialize the lower-half driver structure */
priv->lh.ops = &g_oneshot_ops;
+ priv->running = -1;
priv->cycle_per_tick = arm64_arch_timer_get_cntfrq() / TICK_PER_SEC;
tmrinfo("cycle_per_tick %" PRIu64 "\n", priv->cycle_per_tick);