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Posted to commits@mahout.apache.org by ra...@apache.org on 2017/02/07 04:01:17 UTC
mahout git commit: MAHOUT-1923 Propagate cacheHint in distributed qr
decomp closes apache/mahout#276
Repository: mahout
Updated Branches:
refs/heads/master 771339c82 -> 7a3617b33
MAHOUT-1923 Propagate cacheHint in distributed qr decomp closes apache/mahout#276
Project: http://git-wip-us.apache.org/repos/asf/mahout/repo
Commit: http://git-wip-us.apache.org/repos/asf/mahout/commit/7a3617b3
Tree: http://git-wip-us.apache.org/repos/asf/mahout/tree/7a3617b3
Diff: http://git-wip-us.apache.org/repos/asf/mahout/diff/7a3617b3
Branch: refs/heads/master
Commit: 7a3617b33eb397b0d2f44e3a1456f266196c1282
Parents: 771339c
Author: rawkintrevo <tr...@gmail.com>
Authored: Mon Feb 6 22:01:06 2017 -0600
Committer: rawkintrevo <tr...@gmail.com>
Committed: Mon Feb 6 22:01:06 2017 -0600
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.../main/scala/org/apache/mahout/math/decompositions/DQR.scala | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
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http://git-wip-us.apache.org/repos/asf/mahout/blob/7a3617b3/math-scala/src/main/scala/org/apache/mahout/math/decompositions/DQR.scala
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diff --git a/math-scala/src/main/scala/org/apache/mahout/math/decompositions/DQR.scala b/math-scala/src/main/scala/org/apache/mahout/math/decompositions/DQR.scala
index 4a7681a..389eba0 100644
--- a/math-scala/src/main/scala/org/apache/mahout/math/decompositions/DQR.scala
+++ b/math-scala/src/main/scala/org/apache/mahout/math/decompositions/DQR.scala
@@ -37,7 +37,9 @@ object DQR {
* It also guarantees that Q is partitioned exactly the same way (and in same key-order) as A, so
* their RDD should be able to zip successfully.
*/
- def dqrThin[K](drmA: DrmLike[K], checkRankDeficiency: Boolean = true): (DrmLike[K], Matrix) = {
+ def dqrThin[K](drmA: DrmLike[K],
+ checkRankDeficiency: Boolean = true,
+ cacheHint: CacheHint.CacheHint = CacheHint.MEMORY_ONLY): (DrmLike[K], Matrix) = {
// Some mapBlock() calls need it
implicit val ktag = drmA.keyClassTag
@@ -47,7 +49,7 @@ object DQR {
implicit val ctx = drmA.context
- val AtA = (drmA.t %*% drmA).checkpoint()
+ val AtA = (drmA.t %*% drmA).checkpoint(cacheHint)
val inCoreAtA = AtA.collect
trace("A'A=\n%s\n".format(inCoreAtA))