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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/07/25 15:46:39 UTC
[incubator-nuttx] branch master updated (fc84813b0a -> 8eae3bb5ff)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
from fc84813b0a driver/sensor: add calibrate interface for sensor driver.
new 69986fad84 stm32f0l0g0/hardware/stm32_spi.h: remove unused definitions
new af4d65416a stm32f0l0g0/stm32_spi.c: add missing SPI mode config and fix ifdef
new 351c9dc837 stm32f0l0g0/stm32_spi.c: remove unused spi_readbyte function
new 8eae3bb5ff stm32f0l0g0/stm32_spi.c: fix receiving data for half duplex mode
The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h | 36 ------
arch/arm/src/stm32f0l0g0/stm32_spi.c | 156 +++++++++++++++++---------
2 files changed, 106 insertions(+), 86 deletions(-)
[incubator-nuttx] 03/04: stm32f0l0g0/stm32_spi.c: remove unused spi_readbyte function
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 351c9dc837eee680a5f5fa2f9910b53cdf507db0
Author: raiden00pl <ra...@railab.me>
AuthorDate: Wed Jul 20 16:52:45 2022 +0200
stm32f0l0g0/stm32_spi.c: remove unused spi_readbyte function
---
arch/arm/src/stm32f0l0g0/stm32_spi.c | 39 ------------------------------------
1 file changed, 39 deletions(-)
diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c
index a814dbc3c6..10fa825275 100644
--- a/arch/arm/src/stm32f0l0g0/stm32_spi.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c
@@ -509,45 +509,6 @@ static inline uint16_t spi_readword(struct stm32_spidev_s *priv)
return spi_getreg(priv, STM32_SPI_DR_OFFSET);
}
-/****************************************************************************
- * Name: spi_readbyte
- *
- * Description:
- * Read one byte from SPI
- *
- * Input Parameters:
- * priv - Device-specific state data
- *
- * Returned Value:
- * Byte as read
- *
- ****************************************************************************/
-
-static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv)
-{
- /* Can't receive in tx only mode */
-
- if (priv->config == SIMPLEX_TX)
- {
- return 0;
- }
-
- if (priv->config == HALF_DUPLEX)
- {
- /* Disable output for half-duplex mode */
-
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_BIDIOE);
- }
-
- /* Wait until the receive buffer is not empty */
-
- while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0);
-
- /* Then return the received byte */
-
- return spi_getreg8(priv, STM32_SPI_DR_OFFSET);
-}
-
/****************************************************************************
* Name: spi_writeword
*
[incubator-nuttx] 04/04: stm32f0l0g0/stm32_spi.c: fix receiving data for half duplex mode
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 8eae3bb5ff1270bd1d092baccf8236e63e4c651e
Author: raiden00pl <ra...@railab.me>
AuthorDate: Fri Jul 22 10:32:10 2022 +0200
stm32f0l0g0/stm32_spi.c: fix receiving data for half duplex mode
---
arch/arm/src/stm32f0l0g0/stm32_spi.c | 119 +++++++++++++++++++++++++++++++----
1 file changed, 106 insertions(+), 13 deletions(-)
diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c
index 10fa825275..eab982771d 100644
--- a/arch/arm/src/stm32f0l0g0/stm32_spi.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c
@@ -184,6 +184,8 @@ struct stm32_spidev_s
struct pm_callback_s pm_cb; /* PM callbacks */
#endif
enum spi_config_e config; /* full/half duplex, simplex transmit/read only */
+ bool rx_now; /* Half duplex only: receiving data now */
+ bool rx_mode; /* Half duplex only: SPI_CR1_BIDIOE bit status */
};
/****************************************************************************
@@ -196,6 +198,7 @@ static inline uint16_t spi_getreg(struct stm32_spidev_s *priv,
uint8_t offset);
static inline void spi_putreg(struct stm32_spidev_s *priv,
uint8_t offset, uint16_t value);
+static inline void spi_rx_mode(struct stm32_spidev_s *priv, bool enable);
static inline uint16_t spi_readword(struct stm32_spidev_s *priv);
static inline void spi_writeword(struct stm32_spidev_s *priv,
uint16_t byte);
@@ -430,6 +433,62 @@ static inline void spi_putreg(struct stm32_spidev_s *priv,
putreg16(value, priv->spibase + offset);
}
+/****************************************************************************
+ * Name: spi_rx_mode
+ *
+ * Description:
+ * Activate SPI RX or SPI TX for the half-duplex mode
+ *
+ ****************************************************************************/
+
+static inline void spi_rx_mode(struct stm32_spidev_s *priv, bool enable)
+{
+ if (enable)
+ {
+ /* Enable RX */
+
+ if (!priv->rx_mode)
+ {
+ /* Disable SPI */
+
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
+
+ /* Disable output for half-duplex mode - SPI starts to
+ * automatically output clocks.
+ */
+
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_BIDIOE);
+
+ /* Enable SPI */
+
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+
+ priv->rx_mode = true;
+ }
+ }
+ else
+ {
+ /* Enable TX */
+
+ if (priv->rx_mode)
+ {
+ /* Disable SPI */
+
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
+
+ /* Enable TX output */
+
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_BIDIOE, 0);
+
+ /* Enable SPI */
+
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+
+ priv->rx_mode = false;
+ }
+ }
+}
+
/****************************************************************************
* Name: spi_getreg8
*
@@ -495,15 +554,18 @@ static inline uint16_t spi_readword(struct stm32_spidev_s *priv)
if (priv->config == HALF_DUPLEX)
{
- /* Disable output for half-duplex mode */
-
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_BIDIOE);
+ spi_rx_mode(priv, true);
}
/* Wait until the receive buffer is not empty */
while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0);
+ if (priv->config == HALF_DUPLEX)
+ {
+ spi_rx_mode(priv, false);
+ }
+
/* Then return the received byte */
return spi_getreg(priv, STM32_SPI_DR_OFFSET);
@@ -536,9 +598,7 @@ static inline void spi_writeword(struct stm32_spidev_s *priv,
if (priv->config == HALF_DUPLEX)
{
- /* Enable output for half-duplex mode */
-
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_BIDIOE, 0);
+ spi_rx_mode(priv, false);
}
/* Wait until the transmit buffer is empty */
@@ -576,6 +636,13 @@ static inline void spi_writeword(struct stm32_spidev_s *priv,
{
spi_putreg(priv, STM32_SPI_DR_OFFSET, word);
}
+
+ if (priv->config == HALF_DUPLEX)
+ {
+ /* Wait for data transfer to be completed */
+
+ while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_BSY) != 0);
+ }
}
/****************************************************************************
@@ -1289,12 +1356,32 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
uint32_t regval;
- uint32_t ret;
+ uint32_t ret = 0;
DEBUGASSERT(priv && priv->spibase);
- spi_writeword(priv, (uint16_t)(wd & 0xffff));
- ret = (uint32_t)spi_readword(priv);
+ if (priv->config != HALF_DUPLEX)
+ {
+ spi_writeword(priv, (uint16_t)(wd & 0xffff));
+ ret = (uint32_t)spi_readword(priv);
+ }
+ else
+ {
+ /* In half duplex we must send data and receive data in separate
+ * spi_send() calls.
+ */
+
+ if (!priv->rx_now)
+ {
+ spi_writeword(priv, (uint16_t)(wd & 0xffff));
+ }
+ else
+ {
+ ret = (uint32_t)spi_readword(priv);
+
+ priv->rx_now = false;
+ }
+ }
/* Check and clear any error flags (Reading from the SR clears the error
* flags)
@@ -1361,10 +1448,12 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
if (src)
{
word = *src++;
+ priv->rx_now = false;
}
else
{
word = 0xffff;
+ priv->rx_now = true;
}
/* Exchange one word */
@@ -1394,10 +1483,12 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
if (src)
{
word = *src++;
+ priv->rx_now = false;
}
else
{
word = 0xff;
+ priv->rx_now = true;
}
/* Exchange one word */
@@ -1746,8 +1837,9 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
setbits |= SPI_CR1_RXONLY;
break;
case HALF_DUPLEX:
- clrbits |= SPI_CR1_BIDIOE | SPI_CR1_RXONLY;
- setbits |= SPI_CR1_BIDIMODE;
+ clrbits |= SPI_CR1_RXONLY;
+ setbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; /* TX mode */
+ priv->rx_mode = false;
break;
}
@@ -1787,8 +1879,9 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
setbits |= SPI_CR1_RXONLY;
break;
case HALF_DUPLEX:
- clrbits |= SPI_CR1_BIDIOE | SPI_CR1_RXONLY;
- setbits |= SPI_CR1_BIDIMODE;
+ clrbits |= SPI_CR1_RXONLY;
+ setbits |= SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; /* TX mode */
+ priv->rx_mode = false;
break;
}
[incubator-nuttx] 02/04: stm32f0l0g0/stm32_spi.c: add missing SPI mode config and fix ifdef
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit af4d65416a06774dcd3a15f16222934e7636cf5d
Author: raiden00pl <ra...@railab.me>
AuthorDate: Wed Jul 20 16:41:02 2022 +0200
stm32f0l0g0/stm32_spi.c: add missing SPI mode config and fix ifdef
---
arch/arm/src/stm32f0l0g0/stm32_spi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c
index ccf2fe0a88..a814dbc3c6 100644
--- a/arch/arm/src/stm32f0l0g0/stm32_spi.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c
@@ -325,6 +325,7 @@ static struct stm32_spidev_s g_spi1dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
+ .config = CONFIG_STM32F0L0G0_SPI1_COMMTYPE,
};
#endif
@@ -378,6 +379,7 @@ static struct stm32_spidev_s g_spi2dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
+ .config = CONFIG_STM32F0L0G0_SPI2_COMMTYPE,
};
#endif
@@ -1979,7 +1981,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
goto errout;
}
-#ifdef CONFIG_STM32L4_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
/* SPI DMA supported only for full-duplex mode */
if (priv->rxch && priv->txch && priv->config != FULL_DUPLEX)
[incubator-nuttx] 01/04: stm32f0l0g0/hardware/stm32_spi.h: remove unused definitions
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 69986fad844d9090643d0b2027a6c3479f99cdf4
Author: raiden00pl <ra...@railab.me>
AuthorDate: Wed Jul 20 16:37:37 2022 +0200
stm32f0l0g0/hardware/stm32_spi.h: remove unused definitions
---
arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h | 36 ---------------------------
1 file changed, 36 deletions(-)
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
index 96e4d2d4c9..67bc9826f6 100644
--- a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
@@ -96,42 +96,6 @@
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
-#if STM32_NSPI > 3
-# define STM32_SPI4_CR1 (STM32_SPI4_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI4_CR2 (STM32_SPI4_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI4_SR (STM32_SPI4_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI4_DR (STM32_SPI4_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI4_CRCPR (STM32_SPI4_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI4_I2SPR (STM32_SPI4_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32_NSPI > 4
-# define STM32_SPI5_CR1 (STM32_SPI5_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI5_CR2 (STM32_SPI5_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI5_SR (STM32_SPI5_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI5_DR (STM32_SPI5_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI5_CRCPR (STM32_SPI5_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI5_I2SPR (STM32_SPI5_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32_NSPI > 5
-# define STM32_SPI6_CR1 (STM32_SPI6_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI6_CR2 (STM32_SPI6_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI6_SR (STM32_SPI6_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI6_DR (STM32_SPI6_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI6_CRCPR (STM32_SPI6_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI6_I2SPR (STM32_SPI6_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
/* Register Bitfield Definitions ********************************************/
/* SPI Control Register 1 */