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Posted to commits@nuttx.apache.org by "jlaitine (via GitHub)" <gi...@apache.org> on 2026/10/14 08:30:00 UTC
[PR] Imxrt 118x ele additions [nuttx]
jlaitine opened a new pull request, #20660:
URL: https://github.com/apache/nuttx/pull/20660
## Summary
- Add silicon revision read support to imxrt118x secure element support
- Add support for data buffers residing in TCM memory
## Impact
Impacts only imxrt118x based designs using the internal secure element. Adds new functionality and extends the usability for configurations using TCM memory as primary.
## Testing
Added following code to "examples/hello" app, set CONFIG_IMXRT_ELE=y, CONFIG_EXAMPLES_HELLO=y:
```
+ lifecycle = imxrt118x_ele_get_lifecycle();
+ printf("ELE lifecycle: 0x%04" PRIx32 "\n", lifecycle);
+
+ ret = imxrt118x_ele_get_soc_revision(&revision);
+ if (ret < 0)
+ {
+ fprintf(stderr, "ERROR: ELE SoC revision read failed: %d\n", ret);
+ return 1;
+ }
+
+ printf("ELE SoC revision: 0x%02" PRIx8 "\n", revision);
```
Compiled and flashed imxrt1180-evk:bl and imxrt1180-evk:nsh.
output:
```
nsh> hello
Hello, World!!
ELE lifecycle: 0x0010
ELE SoC revision: 0xc0
```
This is expected, lifecycle 0x10 is OEM_OPEN and SoC silicon revision is C0 matching my board.
DTCM access is now tested, because the imxrt1180-evk:nsh is nowdays using TCM as the primary memory.
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Re: [PR] arch/arm/imxrt: Add ELE TCM and chip revision support for imxrt118x [nuttx]
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 merged PR #20660:
URL: https://github.com/apache/nuttx/pull/20660
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Re: [PR] arch/arm/imxrt: Add ELE TCM and chip revision support for imxrt118x [nuttx]
Posted by "github-actions[bot] (via GitHub)" <gi...@apache.org>.
github-actions[bot] commented on PR #20660:
URL: https://github.com/apache/nuttx/pull/20660#issuecomment-6169468505
<!-- membrowse-pr-comment -->
## <img src="https://membrowse.com/membrowse-logo.svg" height="24" align="top"> MemBrowse Memory Report
*No memory changes detected for:*
- [arduino-mega2560](https://membrowse.com/public/apache/nuttx/target/arduino-mega2560/compare?head=cedc5aa4c54fa7513f0edae1f314a18b67f22547&base=78b54742e42107dd8f31256ee3fff45951cd0af1)
- [esp32-devkitc](https://membrowse.com/public/apache/nuttx/target/esp32-devkitc/compare?head=cedc5aa4c54fa7513f0edae1f314a18b67f22547&base=78b54742e42107dd8f31256ee3fff45951cd0af1)
- [hifive1-revb](https://membrowse.com/public/apache/nuttx/target/hifive1-revb/compare?head=cedc5aa4c54fa7513f0edae1f314a18b67f22547&base=78b54742e42107dd8f31256ee3fff45951cd0af1)
- [mirtoo](https://membrowse.com/public/apache/nuttx/target/mirtoo/compare?head=cedc5aa4c54fa7513f0edae1f314a18b67f22547&base=78b54742e42107dd8f31256ee3fff45951cd0af1)
- [qemu-armv8a](https://membrowse.com/public/apache/nuttx/target/qemu-armv8a/compare?head=cedc5aa4c54fa7513f0edae1f314a18b67f22547&base=78b54742e42107dd8f31256ee3fff45951cd0af1)
- [qemu-intel64](https://membrowse.com/public/apache/nuttx/target/qemu-intel64/compare?head=cedc5aa4c54fa7513f0edae1f314a18b67f22547&base=78b54742e42107dd8f31256ee3fff45951cd0af1)
- [rx65n-rsk2mb](https://membrowse.com/public/apache/nuttx/target/rx65n-rsk2mb/compare?head=cedc5aa4c54fa7513f0edae1f314a18b67f22547&base=78b54742e42107dd8f31256ee3fff45951cd0af1)
- [s698pm-dkit](https://membrowse.com/public/apache/nuttx/target/s698pm-dkit/compare?head=cedc5aa4c54fa7513f0edae1f314a18b67f22547&base=78b54742e42107dd8f31256ee3fff45951cd0af1)
- [stm32-nucleo-f103rb](https://membrowse.com/public/apache/nuttx/target/stm32-nucleo-f103rb/compare?head=cedc5aa4c54fa7513f0edae1f314a18b67f22547&base=78b54742e42107dd8f31256ee3fff45951cd0af1)
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