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Posted to commits@mynewt.apache.org by ja...@apache.org on 2020/02/28 11:36:51 UTC
[mynewt-core] 05/06: Update NRFX to release 2.1.0
This is an automated email from the ASF dual-hosted git repository.
janc pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit c05a0967e80bf60a228a419e7d05b46f1d106d05
Author: Szymon Janc <sz...@codecoup.pl>
AuthorDate: Tue Feb 25 14:09:10 2020 +0100
Update NRFX to release 2.1.0
---
hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md | 33 +
hw/mcu/nordic/src/ext/nrfx/LICENSE | 2 +-
.../src/ext/nrfx/drivers/include/nrf_bitmask.h | 2 +-
.../nordic/src/ext/nrfx/drivers/include/nrfx_adc.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_clock.h | 199 +-
.../src/ext/nrfx/drivers/include/nrfx_comp.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_dppi.h | 2 +-
.../nordic/src/ext/nrfx/drivers/include/nrfx_egu.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_gpiote.h | 2 +-
.../nordic/src/ext/nrfx/drivers/include/nrfx_i2s.h | 53 +-
.../nordic/src/ext/nrfx/drivers/include/nrfx_ipc.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_lpcomp.h | 4 +-
.../src/ext/nrfx/drivers/include/nrfx_nfct.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_nvmc.h | 2 +-
.../nordic/src/ext/nrfx/drivers/include/nrfx_pdm.h | 49 +-
.../src/ext/nrfx/drivers/include/nrfx_power.h | 48 +-
.../ext/nrfx/drivers/include/nrfx_power_clock.h | 2 +-
.../ext/nrfx/drivers/include/nrfx_power_compat.h | 106 +
.../nordic/src/ext/nrfx/drivers/include/nrfx_ppi.h | 2 +-
.../nordic/src/ext/nrfx/drivers/include/nrfx_pwm.h | 33 +-
.../src/ext/nrfx/drivers/include/nrfx_qdec.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_qspi.h | 32 +-
.../nordic/src/ext/nrfx/drivers/include/nrfx_rng.h | 2 +-
.../nordic/src/ext/nrfx/drivers/include/nrfx_rtc.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_saadc.h | 2 +-
.../nordic/src/ext/nrfx/drivers/include/nrfx_spi.h | 4 +-
.../src/ext/nrfx/drivers/include/nrfx_spim.h | 6 +-
.../src/ext/nrfx/drivers/include/nrfx_spis.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_systick.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_temp.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_timer.h | 2 +-
.../nordic/src/ext/nrfx/drivers/include/nrfx_twi.h | 7 +-
.../src/ext/nrfx/drivers/include/nrfx_twi_twim.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_twim.h | 20 +-
.../src/ext/nrfx/drivers/include/nrfx_twis.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_uart.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_uarte.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_usbd.h | 2 +-
.../src/ext/nrfx/drivers/include/nrfx_usbreg.h | 151 +
.../nordic/src/ext/nrfx/drivers/include/nrfx_wdt.h | 6 +-
hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_common.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_errors.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_adc.c | 2 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_clock.c | 237 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_comp.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_dppi.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_egu.c | 2 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c | 283 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c | 16 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ipc.c | 2 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_lpcomp.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nvmc.c | 23 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c | 63 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_power.c | 35 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ppi.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c | 33 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c | 8 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qspi.c | 46 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rng.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c | 2 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_saadc.c | 275 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c | 39 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c | 2 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_systick.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_temp.c | 2 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_timer.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi.c | 62 +-
.../src/ext/nrfx/drivers/src/nrfx_twi_twim.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c | 193 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uart.c | 2 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c | 61 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c | 78 +-
.../src/ext/nrfx/drivers/src/nrfx_usbd_errata.h | 92 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_usbreg.c | 97 +
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_wdt.c | 2 +-
.../nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.c | 2 +-
.../nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h | 8 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_aar.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_acl.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_adc.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_bprot.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_cache.h | 11 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h | 22 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h | 627 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_dcnf.h | 200 +
hw/mcu/nordic/src/ext/nrfx/hal/nrf_dppi.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_ficr.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_fpu.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h | 80 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h | 79 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_ipc.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_kmu.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_mpu.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_mutex.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_mwu.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.h | 20 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_oscillators.h | 121 +
hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h | 83 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h | 93 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h | 4 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h | 206 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h | 10 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_regulators.h | 247 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_reset.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h | 22 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h | 11 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_spu.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_systick.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h | 25 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbd.h | 11 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbreg.h | 173 +
hw/mcu/nordic/src/ext/nrfx/hal/nrf_vmc.h | 2 +-
.../nrfx/hal/{nrf_regulators.h => nrf_vreqctrl.h} | 50 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h | 6 +-
hw/mcu/nordic/src/ext/nrfx/helpers/nrfx_gppi.h | 2 +-
.../ext/nrfx/mdk/arm_startup_nrf5340_application.s | 28 +-
hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S | 2 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf52805.S | 2 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S | 2 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S | 2 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf52833.S | 2 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S | 2 +-
.../ext/nrfx/mdk/gcc_startup_nrf5340_application.S | 22 +-
.../src/ext/nrfx/mdk/gcc_startup_nrf5340_network.S | 2 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf9160.S | 2 +-
.../ext/nrfx/mdk/iar_startup_nrf5340_application.s | 40 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h | 16 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h | 6 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_erratas.h | 2579 -------
.../nordic/src/ext/nrfx/mdk/nrf51422_peripherals.h | 2 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51801_erratas.h | 635 --
.../nordic/src/ext/nrfx/mdk/nrf51801_peripherals.h | 2 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51802_erratas.h | 635 --
.../nordic/src/ext/nrfx/mdk/nrf51802_peripherals.h | 2 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_erratas.h | 2993 --------
.../nordic/src/ext/nrfx/mdk/nrf51822_peripherals.h | 2 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51824_erratas.h | 743 --
.../nordic/src/ext/nrfx/mdk/nrf51824_peripherals.h | 2 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_erratas.h | 6846 +++++++++--------
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_peripherals.h | 1 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.h | 6 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.h | 6 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805_erratas.h | 1427 ----
.../nordic/src/ext/nrfx/mdk/nrf52805_peripherals.h | 2 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52810.h | 6 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52810_erratas.h | 1611 ----
.../nordic/src/ext/nrfx/mdk/nrf52810_peripherals.h | 2 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52811.h | 6 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52811_erratas.h | 1481 ----
.../nordic/src/ext/nrfx/mdk/nrf52811_peripherals.h | 3 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52832_erratas.h | 4268 -----------
.../nordic/src/ext/nrfx/mdk/nrf52832_peripherals.h | 2 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52833.h | 14 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52833.svd | 112 +-
.../nordic/src/ext/nrfx/mdk/nrf52833_bitfields.h | 53 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52833_erratas.h | 1471 ----
.../nordic/src/ext/nrfx/mdk/nrf52833_peripherals.h | 4 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52840.h | 6 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52840_erratas.h | 3239 --------
.../nordic/src/ext/nrfx/mdk/nrf52840_peripherals.h | 4 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52_erratas.h | 7787 ++++++++++++++++++++
.../nordic/src/ext/nrfx/mdk/nrf5340_application.h | 129 +-
.../src/ext/nrfx/mdk/nrf5340_application.svd | 404 +-
.../ext/nrfx/mdk/nrf5340_application_bitfields.h | 96 +-
.../src/ext/nrfx/mdk/nrf5340_application_erratas.h | 801 --
.../ext/nrfx/mdk/nrf5340_application_peripherals.h | 53 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_network.h | 51 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_network.svd | 96 +-
.../src/ext/nrfx/mdk/nrf5340_network_bitfields.h | 74 +-
.../src/ext/nrfx/mdk/nrf5340_network_erratas.h | 619 --
.../src/ext/nrfx/mdk/nrf5340_network_peripherals.h | 4 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf53_erratas.h | 1609 ++++
hw/mcu/nordic/src/ext/nrfx/mdk/nrf9160.h | 6 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf9160_erratas.h | 561 --
.../nordic/src/ext/nrfx/mdk/nrf9160_peripherals.h | 42 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf91_erratas.h | 639 ++
hw/mcu/nordic/src/ext/nrfx/mdk/nrf_erratas.h | 67 +-
.../ext/nrfx/mdk/ses_startup_nrf5340_application.s | 32 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf51.c | 8 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52.c | 22 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52805.c | 10 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52810.c | 26 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52811.c | 14 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52833.c | 6 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52840.c | 14 +-
.../src/ext/nrfx/mdk/system_nrf5340_application.c | 42 +-
.../src/ext/nrfx/mdk/system_nrf5340_network.c | 6 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf9160.c | 10 +-
hw/mcu/nordic/src/ext/nrfx/nrfx.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/soc/nrfx_atomic.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/soc/nrfx_atomic.h | 2 +-
.../nordic/src/ext/nrfx/soc/nrfx_atomic_internal.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/soc/nrfx_coredep.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/soc/nrfx_irqs.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/soc/nrfx_irqs_nrf51.h | 2 +-
.../nordic/src/ext/nrfx/soc/nrfx_irqs_nrf52810.h | 2 +-
.../nordic/src/ext/nrfx/soc/nrfx_irqs_nrf52811.h | 2 +-
.../nordic/src/ext/nrfx/soc/nrfx_irqs_nrf52832.h | 2 +-
.../nordic/src/ext/nrfx/soc/nrfx_irqs_nrf52833.h | 2 +-
.../nordic/src/ext/nrfx/soc/nrfx_irqs_nrf52840.h | 2 +-
.../ext/nrfx/soc/nrfx_irqs_nrf5340_application.h | 42 +-
.../src/ext/nrfx/soc/nrfx_irqs_nrf5340_network.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/soc/nrfx_irqs_nrf9160.h | 2 +-
.../{soc/nrfx_irqs.h => templates/nrfx_config.h} | 28 +-
.../{nRF51/nrfx_config.h => nrfx_config_nrf51.h} | 101 +-
.../nrfx_config.h => nrfx_config_nrf52810.h} | 144 +-
.../nrfx_config.h => nrfx_config_nrf52811.h} | 144 +-
.../nrfx_config.h => nrfx_config_nrf52832.h} | 175 +-
.../nrfx_config.h => nrfx_config_nrf52833.h} | 183 +-
.../nrfx_config.h => nrfx_config_nrf52840.h} | 185 +-
..._config.h => nrfx_config_nrf5340_application.h} | 422 +-
...nrfx_config.h => nrfx_config_nrf5340_network.h} | 130 +-
.../nrfx_config.h => nrfx_config_nrf9160.h} | 163 +-
hw/mcu/nordic/src/ext/nrfx/templates/nrfx_glue.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/templates/nrfx_log.h | 2 +-
237 files changed, 19554 insertions(+), 28389 deletions(-)
diff --git a/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md b/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md
index 7d7773f..f1fb6c6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md
+++ b/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md
@@ -1,6 +1,39 @@
# Changelog
All notable changes to this project are documented in this file.
+## [2.1.0] - 2020-01-24
+### Added
+- Added HALs for DCNF, OSCILLATORS, USBREG, and VREQCTRL.
+- Added support for 1-MHz clock frequency in TWIM.
+- Introduced the NRFX_I2S_STATUS_TRANSFER_STOPPED flag in the I2S driver.
+- Introduced the nrfx_power_compat layer that allows use of the nrfx_power API with new SoC.
+- Added encryption support in the QSPI driver.
+- Added support for USBD in nRF5340.
+- Expanded HALs to cover new functions in nRF5340: GPIO, I2S, PDM, POWER, QSPI, and REGULATORS.
+- Introduced new clock management system in the CLOCK driver.
+- Introduced new audio clock configuration settings in the I2S and PDM drivers for nRF5340.
+- Implemented workaround for nRF5340 anomaly 4 in the CLOCK driver.
+- Implemented workaround for nRF5340 anomaly 10 in the CCM HAL.
+- Implemented workaround for nRF9160 anomaly 21 and nRF5340 anomaly 6 in the NVMC HAL.
+- Implemented workaround for nRF9160 anomaly 23 and nRF5340 anomaly 44 in the UARTE driver.
+- Introduced the NRFX_TWIM_NO_SPURIOUS_STOP_CHECK flag in the TWIM driver.
+- Added functions for getting shortcut configuration in the TWIM HAL.
+
+### Changed
+- Updated MDK to 8.30.2.
+- Reorganized templates of nrfx_config header files for different SoCs. Now they are included through one common file according to the selected SoC.
+- Improved the UARTE driver to consume less current after the driver uninitialization. Now all clocks are disabled properly after uninitialization.
+- Improved the GPIOTE driver robustness by setting the LATCH functionality to be used by default.
+- Changed names of the frequency divider symbols in the QSPI HAL to reflect the new frequencies in nRF5340. Old API names were preserved and are still supported.
+- Improved spurious STOP condition handling in the TWIM driver.
+- Improved sampling procedure in the advanced blocking mode in the SAADC driver.
+- Improved calibration procedure in the SAADC driver for nRF5340 and nRF9160.
+
+### Fixed
+- Fixed address assertions in NVMC driver for the nRF5340 network core.
+- Fixed an issue in the TWI driver that would make the driver stuck when a premature STOP condition was generated by a slave device. The driver now handles this situation properly and signals that a bus error occurred.
+- Fixed the stopping procedure in the PWM driver. Previously in very specific circumstances the PWM output might be not stopped at all or might be immediately restarted.
+
## [2.0.0] - 2019-11-06
### Added
- Added support for nRF5340.
diff --git a/hw/mcu/nordic/src/ext/nrfx/LICENSE b/hw/mcu/nordic/src/ext/nrfx/LICENSE
index ed92c3b..94bd0a0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/LICENSE
+++ b/hw/mcu/nordic/src/ext/nrfx/LICENSE
@@ -1,4 +1,4 @@
-Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
All rights reserved.
Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrf_bitmask.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrf_bitmask.h
index abb281a..3abb6ce 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrf_bitmask.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrf_bitmask.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_adc.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_adc.h
index 78ef700..453cb7a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_adc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_adc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h
index 4dbeb80..08cbee1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -50,10 +50,12 @@ extern "C" {
/** @brief Clock events. */
typedef enum
{
- NRFX_CLOCK_EVT_HFCLK_STARTED, ///< HFCLK has been started.
- NRFX_CLOCK_EVT_LFCLK_STARTED, ///< LFCLK has been started.
- NRFX_CLOCK_EVT_CTTO, ///< Calibration timeout.
- NRFX_CLOCK_EVT_CAL_DONE ///< Calibration has been done.
+ NRFX_CLOCK_EVT_HFCLK_STARTED, ///< HFCLK has been started.
+ NRFX_CLOCK_EVT_LFCLK_STARTED, ///< LFCLK has been started.
+ NRFX_CLOCK_EVT_CTTO, ///< Calibration timeout.
+ NRFX_CLOCK_EVT_CAL_DONE, ///< Calibration has been done.
+ NRFX_CLOCK_EVT_HFCLKAUDIO_STARTED, ///< HFCLKAUDIO has been started.
+ NRFX_CLOCK_EVT_HFCLK192M_STARTED, ///< HFCLK192M has been started.
} nrfx_clock_evt_type_t;
/**
@@ -85,34 +87,137 @@ void nrfx_clock_disable(void);
/** @brief Function for uninitializing the clock module. */
void nrfx_clock_uninit(void);
-/** @brief Function for starting the LFCLK. */
-void nrfx_clock_lfclk_start(void);
+/**
+ * @brief Function for starting the specified clock domain.
+ *
+ * @param[in] domain Clock domain.
+ */
+void nrfx_clock_start(nrf_clock_domain_t domain);
+
+/**
+ * @brief Function for stopping the specified clock domain.
+ *
+ * @param[in] domain Clock domain.
+ */
+void nrfx_clock_stop(nrf_clock_domain_t domain);
+
+/**
+ * @brief Function for checking the specified clock domain state.
+ *
+ * XTAL source is assumed for domains with multiple sources.
+ *
+ * @param[in] domain Clock domain.
+ * @param[out] clk_src Clock source that is running. Set to NULL if not needed.
+ * Ignored for HFCLKAUDIO domain. Typecast it to @ref nrf_clock_lfclk_t for
+ * LFCLK and @ref nrf_clock_hfclk_t for HFCLK and HFCLK192M.
+ *
+ * @retval true The clock domain is running.
+ * @retval false The clock domain is not running.
+ */
+NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * clk_src);
-/** @brief Function for stopping the LFCLK. */
-void nrfx_clock_lfclk_stop(void);
+#if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK_192M
+/**
+ * @brief Function for setting the specified clock domain divider.
+ *
+ * @param[in] domain Clock domain.
+ * @param[in] div New divider for the clock domain.
+ *
+ * @retval NRFX_SUCCESS Divider successfully set.
+ * @retval NRFX_ERROR_NOT_SUPPORTED Domain does not support setting the divider.
+ * @retval NRFX_ERROR_INVALID_PARAM Divider not supported by the specified domain.
+ */
+nrfx_err_t nrfx_clock_divider_set(nrf_clock_domain_t domain,
+ nrf_clock_hfclk_div_t div);
+
+/**
+ * @brief Function for getting the specified clock domain divider.
+ *
+ * @param[in] domain Clock domain.
+ *
+ * @return Current divider for the specified clock domain.
+ */
+
+NRFX_STATIC_INLINE nrf_clock_hfclk_div_t nrfx_clock_divider_get(nrf_clock_domain_t domain);
+#endif
+
+/**
+ * @brief Function for starting the LFCLK.
+ *
+ * @note This function is deprecated. Use @ref nrfx_clock_start instead.
+ */
+NRFX_STATIC_INLINE void nrfx_clock_lfclk_start(void);
+
+/**
+ * @brief Function for stopping the LFCLK.
+ *
+ * @note This function is deprecated. Use @ref nrfx_clock_stop instead.
+ */
+NRFX_STATIC_INLINE void nrfx_clock_lfclk_stop(void);
/**
* @brief Function for checking the LFCLK state.
*
+ * @note This function is deprecated. Use @ref nrfx_clock_is_running instead.
+ *
* @retval true The LFCLK is running.
* @retval false The LFCLK is not running.
*/
NRFX_STATIC_INLINE bool nrfx_clock_lfclk_is_running(void);
-/** @brief Function for starting the high-accuracy source HFCLK. */
-void nrfx_clock_hfclk_start(void);
+/**
+ * @brief Function for starting the high-accuracy source HFCLK.
+ *
+ * @note This function is deprecated. Use @ref nrfx_clock_start instead.
+ */
+NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void);
-/** @brief Function for stopping the external high-accuracy source HFCLK. */
-void nrfx_clock_hfclk_stop(void);
+/**
+ * @brief Function for stopping the external high-accuracy source HFCLK.
+ *
+ * @note This function is deprecated. Use @ref nrfx_clock_stop instead.
+ */
+NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void);
/**
* @brief Function for checking the HFCLK state.
*
+ * @note This function is deprecated. Use @ref nrfx_clock_is_running instead.
+ *
* @retval true The HFCLK is running (XTAL source).
* @retval false The HFCLK is not running.
*/
NRFX_STATIC_INLINE bool nrfx_clock_hfclk_is_running(void);
+
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+/**
+ * @brief Function for setting the HFCLKAUDIO configuration.
+ *
+ * The frequency of HFCLKAUDIO ranges from 10.666 MHz to 13.333 MHz in 40.7 Hz steps.
+ * To calculate @p freq_value corresponding to the chosen frequency, use the following equation:
+ * FREQ_VALUE = 2^16 * ((12 * f_out / 32M) - 4)
+ *
+ * @warning Chosen frequency must fit in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz
+ * frequency bands.
+ *
+ * @param[in] freq_value New FREQ_VALUE for HFCLKAUDIO.
+ */
+NRFX_STATIC_INLINE void nrfx_clock_hfclkaudio_config_set(uint16_t freq_value);
+
+/**
+ * @brief Function for getting the HFCLKAUDIO configuration.
+ *
+ * The frequency of HFCLKAUDIO ranges from 10.666 MHz to 13.333 MHz in 40.7 Hz steps.
+ * To calculate frequency corresponding to the returned FREQ_VALUE, use the following equation:
+ * f_out = 32M * (4 + FREQ_VALUE * 2^(-16))/12
+ *
+ * @return Current value of FREQ_VALUE for HFCLKAUDIO.
+ */
+NRFX_STATIC_INLINE uint16_t nrfx_clock_hfclkaudio_config_get(void);
+
+#endif
+
/**
* @brief Function for starting the calibration of internal LFCLK.
*
@@ -161,8 +266,48 @@ NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task);
*/
NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event);
-
#ifndef NRFX_DECLARE_ONLY
+
+#if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK_192M
+NRFX_STATIC_INLINE nrf_clock_hfclk_div_t nrfx_clock_divider_get(nrf_clock_domain_t domain)
+{
+ switch (domain)
+ {
+#if NRF_CLOCK_HAS_HFCLK_DIV
+ case NRF_CLOCK_DOMAIN_HFCLK:
+ return nrf_clock_hfclk_div_get(NRF_CLOCK);
+#endif
+#if NRF_CLOCK_HAS_HFCLK192M
+ case NRF_CLOCK_DOMAIN_HFCLK192M:
+ return nrf_clock_hfclk192m_div_get(NRF_CLOCK);
+#endif
+ default:
+ NRFX_ASSERT(0);
+ return 0;
+ }
+}
+#endif // NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK_192M
+
+NRFX_STATIC_INLINE void nrfx_clock_lfclk_start(void)
+{
+ nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
+}
+
+NRFX_STATIC_INLINE void nrfx_clock_lfclk_stop(void)
+{
+ nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
+}
+
+NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
+{
+ nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
+}
+
+NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
+{
+ nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
+}
+
NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task)
{
return nrf_clock_task_address_get(NRF_CLOCK, task);
@@ -173,15 +318,37 @@ NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event)
return nrf_clock_event_address_get(NRF_CLOCK, event);
}
+NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * clk_src)
+{
+ return nrf_clock_is_running(NRF_CLOCK, domain, clk_src);
+}
+
NRFX_STATIC_INLINE bool nrfx_clock_hfclk_is_running(void)
{
- return nrf_clock_hf_is_running(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY);
+ nrf_clock_hfclk_t clk_src;
+ bool ret = nrfx_clock_is_running(NRF_CLOCK_DOMAIN_HFCLK, &clk_src);
+ return (ret && (clk_src == NRF_CLOCK_HFCLK_HIGH_ACCURACY));
}
NRFX_STATIC_INLINE bool nrfx_clock_lfclk_is_running(void)
{
- return nrf_clock_lf_is_running(NRF_CLOCK);
+ return nrfx_clock_is_running(NRF_CLOCK_DOMAIN_LFCLK, NULL);
}
+
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+
+NRFX_STATIC_INLINE void nrfx_clock_hfclkaudio_config_set(uint16_t freq_value)
+{
+ nrf_clock_hfclkaudio_config_set(NRF_CLOCK, freq_value);
+}
+
+NRFX_STATIC_INLINE uint16_t nrfx_clock_hfclkaudio_config_get(void)
+{
+ return nrf_clock_hfclkaudio_config_get(NRF_CLOCK);
+}
+
+#endif
+
#endif // NRFX_DECLARE_ONLY
/** @} */
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_comp.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_comp.h
index 7621f48..d42f901 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_comp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_comp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_dppi.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_dppi.h
index 84b1715..e7bc202 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_dppi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_dppi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_egu.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_egu.h
index 1470778..686e526 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_egu.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_egu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_gpiote.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_gpiote.h
index ad1abec..10e57ea 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_gpiote.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_gpiote.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_i2s.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_i2s.h
index 0476a63..698a7d6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_i2s.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_i2s.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -69,13 +69,17 @@ typedef struct
* if this signal is not needed. */
uint8_t irq_priority; ///< Interrupt priority.
- nrf_i2s_mode_t mode; ///< Mode of operation.
- nrf_i2s_format_t format; ///< Frame format.
- nrf_i2s_align_t alignment; ///< Alignment of sample within a frame.
- nrf_i2s_swidth_t sample_width; ///< Sample width.
- nrf_i2s_channels_t channels; ///< Enabled channels.
- nrf_i2s_mck_t mck_setup; ///< Master clock setup.
- nrf_i2s_ratio_t ratio; ///< MCK/LRCK ratio.
+ nrf_i2s_mode_t mode; ///< Mode of operation.
+ nrf_i2s_format_t format; ///< Frame format.
+ nrf_i2s_align_t alignment; ///< Alignment of sample within a frame.
+ nrf_i2s_swidth_t sample_width; ///< Sample width.
+ nrf_i2s_channels_t channels; ///< Enabled channels.
+ nrf_i2s_mck_t mck_setup; ///< Master clock setup.
+ nrf_i2s_ratio_t ratio; ///< MCK/LRCK ratio.
+#if NRF_I2S_HAS_CLKCONFIG
+ nrf_i2s_clksrc_t clksrc; ///< Clock source selection.
+ bool enable_bypass; ///< Bypass clock generator. MCK will be equal to source input.
+#endif
} nrfx_i2s_config_t;
/** @brief I2S driver buffers structure. */
@@ -85,6 +89,14 @@ typedef struct
uint32_t const * p_tx_buffer; ///< Pointer to the buffer with data to be sent.
} nrfx_i2s_buffers_t;
+#if NRF_I2S_HAS_CLKCONFIG || defined(__NRFX_DOXYGEN__)
+ /** @brief I2S additional clock source configuration. */
+ #define NRF_I2S_DEFAULT_EXTENDED_CLKSRC_CONFIG \
+ .clksrc = NRF_I2S_CLKSRC_PCLK32M, \
+ .enable_bypass = false,
+#else
+ #define NRF_I2S_DEFAULT_EXTENDED_CLKSRC_CONFIG
+#endif
/**
* @brief I2S driver default configuration.
*
@@ -118,15 +130,20 @@ typedef struct
.channels = NRF_I2S_CHANNELS_LEFT, \
.mck_setup = NRF_I2S_MCK_32MDIV8, \
.ratio = NRF_I2S_RATIO_32X, \
+ NRF_I2S_DEFAULT_EXTENDED_CLKSRC_CONFIG \
}
-#define NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED (1UL << 0)
+#define NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED (1UL << 0)
/**< The application must provide buffers that are to be used in the next
* part of the transfer. A call to @ref nrfx_i2s_next_buffers_set must
* be done before the currently used buffers are completely processed
* (that is, the time remaining for supplying the next buffers depends on
* the used size of the buffers). */
+#define NRFX_I2S_STATUS_TRANSFER_STOPPED (1UL << 1)
+ /**< The I2S peripheral has been stopped and all buffers that were passed
+ * to the driver have been released. */
+
/**
* @brief I2S driver data handler type.
*
@@ -155,14 +172,22 @@ typedef struct
* Both pointers in this structure are NULL when the
* handler is called for the first time after a transfer
* is started, because no data has been transferred yet
- * at this point. In all successive calls the pointers
+ * at this point. In all successive calls, the pointers
* specify what has been sent (TX) and what has been
- * received (RX) in the part of transfer that has just
- * been completed (provided that a given direction is
- * enabled, see @ref nrfx_i2s_start).
+ * received (RX) in the part of the transfer that has
+ * just been completed (provided that a given direction
+ * is enabled, see @ref nrfx_i2s_start).
+ * @note Since the peripheral is stopped asynchronously,
+ * buffers that are released after the call to
+ * @ref nrfx_i2s_stop are not used entirely.
+ * In this case, only a part (if any) of the TX
+ * buffer has been actually transmitted and only
+ * a part (if any) of the RX buffer is filled with
+ * received data.
* @param[in] status Bit field describing the current status of the transfer.
* It can be 0 or a combination of the following flags:
* - @ref NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED
+ * - @ref NRFX_I2S_STATUS_TRANSFER_STOPPED
*/
typedef void (* nrfx_i2s_data_handler_t)(nrfx_i2s_buffers_t const * p_released,
uint32_t status);
@@ -198,7 +223,7 @@ void nrfx_i2s_uninit(void);
* word can either contain four 8-bit samples, two 16-bit samples, or one
* right-aligned 24-bit sample sign-extended to a 32-bit value.
* For a detailed memory mapping for different supported configurations,
- * see the @linkProductSpecification52.
+ * see the Product Specification.
*
* @note Peripherals using EasyDMA (including I2S) require the transfer buffers
* to be placed in the Data RAM region. If this condition is not met,
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ipc.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ipc.h
index fb4abab..d6331a2 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ipc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ipc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_lpcomp.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_lpcomp.h
index 03a8370..fa5757f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_lpcomp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_lpcomp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -70,7 +70,7 @@ typedef struct
*
* @param[in] _input Comparator input pin.
*/
-#ifdef NRF52_SERIES
+#if defined(LPCOMP_FEATURE_HYST_PRESENT)
#define NRFX_LPCOMP_DEFAULT_CONFIG(_input) \
{ \
.hal = { NRF_LPCOMP_REF_SUPPLY_4_8, \
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h
index 963a935..4d8bea0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nvmc.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nvmc.h
index 2a030e5..cfea373 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nvmc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nvmc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pdm.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pdm.h
index 246c0d6..3396273 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pdm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pdm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -67,16 +67,39 @@ typedef struct
/** @brief PDM interface driver configuration structure. */
typedef struct
{
- nrf_pdm_mode_t mode; ///< Interface operation mode.
- nrf_pdm_edge_t edge; ///< Sampling mode.
- uint8_t pin_clk; ///< CLK pin.
- uint8_t pin_din; ///< DIN pin.
- nrf_pdm_freq_t clock_freq; ///< Clock frequency.
- nrf_pdm_gain_t gain_l; ///< Left channel gain.
- nrf_pdm_gain_t gain_r; ///< Right channel gain.
- uint8_t interrupt_priority; ///< Interrupt priority.
+ nrf_pdm_mode_t mode; ///< Interface operation mode.
+ nrf_pdm_edge_t edge; ///< Sampling mode.
+ uint8_t pin_clk; ///< CLK pin.
+ uint8_t pin_din; ///< DIN pin.
+ nrf_pdm_freq_t clock_freq; ///< Clock frequency.
+ nrf_pdm_gain_t gain_l; ///< Left channel gain.
+ nrf_pdm_gain_t gain_r; ///< Right channel gain.
+ uint8_t interrupt_priority; ///< Interrupt priority.
+#if NRF_PDM_HAS_RATIO_CONFIG
+ nrf_pdm_ratio_t ratio; ///< Ratio between PDM_CLK and output sample rate.
+#endif
+#if NRF_PDM_HAS_MCLKCONFIG
+ nrf_pdm_mclksrc_t mclksrc; ///< Master clock source selection.
+#endif
} nrfx_pdm_config_t;
+
+#if NRF_PDM_HAS_RATIO_CONFIG || defined(__NRFX_DOXYGEN__)
+ /** @brief PDM additional ratio configuration. */
+ #define NRFX_PDM_DEFAULT_EXTENDED_RATIO_CONFIG \
+ .ratio = NRF_PDM_RATIO_64X,
+#else
+ #define NRFX_PDM_DEFAULT_EXTENDED_RATIO_CONFIG
+#endif
+
+#if NRF_PDM_HAS_MCLKCONFIG || defined(__NRFX_DOXYGEN__)
+ /** @brief PDM additional master clock source configuration. */
+ #define NRFX_PDM_DEFAULT_EXTENDED_MCLKSRC_CONFIG \
+ .mclksrc = NRF_PDM_MCLKSRC_PCLK32M,
+#else
+ #define NRFX_PDM_DEFAULT_EXTENDED_MCLKSRC_CONFIG
+#endif
+
/**
* @brief PDM driver default configuration.
*
@@ -98,7 +121,9 @@ typedef struct
.clock_freq = NRF_PDM_FREQ_1032K, \
.gain_l = NRF_PDM_GAIN_DEFAULT, \
.gain_r = NRF_PDM_GAIN_DEFAULT, \
- .interrupt_priority = NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY \
+ .interrupt_priority = NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY, \
+ NRFX_PDM_DEFAULT_EXTENDED_RATIO_CONFIG \
+ NRFX_PDM_DEFAULT_EXTENDED_MCLKSRC_CONFIG \
}
/**
@@ -187,12 +212,12 @@ nrfx_err_t nrfx_pdm_buffer_set(int16_t * buffer, uint16_t buffer_length);
#ifndef NRFX_DECLARE_ONLY
NRFX_STATIC_INLINE uint32_t nrfx_pdm_task_address_get(nrf_pdm_task_t task)
{
- return nrf_pdm_task_address_get(NRF_PDM, task);
+ return nrf_pdm_task_address_get(NRF_PDM0, task);
}
NRFX_STATIC_INLINE bool nrfx_pdm_enable_check(void)
{
- return nrf_pdm_enable_check(NRF_PDM);
+ return nrf_pdm_enable_check(NRF_PDM0);
}
#endif // NRFX_DECLARE_ONLY
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power.h
index 2220fd6..d1136e5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -35,6 +35,7 @@
#include <nrfx.h>
#include <hal/nrf_power.h>
#include <nrfx_power_clock.h>
+#include "nrfx_power_compat.h"
#ifdef __cplusplus
extern "C" {
@@ -47,6 +48,29 @@ extern "C" {
* @brief POWER peripheral driver.
*/
+#if NRF_POWER_HAS_POFCON || NRFX_CHECK(NRF_REGULATORS_HAS_POFCON) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether the power failure comparator is supported. */
+#define NRFX_POWER_SUPPORTS_POFCON 1
+#else
+#define NRFX_POWER_SUPPORTS_POFCON 0
+#endif
+
+#if NRF_POWER_HAS_POFCON_VDDH || NRFX_CHECK(NRF_REGULATORS_HAS_POFCON_VDDH) || \
+ defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether the power failure comparator for VDDH is supported. */
+#define NRFX_POWER_SUPPORTS_POFCON_VDDH 1
+#else
+#define NRFX_POWER_SUPPORTS_POFCON_VDDH 0
+#endif
+
+#if NRF_POWER_HAS_DCDCEN_VDDH || NRFX_CHECK(NRF_REGULATORS_HAS_DCDCEN_VDDH) || \
+ defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether the VDDH regulator is supported. */
+#define NRFX_POWER_SUPPORTS_DCDCEN_VDDH 1
+#else
+#define NRFX_POWER_SUPPORTS_DCDCEN_VDDH 0
+#endif
+
/**
* @brief Power mode possible configurations
*/
@@ -96,7 +120,7 @@ typedef enum
NRFX_POWER_USB_STATE_CONNECTED, /**< The USB power is detected, but USB power regulator is not ready. */
NRFX_POWER_USB_STATE_READY /**< From the power viewpoint, USB is ready for working. */
}nrfx_power_usb_state_t;
-#endif /* NRF_POWER_HAS_USBREG */
+#endif // NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__)
/**
* @name Callback types
@@ -145,7 +169,7 @@ typedef struct
*/
bool dcdcen:1;
-#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__)
+#if NRFX_POWER_SUPPORTS_DCDCEN_VDDH
/**
* @brief Enable HV DCDC regulator.
*
@@ -166,10 +190,10 @@ typedef struct
typedef struct
{
nrfx_power_pofwarn_event_handler_t handler; //!< Event handler.
-#if NRF_POWER_HAS_POFCON || defined(__NRFX_DOXYGEN__)
+#if NRFX_POWER_SUPPORTS_POFCON
nrf_power_pof_thr_t thr; //!< Threshold for power failure detection
#endif
-#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__)
+#if NRFX_POWER_SUPPORTS_POFCON_VDDH
nrf_power_pof_thrvddh_t thrvddh; //!< Threshold for power failure detection on the VDDH pin.
#endif
}nrfx_power_pofwarn_config_t;
@@ -198,7 +222,7 @@ typedef struct
{
nrfx_power_usb_event_handler_t handler; //!< Event processing.
}nrfx_power_usbevt_config_t;
-#endif /* NRF_POWER_HAS_USBREG */
+#endif // NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for getting the handler of the power failure comparator.
@@ -212,7 +236,7 @@ nrfx_power_pofwarn_event_handler_t nrfx_power_pof_handler_get(void);
* @return Handler of the USB power.
*/
nrfx_power_usb_event_handler_t nrfx_power_usb_handler_get(void);
-#endif
+#endif // NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for initializing the power module driver.
@@ -235,7 +259,7 @@ nrfx_err_t nrfx_power_init(nrfx_power_config_t const * p_config);
*/
void nrfx_power_uninit(void);
-#if NRF_POWER_HAS_POFCON || defined(__NRFX_DOXYGEN__)
+#if NRFX_POWER_SUPPORTS_POFCON
/**
* @brief Function for initializing the power failure comparator.
*
@@ -271,7 +295,7 @@ void nrfx_power_pof_disable(void);
* Clears the settings of the power failure comparator.
*/
void nrfx_power_pof_uninit(void);
-#endif // NRF_POWER_HAS_POFCON || defined(__NRFX_DOXYGEN__)
+#endif // NRFX_POWER_SUPPORTS_POFCON
#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__)
/**
@@ -336,7 +360,7 @@ void nrfx_power_usbevt_uninit(void);
*/
NRFX_STATIC_INLINE nrfx_power_usb_state_t nrfx_power_usbstatus_get(void);
-#endif /* NRF_POWER_HAS_USBREG */
+#endif // NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__)
#ifndef NRFX_DECLARE_ONLY
#if NRF_POWER_HAS_USBREG
@@ -353,8 +377,8 @@ NRFX_STATIC_INLINE nrfx_power_usb_state_t nrfx_power_usbstatus_get(void)
}
return NRFX_POWER_USB_STATE_READY;
}
-#endif /* NRF_POWER_HAS_USBREG */
-#endif /* NRFX_DECLARE_ONLY */
+#endif // NRF_POWER_HAS_USBREG
+#endif // NRFX_DECLARE_ONLY
/** @} */
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_clock.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_clock.h
index c1af4bd..50b4603 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_clock.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_compat.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_compat.h
new file mode 100644
index 0000000..508a03f
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_compat.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_POWER_COMPAT_H__
+#define NRFX_POWER_COMPAT_H__
+
+/**
+ * POWER compatibility layer.
+ *
+ * The following definitions allow using of common code involving the POWER peripheral
+ * driver for different SoCs, regardless of whether certain regulator registers
+ * are located in the POWER peripheral or in separate peripherals like USBREG and REGULATORS.
+ */
+
+#if defined(REGULATORS_PRESENT)
+#include <hal/nrf_regulators.h>
+#endif
+
+#if NRF_REGULATORS_HAS_POFCON
+
+typedef nrf_regulators_pof_thr_t nrf_power_pof_thr_t;
+#define NRF_POWER_POFTHR_V19 NRF_REGULATORS_POFTHR_V19
+#define NRF_POWER_POFTHR_V20 NRF_REGULATORS_POFTHR_V20
+#define NRF_POWER_POFTHR_V21 NRF_REGULATORS_POFTHR_V21
+#define NRF_POWER_POFTHR_V22 NRF_REGULATORS_POFTHR_V22
+#define NRF_POWER_POFTHR_V23 NRF_REGULATORS_POFTHR_V23
+#define NRF_POWER_POFTHR_V24 NRF_REGULATORS_POFTHR_V24
+#define NRF_POWER_POFTHR_V25 NRF_REGULATORS_POFTHR_V25
+#define NRF_POWER_POFTHR_V26 NRF_REGULATORS_POFTHR_V26
+#define NRF_POWER_POFTHR_V27 NRF_REGULATORS_POFTHR_V27
+#define NRF_POWER_POFTHR_V28 NRF_REGULATORS_POFTHR_V28
+
+typedef nrf_regulators_pof_thrvddh_t nrf_power_pof_thrvddh_t;
+#define NRF_POWER_POFTHRVDDH_V27 NRF_REGULATORS_POFTHRVDDH_V27
+#define NRF_POWER_POFTHRVDDH_V28 NRF_REGULATORS_POFTHRVDDH_V28
+#define NRF_POWER_POFTHRVDDH_V29 NRF_REGULATORS_POFTHRVDDH_V29
+#define NRF_POWER_POFTHRVDDH_V30 NRF_REGULATORS_POFTHRVDDH_V30
+#define NRF_POWER_POFTHRVDDH_V31 NRF_REGULATORS_POFTHRVDDH_V31
+#define NRF_POWER_POFTHRVDDH_V32 NRF_REGULATORS_POFTHRVDDH_V32
+#define NRF_POWER_POFTHRVDDH_V33 NRF_REGULATORS_POFTHRVDDH_V33
+#define NRF_POWER_POFTHRVDDH_V34 NRF_REGULATORS_POFTHRVDDH_V34
+#define NRF_POWER_POFTHRVDDH_V35 NRF_REGULATORS_POFTHRVDDH_V35
+#define NRF_POWER_POFTHRVDDH_V36 NRF_REGULATORS_POFTHRVDDH_V36
+#define NRF_POWER_POFTHRVDDH_V37 NRF_REGULATORS_POFTHRVDDH_V37
+#define NRF_POWER_POFTHRVDDH_V38 NRF_REGULATORS_POFTHRVDDH_V38
+#define NRF_POWER_POFTHRVDDH_V39 NRF_REGULATORS_POFTHRVDDH_V39
+#define NRF_POWER_POFTHRVDDH_V40 NRF_REGULATORS_POFTHRVDDH_V40
+#define NRF_POWER_POFTHRVDDH_V41 NRF_REGULATORS_POFTHRVDDH_V41
+#define NRF_POWER_POFTHRVDDH_V42 NRF_REGULATORS_POFTHRVDDH_V42
+
+#endif // NRF_REGULATORS_HAS_POFCON
+
+#if defined(USBREG_PRESENT)
+#include "nrfx_usbreg.h"
+
+typedef nrfx_usbreg_event_handler_t nrfx_power_usb_event_handler_t;
+typedef nrfx_usbreg_config_t nrfx_power_usbevt_config_t;
+
+typedef nrfx_usbreg_evt_t nrfx_power_usb_evt_t;
+#define NRFX_POWER_USB_EVT_DETECTED NRFX_USBREG_EVT_DETECTED
+#define NRFX_POWER_USB_EVT_REMOVED NRFX_USBREG_EVT_REMOVED
+#define NRFX_POWER_USB_EVT_READY NRFX_USBREG_EVT_READY
+
+typedef nrfx_usbreg_state_t nrfx_power_usb_state_t;
+#define NRFX_POWER_USB_STATE_DISCONNECTED NRFX_USBREG_STATE_DISCONNECTED
+#define NRFX_POWER_USB_STATE_CONNECTED NRFX_USBREG_STATE_CONNECTED
+#define NRFX_POWER_USB_STATE_READY NRFX_USBREG_STATE_READY
+
+#define nrfx_power_usb_handler_get nrfx_usbreg_handler_get
+#define nrfx_power_usbevt_init nrfx_usbreg_init
+#define nrfx_power_usbevt_enable nrfx_usbreg_enable
+#define nrfx_power_usbevt_disable nrfx_usbreg_disable
+#define nrfx_power_usbevt_uninit nrfx_usbreg_uninit
+#define nrfx_power_usbstatus_get nrfx_usbreg_usbstatus_get
+
+#endif // defined(USBREG_PRESENT)
+
+#endif // NRFX_POWER_COMPAT_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ppi.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ppi.h
index 0696249..42693bf 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ppi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ppi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pwm.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pwm.h
index b3d4a49..a48124e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pwm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pwm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -100,6 +100,10 @@ typedef struct
uint16_t top_value; ///< Value up to which the pulse generator counter counts.
nrf_pwm_dec_load_t load_mode; ///< Mode of loading sequence data from RAM.
nrf_pwm_dec_step_t step_mode; ///< Mode of advancing the active sequence.
+ bool skip_gpio_cfg; ///< Skip the GPIO configuration
+ /**< When this flag is set, the user is responsible for
+ * providing the proper configuration of the output pins,
+ * as the driver does not touch it at all. */
} nrfx_pwm_config_t;
/**
@@ -117,19 +121,20 @@ typedef struct
* @param[in] _out_2 PWM output 2 pin.
* @param[in] _out_3 PWM output 3 pin.
*/
-#define NRFX_PWM_DEFAULT_CONFIG(_out_0, _out_1, _out_2, _out_3) \
-{ \
- .output_pins = { _out_0, \
- _out_1, \
- _out_2, \
- _out_3 \
- }, \
- .irq_priority = NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY, \
- .base_clock = NRF_PWM_CLK_1MHz, \
- .count_mode = NRF_PWM_MODE_UP, \
- .top_value = 1000, \
- .load_mode = NRF_PWM_LOAD_COMMON, \
- .step_mode = NRF_PWM_STEP_AUTO, \
+#define NRFX_PWM_DEFAULT_CONFIG(_out_0, _out_1, _out_2, _out_3) \
+{ \
+ .output_pins = { _out_0, \
+ _out_1, \
+ _out_2, \
+ _out_3 \
+ }, \
+ .irq_priority = NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY, \
+ .base_clock = NRF_PWM_CLK_1MHz, \
+ .count_mode = NRF_PWM_MODE_UP, \
+ .top_value = 1000, \
+ .load_mode = NRF_PWM_LOAD_COMMON, \
+ .step_mode = NRF_PWM_STEP_AUTO, \
+ .skip_gpio_cfg = false \
}
/** @brief PWM flags providing additional playback options. */
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qdec.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qdec.h
index 0591e73..0ac342f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qdec.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qdec.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qspi.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qspi.h
index f435738..fb48d0d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qspi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qspi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -66,7 +66,7 @@ typedef struct
* - PP opcode for writing
* - 24 bit addressing mode
* - Deep Power-down disabled
- * - clock frequency 2 MHz
+ * - clock frequency: 2 MHz for nRF52 Series, 6 MHz for nRF53 Series
* - SCK delay 5 clock ticks
* - mode 0 (data captured on the clock rising edge and transmitted on a falling edge. Clock base level is '0')
*
@@ -99,7 +99,7 @@ typedef struct
.sck_delay = 0x05, \
.dpmen = false, \
.spi_mode = NRF_QSPI_MODE_0, \
- .sck_freq = NRF_QSPI_FREQ_32MDIV16, \
+ .sck_freq = NRF_QSPI_FREQ_DIV16, \
}, \
.irq_priority = (uint8_t)NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY, \
}
@@ -329,6 +329,32 @@ nrfx_err_t nrfx_qspi_lfm_xfer(void const * p_tx_buffer,
size_t transfer_length,
bool finalize);
+#if NRF_QSPI_HAS_XIP_ENC
+/**
+ * @brief Function for setting the XIP encryption.
+ *
+ * @param[in] p_config XIP encryption configuration structure.
+ * To disable encryption, pass NULL pointer as argument.
+ *
+ * @retval NRFX_SUCCESS Operation was successful.
+ * @retval NRFX_ERROR_BUSY Driver currently handles other operation.
+ */
+nrfx_err_t nrfx_qspi_xip_encrypt(nrf_qspi_encryption_t const * p_config);
+#endif
+
+#if NRF_QSPI_HAS_DMA_ENC
+/**
+ * @brief Function for setting the EasyDMA encryption.
+ *
+ * @param[in] p_config DMA encryption configuration structure.
+ * To disable encryption, pass NULL pointer as argument.
+ *
+ * @retval NRFX_SUCCESS Operation was successful.
+ * @retval NRFX_ERROR_BUSY Driver currently handles other operation.
+ */
+nrfx_err_t nrfx_qspi_dma_encrypt(nrf_qspi_encryption_t const * p_config);
+#endif
+
/** @} */
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rng.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rng.h
index cd88f7d..ed9c70c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rng.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rng.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rtc.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rtc.h
index b641a89..93cabe3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rtc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rtc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_saadc.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_saadc.h
index 82f7d03..bf1f78f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_saadc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_saadc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spi.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spi.h
index 3dea9f0..80fab90 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -116,6 +116,7 @@ typedef struct
* - clock frequency 4 MHz
* - mode 0 enabled (SCK active high, sample on leading edge of clock)
* - MSB shifted out first
+ * - MISO pull-up disabled
*
* @param[in] _pin_sck SCK pin.
* @param[in] _pin_mosi MOSI pin.
@@ -133,6 +134,7 @@ typedef struct
.frequency = NRF_SPI_FREQ_4M, \
.mode = NRF_SPI_MODE_0, \
.bit_order = NRF_SPI_BIT_ORDER_MSB_FIRST, \
+ .miso_pull = NRF_GPIO_PIN_NOPULL, \
}
/** @brief Single transfer descriptor structure. */
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h
index 5c22db3..339ab4c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -68,6 +68,9 @@ enum {
#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
NRFX_SPIM3_INST_IDX,
#endif
+#if NRFX_CHECK(NRFX_SPIM4_ENABLED)
+ NRFX_SPIM4_INST_IDX,
+#endif
NRFX_SPIM_ENABLED_COUNT
};
#endif
@@ -391,6 +394,7 @@ void nrfx_spim_0_irq_handler(void);
void nrfx_spim_1_irq_handler(void);
void nrfx_spim_2_irq_handler(void);
void nrfx_spim_3_irq_handler(void);
+void nrfx_spim_4_irq_handler(void);
#ifdef __cplusplus
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spis.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spis.h
index 442901f..9c92503 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spis.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spis.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_systick.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_systick.h
index 5e8feda..0d1b9e1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_systick.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_systick.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_temp.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_temp.h
index 95ac547..17d962f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_temp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_temp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_timer.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_timer.h
index 9da6b5c..3fcbbbb 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_timer.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_timer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi.h
index ca1bd5a..3595a6e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -117,7 +117,8 @@ typedef enum
NRFX_TWI_EVT_DONE, ///< Transfer completed event.
NRFX_TWI_EVT_ADDRESS_NACK, ///< Error event: NACK received after sending the address.
NRFX_TWI_EVT_DATA_NACK, ///< Error event: NACK received after sending a data byte.
- NRFX_TWI_EVT_OVERRUN ///< Error event: The unread data is replaced by new data.
+ NRFX_TWI_EVT_OVERRUN, ///< Error event: The unread data is replaced by new data.
+ NRFX_TWI_EVT_BUS_ERROR ///< Error event: An unexpected transition occurred on the bus.
} nrfx_twi_evt_type_t;
/** @brief TWI master driver transfer types. */
@@ -265,7 +266,7 @@ void nrfx_twi_disable(nrfx_twi_t const * p_instance);
* @retval NRFX_SUCCESS The procedure is successful.
* @retval NRFX_ERROR_BUSY The driver is not ready for a new transfer.
* @retval NRFX_ERROR_NOT_SUPPORTED The provided parameters are not supported.
- * @retval NRFX_ERROR_INTERNAL An error is detected by hardware.
+ * @retval NRFX_ERROR_INTERNAL An unexpected transition occurred on the bus.
* @retval NRFX_ERROR_INVALID_STATE Other direction of transaction is suspended on the bus.
* @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN The unread data is replaced by new data (TXRX and RX)
* @retval NRFX_ERROR_DRV_TWI_ERR_ANACK Negative acknowledgement (NACK) is received after sending
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi_twim.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi_twim.h
index 1c6ebcd..1f62c62 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi_twim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi_twim.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twim.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twim.h
index 78bc802..94ba080 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twim.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -109,17 +109,19 @@ typedef struct
}
/** @brief Flag indicating that TX buffer address will be incremented after the transfer. */
-#define NRFX_TWIM_FLAG_TX_POSTINC (1UL << 0)
+#define NRFX_TWIM_FLAG_TX_POSTINC (1UL << 0)
/** @brief Flag indicating that RX buffer address will be incremented after the transfer. */
-#define NRFX_TWIM_FLAG_RX_POSTINC (1UL << 1)
+#define NRFX_TWIM_FLAG_RX_POSTINC (1UL << 1)
/** @brief Flag indicating that the interrupt after each transfer will be suppressed, and the event handler will not be called. */
-#define NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2)
+#define NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2)
/** @brief Flag indicating that the transfer will be set up, but not started. */
-#define NRFX_TWIM_FLAG_HOLD_XFER (1UL << 3)
+#define NRFX_TWIM_FLAG_HOLD_XFER (1UL << 3)
/** @brief Flag indicating that the transfer will be executed multiple times. */
-#define NRFX_TWIM_FLAG_REPEATED_XFER (1UL << 4)
+#define NRFX_TWIM_FLAG_REPEATED_XFER (1UL << 4)
/** @brief Flag indicating that the TX transfer will not end with a stop condition. */
-#define NRFX_TWIM_FLAG_TX_NO_STOP (1UL << 5)
+#define NRFX_TWIM_FLAG_TX_NO_STOP (1UL << 5)
+/** @brief Flag indicating that checks for spurious STOP condition will not be performed. */
+#define NRFX_TWIM_FLAG_NO_SPURIOUS_STOP_CHECK (1UL << 6)
/** @brief TWI master driver event types. */
typedef enum
@@ -272,6 +274,10 @@ void nrfx_twim_disable(nrfx_twim_t const * p_instance);
* the driver does not set the driver instance into busy state, so you must ensure that the next transfers are set up
* when TWIM is not active.
* - @ref NRFX_TWIM_FLAG_TX_NO_STOP - No stop condition after the TX transfer.
+ * - @ref NRFX_TWIM_FLAG_NO_SPURIOUS_STOP_CHECK - Checks for spurious STOP conditions are disabled.
+ * Used together with @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER can result in lower power consumption
+ * when transfers are triggered externally and CPU is sleeping.
+ * Use only with I2C standard-compliant slave devices.
*
* @note
* Some flag combinations are invalid:
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twis.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twis.h
index cf6833f..9fe599c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twis.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twis.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uart.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uart.h
index 8f2105a..5cd19be 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uart.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uart.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h
index 48945fa..bfba1f8 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_usbd.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_usbd.h
index 1069df4..a8e36c6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_usbd.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_usbd.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_usbreg.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_usbreg.h
new file mode 100644
index 0000000..a9a67d0
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_usbreg.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_USBREG_H__
+#define NRFX_USBREG_H__
+
+#include <nrfx.h>
+#include <hal/nrf_usbreg.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfx_usbreg USBREG driver
+ * @{
+ * @ingroup nrf_usbd
+ * @ingroup nrf_power
+ * @brief USB regulators (USBREG) peripheral driver.
+ */
+
+/** @brief Events from USB power system */
+typedef enum {
+ NRFX_USBREG_EVT_DETECTED, /**< USB power detected on the connector (plugged in). */
+ NRFX_USBREG_EVT_REMOVED, /**< USB power removed from the connector. */
+ NRFX_USBREG_EVT_READY /**< USB power regulator ready. */
+} nrfx_usbreg_evt_t;
+
+/**
+ * @brief USB power state
+ *
+ * The single enumerator that holds all data about current state of USB
+ * related POWER.
+ *
+ * Organized this way that higher power state has higher numeric value
+ */
+typedef enum {
+ NRFX_USBREG_STATE_DISCONNECTED, /**< No power on USB lines detected. */
+ NRFX_USBREG_STATE_CONNECTED, /**< The USB power is detected, but USB power regulator is not ready. */
+ NRFX_USBREG_STATE_READY /**< From the power viewpoint, USB is ready for working. */
+} nrfx_usbreg_state_t;
+
+/**
+ * @brief Event handler for the USB-related power events.
+ *
+ * @param event Event type
+ */
+typedef void (*nrfx_usbreg_event_handler_t)(nrfx_usbreg_evt_t event);
+
+/**
+ * @brief The configuration of the USB-related power events.
+ *
+ * Configuration used to enable and configure USB power event handling.
+ */
+typedef struct
+{
+ nrfx_usbreg_event_handler_t handler; //!< Event processing.
+ uint8_t irq_priority; //!< Priority of the USBREG interrupt.
+} nrfx_usbreg_config_t;
+
+/**
+ * @brief Function for getting the USBREG handler.
+ *
+ * @return Handler of the USB power.
+ */
+nrfx_usbreg_event_handler_t nrfx_usbreg_handler_get(void);
+
+/**
+ * @brief Function for initializing the processing of USBREG events.
+ *
+ * Configures and sets up the USB power event processing.
+ *
+ * @param[in] p_config Configuration structure. Must not be NULL.
+ *
+ * @sa nrfx_usbreg_uninit
+ */
+void nrfx_usbreg_init(nrfx_usbreg_config_t const *p_config);
+
+/** @brief Function for enabling the processing of USBREG events. */
+void nrfx_usbreg_enable(void);
+
+/** @brief Function for disabling the processing of USBREG events. */
+void nrfx_usbreg_disable(void);
+
+/**
+ * @brief Function for uninitalizing the processing of USBREG events.
+ *
+ * @sa nrfx_usbreg_init
+ */
+void nrfx_usbreg_uninit(void);
+
+/**
+ * @brief Function for getting the status of USBREG.
+ *
+ * @return Current USB power status.
+ */
+NRFX_STATIC_INLINE nrfx_usbreg_state_t nrfx_usbreg_usbstatus_get(void);
+
+#ifndef NRFX_DECLARE_ONLY
+NRFX_STATIC_INLINE nrfx_usbreg_state_t nrfx_usbreg_usbstatus_get(void)
+{
+ uint32_t status = nrf_usbreg_status_get(NRF_USBREGULATOR);
+ if (0 == (status & NRF_USBREG_STATUS_VBUSDETECT_MASK))
+ {
+ return NRFX_USBREG_STATE_DISCONNECTED;
+ }
+ if (0 == (status & NRF_USBREG_STATUS_OUTPUTRDY_MASK))
+ {
+ return NRFX_USBREG_STATE_CONNECTED;
+ }
+ return NRFX_USBREG_STATE_READY;
+}
+#endif // NRFX_DECLARE_ONLY
+
+/** @} */
+
+void nrfx_usbreg_irq_handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_USBREG_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_wdt.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_wdt.h
index fc46857..9866c29 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_wdt.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_wdt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,10 +39,6 @@
extern "C" {
#endif
-#ifndef NRF_WDT0
-#define NRF_WDT0 NRF_WDT
-#endif
-
/**
* @defgroup nrfx_wdt WDT driver
* @{
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_common.h b/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_common.h
index 320fb29..50ce150 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_common.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_errors.h b/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_errors.h
index 35645fa..be360f7 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_errors.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_errors.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_adc.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_adc.c
index 6dfe7c8..fbcc9b8 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_adc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_adc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c
index 4659421..593201f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -34,6 +34,7 @@
#if NRFX_CHECK(NRFX_CLOCK_ENABLED)
#include <nrfx_clock.h>
+#include <nrf_erratas.h>
#define NRFX_LOG_MODULE CLOCK
#include <nrfx_log.h>
@@ -42,13 +43,6 @@
extern bool nrfx_power_irq_enabled;
#endif
-#define EVT_TO_STR(event) \
- (event == NRF_CLOCK_EVENT_HFCLKSTARTED ? "NRF_CLOCK_EVENT_HFCLKSTARTED" : \
- (event == NRF_CLOCK_EVENT_LFCLKSTARTED ? "NRF_CLOCK_EVENT_LFCLKSTARTED" : \
- (event == NRF_CLOCK_EVENT_DONE ? "NRF_CLOCK_EVENT_DONE" : \
- (event == NRF_CLOCK_EVENT_CTTO ? "NRF_CLOCK_EVENT_CTTO" : \
- "UNKNOWN EVENT"))))
-
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
#if (NRF_CLOCK_HAS_CALIBRATION == 0)
#error "Calibration is not available in the SoC that is used."
@@ -180,7 +174,12 @@ void nrfx_clock_enable(void)
NRFX_ASSERT(m_clock_cb.module_initialized);
nrfx_power_clock_irq_init();
nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC);
-
+#if NRF_CLOCK_HAS_HFCLKSRC
+ nrf_clock_hf_src_set(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY);
+#endif
+#if NRF_CLOCK_HAS_HFCLK192M
+ nrf_clock_hfclk192m_src_set(NRF_CLOCK, (nrf_clock_hfclk_t)NRFX_CLOCK_CONFIG_HFCLK192M_SRC);
+#endif
#if NRFX_CHECK(NRFX_POWER_ENABLED)
nrfx_clock_irq_enabled = true;
#endif
@@ -202,8 +201,10 @@ void nrfx_clock_disable(void)
CLOCK_INTENSET_LFCLKSTARTED_Msk |
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
CLOCK_INTENSET_DONE_Msk |
+#if NRF_HAS_CALIBRATION_TIMER
CLOCK_INTENSET_CTTO_Msk |
#endif
+#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
0);
#if NRFX_CHECK(NRFX_POWER_ENABLED)
nrfx_clock_irq_enabled = false;
@@ -214,49 +215,97 @@ void nrfx_clock_disable(void)
void nrfx_clock_uninit(void)
{
NRFX_ASSERT(m_clock_cb.module_initialized);
- nrfx_clock_lfclk_stop();
- nrfx_clock_hfclk_stop();
+ nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
+ nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
+#if NRF_CLOCK_HAS_HFCLK192M
+ nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK192M);
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLKAUDIO);
+#endif
m_clock_cb.module_initialized = false;
NRFX_LOG_INFO("Uninitialized.");
}
-void nrfx_clock_lfclk_start(void)
+void nrfx_clock_start(nrf_clock_domain_t domain)
{
NRFX_ASSERT(m_clock_cb.module_initialized);
- nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED);
- nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK);
-
+ switch (domain)
+ {
+ case NRF_CLOCK_DOMAIN_LFCLK:
+ nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED);
+ nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK);
#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)
- nrfx_clock_anomaly_132();
+ nrfx_clock_anomaly_132();
#endif
-
- nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTART);
-}
-
-void nrfx_clock_lfclk_stop(void)
-{
- NRFX_ASSERT(m_clock_cb.module_initialized);
- nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTOP);
- while (nrf_clock_lf_is_running(NRF_CLOCK))
- {}
-}
-
-void nrfx_clock_hfclk_start(void)
-{
- NRFX_ASSERT(m_clock_cb.module_initialized);
- nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
- nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);
- nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTART);
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTART);
+ break;
+ case NRF_CLOCK_DOMAIN_HFCLK:
+ nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
+ nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTART);
+ break;
+#if NRF_CLOCK_HAS_HFCLK192M
+ case NRF_CLOCK_DOMAIN_HFCLK192M:
+ nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED);
+ nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLK192MSTART);
+ break;
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
+ nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED);
+ nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK);
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKAUDIOSTART);
+ break;
+#endif
+ default:
+ NRFX_ASSERT(0);
+ break;
+ }
}
-void nrfx_clock_hfclk_stop(void)
+void nrfx_clock_stop(nrf_clock_domain_t domain)
{
NRFX_ASSERT(m_clock_cb.module_initialized);
- nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
- while (nrf_clock_hf_is_running(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY))
- {}
+ switch (domain)
+ {
+ case NRF_CLOCK_DOMAIN_LFCLK:
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTOP);
+ break;
+ case NRF_CLOCK_DOMAIN_HFCLK:
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
+ break;
+#if NRF_CLOCK_HAS_HFCLK192M
+ case NRF_CLOCK_DOMAIN_HFCLK192M:
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLK192MSTOP);
+ break;
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKAUDIOSTOP);
+ break;
+#endif
+ default:
+ NRFX_ASSERT(0);
+ return;
+ }
+ if (domain == NRF_CLOCK_DOMAIN_HFCLK)
+ {
+ nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
+ while (nrfx_clock_is_running(domain, &clk_src) && (clk_src == NRF_CLOCK_HFCLK_HIGH_ACCURACY))
+ {}
+ }
+ else
+ {
+ while (nrfx_clock_is_running(domain, NULL))
+ {}
+ }
#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
- m_clock_cb.hfclk_started = false;
+ if (domain == NRF_CLOCK_DOMAIN_HFCLK)
+ {
+ m_clock_cb.hfclk_started = false;
+ }
#endif
}
@@ -265,12 +314,18 @@ nrfx_err_t nrfx_clock_calibration_start(void)
nrfx_err_t err_code = NRFX_SUCCESS;
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
- if (nrfx_clock_hfclk_is_running() == false)
+ nrf_clock_hfclk_t clk_src;
+ if (!nrfx_clock_is_running(NRF_CLOCK_DOMAIN_HFCLK, &clk_src))
+ {
+ return NRFX_ERROR_INVALID_STATE;
+ }
+
+ if (clk_src != NRF_CLOCK_HFCLK_HIGH_ACCURACY)
{
return NRFX_ERROR_INVALID_STATE;
}
- if (nrfx_clock_lfclk_is_running() == false)
+ if (!nrfx_clock_is_running(NRF_CLOCK_DOMAIN_LFCLK, NULL))
{
return NRFX_ERROR_INVALID_STATE;
}
@@ -310,7 +365,7 @@ nrfx_err_t nrfx_clock_is_calibrating(void)
void nrfx_clock_calibration_timer_start(uint8_t interval)
{
-#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
+#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) && NRF_CLOCK_HAS_CALIBRATION_TIMER
nrf_clock_cal_timer_timeout_set(NRF_CLOCK, interval);
nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO);
nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK);
@@ -320,18 +375,80 @@ void nrfx_clock_calibration_timer_start(uint8_t interval)
void nrfx_clock_calibration_timer_stop(void)
{
-#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
+#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) && NRF_CLOCK_HAS_CALIBRATION_TIMER
nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK);
nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_CTSTOP);
#endif
}
+#if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK192M
+nrfx_err_t nrfx_clock_divider_set(nrf_clock_domain_t domain,
+ nrf_clock_hfclk_div_t div)
+{
+ switch(domain)
+ {
+#if NRF_CLOCK_HAS_HFCLK_DIV
+ case NRF_CLOCK_DOMAIN_HFCLK:
+ switch (div)
+ {
+ case NRF_CLOCK_HFCLK_DIV_2:
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (nrf53_errata_4())
+ {
+ __DSB();
+ }
+ nrf_clock_hfclk_div_set(NRF_CLOCK, div);
+ if (nrf53_errata_4())
+ {
+ *(volatile uint32_t *)0x5084450C = 0x0;
+ *(volatile uint32_t *)0x50026548 = 0x0;
+ *(volatile uint32_t *)0x50081EE4 = 0x0D;
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+ break;
+ case NRF_CLOCK_HFCLK_DIV_1:
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (nrf53_errata_4())
+ {
+ __DSB();
+ *(volatile uint32_t *)0x5084450C = 0x4040;
+ *(volatile uint32_t *)0x50026548 = 0x40;
+ *(volatile uint32_t *)0x50081EE4 = 0x4D;
+ }
+ nrf_clock_hfclk_div_set(NRF_CLOCK, div);
+ NRFX_CRITICAL_SECTION_EXIT();
+ break;
+ default:
+ return NRFX_ERROR_INVALID_PARAM;
+ }
+ SystemCoreClockUpdate();
+ return NRFX_SUCCESS;
+#endif
+#if NRF_CLOCK_HAS_HFCLK192M
+ case NRF_CLOCK_DOMAIN_HFCLK192M:
+ if (div > NRF_CLOCK_HFCLK_DIV_4)
+ {
+ return NRFX_ERROR_INVALID_PARAM;
+ }
+ else
+ {
+ nrf_clock_hfclk192m_div_set(NRF_CLOCK, div);
+ }
+ return NRFX_SUCCESS;
+#endif
+ default:
+ NRFX_ASSERT(0);
+ return NRFX_ERROR_NOT_SUPPORTED;
+ }
+}
+#endif
+
void nrfx_clock_irq_handler(void)
{
if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
{
nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
- NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_HFCLKSTARTED));
+ NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED");
nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);
#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
@@ -347,21 +464,23 @@ void nrfx_clock_irq_handler(void)
if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
{
nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED);
- NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_LFCLKSTARTED));
+ NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");
nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK);
m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
}
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
+#if NRF_CLOCK_HAS_CALIBRATION_TIMER
if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO))
{
nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO);
- NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_CTTO));
+ NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_CTTO");
nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK);
m_clock_cb.event_handler(NRFX_CLOCK_EVT_CTTO);
}
+#endif // NRF_CLOCK_HAS_CALIBRATION_TIMER
if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_DONE))
{
@@ -369,12 +488,34 @@ void nrfx_clock_irq_handler(void)
*(volatile uint32_t *)0x40000C34 = 0x00000000;
#endif
nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_DONE);
- NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_DONE));
+ NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_DONE");
nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_DONE_MASK);
m_clock_cb.cal_state = CAL_STATE_IDLE;
m_clock_cb.event_handler(NRFX_CLOCK_EVT_CAL_DONE);
}
-#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
+#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
+
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED))
+ {
+ nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED);
+ NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED");
+ nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK);
+
+ m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLKAUDIO_STARTED);
+ }
+#endif
+
+#if NRF_CLOCK_HAS_HFCLK192M
+ if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED))
+ {
+ nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED);
+ NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLK192MSTARTED");
+ nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);
+
+ m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
+ }
+#endif
}
#endif // NRFX_CHECK(NRFX_CLOCK_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_comp.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_comp.c
index c8ebb4d..84c23d1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_comp.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_comp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_dppi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_dppi.c
index 3c7df6a..a845867 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_dppi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_dppi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_egu.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_egu.c
index 9948f39..07fccaf 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_egu.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_egu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c
index 515b289..73f8e44 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -44,11 +44,11 @@
#define PIN_NOT_USED (-1)
#define PIN_USED (-2)
#define NO_CHANNELS (-1)
-#define SENSE_FIELD_POS (6)
-#define SENSE_FIELD_MASK (0xC0)
+#define POLARITY_FIELD_POS (6)
+#define POLARITY_FIELD_MASK (0xC0)
/* Check if every pin can be encoded on provided number of bits. */
-NRFX_STATIC_ASSERT(NUMBER_OF_PINS <= (1 << SENSE_FIELD_POS));
+NRFX_STATIC_ASSERT(NUMBER_OF_PINS <= (1 << POLARITY_FIELD_POS));
/*lint -save -e571*/ /* Suppress "Warning 571: Suspicious cast" */
typedef struct
@@ -145,6 +145,17 @@ static nrfx_gpiote_evt_handler_t channel_handler_get(uint32_t channel)
return m_cb.handlers[channel];
}
+static nrfx_gpiote_pin_t port_handler_pin_get(uint32_t handler_idx)
+{
+ uint8_t pin_and_polarity = (uint8_t)m_cb.port_handlers_pins[handler_idx];
+ return (nrfx_gpiote_pin_t)(pin_and_polarity & ~POLARITY_FIELD_MASK);
+}
+
+static nrf_gpiote_polarity_t port_handler_polarity_get(uint32_t handler_idx)
+{
+ uint8_t pin_and_polarity = (uint8_t)m_cb.port_handlers_pins[handler_idx];
+ return (nrf_gpiote_polarity_t)((pin_and_polarity & POLARITY_FIELD_MASK) >> POLARITY_FIELD_POS);
+}
static int8_t channel_port_alloc(uint32_t pin, nrfx_gpiote_evt_handler_t handler, bool channel)
{
@@ -522,7 +533,7 @@ nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin,
else
{
m_cb.port_handlers_pins[channel - GPIOTE_CH_NUM] |= (p_config->sense) <<
- SENSE_FIELD_POS;
+ POLARITY_FIELD_POS;
}
}
else
@@ -541,10 +552,8 @@ void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable)
NRFX_ASSERT(pin_in_use_by_gpiote(pin));
if (pin_in_use_by_port(pin))
{
- uint8_t pin_and_sense = (uint8_t)
- m_cb.port_handlers_pins[channel_port_get(pin) - GPIOTE_CH_NUM];
nrf_gpiote_polarity_t polarity =
- (nrf_gpiote_polarity_t)(pin_and_sense >> SENSE_FIELD_POS);
+ port_handler_polarity_get(channel_port_get(pin) - GPIOTE_CH_NUM);
nrf_gpio_pin_sense_t sense;
if (polarity == NRF_GPIOTE_POLARITY_TOGGLE)
{
@@ -643,6 +652,159 @@ uint32_t nrfx_gpiote_in_event_addr_get(nrfx_gpiote_pin_t pin)
return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}
+#if defined(NRF_GPIO_LATCH_PRESENT)
+static bool latch_pending_read_and_check(uint32_t * latch)
+{
+ nrf_gpio_latches_read_and_clear(0, GPIO_COUNT, latch);
+
+ for (uint32_t port_idx = 0; port_idx < GPIO_COUNT; port_idx++)
+ {
+ if (latch[port_idx])
+ {
+ /* If any of the latch bits is still set, it means another edge has been captured
+ * before or during the interrupt processing. Therefore event-processing loop
+ * should be executed again. */
+ return true;
+ }
+ }
+ return false;
+}
+
+static void port_event_handle(uint32_t * latch)
+{
+ do {
+ for (uint32_t i = 0; i < NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS; i++)
+ {
+ if (m_cb.port_handlers_pins[i] == PIN_NOT_USED)
+ {
+ continue;
+ }
+
+ /* Process pin further only if LATCH bit associated with this pin was set. */
+ nrfx_gpiote_pin_t pin = port_handler_pin_get(i);
+ if (nrf_bitmask_bit_is_set(pin, latch))
+ {
+ nrf_gpiote_polarity_t polarity = port_handler_polarity_get(i);
+ nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin);
+
+ NRFX_LOG_DEBUG("PORT event for pin: %d, polarity: %d.", pin, polarity);
+
+ /* Reconfigure sense to the opposite level, so the internal PINx.DETECT signal
+ * can be deasserted. Therefore PORT event generated again,
+ * unless some other PINx.DETECT signal is still active. */
+ nrf_gpio_pin_sense_t next_sense =
+ (sense == NRF_GPIO_PIN_SENSE_HIGH) ? NRF_GPIO_PIN_SENSE_LOW :
+ NRF_GPIO_PIN_SENSE_HIGH;
+ nrf_gpio_cfg_sense_set(pin, next_sense);
+
+ /* Try to clear LATCH bit corresponding to currently processed pin.
+ * This may not succeed if the pin's state changed during the interrupt processing
+ * and now it matches the new sense configuration. In such case,
+ * the pin will be processed again in another iteration of the outer loop. */
+ nrf_gpio_pin_latch_clear(pin);
+
+ /* Invoke user handler only if the sensed pin level
+ * matches its polarity configuration. */
+ nrfx_gpiote_evt_handler_t handler =
+ channel_handler_get((uint32_t)channel_port_get(pin));
+ if (handler &&
+ ((polarity == NRF_GPIOTE_POLARITY_TOGGLE) ||
+ (sense == NRF_GPIO_PIN_SENSE_HIGH && polarity == NRF_GPIOTE_POLARITY_LOTOHI) ||
+ (sense == NRF_GPIO_PIN_SENSE_LOW && polarity == NRF_GPIOTE_POLARITY_HITOLO)))
+ {
+ handler(pin, polarity);
+ }
+ }
+ }
+ } while (latch_pending_read_and_check(latch));
+}
+
+#else
+
+static bool input_read_and_check(uint32_t * input, uint32_t * pins_to_check)
+{
+ bool process_inputs_again;
+ uint32_t new_input[GPIO_COUNT];
+
+ nrf_gpio_ports_read(0, GPIO_COUNT, new_input);
+
+ process_inputs_again = false;
+ for (uint32_t port_idx = 0; port_idx < GPIO_COUNT; port_idx++)
+ {
+ /* Execute XOR to find out which inputs have changed. */
+ uint32_t input_diff = input[port_idx] ^ new_input[port_idx];
+ input[port_idx] = new_input[port_idx];
+ if (input_diff)
+ {
+ /* If any differences among inputs were found, mark those pins
+ * to be processed again. */
+ pins_to_check[port_idx] = input_diff;
+ process_inputs_again = true;
+ }
+ else
+ {
+ pins_to_check[port_idx] = 0;
+ }
+ }
+ return process_inputs_again;
+}
+
+static void port_event_handle(uint32_t * input)
+{
+ uint32_t pins_to_check[GPIO_COUNT];
+
+ for (uint32_t port_idx = 0; port_idx < GPIO_COUNT; port_idx++)
+ {
+ pins_to_check[port_idx] = 0xFFFFFFFF;
+ }
+
+ do {
+ for (uint32_t i = 0; i < NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS; i++)
+ {
+ if (m_cb.port_handlers_pins[i] == PIN_NOT_USED)
+ {
+ continue;
+ }
+
+ nrfx_gpiote_pin_t pin = port_handler_pin_get(i);
+ if (nrf_bitmask_bit_is_set(pin, pins_to_check))
+ {
+ nrf_gpiote_polarity_t polarity = port_handler_polarity_get(i);
+ nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin);
+ bool pin_state = nrf_bitmask_bit_is_set(pin, input);
+
+ /* Process pin further only if its state matches its sense level. */
+ if ((pin_state && (sense == NRF_GPIO_PIN_SENSE_HIGH)) ||
+ (!pin_state && (sense == NRF_GPIO_PIN_SENSE_LOW)) )
+ {
+ /* Reconfigure sense to the opposite level, so the internal PINx.DETECT signal
+ * can be deasserted. Therefore PORT event can be generated again,
+ * unless some other PINx.DETECT signal is still active. */
+ NRFX_LOG_DEBUG("PORT event for pin: %d, polarity: %d.", pin, polarity);
+ nrf_gpio_pin_sense_t next_sense =
+ (sense == NRF_GPIO_PIN_SENSE_HIGH) ? NRF_GPIO_PIN_SENSE_LOW :
+ NRF_GPIO_PIN_SENSE_HIGH;
+ nrf_gpio_cfg_sense_set(pin, next_sense);
+
+ /* Invoke user handler only if the sensed pin level
+ * matches its polarity configuration. */
+ nrfx_gpiote_evt_handler_t handler =
+ channel_handler_get((uint32_t)channel_port_get(pin));
+ if (handler &&
+ ((polarity == NRF_GPIOTE_POLARITY_TOGGLE) ||
+ (sense == NRF_GPIO_PIN_SENSE_HIGH &&
+ polarity == NRF_GPIOTE_POLARITY_LOTOHI) ||
+ (sense == NRF_GPIO_PIN_SENSE_LOW &&
+ polarity == NRF_GPIOTE_POLARITY_HITOLO)))
+ {
+ handler(pin, polarity);
+ }
+ }
+ }
+ }
+ } while (input_read_and_check(input, pins_to_check));
+}
+#endif // defined(NRF_GPIO_LATCH_PRESENT)
void nrfx_gpiote_irq_handler(void)
{
@@ -674,7 +836,11 @@ void nrfx_gpiote_irq_handler(void)
{
nrf_gpiote_event_clear(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT);
status |= (uint32_t)NRF_GPIOTE_INT_PORT_MASK;
+#if defined(NRF_GPIO_LATCH_PRESENT)
+ nrf_gpio_latches_read_and_clear(0, GPIO_COUNT, input);
+#else
nrf_gpio_ports_read(0, GPIO_COUNT, input);
+#endif
}
/* Process pin events. */
@@ -700,107 +866,10 @@ void nrfx_gpiote_irq_handler(void)
}
}
+ /* Process PORT event. */
if (status & (uint32_t)NRF_GPIOTE_INT_PORT_MASK)
{
- /* Process port event. */
- uint32_t port_idx;
- uint8_t repeat = 0;
- uint32_t toggle_mask[GPIO_COUNT] = {0};
- uint32_t pins_to_check[GPIO_COUNT];
-
- // Faster way of doing memset because in interrupt context.
- for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++)
- {
- pins_to_check[port_idx] = 0xFFFFFFFF;
- }
-
- do
- {
- repeat = 0;
-
- for (i = 0; i < NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS; i++)
- {
- uint8_t pin_and_sense = (uint8_t)m_cb.port_handlers_pins[i];
- nrfx_gpiote_pin_t pin = (pin_and_sense & ~SENSE_FIELD_MASK);
-
- if ((m_cb.port_handlers_pins[i] != PIN_NOT_USED)
- && nrf_bitmask_bit_is_set(pin, pins_to_check))
- {
- nrf_gpiote_polarity_t polarity =
- (nrf_gpiote_polarity_t)((pin_and_sense &
- SENSE_FIELD_MASK) >> SENSE_FIELD_POS);
- nrfx_gpiote_evt_handler_t handler =
- channel_handler_get((uint32_t)channel_port_get(pin));
- if (handler || (polarity == NRF_GPIOTE_POLARITY_TOGGLE))
- {
- if (polarity == NRF_GPIOTE_POLARITY_TOGGLE)
- {
- nrf_bitmask_bit_set(pin, toggle_mask);
- }
- nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin);
- uint32_t pin_state = nrf_bitmask_bit_is_set(pin, input);
- if ((pin_state && (sense == NRF_GPIO_PIN_SENSE_HIGH)) ||
- (!pin_state && (sense == NRF_GPIO_PIN_SENSE_LOW)) )
- {
- NRFX_LOG_DEBUG("PORT event for pin: %d, polarity: %d.", pin, polarity);
- if (polarity == NRF_GPIOTE_POLARITY_TOGGLE)
- {
- nrf_gpio_pin_sense_t next_sense =
- (sense == NRF_GPIO_PIN_SENSE_HIGH) ?
- NRF_GPIO_PIN_SENSE_LOW :
- NRF_GPIO_PIN_SENSE_HIGH;
- nrf_gpio_cfg_sense_set(pin, next_sense);
- ++repeat;
-
- }
- if (handler)
- {
- handler(pin, polarity);
- }
- }
- }
- }
- }
-
- if (repeat)
- {
- // When one of the pins in low-accuracy and toggle mode becomes active,
- // it's sense mode is inverted to clear the internal SENSE signal.
- // State of any other enabled low-accuracy input in toggle mode must be checked
- // explicitly, because it does not trigger the interrput when SENSE signal is active.
- // For more information about SENSE functionality, refer to Product Specification.
-
- uint32_t new_input[GPIO_COUNT];
- bool input_unchanged = true;
- nrf_gpio_ports_read(0, GPIO_COUNT, new_input);
-
- // Faster way of doing memcmp because in interrupt context.
- for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++)
- {
- if (new_input[port_idx] != input[port_idx])
- {
- input_unchanged = false;
- break;
- }
- }
-
- if (input_unchanged)
- {
- // No change.
- repeat = 0;
- }
- else
- {
- // Faster way of doing memcpy because in interrupt context.
- for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++)
- {
- input[port_idx] = new_input[port_idx];
- pins_to_check[port_idx] = toggle_mask[port_idx];
- }
- }
- }
- }
- while (repeat);
+ port_event_handle(input);
}
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c
index d90d6f0..6072083 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -167,6 +167,10 @@ nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config,
NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
}
+
+#if NRF_I2S_HAS_CLKCONFIG
+ nrf_i2s_clk_configure(NRF_I2S, p_config->clksrc, p_config->enable_bypass);
+#endif
configure_pins(p_config);
m_cb.handler = handler;
@@ -377,12 +381,18 @@ void nrfx_i2s_irq_handler(void)
nrf_i2s_disable(NRF_I2S);
// When stopped, release all buffers, including these scheduled for
- // the next transfer.
+ // the next part of the transfer, and signal that the transfer has
+ // finished.
+
m_cb.handler(&m_cb.current_buffers, 0);
- m_cb.handler(&m_cb.next_buffers, 0);
+ // Change the state of the driver before calling the handler with
+ // the flag signaling that the transfer has finished, so that it is
+ // possible to start a new transfer directly from the handler function.
m_cb.state = NRFX_DRV_STATE_INITIALIZED;
NRFX_LOG_INFO("Stopped.");
+
+ m_cb.handler(&m_cb.next_buffers, NRFX_I2S_STATUS_TRANSFER_STOPPED);
}
else
{
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ipc.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ipc.c
index dcfd28a..f47b70c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ipc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ipc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_lpcomp.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_lpcomp.c
index 9e654e4..bbc51c8 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_lpcomp.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_lpcomp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c
index fa8116e..952ba64 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nvmc.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nvmc.c
index f4e93ca..7eff994 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nvmc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nvmc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -43,6 +43,13 @@
*/
#define NVMC_BYTES_IN_WORD 4
+/** Value representing non-volatile memory (NVM) base address. */
+#if defined(NRF5340_XXAA_NETWORK)
+ #define NVMC_FLASH_BASE_ADDRESS 0x01000000uL
+#else
+ #define NVMC_FLASH_BASE_ADDRESS 0
+#endif
+
/**
* Value representing non-volatile memory (NVM) page count.
*
@@ -211,7 +218,7 @@ static void nvmc_words_write(uint32_t addr, void const * src, uint32_t num_words
nrfx_err_t nrfx_nvmc_page_erase(uint32_t addr)
{
- NRFX_ASSERT(addr < flash_total_size_get());
+ NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
if (!is_page_aligned_check(addr))
{
@@ -253,7 +260,7 @@ void nrfx_nvmc_all_erase(void)
#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
nrfx_err_t nrfx_nvmc_page_partial_erase_init(uint32_t addr, uint32_t duration_ms)
{
- NRFX_ASSERT(addr < flash_total_size_get());
+ NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
if (!is_page_aligned_check(addr))
{
@@ -299,7 +306,7 @@ bool nrfx_nvmc_page_partial_erase_continue(void)
bool nrfx_nvmc_byte_writable_check(uint32_t addr, uint8_t val_to_check)
{
- NRFX_ASSERT(addr < flash_total_size_get());
+ NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
uint8_t val_on_addr = *(uint8_t const *)addr;
return (val_to_check & val_on_addr) == val_to_check;
@@ -307,7 +314,7 @@ bool nrfx_nvmc_byte_writable_check(uint32_t addr, uint8_t val_to_check)
bool nrfx_nvmc_word_writable_check(uint32_t addr, uint32_t val_to_check)
{
- NRFX_ASSERT(addr < flash_total_size_get());
+ NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));
uint32_t val_on_addr = *(uint32_t const *)addr;
@@ -323,7 +330,7 @@ void nrfx_nvmc_byte_write(uint32_t addr, uint8_t value)
void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
{
- NRFX_ASSERT(addr < flash_total_size_get());
+ NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));
nvmc_write_mode_set();
@@ -335,7 +342,7 @@ void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
void nrfx_nvmc_bytes_write(uint32_t addr, void const * src, uint32_t num_bytes)
{
- NRFX_ASSERT(addr < flash_total_size_get());
+ NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
nvmc_write_mode_set();
@@ -397,7 +404,7 @@ void nrfx_nvmc_bytes_write(uint32_t addr, void const * src, uint32_t num_bytes)
void nrfx_nvmc_words_write(uint32_t addr, void const * src, uint32_t num_words)
{
- NRFX_ASSERT(addr < flash_total_size_get());
+ NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));
NRFX_ASSERT(nrfx_is_word_aligned(src));
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c
index 8b14b33..7bd1bce 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -73,9 +73,9 @@ static nrfx_pdm_cb_t m_cb;
void nrfx_pdm_irq_handler(void)
{
- if (nrf_pdm_event_check(NRF_PDM, NRF_PDM_EVENT_STARTED))
+ if (nrf_pdm_event_check(NRF_PDM0, NRF_PDM_EVENT_STARTED))
{
- nrf_pdm_event_clear(NRF_PDM, NRF_PDM_EVENT_STARTED);
+ nrf_pdm_event_clear(NRF_PDM0, NRF_PDM_EVENT_STARTED);
NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_PDM_EVENT_STARTED));
uint8_t finished_buffer = m_cb.active_buffer;
@@ -125,11 +125,11 @@ void nrfx_pdm_irq_handler(void)
m_cb.op_state = NRFX_PDM_STATE_RUNNING;
}
}
- else if (nrf_pdm_event_check(NRF_PDM, NRF_PDM_EVENT_STOPPED))
+ else if (nrf_pdm_event_check(NRF_PDM0, NRF_PDM_EVENT_STOPPED))
{
- nrf_pdm_event_clear(NRF_PDM, NRF_PDM_EVENT_STOPPED);
+ nrf_pdm_event_clear(NRF_PDM0, NRF_PDM_EVENT_STOPPED);
NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_PDM_EVENT_STOPPED));
- nrf_pdm_disable(NRF_PDM);
+ nrf_pdm_disable(NRF_PDM0);
m_cb.op_state = NRFX_PDM_STATE_IDLE;
// Release the buffers.
@@ -200,21 +200,28 @@ nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config,
m_cb.event_handler = event_handler;
m_cb.op_state = NRFX_PDM_STATE_IDLE;
- nrf_pdm_clock_set(NRF_PDM, p_config->clock_freq);
- nrf_pdm_mode_set(NRF_PDM, p_config->mode, p_config->edge);
- nrf_pdm_gain_set(NRF_PDM, p_config->gain_l, p_config->gain_r);
+#if NRF_PDM_HAS_RATIO_CONFIG
+ nrf_pdm_ratio_set(NRF_PDM0, p_config->ratio);
+#endif
+
+#if NRF_PDM_HAS_MCLKCONFIG
+ nrf_pdm_mclksrc_configure(NRF_PDM0, p_config->mclksrc);
+#endif
+ nrf_pdm_clock_set(NRF_PDM0, p_config->clock_freq);
+ nrf_pdm_mode_set(NRF_PDM0, p_config->mode, p_config->edge);
+ nrf_pdm_gain_set(NRF_PDM0, p_config->gain_l, p_config->gain_r);
nrf_gpio_cfg_output(p_config->pin_clk);
nrf_gpio_pin_clear(p_config->pin_clk);
nrf_gpio_cfg_input(p_config->pin_din, NRF_GPIO_PIN_NOPULL);
- nrf_pdm_psel_connect(NRF_PDM, p_config->pin_clk, p_config->pin_din);
-
- nrf_pdm_event_clear(NRF_PDM, NRF_PDM_EVENT_STARTED);
- nrf_pdm_event_clear(NRF_PDM, NRF_PDM_EVENT_END);
- nrf_pdm_event_clear(NRF_PDM, NRF_PDM_EVENT_STOPPED);
- nrf_pdm_int_enable(NRF_PDM, NRF_PDM_INT_STARTED | NRF_PDM_INT_STOPPED);
- NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_PDM), p_config->interrupt_priority);
- NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_PDM));
+ nrf_pdm_psel_connect(NRF_PDM0, p_config->pin_clk, p_config->pin_din);
+
+ nrf_pdm_event_clear(NRF_PDM0, NRF_PDM_EVENT_STARTED);
+ nrf_pdm_event_clear(NRF_PDM0, NRF_PDM_EVENT_END);
+ nrf_pdm_event_clear(NRF_PDM0, NRF_PDM_EVENT_STOPPED);
+ nrf_pdm_int_enable(NRF_PDM0, NRF_PDM_INT_STARTED | NRF_PDM_INT_STOPPED);
+ NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_PDM0), p_config->interrupt_priority);
+ NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_PDM0));
m_cb.drv_state = NRFX_DRV_STATE_INITIALIZED;
err_code = NRFX_SUCCESS;
@@ -226,8 +233,8 @@ nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config,
void nrfx_pdm_uninit(void)
{
- nrf_pdm_disable(NRF_PDM);
- nrf_pdm_psel_disconnect(NRF_PDM);
+ nrf_pdm_disable(NRF_PDM0);
+ nrf_pdm_psel_disconnect(NRF_PDM0);
m_cb.drv_state = NRFX_DRV_STATE_UNINITIALIZED;
NRFX_LOG_INFO("Uninitialized.");
}
@@ -235,15 +242,15 @@ void nrfx_pdm_uninit(void)
static void pdm_start()
{
m_cb.drv_state = NRFX_DRV_STATE_POWERED_ON;
- nrf_pdm_enable(NRF_PDM);
- nrf_pdm_event_clear(NRF_PDM, NRF_PDM_EVENT_STARTED);
- nrf_pdm_task_trigger(NRF_PDM, NRF_PDM_TASK_START);
+ nrf_pdm_enable(NRF_PDM0);
+ nrf_pdm_event_clear(NRF_PDM0, NRF_PDM_EVENT_STARTED);
+ nrf_pdm_task_trigger(NRF_PDM0, NRF_PDM_TASK_START);
}
static void pdm_buf_request()
{
m_cb.irq_buff_request = 1;
- NRFX_IRQ_PENDING_SET(nrfx_get_irq_number(NRF_PDM));
+ NRFX_IRQ_PENDING_SET(nrfx_get_irq_number(NRF_PDM0));
}
nrfx_err_t nrfx_pdm_start(void)
@@ -296,7 +303,7 @@ nrfx_err_t nrfx_pdm_buffer_set(int16_t * buffer, uint16_t buffer_length)
nrfx_err_t err_code = NRFX_SUCCESS;
// Enter the PDM critical section.
- NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_PDM));
+ NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_PDM0));
uint8_t next_buffer = (~m_cb.active_buffer) & 0x01;
if (m_cb.op_state == NRFX_PDM_STATE_STARTING)
@@ -313,7 +320,7 @@ nrfx_err_t nrfx_pdm_buffer_set(int16_t * buffer, uint16_t buffer_length)
{
m_cb.buff_address[next_buffer] = buffer;
m_cb.buff_length[next_buffer] = buffer_length;
- nrf_pdm_buffer_set(NRF_PDM, (uint32_t *)buffer, buffer_length);
+ nrf_pdm_buffer_set(NRF_PDM0, (uint32_t *)buffer, buffer_length);
if (m_cb.drv_state != NRFX_DRV_STATE_POWERED_ON)
{
@@ -321,7 +328,7 @@ nrfx_err_t nrfx_pdm_buffer_set(int16_t * buffer, uint16_t buffer_length)
}
}
- NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_PDM));
+ NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_PDM0));
return err_code;
}
@@ -335,7 +342,7 @@ nrfx_err_t nrfx_pdm_stop(void)
if (m_cb.op_state == NRFX_PDM_STATE_IDLE ||
m_cb.op_state == NRFX_PDM_STATE_STARTING)
{
- nrf_pdm_disable(NRF_PDM);
+ nrf_pdm_disable(NRF_PDM0);
m_cb.op_state = NRFX_PDM_STATE_IDLE;
err_code = NRFX_SUCCESS;
NRFX_LOG_INFO("Function: %s, error code: %s.",
@@ -352,7 +359,7 @@ nrfx_err_t nrfx_pdm_stop(void)
m_cb.drv_state = NRFX_DRV_STATE_INITIALIZED;
m_cb.op_state = NRFX_PDM_STATE_STOPPING;
- nrf_pdm_task_trigger(NRF_PDM, NRF_PDM_TASK_STOP);
+ nrf_pdm_task_trigger(NRF_PDM0, NRF_PDM_TASK_STOP);
err_code = NRFX_SUCCESS;
NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power.c
index 5bb5da8..3327c14 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -34,9 +34,6 @@
#if NRFX_CHECK(NRFX_POWER_ENABLED)
#include <nrfx_power.h>
-#if defined(REGULATORS_PRESENT)
-#include <hal/nrf_regulators.h>
-#endif
#if NRFX_CHECK(NRFX_CLOCK_ENABLED)
extern bool nrfx_clock_irq_enabled;
@@ -108,7 +105,10 @@ nrfx_err_t nrfx_power_init(nrfx_power_config_t const * p_config)
#if NRF_POWER_HAS_DCDCEN_VDDH
nrf_power_dcdcen_vddh_set(NRF_POWER, p_config->dcdcenhv);
+#elif NRF_REGULATORS_HAS_DCDCEN_VDDH
+ nrf_regulators_dcdcen_vddh_set(NRF_REGULATORS, p_config->dcdcenhv);
#endif
+
#if NRF_POWER_HAS_DCDCEN
nrf_power_dcdcen_set(NRF_POWER, p_config->dcdcen);
#elif defined(REGULATORS_PRESENT)
@@ -132,19 +132,19 @@ void nrfx_power_uninit(void)
{
NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_POWER));
}
-#if NRF_POWER_HAS_POFCON
+#if NRFX_POWER_SUPPORTS_POFCON
nrfx_power_pof_uninit();
#endif
#if NRF_POWER_HAS_SLEEPEVT
nrfx_power_sleepevt_uninit();
#endif
-#if NRF_POWER_HAS_USBREG
+#if NRF_POWER_HAS_USBREG || defined(USBREG_PRESENT)
nrfx_power_usbevt_uninit();
#endif
m_initialized = false;
}
-#if NRF_POWER_HAS_POFCON
+#if NRFX_POWER_SUPPORTS_POFCON
void nrfx_power_pof_init(nrfx_power_pofwarn_config_t const * p_config)
{
NRFX_ASSERT(p_config != NULL);
@@ -159,10 +159,18 @@ void nrfx_power_pof_init(nrfx_power_pofwarn_config_t const * p_config)
void nrfx_power_pof_enable(nrfx_power_pofwarn_config_t const * p_config)
{
+#if NRF_POWER_HAS_POFCON
nrf_power_pofcon_set(NRF_POWER, true, p_config->thr);
-#if NRF_POWER_HAS_VDDH
+#elif NRF_REGULATORS_HAS_POFCON
+ nrf_regulators_pofcon_set(NRF_REGULATORS, true, p_config->thr);
+#endif
+
+#if NRF_POWER_HAS_POFCON_VDDH
nrf_power_pofcon_vddh_set(NRF_POWER, p_config->thrvddh);
+#elif NRF_REGULATORS_HAS_POFCON_VDDH
+ nrf_regulators_pofcon_vddh_set(NRF_REGULATORS, p_config->thrvddh);
#endif
+
if (m_pofwarn_handler != NULL)
{
nrf_power_int_enable(NRF_POWER, NRF_POWER_INT_POFWARN_MASK);
@@ -171,7 +179,11 @@ void nrfx_power_pof_enable(nrfx_power_pofwarn_config_t const * p_config)
void nrfx_power_pof_disable(void)
{
+#if NRF_POWER_HAS_POFCON
nrf_power_pofcon_set(NRF_POWER, false, NRF_POWER_POFTHR_V27);
+#elif NRF_REGULATORS_HAS_POFCON
+ nrf_regulators_pofcon_set(NRF_REGULATORS, false, NRF_REGULATORS_POFTHR_V27);
+#endif
nrf_power_int_disable(NRF_POWER, NRF_POWER_INT_POFWARN_MASK);
}
@@ -179,7 +191,7 @@ void nrfx_power_pof_uninit(void)
{
m_pofwarn_handler = NULL;
}
-#endif // NRF_POWER_HAS_POFCON
+#endif // NRFX_POWER_SUPPORTS_POFCON
#if NRF_POWER_HAS_SLEEPEVT
void nrfx_power_sleepevt_init(nrfx_power_sleepevt_config_t const * p_config)
@@ -249,8 +261,11 @@ void nrfx_power_usbevt_disable(void)
void nrfx_power_usbevt_uninit(void)
{
+ nrfx_power_usbevt_disable();
m_usbevt_handler = NULL;
}
+
+
#endif /* NRF_POWER_HAS_USBREG */
@@ -258,7 +273,7 @@ void nrfx_power_irq_handler(void)
{
uint32_t enabled = nrf_power_int_enable_get(NRF_POWER);
-#if NRF_POWER_HAS_POFCON
+#if NRFX_POWER_SUPPORTS_POFCON
if ((0 != (enabled & NRF_POWER_INT_POFWARN_MASK)) &&
nrf_power_event_get_and_clear(NRF_POWER, NRF_POWER_EVENT_POFWARN))
{
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ppi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ppi.c
index 7981c1e..de7f65f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ppi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ppi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c
index c3eb7e7..d89bc7c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -92,16 +92,19 @@ static void configure_pins(nrfx_pwm_t const * p_instance,
bool inverted = output_pin & NRFX_PWM_PIN_INVERTED;
out_pins[i] = output_pin & ~NRFX_PWM_PIN_INVERTED;
- if (inverted)
+ if (!p_config->skip_gpio_cfg)
{
- nrf_gpio_pin_set(out_pins[i]);
+ if (inverted)
+ {
+ nrf_gpio_pin_set(out_pins[i]);
+ }
+ else
+ {
+ nrf_gpio_pin_clear(out_pins[i]);
+ }
+
+ nrf_gpio_cfg_output(out_pins[i]);
}
- else
- {
- nrf_gpio_pin_clear(out_pins[i]);
- }
-
- nrf_gpio_cfg_output(out_pins[i]);
}
else
{
@@ -365,14 +368,22 @@ bool nrfx_pwm_stop(nrfx_pwm_t const * p_instance,
bool ret_val = false;
+ // Deactivate shortcuts before triggering the STOP task, otherwise the PWM
+ // could be immediately started again if the LOOPSDONE event occurred in
+ // the same peripheral clock cycle as the STOP task was triggered.
+ nrf_pwm_shorts_set(p_instance->p_registers, 0);
+
+ // Trigger the STOP task even if the PWM appears to be already stopped.
+ // It won't harm, but it could help if for some strange reason the stopped
+ // status was not reported correctly.
+ nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_STOP);
+
if (nrfx_pwm_is_stopped(p_instance))
{
ret_val = true;
}
else
{
- nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_STOP);
-
do {
if (nrfx_pwm_is_stopped(p_instance))
{
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c
index 81937e0..a83e28c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -141,8 +141,8 @@ nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config,
}
nrf_qdec_int_enable(NRF_QDEC, int_mask);
- NRFX_IRQ_PRIORITY_SET(QDEC_IRQn, p_config->interrupt_priority);
- NRFX_IRQ_ENABLE(QDEC_IRQn);
+ NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_QDEC), p_config->interrupt_priority);
+ NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_QDEC));
m_state = NRFX_DRV_STATE_INITIALIZED;
@@ -155,7 +155,7 @@ void nrfx_qdec_uninit(void)
{
NRFX_ASSERT(m_state != NRFX_DRV_STATE_UNINITIALIZED);
nrfx_qdec_disable();
- NRFX_IRQ_DISABLE(QDEC_IRQn);
+ NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_QDEC));
m_state = NRFX_DRV_STATE_UNINITIALIZED;
NRFX_LOG_INFO("Uninitialized.");
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qspi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qspi.c
index 4583017..3983e8c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qspi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qspi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -394,6 +394,50 @@ nrfx_err_t nrfx_qspi_chip_erase(void)
return nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_ALL, 0);
}
+#if NRF_QSPI_HAS_XIP_ENC
+nrfx_err_t nrfx_qspi_xip_encrypt(nrf_qspi_encryption_t const * p_config)
+{
+ if (m_cb.is_busy)
+ {
+ return NRFX_ERROR_BUSY;
+ }
+
+ if (p_config)
+ {
+ nrf_qspi_xip_encryption_configure(NRF_QSPI, p_config);
+ nrf_qspi_xip_encryption_set(NRF_QSPI, true);
+ }
+ else
+ {
+ nrf_qspi_xip_encryption_set(NRF_QSPI, false);
+ }
+
+ return NRFX_SUCCESS;
+}
+#endif
+
+#if NRF_QSPI_HAS_DMA_ENC
+nrfx_err_t nrfx_qspi_dma_encrypt(nrf_qspi_encryption_t const * p_config)
+{
+ if (m_cb.is_busy)
+ {
+ return NRFX_ERROR_BUSY;
+ }
+
+ if (p_config)
+ {
+ nrf_qspi_dma_encryption_configure(NRF_QSPI, p_config);
+ nrf_qspi_dma_encryption_set(NRF_QSPI, true);
+ }
+ else
+ {
+ nrf_qspi_dma_encryption_set(NRF_QSPI, false);
+ }
+
+ return NRFX_SUCCESS;
+}
+#endif
+
void nrfx_qspi_irq_handler(void)
{
// Catch Event ready interrupts
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rng.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rng.c
index 8343866..bf5b4ef 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rng.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rng.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c
index 53a0ed9..60fe2ae 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_saadc.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_saadc.c
index 371cdc9..4e24409 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_saadc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_saadc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -36,24 +36,18 @@
#define NRFX_LOG_MODULE SAADC
#include <nrfx_log.h>
-#define EVT_TO_STR(event) \
- (event == NRF_SAADC_EVENT_STARTED ? "NRF_SAADC_EVENT_STARTED" : \
- (event == NRF_SAADC_EVENT_END ? "NRF_SAADC_EVENT_END" : \
- (event == NRF_SAADC_EVENT_DONE ? "NRF_SAADC_EVENT_DONE" : \
- (event == NRF_SAADC_EVENT_RESULTDONE ? "NRF_SAADC_EVENT_RESULTDONE" : \
- (event == NRF_SAADC_EVENT_CALIBRATEDONE ? "NRF_SAADC_EVENT_CALIBRATEDONE" : \
- (event == NRF_SAADC_EVENT_STOPPED ? "NRF_SAADC_EVENT_STOPPED" : \
- "UNKNOWN EVENT"))))))
-
#if defined(NRF52_SERIES) && !defined(USE_WORKAROUND_FOR_ANOMALY_212)
// ANOMALY 212 - SAADC events are missing when switching from single channel
// to multi channel configuration with burst enabled.
#define USE_WORKAROUND_FOR_ANOMALY_212 1
#endif
-#if defined(NRF91_SERIES) || defined(NRF53_SERIES)
+#if defined(NRF53_SERIES) || defined(NRF91_SERIES)
// Make sure that SAADC is stopped before channel configuration.
#define STOP_SAADC_ON_CHANNEL_CONFIG 1
+
+ // Make sure that SAADC calibration samples do not affect next conversions.
+ #define INTERCEPT_SAADC_CALIBRATION_SAMPLES 1
#endif
/** @brief SAADC driver states.*/
@@ -75,9 +69,12 @@ typedef struct
nrfx_saadc_event_handler_t event_handler; ///< Event handler function pointer.
nrf_saadc_value_t * p_buffer_primary; ///< Pointer to the primary result buffer.
nrf_saadc_value_t * p_buffer_secondary; ///< Pointer to the secondary result buffer.
+#if NRFX_CHECK(INTERCEPT_SAADC_CALIBRATION_SAMPLES)
+ nrf_saadc_value_t calib_samples[6]; ///< Scratch buffer for calibration samples.
+#endif
uint16_t size_primary; ///< Size of the primary result buffer.
uint16_t size_secondary; ///< Size of the secondary result buffer.
- uint16_t samples_per_trigger; ///< Samples to take per one trigger in the blocking mode.
+ uint16_t samples_converted; ///< Number of samples present in result buffer when in the blocking mode.
nrf_saadc_input_t channels_pselp[SAADC_CH_NUM]; ///< Array holding each channel positive input.
nrf_saadc_input_t channels_pseln[SAADC_CH_NUM]; ///< Array holding each channel negative input.
nrf_saadc_state_t saadc_state; ///< State of the SAADC driver.
@@ -87,6 +84,7 @@ typedef struct
uint8_t limits_low_activated; ///< Bitmask of the activated low limits.
uint8_t limits_high_activated; ///< Bitmask of the activated high limits.
bool start_on_end; ///< Flag indicating if the START task is to be triggered on the END event.
+ bool oversampling_without_burst; ///< Flag indicating whether oversampling without burst is configured.
} nrfx_saadc_cb_t;
static nrfx_saadc_cb_t m_cb;
@@ -122,17 +120,6 @@ static void saadc_anomaly_212_workaround_apply(void)
}
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_212)
-static void saadc_enabled_channels_sample(void)
-{
- for (uint32_t sample_idx = 0; sample_idx < m_cb.samples_per_trigger; sample_idx++)
- {
- nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_SAMPLE);
- while (!nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_DONE))
- {}
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_DONE);
- }
-}
-
static nrfx_err_t saadc_channel_count_get(uint32_t ch_to_activate_mask,
uint8_t * p_active_ch_count)
{
@@ -183,11 +170,9 @@ static void saadc_generic_mode_set(uint32_t ch_to_activate_mas
#if NRFX_CHECK(STOP_SAADC_ON_CHANNEL_CONFIG)
nrf_saadc_int_disable(NRF_SAADC, NRF_SAADC_INT_STOPPED);
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STOPPED);
nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_STOP);
while (!nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STOPPED))
- {
- }
+ {}
nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STOPPED);
#endif
@@ -198,25 +183,20 @@ static void saadc_generic_mode_set(uint32_t ch_to_activate_mas
m_cb.p_buffer_secondary = NULL;
m_cb.event_handler = event_handler;
m_cb.channels_activated = ch_to_activate_mask;
+ m_cb.samples_converted = 0;
nrf_saadc_resolution_set(NRF_SAADC, resolution);
nrf_saadc_oversample_set(NRF_SAADC, oversampling);
if (event_handler)
{
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STARTED);
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STOPPED);
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END);
- nrf_saadc_int_enable(NRF_SAADC,
- NRF_SAADC_INT_STARTED |
- NRF_SAADC_INT_STOPPED |
- NRF_SAADC_INT_END);
+ nrf_saadc_int_set(NRF_SAADC,
+ NRF_SAADC_INT_STARTED |
+ NRF_SAADC_INT_STOPPED |
+ NRF_SAADC_INT_END);
}
else
{
- nrf_saadc_int_disable(NRF_SAADC,
- NRF_SAADC_INT_STARTED |
- NRF_SAADC_INT_STOPPED |
- NRF_SAADC_INT_END);
+ nrf_saadc_int_set(NRF_SAADC, 0);
}
for (uint32_t ch_pos = 0; ch_pos < SAADC_CH_NUM; ch_pos++)
@@ -243,22 +223,28 @@ static void saadc_generic_mode_set(uint32_t ch_to_activate_mas
nrfx_err_t nrfx_saadc_init(uint8_t interrupt_priority)
{
+ nrfx_err_t err_code;
if (m_cb.saadc_state != NRF_SAADC_STATE_UNINITIALIZED)
{
+ err_code = NRFX_ERROR_INVALID_STATE;
NRFX_LOG_WARNING("Function: %s, error code: %s.",
__func__,
NRFX_LOG_ERROR_STRING_GET(err_code));
- return NRFX_ERROR_INVALID_STATE;
+ return err_code;
}
m_cb.saadc_state = NRF_SAADC_STATE_IDLE;
- nrf_saadc_int_disable(NRF_SAADC, NRF_SAADC_INT_ALL);
+ nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STARTED);
+ nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STOPPED);
+ nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END);
+ nrf_saadc_int_set(NRF_SAADC, 0);
NRFX_IRQ_ENABLE(SAADC_IRQn);
NRFX_IRQ_PRIORITY_SET(SAADC_IRQn, interrupt_priority);
+ err_code = NRFX_SUCCESS;
NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
- return NRFX_SUCCESS;
+ return err_code;
}
void nrfx_saadc_uninit(void)
@@ -335,6 +321,7 @@ nrfx_err_t nrfx_saadc_simple_mode_set(uint32_t channel_mask,
}
else
{
+ // Burst is implicitly enabled if oversampling is enabled.
burst = NRF_SAADC_BURST_ENABLED;
}
@@ -344,17 +331,6 @@ nrfx_err_t nrfx_saadc_simple_mode_set(uint32_t channel_mask,
burst,
event_handler);
- if (event_handler)
- {
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_RESULTDONE);
- nrf_saadc_int_enable(NRF_SAADC, NRF_SAADC_INT_RESULTDONE);
- }
- else
- {
- nrf_saadc_int_disable(NRF_SAADC, NRF_SAADC_INT_RESULTDONE);
- }
-
- m_cb.samples_per_trigger = active_ch_count;
m_cb.channels_activated_count = active_ch_count;
m_cb.saadc_state = NRF_SAADC_STATE_SIMPLE_MODE;
@@ -386,24 +362,20 @@ nrfx_err_t nrfx_saadc_advanced_mode_set(uint32_t channel_
return NRFX_ERROR_NOT_SUPPORTED;
}
+ bool oversampling_without_burst = false;
if ((p_config->oversampling != NRF_SAADC_OVERSAMPLE_DISABLED) &&
(p_config->burst == NRF_SAADC_BURST_DISABLED))
{
- // Oversampling without burst
if (active_ch_count > 1)
{
+ // Oversampling without burst is possible only on single channel.
return NRFX_ERROR_NOT_SUPPORTED;
}
else
{
- m_cb.samples_per_trigger =
- nrf_saadc_oversample_sample_count_get(p_config->oversampling);
+ oversampling_without_burst = true;
}
}
- else
- {
- m_cb.samples_per_trigger = active_ch_count;
- }
saadc_generic_mode_set(channel_mask,
resolution,
@@ -422,6 +394,7 @@ nrfx_err_t nrfx_saadc_advanced_mode_set(uint32_t channel_
m_cb.channels_activated_count = active_ch_count;
m_cb.start_on_end = p_config->start_on_end;
+ m_cb.oversampling_without_burst = oversampling_without_burst;
m_cb.saadc_state = NRF_SAADC_STATE_ADV_MODE;
@@ -456,9 +429,8 @@ nrfx_err_t nrfx_saadc_buffer_set(nrf_saadc_value_t * p_buffer, uint16_t size)
{
return NRFX_ERROR_INVALID_LENGTH;
}
- m_cb.p_buffer_primary = p_buffer;
m_cb.size_primary = size;
- nrf_saadc_buffer_init(NRF_SAADC, p_buffer, size);
+ m_cb.p_buffer_primary = p_buffer;
break;
case NRF_SAADC_STATE_ADV_MODE_SAMPLE_STARTED:
@@ -471,14 +443,13 @@ nrfx_err_t nrfx_saadc_buffer_set(nrf_saadc_value_t * p_buffer, uint16_t size)
case NRF_SAADC_STATE_ADV_MODE_SAMPLE:
if (m_cb.p_buffer_primary)
{
- m_cb.p_buffer_secondary = p_buffer;
m_cb.size_secondary = size;
+ m_cb.p_buffer_secondary = p_buffer;
}
else
{
- m_cb.p_buffer_primary = p_buffer;
m_cb.size_primary = size;
- nrf_saadc_buffer_init(NRF_SAADC, p_buffer, size);
+ m_cb.p_buffer_primary = p_buffer;
}
break;
@@ -500,9 +471,14 @@ nrfx_err_t nrfx_saadc_mode_trigger(void)
}
nrfx_err_t result = NRFX_SUCCESS;
- switch (m_cb.saadc_state) {
+ switch (m_cb.saadc_state)
+ {
case NRF_SAADC_STATE_SIMPLE_MODE:
nrf_saadc_enable(NRF_SAADC);
+ // When in simple blocking or non-blocking mode, buffer size is equal to activated channel count.
+ // Single SAMPLE task is enough to obtain one sample on each activated channel.
+ // This will result in buffer being filled with samples and therefore END event will appear.
+ nrf_saadc_buffer_init(NRF_SAADC, m_cb.p_buffer_primary, m_cb.size_primary);
if (m_cb.event_handler)
{
m_cb.saadc_state = NRF_SAADC_STATE_SIMPLE_MODE_SAMPLE;
@@ -515,7 +491,7 @@ nrfx_err_t nrfx_saadc_mode_trigger(void)
{}
nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STARTED);
- saadc_enabled_channels_sample();
+ nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_SAMPLE);
while (!nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_END))
{}
nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END);
@@ -527,49 +503,64 @@ nrfx_err_t nrfx_saadc_mode_trigger(void)
nrf_saadc_enable(NRF_SAADC);
if (m_cb.event_handler)
{
+ // When in advanced non-blocking mode, latch whole buffer in EasyDMA.
+ // END event will arrive when whole buffer is filled with samples.
m_cb.saadc_state = NRF_SAADC_STATE_ADV_MODE_SAMPLE;
+ nrf_saadc_buffer_init(NRF_SAADC, m_cb.p_buffer_primary, m_cb.size_primary);
nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_START);
break;
}
- m_cb.saadc_state = NRF_SAADC_STATE_ADV_MODE_SAMPLE_STARTED;
+ // When in advanced blocking mode, latch single chunk of buffer in EasyDMA.
+ // Each chunk consists of single sample from each activated channels.
+ // END event will arrive when single chunk is filled with samples.
+ nrf_saadc_buffer_init(NRF_SAADC,
+ &m_cb.p_buffer_primary[m_cb.samples_converted],
+ m_cb.channels_activated_count);
+
nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_START);
while (!nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STARTED))
{}
nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STARTED);
- /* fall-through */
- case NRF_SAADC_STATE_ADV_MODE_SAMPLE_STARTED:
- if (m_cb.event_handler)
+ if (m_cb.oversampling_without_burst)
{
- result = NRFX_ERROR_INVALID_STATE;
- break;
- }
+ // Oversampling without burst is possible only on single channel.
+ // In this configuration more than one SAMPLE task is needed to obtain single sample.
+ uint32_t samples_to_take =
+ nrf_saadc_oversample_sample_count_get(nrf_saadc_oversample_get(NRF_SAADC));
- saadc_enabled_channels_sample();
- if (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_END))
- {
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END);
- m_cb.saadc_state = NRF_SAADC_STATE_ADV_MODE;
- m_cb.p_buffer_primary = m_cb.p_buffer_secondary;
- m_cb.size_primary = m_cb.size_secondary;
- m_cb.p_buffer_secondary = NULL;
- if (m_cb.p_buffer_primary)
- {
- nrf_saadc_buffer_init(NRF_SAADC,
- m_cb.p_buffer_primary,
- m_cb.size_primary);
- }
- else
+ for (uint32_t sample_idx = 0; sample_idx < samples_to_take; sample_idx++)
{
- nrf_saadc_disable(NRF_SAADC);
+ nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_DONE);
+ nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_SAMPLE);
+ while (!nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_DONE))
+ {}
}
- result = NRFX_SUCCESS;
}
else
{
+ // Single SAMPLE task is enough to obtain one sample on each activated channel.
+ // This will result in chunk being filled with samples and therefore END event will appear.
+ nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_SAMPLE);
+ }
+ while (!nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_END))
+ {}
+ nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END);
+
+ m_cb.samples_converted += m_cb.channels_activated_count;
+ if (m_cb.samples_converted < m_cb.size_primary)
+ {
result = NRFX_ERROR_BUSY;
}
+ else
+ {
+ m_cb.samples_converted = 0;
+ m_cb.p_buffer_primary = m_cb.p_buffer_secondary;
+ m_cb.size_primary = m_cb.size_secondary;
+ m_cb.p_buffer_secondary = NULL;
+ }
+ nrf_saadc_disable(NRF_SAADC);
break;
default:
@@ -584,43 +575,19 @@ void nrfx_saadc_abort(void)
{
NRFX_ASSERT(m_cb.saadc_state != NRF_SAADC_STATE_UNINITIALIZED);
- if (!saadc_busy_check())
- {
- return;
- }
-
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STOPPED);
- nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_STOP);
-
- if (m_cb.saadc_state == NRF_SAADC_STATE_CALIBRATION)
- {
- // STOPPED event does not appear when the calibration is ongoing
- m_cb.saadc_state = NRF_SAADC_STATE_IDLE;
- }
- else if (!m_cb.event_handler)
+ if (!m_cb.event_handler)
{
- while (!nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STOPPED))
- {}
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STOPPED);
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END);
-
m_cb.p_buffer_primary = NULL;
m_cb.p_buffer_secondary = NULL;
- switch (m_cb.saadc_state)
+ m_cb.samples_converted = 0;
+ }
+ else
+ {
+ nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_STOP);
+ if (m_cb.saadc_state == NRF_SAADC_STATE_CALIBRATION)
{
- case NRF_SAADC_STATE_SIMPLE_MODE_SAMPLE:
- m_cb.saadc_state = NRF_SAADC_STATE_SIMPLE_MODE;
- break;
-
- case NRF_SAADC_STATE_ADV_MODE_SAMPLE:
- /* fall-through */
-
- case NRF_SAADC_STATE_ADV_MODE_SAMPLE_STARTED:
- m_cb.saadc_state = NRF_SAADC_STATE_ADV_MODE;
- break;
-
- default:
- break;
+ // STOPPED event does not appear when the calibration is ongoing
+ m_cb.saadc_state = NRF_SAADC_STATE_IDLE;
}
}
}
@@ -687,8 +654,31 @@ nrfx_err_t nrfx_saadc_offset_calibrate(nrfx_saadc_event_handler_t event_handler)
m_cb.saadc_state = NRF_SAADC_STATE_CALIBRATION;
m_cb.event_handler = event_handler;
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_CALIBRATEDONE);
nrf_saadc_enable(NRF_SAADC);
+#if NRFX_CHECK(INTERCEPT_SAADC_CALIBRATION_SAMPLES)
+ nrf_saadc_buffer_init(NRF_SAADC, m_cb.calib_samples, NRFX_ARRAY_SIZE(m_cb.calib_samples));
+ if (event_handler)
+ {
+ nrf_saadc_int_set(NRF_SAADC, NRF_SAADC_INT_STARTED | NRF_SAADC_INT_CALIBRATEDONE);
+ nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_START);
+ }
+ else
+ {
+ nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_START);
+ while (!nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STARTED))
+ {}
+ nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STARTED);
+
+ nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_CALIBRATEOFFSET);
+ while (!nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_CALIBRATEDONE))
+ {}
+ nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_CALIBRATEDONE);
+ nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END);
+
+ nrf_saadc_disable(NRF_SAADC);
+ m_cb.saadc_state = NRF_SAADC_STATE_IDLE;
+ }
+#else
nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_CALIBRATEOFFSET);
if (event_handler)
{
@@ -702,6 +692,7 @@ nrfx_err_t nrfx_saadc_offset_calibrate(nrfx_saadc_event_handler_t event_handler)
nrf_saadc_disable(NRF_SAADC);
m_cb.saadc_state = NRF_SAADC_STATE_IDLE;
}
+#endif // NRFX_CHECK(INTERCEPT_SAADC_CALIBRATION_SAMPLES)
return NRFX_SUCCESS;
}
@@ -732,14 +723,25 @@ static void saadc_event_started_handle(void)
/* fall-through */
case NRF_SAADC_STATE_ADV_MODE_SAMPLE_STARTED:
- evt_data.type = NRFX_SAADC_EVT_BUF_REQ;
- m_cb.event_handler(&evt_data);
+ if (!m_cb.p_buffer_secondary)
+ {
+ // Send next buffer request only if it was not provided earlier,
+ // before conversion start or outside of user's callback context.
+ evt_data.type = NRFX_SAADC_EVT_BUF_REQ;
+ m_cb.event_handler(&evt_data);
+ }
break;
case NRF_SAADC_STATE_SIMPLE_MODE_SAMPLE:
nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_SAMPLE);
break;
+#if NRFX_CHECK(INTERCEPT_SAADC_CALIBRATION_SAMPLES)
+ case NRF_SAADC_STATE_CALIBRATION:
+ nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_CALIBRATEOFFSET);
+ break;
+#endif
+
default:
break;
}
@@ -814,16 +816,6 @@ void nrfx_saadc_irq_handler(void)
saadc_event_started_handle();
}
- if (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_RESULTDONE))
- {
- nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_RESULTDONE);
-
- if (m_cb.saadc_state == NRF_SAADC_STATE_SIMPLE_MODE_SAMPLE)
- {
- nrf_saadc_task_trigger(NRF_SAADC, NRF_SAADC_TASK_SAMPLE);
- }
- }
-
if (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_STOPPED))
{
nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STOPPED);
@@ -837,7 +829,15 @@ void nrfx_saadc_irq_handler(void)
if (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_END))
{
nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END);
- saadc_event_end_handle();
+
+#if NRFX_CHECK(INTERCEPT_SAADC_CALIBRATION_SAMPLES)
+ // When samples are intercepted into scratch buffer during calibration,
+ // END event appears when the calibration finishes. This event should be ignored.
+ if (m_cb.saadc_state != NRF_SAADC_STATE_CALIBRATION)
+#endif
+ {
+ saadc_event_end_handle();
+ }
}
saadc_event_limits_handle(m_cb.limits_low_activated, NRF_SAADC_LIMIT_LOW);
@@ -846,6 +846,7 @@ void nrfx_saadc_irq_handler(void)
if (nrf_saadc_event_check(NRF_SAADC, NRF_SAADC_EVENT_CALIBRATEDONE))
{
nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_CALIBRATEDONE);
+ nrf_saadc_disable(NRF_SAADC);
m_cb.saadc_state = NRF_SAADC_STATE_IDLE;
@@ -853,8 +854,6 @@ void nrfx_saadc_irq_handler(void)
evt_data.type = NRFX_SAADC_EVT_CALIBRATEDONE;
m_cb.event_handler(&evt_data);
- nrf_saadc_int_disable(NRF_SAADC, NRF_SAADC_INT_CALIBRATEDONE);
- nrf_saadc_disable(NRF_SAADC);
}
}
#endif // NRFX_CHECK(NRFX_SAADC_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c
index 1fa4b8a..1cbed19 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c
index bd8bc84..007d177 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -34,7 +34,8 @@
#if NRFX_CHECK(NRFX_SPIM_ENABLED)
#if !(NRFX_CHECK(NRFX_SPIM0_ENABLED) || NRFX_CHECK(NRFX_SPIM1_ENABLED) || \
- NRFX_CHECK(NRFX_SPIM2_ENABLED) || NRFX_CHECK(NRFX_SPIM3_ENABLED))
+ NRFX_CHECK(NRFX_SPIM2_ENABLED) || NRFX_CHECK(NRFX_SPIM3_ENABLED) || \
+ NRFX_CHECK(NRFX_SPIM4_ENABLED))
#error "No enabled SPIM instances. Check <nrfx_config.h>."
#endif
@@ -121,29 +122,45 @@
#define SPIM3_SUPPORTED_FREQ_VALIDATE(...) 0
#endif
+#if NRFX_CHECK(NRFX_SPIM4_ENABLED)
+#define SPIM4_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM4, __VA_ARGS__)
+#define SPIM4_HW_CSN_PRESENT_VALIDATE(...) SPIMX_HW_CSN_PRESENT_VALIDATE(SPIM4, __VA_ARGS__)
+#define SPIM4_DCX_PRESENT_VALIDATE(...) SPIMX_DCX_PRESENT_VALIDATE(SPIM4, __VA_ARGS__)
+#define SPIM4_SUPPORTED_FREQ_VALIDATE(...) SPIMX_SUPPORTED_FREQ_VALIDATE(SPIM4, __VA_ARGS__)
+#else
+#define SPIM4_LENGTH_VALIDATE(...) 0
+#define SPIM4_HW_CSN_PRESENT_VALIDATE(...) 0
+#define SPIM4_DCX_PRESENT_VALIDATE(...) 0
+#define SPIM4_SUPPORTED_FREQ_VALIDATE(...) 0
+#endif
+
#define SPIM_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) \
(SPIM0_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \
SPIM1_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \
SPIM2_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \
- SPIM3_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len))
+ SPIM3_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \
+ SPIM4_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len))
#define SPIM_HW_CSN_PRESENT_VALIDATE(drv_inst_idx) \
(SPIM0_HW_CSN_PRESENT_VALIDATE(drv_inst_idx) || \
SPIM1_HW_CSN_PRESENT_VALIDATE(drv_inst_idx) || \
SPIM2_HW_CSN_PRESENT_VALIDATE(drv_inst_idx) || \
- SPIM3_HW_CSN_PRESENT_VALIDATE(drv_inst_idx))
+ SPIM3_HW_CSN_PRESENT_VALIDATE(drv_inst_idx) || \
+ SPIM4_HW_CSN_PRESENT_VALIDATE(drv_inst_idx))
#define SPIM_DCX_PRESENT_VALIDATE(drv_inst_idx) \
(SPIM0_DCX_PRESENT_VALIDATE(drv_inst_idx) || \
SPIM1_DCX_PRESENT_VALIDATE(drv_inst_idx) || \
SPIM2_DCX_PRESENT_VALIDATE(drv_inst_idx) || \
- SPIM3_DCX_PRESENT_VALIDATE(drv_inst_idx))
+ SPIM3_DCX_PRESENT_VALIDATE(drv_inst_idx) || \
+ SPIM4_DCX_PRESENT_VALIDATE(drv_inst_idx))
#define SPIM_SUPPORTED_FREQ_VALIDATE(drv_inst_idx, freq) \
(SPIM0_SUPPORTED_FREQ_VALIDATE(drv_inst_idx, freq) || \
SPIM1_SUPPORTED_FREQ_VALIDATE(drv_inst_idx, freq) || \
SPIM2_SUPPORTED_FREQ_VALIDATE(drv_inst_idx, freq) || \
- SPIM3_SUPPORTED_FREQ_VALIDATE(drv_inst_idx, freq))
+ SPIM3_SUPPORTED_FREQ_VALIDATE(drv_inst_idx, freq) || \
+ SPIM4_SUPPORTED_FREQ_VALIDATE(drv_inst_idx, freq))
#if defined(NRF52840_XXAA) && (NRFX_CHECK(NRFX_SPIM3_ENABLED))
// Enable workaround for nRF52840 anomaly 195 (SPIM3 continues to draw current after disable).
@@ -271,6 +288,9 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance,
#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
nrfx_spim_3_irq_handler,
#endif
+ #if NRFX_CHECK(NRFX_SPIM4_ENABLED)
+ nrfx_spim_4_irq_handler,
+ #endif
};
if (nrfx_prs_acquire(p_instance->p_reg,
irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS)
@@ -754,4 +774,11 @@ void nrfx_spim_3_irq_handler(void)
}
#endif
+#if NRFX_CHECK(NRFX_SPIM4_ENABLED)
+void nrfx_spim_4_irq_handler(void)
+{
+ irq_handler(NRF_SPIM4, &m_cb[NRFX_SPIM4_INST_IDX]);
+}
+#endif
+
#endif // NRFX_CHECK(NRFX_SPIM_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c
index ebdf74f..be30e79 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2013 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_systick.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_systick.c
index 878c068..708826a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_systick.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_systick.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_temp.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_temp.c
index a481df7..98ebb21 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_temp.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_temp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c
index 06ac1dc..d8df49b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi.c
index 37f7dd9..4199400 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -49,7 +49,8 @@
(event == NRFX_TWI_EVT_ADDRESS_NACK ? "EVT_ADDRESS_NACK" : \
(event == NRFX_TWI_EVT_DATA_NACK ? "EVT_DATA_NACK" : \
(event == NRFX_TWI_EVT_OVERRUN ? "EVT_OVERRUN" : \
- "UNKNOWN ERROR"))))
+ (event == NRFX_TWI_EVT_BUS_ERROR ? "EVT_BUS_ERROR" : \
+ "UNKNOWN ERROR")))))
#define EVT_TO_STR_TWI(event) \
(event == NRF_TWI_EVENT_STOPPED ? "NRF_TWI_EVENT_STOPPED" : \
@@ -132,7 +133,25 @@ static nrfx_err_t twi_process_error(uint32_t errorsrc)
return ret;
}
+static bool xfer_completeness_check(NRF_TWI_Type * p_twi, twi_control_block_t const * p_cb)
+{
+ // If the actual number of transferred bytes is not equal to what was requested,
+ // but there was no error signaled by the peripheral, this means that something
+ // unexpected, like a premature STOP condition, was received on the bus.
+ // In such case the peripheral has to be disabled and re-enabled, so that its
+ // internal state machine is reinitialized.
+ if (p_cb->bytes_transferred != p_cb->curr_length)
+ {
+ nrf_twi_disable(p_twi);
+ nrf_twi_enable(p_twi);
+ return false;
+ }
+ else
+ {
+ return true;
+ }
+}
nrfx_err_t nrfx_twi_init(nrfx_twi_t const * p_instance,
nrfx_twi_config_t const * p_config,
@@ -264,7 +283,6 @@ static bool twi_send_byte(NRF_TWI_Type * p_twi,
if (p_cb->bytes_transferred < p_cb->curr_length)
{
nrf_twi_txd_set(p_twi, p_cb->p_curr_buf[p_cb->bytes_transferred]);
- ++(p_cb->bytes_transferred);
}
else
{
@@ -318,7 +336,19 @@ static bool twi_receive_byte(NRF_TWI_Type * p_twi,
static bool twi_transfer(NRF_TWI_Type * p_twi,
twi_control_block_t * p_cb)
{
- bool do_stop_check = ((p_cb->error) || ((p_cb->bytes_transferred) == p_cb->curr_length));
+ bool stopped = false;
+ if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_STOPPED))
+ {
+ nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED);
+ NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_STOPPED));
+
+ // Delay handling of STOPPED event till the end of events processing procedure.
+ // If penultimate byte is received and function gets interrupted for long enough
+ // after enabling BB_STOP shortcut, RXDREADY for last byte as well as STOPPED
+ // may be active at the same time. Therefore RXREADY has to be processed before STOPPED to
+ // acquire last byte before finishing transmission by returning 'false'.
+ stopped = true;
+ }
if (p_cb->error)
{
@@ -338,6 +368,7 @@ static bool twi_transfer(NRF_TWI_Type * p_twi,
if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_TXDSENT))
{
nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
+ ++(p_cb->bytes_transferred);
NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_TXDSENT));
if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR))
{
@@ -375,11 +406,13 @@ static bool twi_transfer(NRF_TWI_Type * p_twi,
}
}
- if (do_stop_check && nrf_twi_event_check(p_twi, NRF_TWI_EVENT_STOPPED))
+ if (stopped)
{
- nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED);
p_cb->prev_suspend = TWI_NO_SUSPEND;
- NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_STOPPED));
+ if (!p_cb->error)
+ {
+ p_cb->error = !xfer_completeness_check(p_twi, p_cb);
+ }
return false;
}
@@ -438,6 +471,10 @@ static nrfx_err_t twi_tx_start_transfer(NRF_TWI_Type * p_twi,
{
ret_code = twi_process_error(errorsrc);
}
+ else
+ {
+ ret_code = NRFX_ERROR_INTERNAL;
+ }
}
if (hw_timeout <= 0)
@@ -507,6 +544,10 @@ static nrfx_err_t twi_rx_start_transfer(NRF_TWI_Type * p_twi,
{
ret_code = twi_process_error(errorsrc);
}
+ else
+ {
+ ret_code = NRFX_ERROR_INTERNAL;
+ }
}
if (hw_timeout <= 0)
{
@@ -675,6 +716,11 @@ static void twi_irq_handler(NRF_TWI_Type * p_twi, twi_control_block_t * p_cb)
event.type = NRFX_TWI_EVT_OVERRUN;
NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_OVERRUN));
}
+ else
+ {
+ event.type = NRFX_TWI_EVT_BUS_ERROR;
+ NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_BUS_ERROR));
+ }
}
else
{
@@ -684,7 +730,7 @@ static void twi_irq_handler(NRF_TWI_Type * p_twi, twi_control_block_t * p_cb)
p_cb->busy = false;
- if (!(TWI_FLAG_NO_HANDLER_IN_USE(p_cb->flags)))
+ if (!(TWI_FLAG_NO_HANDLER_IN_USE(p_cb->flags)) || p_cb->error)
{
p_cb->handler(&event, p_cb->p_context);
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi_twim.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi_twim.c
index f37c227..8452ccf 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi_twim.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi_twim.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c
index 94ba4e7..8c0085c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -51,7 +51,9 @@
(event == NRFX_TWIM_EVT_DONE ? "EVT_DONE" : \
(event == NRFX_TWIM_EVT_ADDRESS_NACK ? "EVT_ADDRESS_NACK" : \
(event == NRFX_TWIM_EVT_DATA_NACK ? "EVT_DATA_NACK" : \
- "UNKNOWN ERROR")))
+ (event == NRFX_TWIM_EVT_OVERRUN ? "EVT_OVERRUN" : \
+ (event == NRFX_TWIM_EVT_BUS_ERROR ? "EVT_BUS_ERROR" : \
+ "UNKNOWN ERROR")))))
#define EVT_TO_STR_TWIM(event) \
(event == NRF_TWIM_EVENT_STOPPED ? "NRF_TWIM_EVENT_STOPPED" : \
@@ -157,11 +159,11 @@ static nrfx_err_t twi_process_error(uint32_t errorsrc)
return ret;
}
-static bool xfer_completeness_check(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb)
+static bool xfer_completeness_check(NRF_TWIM_Type * p_twim, twim_control_block_t const * p_cb)
{
// If the actual number of transferred bytes is not equal to what was requested,
// but there was no error signaled by the peripheral, this means that something
- // unexpected, like a premature STOP condition, happened on the bus.
+ // unexpected, like a premature STOP condition, was received on the bus.
// In such case the peripheral has to be disabled and re-enabled, so that its
// internal state machine is reinitialized.
@@ -169,9 +171,12 @@ static bool xfer_completeness_check(NRF_TWIM_Type * p_twim, twim_control_block_t
switch (p_cb->xfer_desc.type)
{
case NRFX_TWIM_XFER_TXTX:
- if (((p_cb->int_mask == (NRF_TWIM_INT_SUSPENDED_MASK | NRF_TWIM_INT_ERROR_MASK)) &&
+ // int_mask variable is used to determine which length should be checked
+ // against number of bytes latched in EasyDMA.
+ // NRF_TWIM_INT_SUSPENDED_MASK is configured only in first TX of TXTX transfer.
+ if (((p_cb->int_mask & NRF_TWIM_INT_SUSPENDED_MASK) &&
(nrf_twim_txd_amount_get(p_twim) != p_cb->xfer_desc.primary_length)) ||
- ((p_cb->int_mask == (NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK)) &&
+ (!(p_cb->int_mask & NRF_TWIM_INT_SUSPENDED_MASK) &&
(nrf_twim_txd_amount_get(p_twim) != p_cb->xfer_desc.secondary_length)))
{
transfer_complete = false;
@@ -376,7 +381,6 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
{
nrfx_err_t err_code = NRFX_SUCCESS;
nrf_twim_task_t start_task = NRF_TWIM_TASK_STARTTX;
- nrf_twim_event_t evt_to_wait = NRF_TWIM_EVENT_STOPPED;
p_cb->error = false;
if (!nrfx_is_in_ram(p_xfer_desc->p_primary_buf))
@@ -406,10 +410,13 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
p_cb->xfer_desc = *p_xfer_desc;
p_cb->repeated = (flags & NRFX_TWIM_FLAG_REPEATED_XFER) ? true : false;
+ p_cb->flags = flags;
nrf_twim_address_set(p_twim, p_xfer_desc->address);
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_STOPPED);
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR);
+ nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX);
+ nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED);
twim_list_enable_handle(p_twim, flags);
switch (p_xfer_desc->type)
@@ -429,8 +436,6 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK);
nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED);
- nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX);
- nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED);
nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STARTTX);
while (!nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_TXSTARTED))
@@ -438,7 +443,7 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_TXSTARTED));
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED);
nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_secondary_buf, p_xfer_desc->secondary_length);
- p_cb->int_mask = NRF_TWIM_INT_SUSPENDED_MASK | NRF_TWIM_INT_ERROR_MASK;
+ p_cb->int_mask = NRF_TWIM_INT_SUSPENDED_MASK;
break;
case NRFX_TWIM_XFER_TXRX:
nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
@@ -453,7 +458,7 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
nrf_twim_rx_buffer_set(p_twim, p_xfer_desc->p_secondary_buf, p_xfer_desc->secondary_length);
nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STARTRX_MASK |
NRF_TWIM_SHORT_LASTRX_STOP_MASK);
- p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+ p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK;
nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
break;
case NRFX_TWIM_XFER_TX:
@@ -461,21 +466,19 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
if (NRFX_TWIM_FLAG_TX_NO_STOP & flags)
{
nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK);
- p_cb->int_mask = NRF_TWIM_INT_SUSPENDED_MASK | NRF_TWIM_INT_ERROR_MASK;
- nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED);
- evt_to_wait = NRF_TWIM_EVENT_SUSPENDED;
+ p_cb->int_mask = NRF_TWIM_INT_SUSPENDED_MASK;
}
else
{
nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STOP_MASK);
- p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+ p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK;
}
nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
break;
case NRFX_TWIM_XFER_RX:
nrf_twim_rx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTRX_STOP_MASK);
- p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+ p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK;
start_task = NRF_TWIM_TASK_STARTRX;
nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
break;
@@ -493,35 +496,90 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
{
if (flags & NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER)
{
- p_cb->int_mask = NRF_TWIM_INT_ERROR_MASK;
+ p_cb->int_mask = 0;
+ }
+
+ if (!(flags & NRFX_TWIM_FLAG_NO_SPURIOUS_STOP_CHECK))
+ {
+ p_cb->int_mask |= NRF_TWIM_INT_STOPPED_MASK;
}
+
+ // Interrupts for ERROR are implicitly enabled, regardless of driver configuration.
+ p_cb->int_mask |= NRF_TWIM_INT_ERROR_MASK;
nrf_twim_int_enable(p_twim, p_cb->int_mask);
#if NRFX_CHECK(NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED)
- if ((flags & NRFX_TWIM_FLAG_HOLD_XFER) && ((p_xfer_desc->type == NRFX_TWIM_XFER_TX) ||
- (p_xfer_desc->type == NRFX_TWIM_XFER_TXRX)))
+ if ((flags & NRFX_TWIM_FLAG_HOLD_XFER) && (p_xfer_desc->type != NRFX_TWIM_XFER_RX))
{
- p_cb->flags = flags;
twim_list_enable_handle(p_twim, 0);
p_twim->FREQUENCY = 0;
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED);
nrf_twim_int_enable(p_twim, NRF_TWIM_INT_TXSTARTED_MASK);
+ }
+ else
+ {
+ nrf_twim_frequency_set(p_twim, p_cb->bus_frequency);
}
#endif
}
else
{
- while (!nrf_twim_event_check(p_twim, evt_to_wait))
- {
+ bool transmission_finished = false;
+ do {
+ if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_SUSPENDED))
+ {
+ NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_SUSPENDED));
+ transmission_finished = true;
+ }
+
+ if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_STOPPED))
+ {
+ nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_STOPPED);
+ NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_STOPPED));
+ transmission_finished = true;
+ }
+
if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_ERROR))
{
- NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_ERROR));
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR);
- nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
- nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP);
- evt_to_wait = NRF_TWIM_EVENT_STOPPED;
+ NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_ERROR));
+
+ bool lasttx_triggered = nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_LASTTX);
+ uint32_t shorts_mask = nrf_twim_shorts_get(p_twim);
+
+ if (!(lasttx_triggered && (shorts_mask & NRF_TWIM_SHORT_LASTTX_STOP_MASK)))
+ {
+ // Unless LASTTX event arrived and LASTTX_STOP shortcut is active,
+ // triggering of STOP task in case of error has to be done manually.
+ nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+ nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP);
+
+ // Mark transmission as not finished yet,
+ // as STOPPED event is expected to arrive.
+ // If LASTTX_SUSPENDED shortcut is active,
+ // NACK has been received on last byte sent
+ // and SUSPENDED event happened to be checked before ERROR,
+ // transmission will be marked as finished.
+ // In such case this flag has to be overwritten.
+ transmission_finished = false;
+ }
+
+ if (lasttx_triggered && (shorts_mask & NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK))
+ {
+ // When STOP task was triggered just before SUSPEND task has taken effect,
+ // SUSPENDED event may not arrive.
+ // However if SUSPENDED arrives it always arrives after ERROR.
+ // Therefore SUSPENDED has to be cleared
+ // so it does not cause premature termination of busy loop
+ // waiting for STOPPED event to arrive.
+ nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED);
+
+ // Mark transmission as not finished yet,
+ // for same reasons as above.
+ transmission_finished = false;
+ }
}
- }
+ } while (!transmission_finished);
uint32_t errorsrc = nrf_twim_errorsrc_get_and_clear(p_twim);
@@ -533,7 +591,8 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
}
else
{
- if (!xfer_completeness_check(p_twim, p_cb))
+ if (!(flags & NRFX_TWIM_FLAG_NO_SPURIOUS_STOP_CHECK) &&
+ !xfer_completeness_check(p_twim, p_cb))
{
err_code = NRFX_ERROR_INTERNAL;
}
@@ -626,8 +685,12 @@ static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb
p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK;
nrf_twim_int_enable(p_twim, p_cb->int_mask);
- nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
- nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP);
+ if (!(nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_LASTTX) &&
+ (nrf_twim_shorts_get(p_twim) & NRF_TWIM_SHORT_LASTTX_STOP_MASK)))
+ {
+ nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+ nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP);
+ }
p_cb->error = true;
return;
@@ -640,19 +703,43 @@ static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb
{
NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_STOPPED));
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_STOPPED);
- event.xfer_desc = p_cb->xfer_desc;
- if (!p_cb->error)
+
+ if (!(p_cb->flags & NRFX_TWIM_FLAG_NO_SPURIOUS_STOP_CHECK) && !p_cb->error)
{
p_cb->error = !xfer_completeness_check(p_twim, p_cb);
}
- nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX);
- nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTRX);
- if (!p_cb->repeated || p_cb->error)
+
+ // Further processing of STOPPED event is valid only if NO_XFER_EVT_HANDLER
+ // setting is not used.
+ if (!(p_cb->flags & NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER))
{
- nrf_twim_shorts_set(p_twim, 0);
- p_cb->int_mask = 0;
- nrf_twim_int_disable(p_twim, NRF_TWIM_ALL_INTS_MASK);
+ event.xfer_desc = p_cb->xfer_desc;
+ nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX);
+ nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTRX);
+ if (!p_cb->repeated || p_cb->error)
+ {
+ nrf_twim_shorts_set(p_twim, 0);
+ p_cb->int_mask = 0;
+ nrf_twim_int_disable(p_twim, NRF_TWIM_ALL_INTS_MASK);
+
+ // At this point interrupt handler should not be invoked again for current transfer.
+ // If STOPPED arrived during ERROR processing,
+ // its pending interrupt should be ignored.
+ // Otherwise spurious NRFX_TWIM_EVT_DONE or NRFX_TWIM_EVT_BUS_ERROR
+ // would be passed to user's handler.
+ NRFX_IRQ_PENDING_CLEAR(nrfx_get_irq_number(p_twim));
+ }
+ }
+
+#if NRFX_CHECK(NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED)
+ else if (p_cb->xfer_desc.type != NRFX_TWIM_XFER_RX)
+ {
+ /* Add Anomaly 109 workaround for each potential repeated transfer starting from TX. */
+ twim_list_enable_handle(p_twim, 0);
+ p_twim->FREQUENCY = 0;
+ nrf_twim_int_enable(p_twim, NRF_TWIM_INT_TXSTARTED_MASK);
}
+#endif
}
else
{
@@ -666,6 +753,13 @@ static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb
nrf_twim_shorts_set(p_twim, 0);
p_cb->int_mask = 0;
nrf_twim_int_disable(p_twim, NRF_TWIM_ALL_INTS_MASK);
+
+ // At this point interrupt handler should not be invoked again for current transfer.
+ // If STOPPED arrived during SUSPENDED processing,
+ // its pending interrupt should be ignored.
+ // Otherwise spurious NRFX_TWIM_EVT_DONE or NRFX_TWIM_EVT_BUS_ERROR
+ // would be passed to user's handler.
+ NRFX_IRQ_PENDING_CLEAR(nrfx_get_irq_number(p_twim));
}
}
else
@@ -693,19 +787,17 @@ static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb
}
else if (errorsrc & NRF_TWIM_ERROR_OVERRUN)
{
- event.type = NRFX_TWIM_EVT_DATA_NACK;
- NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWIM_EVT_DATA_NACK));
+ event.type = NRFX_TWIM_EVT_OVERRUN;
+ NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWIM_EVT_OVERRUN));
+ }
+ else if (p_cb->error)
+ {
+ event.type = NRFX_TWIM_EVT_BUS_ERROR;
+ NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWIM_EVT_BUS_ERROR));
}
else
{
- if (p_cb->error)
- {
- event.type = NRFX_TWIM_EVT_BUS_ERROR;
- }
- else
- {
- event.type = NRFX_TWIM_EVT_DONE;
- }
+ event.type = NRFX_TWIM_EVT_DONE;
NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWIM_EVT_DONE));
}
@@ -714,7 +806,10 @@ static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb
p_cb->busy = false;
}
- p_cb->handler(&event, p_cb->p_context);
+ if (!(p_cb->flags & NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER) || p_cb->error)
+ {
+ p_cb->handler(&event, p_cb->p_context);
+ }
}
#if NRFX_CHECK(NRFX_TWIM0_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c
index 10b827f..9298348 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uart.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uart.c
index 64edf86..e8c5a96 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uart.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c
index 64a43e8..88a06d3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -191,6 +191,38 @@ static void pins_to_default(nrfx_uarte_t const * p_instance)
}
}
+static void apply_workaround_for_enable_anomaly(nrfx_uarte_t const * p_instance)
+{
+#if defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) || defined(NRF9160_XXAA)
+ // Apply workaround for anomalies:
+ // - nRF9160 - anomaly 23
+ // - nRF5340 - anomaly 44
+ volatile uint32_t const * rxenable_reg =
+ (volatile uint32_t *)(((uint32_t)p_instance->p_reg) + 0x564);
+ volatile uint32_t const * txenable_reg =
+ (volatile uint32_t *)(((uint32_t)p_instance->p_reg) + 0x568);
+
+ if (*txenable_reg == 1)
+ {
+ nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPTX);
+ }
+
+ if (*rxenable_reg == 1)
+ {
+ nrf_uarte_enable(p_instance->p_reg);
+ nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX);
+
+ while (*rxenable_reg)
+ {}
+
+ (void)nrf_uarte_errorsrc_get_and_clear(p_instance->p_reg);
+ nrf_uarte_disable(p_instance->p_reg);
+ }
+#else
+ (void)(p_instance);
+#endif // defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) || defined(NRF9160_XXAA)
+}
+
nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance,
nrfx_uarte_config_t const * p_config,
nrfx_uarte_event_handler_t event_handler)
@@ -236,6 +268,8 @@ nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance,
apply_config(p_instance, p_config);
+ apply_workaround_for_enable_anomaly(p_instance);
+
p_cb->handler = event_handler;
p_cb->p_context = p_config->p_context;
@@ -258,6 +292,7 @@ nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance,
void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance)
{
uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+ NRF_UARTE_Type * p_reg = p_instance->p_reg;
if (p_cb->handler)
{
@@ -265,18 +300,28 @@ void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance)
}
// Make sure all transfers are finished before UARTE is disabled
// to achieve the lowest power consumption.
- nrf_uarte_shorts_disable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX);
- nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX);
- nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED);
- nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPTX);
- while (!nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED))
+ nrf_uarte_shorts_disable(p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX);
+
+ // Check if there is any ongoing reception.
+ if (p_cb->rx_buffer_length)
+ {
+ nrf_uarte_event_clear(p_reg, NRF_UARTE_EVENT_RXTO);
+ nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPRX);
+ }
+
+ nrf_uarte_event_clear(p_reg, NRF_UARTE_EVENT_TXSTOPPED);
+ nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPTX);
+
+ // Wait for TXSTOPPED event and for RXTO event, provided that there was ongoing reception.
+ while (!nrf_uarte_event_check(p_reg, NRF_UARTE_EVENT_TXSTOPPED) ||
+ (p_cb->rx_buffer_length && !nrf_uarte_event_check(p_reg, NRF_UARTE_EVENT_RXTO)))
{}
- nrf_uarte_disable(p_instance->p_reg);
+ nrf_uarte_disable(p_reg);
pins_to_default(p_instance);
#if NRFX_CHECK(NRFX_PRS_ENABLED)
- nrfx_prs_release(p_instance->p_reg);
+ nrfx_prs_release(p_reg);
#endif
p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c
index 17f3bfc..c0598e0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -809,19 +809,19 @@ static inline void usbd_ep_abort(nrfx_usbd_ep_t ep)
/* Workaround: Disarm the endpoint if there is any data buffered. */
if(ep != NRFX_USBD_EPIN0)
{
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7B6 + (2u * (NRF_USBD_EP_NR_GET(ep) - 1));
- uint8_t temp = *((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7B6 + (2u * (NRF_USBD_EP_NR_GET(ep) - 1));
+ uint8_t temp = *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
temp |= (1U << 1);
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) |= temp;
- (void)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) |= temp;
+ (void)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
}
else
{
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7B4;
- uint8_t temp = *((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7B4;
+ uint8_t temp = *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
temp |= (1U << 2);
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) |= temp;
- (void)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) |= temp;
+ (void)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
}
}
if ((m_ep_dma_waiting | (~m_ep_ready)) & (1U << ep2bit(ep)))
@@ -1466,7 +1466,7 @@ static void usbd_dmareq_process(void)
}
nrfx_systick_delay_us(30);
- while (0 == (0x20 & *((volatile uint32_t *)(NRF_USBD_BASE + 0x474))))
+ while (0 == (0x20 & *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x474))))
{
nrfx_systick_delay_us(2);
}
@@ -1573,54 +1573,54 @@ void nrfx_usbd_irq_handler(void)
{
uint8_t usbi, uoi, uii;
/* Testing */
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7A9;
- uii = (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7A9;
+ uii = (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
if (0 != uii)
{
- uii &= (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ uii &= (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
}
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AA;
- uoi = (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AA;
+ uoi = (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
if (0 != uoi)
{
- uoi &= (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ uoi &= (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
}
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AB;
- usbi = (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AB;
+ usbi = (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
if (0 != usbi)
{
- usbi &= (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ usbi &= (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
}
/* Processing */
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AC;
- uii &= (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AC;
+ uii &= (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
if (0 != uii)
{
uint8_t rb;
m_simulated_dataepstatus |= ((uint32_t)uii) << NRFX_USBD_EPIN_BITPOS_0;
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7A9;
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = uii;
- rb = (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7A9;
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) = uii;
+ rb = (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" uii: 0x%.2x (0x%.2x)", uii, rb);
(void)rb;
}
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AD;
- uoi &= (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AD;
+ uoi &= (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
if (0 != uoi)
{
uint8_t rb;
m_simulated_dataepstatus |= ((uint32_t)uoi) << NRFX_USBD_EPOUT_BITPOS_0;
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AA;
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = uoi;
- rb = (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AA;
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) = uoi;
+ rb = (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" uoi: 0x%.2u (0x%.2x)", uoi, rb);
(void)rb;
}
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AE;
- usbi &= (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AE;
+ usbi &= (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
if (0 != usbi)
{
uint8_t rb;
@@ -1632,9 +1632,9 @@ void nrfx_usbd_irq_handler(void)
{
active |= USBD_INTEN_USBRESET_Msk;
}
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AB;
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = usbi;
- rb = (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AB;
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) = usbi;
+ rb = (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" usbi: 0x%.2u (0x%.2x)", usbi, rb);
(void)rb;
}
@@ -1791,8 +1791,8 @@ void nrfx_usbd_enable(void)
if (nrfx_usbd_errata_166())
{
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7E3;
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = 0x40;
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7E3;
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) = 0x40;
__ISB();
__DSB();
}
@@ -2339,9 +2339,9 @@ void nrfx_usbd_transfer_out_drop(nrfx_usbd_ep_t ep)
{
NRFX_CRITICAL_SECTION_ENTER();
m_ep_ready &= ~(1U << ep2bit(ep));
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7C5 + (2u * NRF_USBD_EP_NR_GET(ep));
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = 0;
- (void)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7C5 + (2u * NRF_USBD_EP_NR_GET(ep));
+ *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) = 0;
+ (void)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
NRFX_CRITICAL_SECTION_EXIT();
}
else
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h
index c50d9de..76f0c87 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,6 +33,8 @@
#define NRFX_USBD_ERRATA_H__
#include <stdbool.h>
+#include <nrfx.h>
+#include <nrf_erratas.h>
#ifndef NRFX_USBD_ERRATA_ENABLE
/**
@@ -43,106 +45,46 @@
#define NRFX_USBD_ERRATA_ENABLE 1
#endif
-static inline bool nrfx_usbd_errata_type_52840(void)
-{
- return (*(uint32_t const *)0x10000130UL == 0x8UL);
-}
-
-static inline bool nrfx_usbd_errata_type_52840_eng_a_or_later(void)
-{
- return nrfx_usbd_errata_type_52840();
-}
-
-static inline bool nrfx_usbd_errata_type_52840_eng_b_or_later(void)
-{
- return (nrfx_usbd_errata_type_52840() && (*(uint32_t const *)0x10000134UL >= 0x1UL));
-}
-
-static inline bool nrfx_usbd_errata_type_52840_eng_c_or_later(void)
-{
- return (nrfx_usbd_errata_type_52840() && (*(uint32_t const *)0x10000134UL >= 0x2UL));
-}
-
-static inline bool nrfx_usbd_errata_type_52840_eng_d_or_later(void)
-{
- return (nrfx_usbd_errata_type_52840() && (*(uint32_t const *)0x10000134UL >= 0x3UL));
-}
-
-static inline bool nrfx_usbd_errata_type_52833(void)
-{
- return (*(uint32_t const *)0x10000130UL == 0x0DUL);
-}
-
-static inline bool nrfx_usbd_errata_type_52833_eng_a_or_later(void)
-{
- return nrfx_usbd_errata_type_52833();
-}
-
-/* Errata: USBD: EPDATA event is not always generated.
- *
- * Applies to nRF52840 Engineering A.
- **/
+/* Errata: USBD: EPDATA event is not always generated. **/
static inline bool nrfx_usbd_errata_104(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && (nrfx_usbd_errata_type_52840()
- && !nrfx_usbd_errata_type_52840_eng_b_or_later()));
+ return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_104();
}
-/* Errata: During setup read/write transfer USBD acknowledges setup stage without SETUP task.
- *
- * Applies to nRF52840 Engineering A.
- **/
+/* Errata: During setup read/write transfer USBD acknowledges setup stage without SETUP task. **/
static inline bool nrfx_usbd_errata_154(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && (nrfx_usbd_errata_type_52840()
- && !nrfx_usbd_errata_type_52840_eng_b_or_later()));
+ return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_154();
}
-/* Errata: ISO double buffering not functional.
- *
- * Applies to nRF52840.
- **/
+/* Errata: ISO double buffering not functional. **/
static inline bool nrfx_usbd_errata_166(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840());
+ return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_166();
}
-/* Errata: USBD might not reach its active state.
- *
- * Applies to nRF52840.
- **/
+/* Errata: USBD might not reach its active state. **/
static inline bool nrfx_usbd_errata_171(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840());
+ return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_171();
}
-/* Errata: USB cannot be enabled.
- *
- * Applies to nRF52840 Engineering B or later and nRF52833.
- **/
+/* Errata: USB cannot be enabled. **/
static inline bool nrfx_usbd_errata_187(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && (nrfx_usbd_errata_type_52840_eng_b_or_later()
- || nrfx_usbd_errata_type_52833()));
+ return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_187();
}
-/* Errata: USBD cannot receive tasks during DMA.
- *
- * Applies to nRF52840.
- **/
+/* Errata: USBD cannot receive tasks during DMA. **/
static inline bool nrfx_usbd_errata_199(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840());
+ return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_199();
}
-/* Errata: SIZE.EPOUT not writable.
- *
- * Applies to nRF52840 Engineering A.
- **/
+/* Errata: SIZE.EPOUT not writable. **/
static inline bool nrfx_usbd_errata_200(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && (nrfx_usbd_errata_type_52840()
- && !nrfx_usbd_errata_type_52840_eng_b_or_later()));
+ return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_200();
}
#endif // NRFX_USBD_ERRATA_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbreg.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbreg.c
new file mode 100644
index 0000000..abac8b4
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbreg.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <nrfx.h>
+
+#if NRFX_CHECK(NRFX_USBREG_ENABLED)
+
+#include <nrfx_usbreg.h>
+
+static nrfx_usbreg_event_handler_t m_usbevt_handler;
+
+nrfx_usbreg_event_handler_t nrfx_usbreg_handler_get(void)
+{
+ return m_usbevt_handler;
+}
+
+void nrfx_usbreg_init(nrfx_usbreg_config_t const * p_config)
+{
+ NRFX_ASSERT(p_config != NULL);
+ NRFX_ASSERT(p_config->handler != NULL);
+
+ nrfx_usbreg_uninit();
+ m_usbevt_handler = p_config->handler;
+
+ NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_USBREGULATOR), p_config->irq_priority);
+ NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_USBREGULATOR));
+}
+
+void nrfx_usbreg_enable(void)
+{
+ nrf_usbreg_int_enable(NRF_USBREGULATOR, NRF_USBREG_INT_USBDETECTED |
+ NRF_USBREG_INT_USBREMOVED |
+ NRF_USBREG_INT_USBPWRRDY);
+}
+
+void nrfx_usbreg_disable(void)
+{
+ nrf_usbreg_int_disable(NRF_USBREGULATOR, NRF_USBREG_INT_USBDETECTED |
+ NRF_USBREG_INT_USBREMOVED |
+ NRF_USBREG_INT_USBPWRRDY);
+}
+
+void nrfx_usbreg_uninit(void)
+{
+ nrfx_usbreg_disable();
+ NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_USBREGULATOR));
+ m_usbevt_handler = NULL;
+}
+
+void nrfx_usbreg_irq_handler(void)
+{
+ if (nrf_usbreg_event_check(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBDETECTED))
+ {
+ nrf_usbreg_event_clear(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBDETECTED);
+ m_usbevt_handler(NRFX_USBREG_EVT_DETECTED);
+ }
+ if (nrf_usbreg_event_check(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBREMOVED))
+ {
+ nrf_usbreg_event_clear(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBREMOVED);
+ m_usbevt_handler(NRFX_USBREG_EVT_REMOVED);
+ }
+ if (nrf_usbreg_event_check(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBPWRRDY))
+ {
+ nrf_usbreg_event_clear(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBPWRRDY);
+ m_usbevt_handler(NRFX_USBREG_EVT_READY);
+ }
+}
+
+#endif // NRFX_CHECK(NRFX_USBREG_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_wdt.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_wdt.c
index 863b3ac..63dec1c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_wdt.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_wdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.c
index 4eaf178..37de8b9 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h b/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h
index 693b273..2767b54 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -82,8 +82,12 @@ extern "C" {
#define NRFX_PRS_BOX_0_ADDR NRF_UARTE0
// SPIM1, SPIS1, TWIM1, TWIS1, UARTE1
#define NRFX_PRS_BOX_1_ADDR NRF_UARTE1
+ // SPIM2, SPIS2, TWIM2, TWIS2, UARTE2
+ #define NRFX_PRS_BOX_2_ADDR NRF_UARTE2
+ // SPIM3, SPIS3, TWIM3, TWIS3, UARTE3
+ #define NRFX_PRS_BOX_3_ADDR NRF_UARTE3
// COMP, LPCOMP
- #define NRFX_PRS_BOX_2_ADDR NRF_COMP
+ #define NRFX_PRS_BOX_4_ADDR NRF_COMP
#elif defined(NRF5340_XXAA_NETWORK)
// SPIM0, SPIS0, TWIM0, TWIS0, UARTE0
#define NRFX_PRS_BOX_0_ADDR NRF_UARTE0
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_aar.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_aar.h
index 6d2828b..0b35fae 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_aar.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_aar.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_acl.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_acl.h
index d07b52d..b205a2e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_acl.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_acl.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_adc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_adc.h
index 951a4a9..2313130 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_adc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_adc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_bprot.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_bprot.h
index bbb97d1..18d8247 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_bprot.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_bprot.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -67,8 +67,7 @@ NRF_STATIC_INLINE void nrf_bprot_nvm_blocks_protection_enable(NRF_BPROT_Type * p
* NVM protection is disabled by default while debugging.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] enable True if NVM protection during debug is to be enabled.
- * False if otherwise.
+ * @param[in] enable True if NVM protection during debug is to be enabled, false otherwise.
*/
NRF_STATIC_INLINE void nrf_bprot_nvm_protection_in_debug_set(NRF_BPROT_Type * p_reg,
bool enable);
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_cache.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_cache.h
index dd1ff43..28d5b79 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_cache.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_cache.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -101,8 +101,7 @@ NRF_STATIC_INLINE void nrf_cache_erase_status_clear(NRF_CACHE_Type * p_reg);
* @brief Function for setting the cache profiling.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] enable True if cache profiling is to be enabled.
- * False if otherwise.
+ * @param[in] enable True if cache profiling is to be enabled, false otherwise.
*/
NRF_STATIC_INLINE void nrf_cache_profiling_set(NRF_CACHE_Type * p_reg, bool enable);
@@ -184,8 +183,7 @@ NRF_STATIC_INLINE uint32_t nrf_cache_data_miss_counter_get(NRF_CACHE_Type const
* @note -Disabling the RAM mode causes the cache to be invalidated.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] enable True if the cache RAM mode is to be enabled.
- * False if otherwise.
+ * @param[in] enable True if the cache RAM mode is to be enabled, false otherwise.
*/
NRF_STATIC_INLINE void nrf_cache_ram_mode_set(NRF_CACHE_Type * p_reg, bool enable);
@@ -210,8 +208,7 @@ NRF_STATIC_INLINE void nrf_cache_read_lock_enable(NRF_CACHE_Type * p_reg);
* @note Blocking is ignored in the RAM mode.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] enable True if cache content update lock is to be enabled.
- * False if otherwise.
+ * @param[in] enable True if cache content update lock is to be enabled, false otherwise.
*/
NRF_STATIC_INLINE void nrf_cache_update_lock_set(NRF_CACHE_Type * p_reg, bool enable);
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h
index 7813046..189eca2 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -421,7 +421,12 @@ NRF_STATIC_INLINE void nrf_ccm_cnfptr_set(NRF_CCM_Type * p_reg,
NRF_STATIC_INLINE uint32_t * nrf_ccm_cnfptr_get(NRF_CCM_Type const * p_reg)
{
+#if defined(NRF5340_XXAA_NETWORK)
+ // Apply workaround for anomaly 10.
+ return (uint32_t *)(p_reg->CNFPTR | 0x01000000);
+#else
return (uint32_t *)(p_reg->CNFPTR);
+#endif
}
NRF_STATIC_INLINE void nrf_ccm_inptr_set(NRF_CCM_Type * p_reg,
@@ -432,7 +437,12 @@ NRF_STATIC_INLINE void nrf_ccm_inptr_set(NRF_CCM_Type * p_reg,
NRF_STATIC_INLINE uint32_t * nrf_ccm_inptr_get(NRF_CCM_Type const * p_reg)
{
+#if defined(NRF5340_XXAA_NETWORK)
+ // Apply workaround for anomaly 10.
+ return (uint32_t *)(p_reg->INPTR | 0x01000000);
+#else
return (uint32_t *)(p_reg->INPTR);
+#endif
}
NRF_STATIC_INLINE void nrf_ccm_outptr_set(NRF_CCM_Type * p_reg,
@@ -443,7 +453,12 @@ NRF_STATIC_INLINE void nrf_ccm_outptr_set(NRF_CCM_Type * p_reg,
NRF_STATIC_INLINE uint32_t * nrf_ccm_outptr_get(NRF_CCM_Type const * p_reg)
{
+#if defined(NRF5340_XXAA_NETWORK)
+ // Apply workaround for anomaly 10.
+ return (uint32_t *)(p_reg->OUTPTR | 0x01000000);
+#else
return (uint32_t *)(p_reg->OUTPTR);
+#endif
}
NRF_STATIC_INLINE void nrf_ccm_scratchptr_set(NRF_CCM_Type * p_reg,
@@ -454,7 +469,12 @@ NRF_STATIC_INLINE void nrf_ccm_scratchptr_set(NRF_CCM_Type * p_reg,
NRF_STATIC_INLINE uint32_t * nrf_ccm_stratchptr_get(NRF_CCM_Type const * p_reg)
{
+#if defined(NRF5340_XXAA_NETWORK)
+ // Apply workaround for anomaly 10.
+ return (uint32_t *)(p_reg->SCRATCHPTR | 0x01000000);
+#else
return (uint32_t *)(p_reg->SCRATCHPTR);
+#endif
}
#if defined(CCM_RATEOVERRIDE_RATEOVERRIDE_Pos)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h
index 0169f82..553e19b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -44,8 +44,9 @@ extern "C" {
* @ingroup nrf_clock
* @brief Hardware access layer for managing the CLOCK peripheral.
*
- * This code can be used to managing low-frequency clock (LFCLK) and the high-frequency clock
- * (HFCLK) settings.
+ * This code can be used to manage low-frequency clock (LFCLK), high-frequency clock (HFCLK),
+ * high-frequency 192 MHz clock (HFCLK192M) and high-frequency audio clock (HFCLKAUDIO)
+ * settings.
*/
#if defined(CLOCK_LFCLKSRC_BYPASS_Msk) && defined(CLOCK_LFCLKSRC_EXTERNAL_Msk)
@@ -53,16 +54,57 @@ extern "C" {
#define NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES
#endif
-#if defined(CLOCK_CTIV_CTIV_Msk) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief Presence of the Low Frequency Clock calibration.
- *
- * In some MCUs there is possibility to use LFCLK calibration.
- */
+#if defined(CLOCK_INTENSET_DONE_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of the Low Frequency Clock calibration. */
#define NRF_CLOCK_HAS_CALIBRATION 1
#else
#define NRF_CLOCK_HAS_CALIBRATION 0
-#endif // defined(CLOCK_CTIV_CTIV_Msk) || defined(__NRFX_DOXYGEN__)
+#endif
+
+#if defined(CLOCK_CTIV_CTIV_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of the Low Frequency Clock calibration timer. */
+#define NRF_CLOCK_HAS_CALIBRATION_TIMER 1
+#else
+#define NRF_CLOCK_HAS_CALIBRATION_TIMER 0
+#endif
+
+#if (defined(CLOCK_INTENSET_HFCLK192MSTARTED_Msk) && !defined(NRF5340_XXAA_NETWORK)) \
+ || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of the 192 MHz clock. */
+#define NRF_CLOCK_HAS_HFCLK192M 1
+#else
+#define NRF_CLOCK_HAS_HFCLK192M 0
+#endif
+
+#if (defined(CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk) && !defined(NRF5340_XXAA_NETWORK)) \
+ || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of the Audio clock. */
+#define NRF_CLOCK_HAS_HFCLKAUDIO 1
+#else
+#define NRF_CLOCK_HAS_HFCLKAUDIO 0
+#endif
+
+#if (defined(CLOCK_HFCLKCTRL_HCLK_Msk) && !defined(NRF5340_XXAA_NETWORK)) \
+ || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of HFCLK frequency configuration. */
+#define NRF_CLOCK_HAS_HFCLK_DIV 1
+#else
+#define NRF_CLOCK_HAS_HFCLK_DIV 0
+#endif
+
+#if defined(CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of ALWAYSRUN registers. */
+#define NRF_CLOCK_HAS_ALWAYSRUN 1
+#else
+#define NRF_CLOCK_HAS_ALWAYSRUN 0
+#endif
+
+#if defined(CLOCK_HFCLKSRC_SRC_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of HFCLKSRC register. */
+#define NRF_CLOCK_HAS_HFCLKSRC 1
+#else
+#define NRF_CLOCK_HAS_HFCLKSRC 0
+#endif
/**
* @brief Low-frequency clock sources.
@@ -70,6 +112,9 @@ extern "C" {
*/
typedef enum
{
+#if defined(CLOCK_LFCLKSRC_SRC_LFULP) || defined(__NRFX_DOXYGEN__)
+ NRF_CLOCK_LFCLK_LFULP = CLOCK_LFCLKSRC_SRC_LFULP, /**< Internal 32 kHz Ultra-low power oscillator. */
+#endif
#if defined(CLOCK_LFCLKSRC_SRC_RC) || defined(__NRFX_DOXYGEN__)
NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */
#else
@@ -102,11 +147,16 @@ typedef enum
#endif // defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__)
} nrf_clock_lfclk_t;
-/** @brief High-frequency clock sources. */
+/**
+ * @brief High-frequency clock sources.
+ * @details Used by HFCLKSTAT and HFCLK192MSTAT registers.
+ */
typedef enum
{
#if defined(CLOCK_HFCLKSTAT_SRC_RC) || defined(__NRFX_DOXYGEN__)
NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_RC, /**< Internal 16 MHz RC oscillator. */
+#elif defined(CLOCK_HFCLKSTAT_SRC_HFINT)
+ NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_HFINT, /**< Internal 16 MHz RC oscillator. */
#endif
#if defined(CLOCK_HFCLKSTAT_SRC_Xtal) || defined(__NRFX_DOXYGEN__)
NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscillator. */
@@ -115,8 +165,39 @@ typedef enum
#endif
} nrf_clock_hfclk_t;
+/** @brief Clock domains. */
+typedef enum
+{
+ NRF_CLOCK_DOMAIN_LFCLK,
+ NRF_CLOCK_DOMAIN_HFCLK,
+#if NRF_CLOCK_HAS_HFCLK192M
+ NRF_CLOCK_DOMAIN_HFCLK192M,
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ NRF_CLOCK_DOMAIN_HFCLKAUDIO,
+#endif
+} nrf_clock_domain_t;
+
+#if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK192M
+/**
+ * @brief High-frequency clock frequency configuration.
+ * @details Used by HFCLKCTRL and HFCLK192MCTRL registers.
+ */
+typedef enum
+{
+ NRF_CLOCK_HFCLK_DIV_1 = CLOCK_HFCLKCTRL_HCLK_Div1, /**< Divide HFCLK/HFCLK192M by 1 */
+ NRF_CLOCK_HFCLK_DIV_2 = CLOCK_HFCLKCTRL_HCLK_Div2, /**< Divide HFCLK/HFCLK192M by 2 */
+#if NRF_CLOCK_HAS_HFCLK192M
+ NRF_CLOCK_HFCLK_DIV_4 = CLOCK_HFCLK192MCTRL_HCLK192M_Div4, /**< Divide HFCLK192M by 4 */
+#endif
+} nrf_clock_hfclk_div_t;
+#endif // NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK192M
+
/**
* @brief Trigger status of task LFCLKSTART/HFCLKSTART.
+ *
+ * @note This enum is deprecated.
+ *
* @details Used by LFCLKRUN and HFCLKRUN registers.
*/
typedef enum
@@ -128,15 +209,24 @@ typedef enum
/** @brief Interrupts. */
typedef enum
{
- NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */
- NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */
-#if (NRF_CLOCK_HAS_CALIBRATION) || defined(__NRFX_DOXYGEN__)
- NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */
- NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk, /**< Interrupt on CTTO event. */
+ NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */
+ NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */
+#if NRF_CLOCK_HAS_CALIBRATION
+ NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */
+#endif
+#if NRF_CLOCK_HAS_CALIBRATION_TIMER
+ NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk, /**< Interrupt on CTTO event. */
#endif
#if defined(CLOCK_INTENSET_CTSTARTED_Msk) || defined(__NRFX_DOXYGEN__)
- NRF_CLOCK_INT_CTSTARTED_MASK = CLOCK_INTENSET_CTSTARTED_Msk, /**< Interrupt on CTSTARTED event. */
- NRF_CLOCK_INT_CTSTOPPED_MASK = CLOCK_INTENSET_CTSTOPPED_Msk /**< Interrupt on CTSTOPPED event. */
+ NRF_CLOCK_INT_CTSTARTED_MASK = CLOCK_INTENSET_CTSTARTED_Msk, /**< Interrupt on CTSTARTED event. */
+ NRF_CLOCK_INT_CTSTOPPED_MASK = CLOCK_INTENSET_CTSTOPPED_Msk /**< Interrupt on CTSTOPPED event. */
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ NRF_CLOCK_INT_HFAUDIO_STARTED_MASK = CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk, /**< Interrupt on HFCLKAUDIOSTARTED event. */
+#endif
+
+#if NRF_CLOCK_HAS_HFCLK192M
+ NRF_CLOCK_INT_HF192M_STARTED_MASK = CLOCK_INTENSET_HFCLK192MSTARTED_Msk, /**< Interrupt on HFCLK192MSTARTED event. */
#endif
} nrf_clock_int_mask_t;
@@ -148,29 +238,47 @@ typedef enum
*/
typedef enum
{
- NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source.*/
- NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source.*/
- NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source.*/
- NRF_CLOCK_TASK_LFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP), /**< Stop LFCLK clock source.*/
-#if (NRF_CLOCK_HAS_CALIBRATION) || defined(__NRFX_DOXYGEN__)
- NRF_CLOCK_TASK_CAL = offsetof(NRF_CLOCK_Type, TASKS_CAL), /**< Start calibration of LFCLK RC oscillator.*/
- NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer.*/
- NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer.*/
+ NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source. */
+ NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source. */
+ NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source. */
+ NRF_CLOCK_TASK_LFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP), /**< Stop LFCLK clock source. */
+#if NRF_CLOCK_HAS_CALIBRATION
+ NRF_CLOCK_TASK_CAL = offsetof(NRF_CLOCK_Type, TASKS_CAL), /**< Start calibration of LFCLK RC oscillator. */
+#endif
+#if NRF_CLOCK_HAS_CALIBRATION_TIMER
+ NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer. */
+ NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer. */
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ NRF_CLOCK_TASK_HFCLKAUDIOSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKAUDIOSTART), /**< Start HFCLKAUDIO clock source. */
+ NRF_CLOCK_TASK_HFCLKAUDIOSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKAUDIOSTOP), /**< Stop HFCLKAUDIO clock source. */
+#endif
+#if NRF_CLOCK_HAS_HFCLK192M
+ NRF_CLOCK_TASK_HFCLK192MSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLK192MSTART), /**< Start HFCLK192M clock source. */
+ NRF_CLOCK_TASK_HFCLK192MSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLK192MSTOP), /**< Stop HFCLK192M clock source. */
#endif
} nrf_clock_task_t;
/** @brief Events. */
typedef enum
{
- NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started.*/
- NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started.*/
-#if (NRF_CLOCK_HAS_CALIBRATION) || defined(__NRFX_DOXYGEN__)
- NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed.*/
- NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO), /**< Calibration timer time-out.*/
+ NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started. */
+ NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started. */
+#if NRF_CLOCK_HAS_CALIBRATION
+ NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed. */
+#endif
+#if NRF_CLOCK_HAS_CALIBRATION_TIMER
+ NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO), /**< Calibration timer time-out. */
#endif
#if defined(CLOCK_INTENSET_CTSTARTED_Msk) || defined(__NRFX_DOXYGEN__)
- NRF_CLOCK_EVENT_CTSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_CTSTARTED), /**< Calibration timer started.*/
- NRF_CLOCK_EVENT_CTSTOPPED = offsetof(NRF_CLOCK_Type, EVENTS_CTSTOPPED) /**< Calibration timer stopped.*/
+ NRF_CLOCK_EVENT_CTSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_CTSTARTED), /**< Calibration timer started. */
+ NRF_CLOCK_EVENT_CTSTOPPED = offsetof(NRF_CLOCK_Type, EVENTS_CTSTOPPED) /**< Calibration timer stopped. */
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKAUDIOSTARTED), /**< HFCLKAUDIO oscillator started. */
+#endif
+#if NRF_CLOCK_HAS_HFCLK192M
+ NRF_CLOCK_EVENT_HFCLK192MSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLK192MSTARTED), /**< HFCLK192M oscillator started. */
#endif
} nrf_clock_event_t;
@@ -252,8 +360,37 @@ NRF_STATIC_INLINE void nrf_clock_event_clear(NRF_CLOCK_Type * p_reg, nrf_clock_e
NRF_STATIC_INLINE bool nrf_clock_event_check(NRF_CLOCK_Type const * p_reg, nrf_clock_event_t event);
/**
+ * @brief Function for retrieving the trigger status of the task START for given domain.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] domain Clock domain.
+ *
+ * @retval false The task START for the given domain has not been triggered.
+ * @retval true The task START for the given domain has been triggered.
+ */
+NRF_STATIC_INLINE bool nrf_clock_start_task_check(NRF_CLOCK_Type const * p_reg,
+ nrf_clock_domain_t domain);
+
+/**
+ * @brief Function for retrieving the state of the clock.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] domain Clock domain.
+ * @param[out] clk_src Clock source that is running. Set to NULL if not needed.
+ * Ignored for HFCLKAUDIO domain. Typecast it to @ref nrf_clock_lfclk_t for
+ * LFCLK and @ref nrf_clock_hfclk_t for HFCLK and HFCLK192M.
+ *
+ * @retval false The clock is not running.
+ * @retval true The clock is running.
+ */
+NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg,
+ nrf_clock_domain_t domain,
+ void * clk_src);
+
+/**
* @brief Function for changing the low-frequency clock source.
- * @details This function cannot be called when the low-frequency clock is running.
+ * @details Check in Product Specification if this function can be called when
+ * the low-frequency clock is running.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] source New low-frequency clock source.
@@ -277,6 +414,8 @@ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(NRF_CLOCK_Type const *
/**
* @brief Function for retrieving the active source of the low-frequency clock.
*
+ * @note This function is deprecated. Use @ref nrf_clock_is_running instead.
+ *
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @retval NRF_CLOCK_LFCLK_RC The internal 32 kHz RC oscillator
@@ -306,6 +445,8 @@ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type cons
/**
* @brief Function for retrieving the state of the LFCLK clock.
*
+ * @note This function is deprecated. Use @ref nrf_clock_is_running instead.
+ *
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @retval false The LFCLK clock is not running.
@@ -316,6 +457,8 @@ NRF_STATIC_INLINE bool nrf_clock_lf_is_running(NRF_CLOCK_Type const * p_reg);
/**
* @brief Function for retrieving the trigger status of the task LFCLKSTART.
*
+ * @note This function is deprecated. Use @ref nrf_clock_start_task_check instead.
+ *
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED The task LFCLKSTART has not been triggered.
@@ -324,14 +467,27 @@ NRF_STATIC_INLINE bool nrf_clock_lf_is_running(NRF_CLOCK_Type const * p_reg);
NRF_STATIC_INLINE
nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(NRF_CLOCK_Type const * p_reg);
+#if NRF_CLOCK_HAS_HFCLKSRC
+/**
+ * @brief Function for changing the high-frequency clock source.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] source New high-frequency clock source.
+ */
+NRF_STATIC_INLINE void nrf_clock_hf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source);
+#endif
+
/**
- * @brief Function for retrieving the active source of the high-frequency clock.
+ * @brief Function for retrieving the selected source of the high-frequency clock.
+ *
+ * For SoCs not featuring the HFCLKSRC register, this is always also the active source
+ * of the high-frequency clock.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY The internal RC oscillator is the active
+ * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY The internal RC oscillator is the selected
* source of the high-frequency clock.
- * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY An external crystal oscillator is the active
+ * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY An external crystal oscillator is the selected
* source of the high-frequency clock.
*/
NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(NRF_CLOCK_Type const * p_reg);
@@ -339,6 +495,8 @@ NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(NRF_CLOCK_Type const *
/**
* @brief Function for retrieving the state of the HFCLK clock.
*
+ * @note This function is deprecated. Use @ref nrf_clock_is_running instead.
+ *
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] clk_src Clock source to be checked.
*
@@ -351,6 +509,8 @@ NRF_STATIC_INLINE bool nrf_clock_hf_is_running(NRF_CLOCK_Type const * p_reg,
/**
* @brief Function for retrieving the trigger status of the task HFCLKSTART.
*
+ * @note This function is deprecated. Use @ref nrf_clock_start_task_check instead.
+ *
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED The task HFCLKSTART has not been triggered.
@@ -359,7 +519,38 @@ NRF_STATIC_INLINE bool nrf_clock_hf_is_running(NRF_CLOCK_Type const * p_reg,
NRF_STATIC_INLINE
nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(NRF_CLOCK_Type const * p_reg);
-#if (NRF_CLOCK_HAS_CALIBRATION) || defined(__NRFX_DOXYGEN__)
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+/**
+ * @brief Function for changing the Audio clock FREQ_VALUE.
+ *
+ * The frequency of HFCLKAUDIO ranges from 10.666 MHz to 13.333 MHz in 40.7 Hz steps.
+ * To calculate @p freq_value corresponding to the chosen frequency, use the following equation:
+ * FREQ_VALUE = 2^16 * ((12 * f_out / 32M) - 4)
+ *
+ * @warning Chosen frequency must fit in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] freq_value New FREQ_VALUE
+ */
+NRF_STATIC_INLINE
+void nrf_clock_hfclkaudio_config_set(NRF_CLOCK_Type * p_reg, uint16_t freq_value);
+
+/**
+ * @brief Function for retrieving the Audio clock FREQ_VALUE.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * The frequency of HFCLKAUDIO ranges from 10.666 MHz to 13.333 MHz in 40.7 Hz steps.
+ * To calculate frequency corresponding to the returned FREQ_VALUE, use the following equation:
+ * f_out = 32M * (4 + FREQ_VALUE * 2^(-16))/12
+
+ * @return FREQ_VALUE of the Audio clock.
+ */
+NRF_STATIC_INLINE
+uint16_t nrf_clock_hfclkaudio_config_get(NRF_CLOCK_Type const * p_reg);
+#endif
+
+#if NRF_CLOCK_HAS_CALIBRATION_TIMER
/**
* @brief Function for changing the calibration timer interval.
*
@@ -370,6 +561,102 @@ nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(NRF_CLOCK_Type
NRF_STATIC_INLINE void nrf_clock_cal_timer_timeout_set(NRF_CLOCK_Type * p_reg, uint32_t interval);
#endif
+#if NRF_CLOCK_HAS_HFCLK_DIV
+/**
+ * @brief Function for changing the HFCLK frequency divider.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] divider New HFCLK divider.
+ */
+NRF_STATIC_INLINE void nrf_clock_hfclk_div_set(NRF_CLOCK_Type * p_reg,
+ nrf_clock_hfclk_div_t divider);
+
+/**
+ * @brief Function for retrieving the HFCLK frequency divider.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return HFCLK frequency divider.
+ */
+NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk_div_get(NRF_CLOCK_Type const * p_reg);
+#endif
+
+#if NRF_CLOCK_HAS_HFCLK192M
+/**
+ * @brief Function for changing the HFCLK192M frequency divider.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] divider New HFCLK192M divider.
+ */
+NRF_STATIC_INLINE void nrf_clock_hfclk192m_div_set(NRF_CLOCK_Type * p_reg,
+ nrf_clock_hfclk_div_t divider);
+
+/**
+ * @brief Function for retrieving the HFCLK192M frequency divider.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return HFCLK192M frequency divider.
+ */
+NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk192m_div_get(NRF_CLOCK_Type const * p_reg);
+
+/**
+ * @brief Function for changing the HFCLK192M source.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] source New HFCLK192M source.
+ */
+NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg,
+ nrf_clock_hfclk_t source);
+
+/**
+ * @brief Function for retrieving the selected source of the HFCLK192M.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY The internal RC oscillator is the selected
+ * source of the HFCLK192M.
+ * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY An external crystal oscillator is the selected
+ * source of the HFCLK192M.
+ */
+NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hfclk192m_src_get(NRF_CLOCK_Type const * p_reg);
+#endif // NRF_CLOCK_HAS_HFCLK192M
+
+#if NRF_CLOCK_HAS_ALWAYSRUN
+/**
+ * @brief Function for setting the clock domain to always run.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] domain Clock domain.
+ * @param[in] alwaysrun Ensure the clock is always running.
+ */
+NRF_STATIC_INLINE void nrf_clock_alwaysrun_set(NRF_CLOCK_Type const * p_reg,
+ nrf_clock_domain_t domain,
+ bool alwaysrun);
+/**
+ * @brief Function for checking if the clock domain is configured to always run.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] domain Clock domain.
+ *
+ * @retval true The clock domain is configured to always run.
+ * @retval false The clock domain is not configured to always run.
+ */
+NRF_STATIC_INLINE bool nrf_clock_alwaysrun_get(NRF_CLOCK_Type const * p_reg,
+ nrf_clock_domain_t domain);
+/**
+ * @brief Function for checking if the clock domain always run setting is active.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] domain Clock domain.
+ *
+ * @retval true The clock domain always run setting is active.
+ * @retval false The clock domain always run setting is not active.
+ */
+NRF_STATIC_INLINE bool nrf_clock_alwaysrun_active_get(NRF_CLOCK_Type const * p_reg,
+ nrf_clock_domain_t domain);
+#endif
+
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for setting the subscribe configuration for a given
@@ -462,6 +749,89 @@ NRF_STATIC_INLINE bool nrf_clock_event_check(NRF_CLOCK_Type const * p_reg, nrf_c
return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
}
+NRF_STATIC_INLINE bool nrf_clock_start_task_check(NRF_CLOCK_Type const * p_reg,
+ nrf_clock_domain_t domain)
+{
+ switch (domain)
+ {
+ case NRF_CLOCK_DOMAIN_LFCLK:
+ return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
+ >> CLOCK_LFCLKRUN_STATUS_Pos);
+ case NRF_CLOCK_DOMAIN_HFCLK:
+ return ((p_reg->HFCLKRUN & CLOCK_HFCLKRUN_STATUS_Msk)
+ >> CLOCK_HFCLKRUN_STATUS_Pos);
+#if NRF_CLOCK_HAS_HFCLK192M
+ case NRF_CLOCK_DOMAIN_HFCLK192M:
+ return ((p_reg->HFCLK192MRUN & CLOCK_HFCLK192MRUN_STATUS_Msk)
+ >> CLOCK_HFCLK192MRUN_STATUS_Pos);
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
+ return ((p_reg->HFCLKAUDIORUN & CLOCK_HFCLKAUDIORUN_STATUS_Msk)
+ >> CLOCK_HFCLKAUDIORUN_STATUS_Pos);
+#endif
+ default:
+ NRFX_ASSERT(0);
+ return false;
+ }
+}
+
+NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg,
+ nrf_clock_domain_t domain,
+ void * clk_src)
+{
+ switch (domain)
+ {
+ case NRF_CLOCK_DOMAIN_LFCLK:
+ if (clk_src != NULL)
+ {
+ (*(uint32_t *)clk_src) = ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
+ >> CLOCK_LFCLKSTAT_SRC_Pos);
+ }
+ if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
+ >> CLOCK_LFCLKSTAT_STATE_Pos)
+ {
+ return true;
+ }
+ break;
+ case NRF_CLOCK_DOMAIN_HFCLK:
+ if (clk_src != NULL)
+ {
+ (*(uint32_t *)clk_src) = ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
+ >> CLOCK_HFCLKSTAT_SRC_Pos);
+ }
+ if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
+ >> CLOCK_HFCLKSTAT_STATE_Pos)
+ {
+ return true;
+ }
+ break;
+#if NRF_CLOCK_HAS_HFCLK192M
+ case NRF_CLOCK_DOMAIN_HFCLK192M:
+ if (clk_src != NULL)
+ {
+ (*(uint32_t *)clk_src) = ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_SRC_Msk)
+ >> CLOCK_HFCLK192MSTAT_SRC_Pos);
+ }
+ if ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_STATE_Msk)
+ >> CLOCK_HFCLK192MSTAT_STATE_Pos)
+ {
+ return true;
+ }
+ break;
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
+ return (p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_STATE_Msk) ==
+ CLOCK_HFCLKAUDIOSTAT_STATE_Msk;
+#endif
+ default:
+ NRFX_ASSERT(0);
+ return false;
+ }
+ return false;
+}
+
NRF_STATIC_INLINE void nrf_clock_lf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_lfclk_t source)
{
p_reg->LFCLKSRC = (uint32_t)(source);
@@ -474,8 +844,9 @@ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(NRF_CLOCK_Type const *
NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(NRF_CLOCK_Type const * p_reg)
{
- return (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
- >> CLOCK_LFCLKSTAT_SRC_Pos);
+ nrf_clock_lfclk_t clk_src;
+ (void)nrf_clock_is_running(p_reg, NRF_CLOCK_DOMAIN_LFCLK, &clk_src);
+ return clk_src;
}
NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
@@ -486,43 +857,203 @@ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type cons
NRF_STATIC_INLINE bool nrf_clock_lf_is_running(NRF_CLOCK_Type const * p_reg)
{
- return ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk) >> CLOCK_LFCLKSTAT_STATE_Pos);
+ return nrf_clock_is_running(p_reg, NRF_CLOCK_DOMAIN_LFCLK, NULL);
}
NRF_STATIC_INLINE
nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(NRF_CLOCK_Type const * p_reg)
{
- return (nrf_clock_start_task_status_t)((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
- >> CLOCK_LFCLKRUN_STATUS_Pos);
+ return (nrf_clock_start_task_status_t)nrf_clock_start_task_check(p_reg,
+ NRF_CLOCK_DOMAIN_LFCLK);
+}
+
+#if NRF_CLOCK_HAS_HFCLKSRC
+NRF_STATIC_INLINE void nrf_clock_hf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
+{
+ p_reg->HFCLKSRC = (uint32_t)(source);
}
+#endif
NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(NRF_CLOCK_Type const * p_reg)
{
+#if NRF_CLOCK_HAS_HFCLKSRC
+ return (nrf_clock_hfclk_t)(p_reg->HFCLKSRC);
+#else
return (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
>> CLOCK_HFCLKSTAT_SRC_Pos);
+#endif
}
NRF_STATIC_INLINE bool nrf_clock_hf_is_running(NRF_CLOCK_Type const * p_reg,
nrf_clock_hfclk_t clk_src)
{
- return (p_reg->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) ==
- (CLOCK_HFCLKSTAT_STATE_Msk | (clk_src << CLOCK_HFCLKSTAT_SRC_Pos));
+ nrf_clock_hfclk_t active_clk_src;
+ bool ret = nrf_clock_is_running(p_reg, NRF_CLOCK_DOMAIN_HFCLK, &active_clk_src);
+ return (ret && (active_clk_src == clk_src));
}
NRF_STATIC_INLINE
nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(NRF_CLOCK_Type const * p_reg)
{
- return (nrf_clock_start_task_status_t)((p_reg->HFCLKRUN & CLOCK_HFCLKRUN_STATUS_Msk)
- >> CLOCK_HFCLKRUN_STATUS_Pos);
+ return (nrf_clock_start_task_status_t)nrf_clock_start_task_check(p_reg,
+ NRF_CLOCK_DOMAIN_HFCLK);
+}
+
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+NRF_STATIC_INLINE
+void nrf_clock_hfclkaudio_config_set(NRF_CLOCK_Type * p_reg, uint16_t freq_value)
+{
+ p_reg->HFCLKAUDIO.FREQUENCY = freq_value;
+}
+
+NRF_STATIC_INLINE
+uint16_t nrf_clock_hfclkaudio_config_get(NRF_CLOCK_Type const * p_reg)
+{
+ return (uint16_t)(p_reg->HFCLKAUDIO.FREQUENCY);
+}
+#endif
+
+#if NRF_CLOCK_HAS_HFCLK_DIV
+NRF_STATIC_INLINE
+void nrf_clock_hfclk_div_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_div_t divider)
+{
+ p_reg->HFCLKCTRL = (((uint8_t)(divider) << CLOCK_HFCLKCTRL_HCLK_Pos) &
+ CLOCK_HFCLKCTRL_HCLK_Msk);
+}
+
+NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk_div_get(NRF_CLOCK_Type const * p_reg)
+{
+ return (nrf_clock_hfclk_div_t)((p_reg->HFCLKCTRL & CLOCK_HFCLKCTRL_HCLK_Msk)
+ >> CLOCK_HFCLKCTRL_HCLK_Pos);
+}
+#endif
+
+#if NRF_CLOCK_HAS_HFCLK192M
+NRF_STATIC_INLINE
+void nrf_clock_hfclk192m_div_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_div_t divider)
+{
+ p_reg->HFCLK192MCTRL = (((uint8_t)(divider) << CLOCK_HFCLK192MCTRL_HCLK192M_Pos) &
+ CLOCK_HFCLK192MCTRL_HCLK192M_Msk);
}
-#if (NRF_CLOCK_HAS_CALIBRATION)
+NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk192m_div_get(NRF_CLOCK_Type const * p_reg)
+{
+ return (nrf_clock_hfclk_div_t)((p_reg->HFCLK192MCTRL & CLOCK_HFCLK192MCTRL_HCLK192M_Msk)
+ >> CLOCK_HFCLK192MCTRL_HCLK192M_Pos);
+}
+
+NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
+{
+ p_reg->HFCLK192MSRC = (uint32_t)(source);
+}
+
+NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hfclk192m_src_get(NRF_CLOCK_Type const * p_reg)
+{
+ return (nrf_clock_hfclk_t)(p_reg->HFCLK192MSRC);
+}
+#endif
+
+#if NRF_CLOCK_HAS_CALIBRATION_TIMER
NRF_STATIC_INLINE void nrf_clock_cal_timer_timeout_set(NRF_CLOCK_Type * p_reg, uint32_t interval)
{
p_reg->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk);
}
#endif
+#if NRF_CLOCK_HAS_ALWAYSRUN
+NRF_STATIC_INLINE void nrf_clock_alwaysrun_set(NRF_CLOCK_Type const * p_reg,
+ nrf_clock_domain_t domain,
+ bool alwaysrun)
+{
+ /* ALWAYSRUN registers should be R/W, but are marked as read-only.
+ * Redefine them as R/W as a workaround. */
+ switch (domain)
+ {
+ case NRF_CLOCK_DOMAIN_LFCLK:
+ *(volatile uint32_t *)(&p_reg->LFCLKALWAYSRUN) =
+ ((alwaysrun << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos)
+ & CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk);
+ break;
+ case NRF_CLOCK_DOMAIN_HFCLK:
+ *(volatile uint32_t *)(&p_reg->HFCLKALWAYSRUN) =
+ ((alwaysrun << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos)
+ & CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk);
+ break;
+#if NRF_CLOCK_HAS_HFCLK192M
+ case NRF_CLOCK_DOMAIN_HFCLK192M:
+ *(volatile uint32_t *)(&p_reg->HFCLK192MALWAYSRUN) =
+ ((alwaysrun << CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos)
+ & CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk);
+ break;
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
+ *(volatile uint32_t *)(&p_reg->HFCLKAUDIOALWAYSRUN) =
+ ((alwaysrun << CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos)
+ & CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk);
+ break;
+#endif
+ default:
+ NRFX_ASSERT(0);
+ break;
+ }
+}
+
+NRF_STATIC_INLINE bool nrf_clock_alwaysrun_get(NRF_CLOCK_Type const * p_reg,
+ nrf_clock_domain_t domain)
+{
+ switch (domain)
+ {
+ case NRF_CLOCK_DOMAIN_LFCLK:
+ return ((p_reg->LFCLKALWAYSRUN & CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk)
+ >> CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos);
+ case NRF_CLOCK_DOMAIN_HFCLK:
+ return ((p_reg->HFCLKALWAYSRUN & CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk)
+ >> CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos);
+#if NRF_CLOCK_HAS_HFCLK192M
+ case NRF_CLOCK_DOMAIN_HFCLK192M:
+ return ((p_reg->HFCLK192MALWAYSRUN & CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk)
+ >> CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos);
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
+ return ((p_reg->HFCLKAUDIOALWAYSRUN & CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk)
+ >> CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos);
+#endif
+ default:
+ NRFX_ASSERT(0);
+ return false;
+ }
+}
+
+NRF_STATIC_INLINE bool nrf_clock_alwaysrun_active_get(NRF_CLOCK_Type const * p_reg,
+ nrf_clock_domain_t domain)
+{
+ switch (domain)
+ {
+ case NRF_CLOCK_DOMAIN_LFCLK:
+ return ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk)
+ >> CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos);
+ case NRF_CLOCK_DOMAIN_HFCLK:
+ return ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk)
+ >> CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos);
+#if NRF_CLOCK_HAS_HFCLK192M
+ case NRF_CLOCK_DOMAIN_HFCLK192M:
+ return ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk)
+ >> CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos);
+#endif
+#if NRF_CLOCK_HAS_HFCLKAUDIO
+ case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
+ return ((p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Msk)
+ >> CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos);
+#endif
+ default:
+ NRFX_ASSERT(0);
+ return false;
+ }
+}
+#endif // NRF_CLOCK_HAS_ALWAYSRUN
+
#if defined(DPPI_PRESENT)
NRF_STATIC_INLINE void nrf_clock_subscribe_set(NRF_CLOCK_Type * p_reg,
nrf_clock_task_t task,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h
index 804abe3..3a00c48 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_dcnf.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_dcnf.h
new file mode 100644
index 0000000..79dc7c5
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_dcnf.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRF_DCNF_H__
+#define NRF_DCNF_H__
+
+#include <nrfx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_dcnf_hal DCNF HAL
+ * @{
+ * @ingroup nrf_dcnf
+ * @brief Hardware access layer for managing the Domain Configuration (DCNF) module.
+ */
+
+/**
+ * @brief Function for getting the value of the CPU ID.
+ *
+ * CPU ID can be used to identify the specific CPU in the multi-core environment.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return CPU ID.
+ */
+NRF_STATIC_INLINE uint32_t nrf_dcnf_cpuid_get(NRF_DCNF_Type const * p_reg);
+
+#if defined(DCNF_EXTPERI_PROTECT_SLAVE0_Msk)
+/**
+ * @brief Function for configuring the control access to local peripheral memory regions.
+ * Intended for external master connected to specified AMLI master port.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] port_idx Index of the master port to configure.
+ * @param[in] mask Mask of the AHB slaves to be protected from being accessed
+ * by external AHB masters.
+ */
+NRF_STATIC_INLINE void nrf_dcnf_peripheral_access_set(NRF_DCNF_Type * p_reg,
+ uint8_t port_idx,
+ uint32_t mask);
+
+/**
+ * @brief Function for getting the configuration of control access to local peripheral
+ * memory regions. Intended for external master connected to specified AMLI master port.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] port_idx Index of the master port to configure.
+ *
+ * @return Mask of the AHB slaves that are currently protected.
+ */
+NRF_STATIC_INLINE uint32_t nrf_dcnf_peripheral_access_get(NRF_DCNF_Type const * p_reg,
+ uint8_t port_idx);
+#endif // defined(DCNF_EXTPERI_PROTECT_SLAVE0_Msk)
+
+#if defined(DCNF_EXTRAM_PROTECT_SLAVE0_Msk)
+/**
+ * @brief Function for configuring the control access to local RAM memory regions.
+ * Intended for external master connected to specified AMLI master port.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] port_idx Index of the master port to configure.
+ * @param[in] mask Mask of the AHB slaves to be protected from being accessed
+ * by external AHB masters.
+ */
+NRF_STATIC_INLINE void nrf_dcnf_ram_access_set(NRF_DCNF_Type * p_reg,
+ uint8_t port_idx,
+ uint32_t mask);
+
+/**
+ * @brief Function for getting the configuration of control access to local RAM
+ * memory regions. Intended for external master connected to specified AMLI master port.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] port_idx Index of the master port to configure.
+ *
+ * @return Mask of the AHB slaves that are currently protected.
+ */
+NRF_STATIC_INLINE uint32_t nrf_dcnf_ram_access_get(NRF_DCNF_Type const * p_reg,
+ uint8_t port_idx);
+#endif // defined(DCNF_EXTRAM_PROTECT_SLAVE0_Msk)
+
+#if defined(DCNF_EXTCODE_PROTECT_SLAVE0_Msk)
+/**
+ * @brief Function for configuring the control access to local code memory regions.
+ * Intended for external master connected to specified AMLI master port.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] port_idx Index of the master port to configure.
+ * @param[in] mask Mask of the AHB slaves to be protected from being accessed
+ * by external AHB masters.
+ */
+NRF_STATIC_INLINE void nrf_dcnf_code_access_set(NRF_DCNF_Type * p_reg,
+ uint8_t port_idx,
+ uint32_t mask);
+
+/**
+ * @brief Function for getting the configuration of control access to local code
+ * memory regions. Intended for external master connected to specified AMLI master port.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] port_idx Index of the master port to configure.
+ *
+ * @return Mask of the AHB slaves that are currently protected.
+ */
+NRF_STATIC_INLINE uint32_t nrf_dcnf_code_access_get(NRF_DCNF_Type const * p_reg,
+ uint8_t port_idx);
+#endif // defined(DCNF_EXTCODE_PROTECT_SLAVE0_Msk)
+
+#ifndef NRF_DECLARE_ONLY
+
+NRF_STATIC_INLINE uint32_t nrf_dcnf_cpuid_get(NRF_DCNF_Type const * p_reg)
+{
+ return p_reg->CPUID;
+}
+
+#if defined(DCNF_EXTPERI_PROTECT_SLAVE0_Msk)
+NRF_STATIC_INLINE void nrf_dcnf_peripheral_access_set(NRF_DCNF_Type * p_reg,
+ uint8_t port_idx,
+ uint32_t mask)
+{
+ p_reg->EXTPERI[port_idx].PROTECT = mask;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_dcnf_peripheral_access_get(NRF_DCNF_Type const * p_reg,
+ uint8_t port_idx)
+{
+ return p_reg->EXTPERI[port_idx].PROTECT;
+}
+#endif
+
+#if defined(DCNF_EXTRAM_PROTECT_SLAVE0_Msk)
+NRF_STATIC_INLINE void nrf_dcnf_ram_access_set(NRF_DCNF_Type * p_reg,
+ uint8_t port_idx,
+ uint32_t mask)
+{
+ p_reg->EXTRAM[port_idx].PROTECT = mask;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_dcnf_ram_access_get(NRF_DCNF_Type const * p_reg,
+ uint8_t port_idx)
+{
+ return p_reg->EXTRAM[port_idx].PROTECT;
+}
+#endif
+
+#if defined(DCNF_EXTCODE_PROTECT_SLAVE0_Msk)
+NRF_STATIC_INLINE void nrf_dcnf_code_access_set(NRF_DCNF_Type * p_reg,
+ uint8_t port_idx,
+ uint32_t mask)
+{
+ p_reg->EXTCODE[port_idx].PROTECT = mask;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_dcnf_code_access_get(NRF_DCNF_Type const * p_reg,
+ uint8_t port_idx)
+{
+ return p_reg->EXTCODE[port_idx].PROTECT;
+}
+#endif
+
+#endif // NRF_DECLARE_ONLY
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DCNF_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_dppi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_dppi.h
index 486224b..9ff7e08 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_dppi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_dppi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h
index 9cef4ad..e734e14 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2012 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h
index 3a7bf4e..8c5cdc2 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ficr.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ficr.h
index 5967b06..193c83a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ficr.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ficr.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_fpu.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_fpu.h
index 35ff12c..14bcab8 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_fpu.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_fpu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h
index d2b9366..6fcf5e6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -59,6 +59,11 @@ extern "C" {
* @brief Hardware access layer for managing the GPIO peripheral.
*/
+#if defined(GPIO_LATCH_PIN0_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether the functionality of latching GPIO state change is present. */
+#define NRF_GPIO_LATCH_PRESENT
+#endif
+
/** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */
#define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F))
@@ -91,14 +96,35 @@ typedef enum
/** @brief Enumerator used for selecting output drive mode. */
typedef enum
{
- NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'.
- NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'.
- NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'.
- NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'.
- NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'.
- NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'.
- NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'.
- NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'.
+ NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< Standard '0', standard '1'.
+ NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< High drive '0', standard '1'.
+ NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< Standard '0', high drive '1'.
+ NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< High drive '0', high drive '1'.
+ NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< Disconnect '0' standard '1'.
+ NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< Disconnect '0', high drive '1'.
+ NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< Standard '0', disconnect '1'.
+ NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< High drive '0', disconnect '1'.
+#if defined(GPIO_PIN_CNF_DRIVE_E0S1) || defined(__NRFX_DOXYGEN__)
+ NRF_GPIO_PIN_E0S1 = GPIO_PIN_CNF_DRIVE_E0S1, ///< Extra high drive '0', standard '1'.
+#endif
+#if defined(GPIO_PIN_CNF_DRIVE_S0E1) || defined(__NRFX_DOXYGEN__)
+ NRF_GPIO_PIN_S0E1 = GPIO_PIN_CNF_DRIVE_S0E1, ///< Standard '0', extra high drive '1'.
+#endif
+#if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(__NRFX_DOXYGEN__)
+ NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE_E0E1, ///< Extra high drive '0', extra high drive '1'.
+#endif
+#if defined(GPIO_PIN_CNF_DRIVE_E0H1) || defined(__NRFX_DOXYGEN__)
+ NRF_GPIO_PIN_E0H1 = GPIO_PIN_CNF_DRIVE_E0H1, ///< Extra high drive '0', high drive '1'.
+#endif
+#if defined(GPIO_PIN_CNF_DRIVE_H0E1) || defined(__NRFX_DOXYGEN__)
+ NRF_GPIO_PIN_H0E1 = GPIO_PIN_CNF_DRIVE_H0E1, ///< High drive '0', extra high drive '1'.
+#endif
+#if defined(GPIO_PIN_CNF_DRIVE_D0E1) || defined(__NRFX_DOXYGEN__)
+ NRF_GPIO_PIN_D0E1 = GPIO_PIN_CNF_DRIVE_D0E1, ///< Disconnect '0', extra high drive '1'.
+#endif
+#if defined(GPIO_PIN_CNF_DRIVE_E0D1) || defined(__NRFX_DOXYGEN__)
+ NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE_E0D1, ///< Extra high drive '0', disconnect '1'.
+#endif
} nrf_gpio_pin_drive_t;
/** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */
@@ -421,7 +447,7 @@ NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
uint32_t length,
uint32_t * p_masks);
-#if defined(GPIO_DETECTMODE_DETECTMODE_LDETECT) || defined(__NRF_DOXYGEN__)
+#if defined(NRF_GPIO_LATCH_PRESENT)
/**
* @brief Function for reading latch state of multiple consecutive ports.
*
@@ -434,6 +460,17 @@ NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
uint32_t * p_masks);
/**
+ * @brief Function for reading and immediate clearing latch state of multiple consecutive ports.
+ *
+ * @param start_port Index of the first port to read and clear.
+ * @param length Number of ports to read and clear.
+ * @param p_masks Pointer to output array where latch states will be stored.
+ */
+NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
+ uint32_t length,
+ uint32_t * p_masks);
+
+/**
* @brief Function for reading latch state of single pin.
*
* @param pin_number Pin number.
@@ -448,7 +485,7 @@ NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
* @param pin_number Pin number.
*/
NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
-#endif
+#endif // defined(NRF_GPIO_LATCH_PRESENT)
#if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__)
/**
@@ -789,7 +826,7 @@ NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
}
-#ifdef GPIO_DETECTMODE_DETECTMODE_LDETECT
+#if defined(NRF_GPIO_LATCH_PRESENT)
NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
uint32_t length,
uint32_t * p_masks)
@@ -804,6 +841,23 @@ NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
}
}
+NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
+ uint32_t length,
+ uint32_t * p_masks)
+{
+ NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
+ uint32_t i;
+
+ for (i = start_port; i < (start_port + length); i++)
+ {
+ *p_masks = gpio_regs[i]->LATCH;
+
+ // The LATCH register is cleared by writing a '1' to the bit that shall be cleared.
+ gpio_regs[i]->LATCH = *p_masks;
+
+ p_masks++;
+ }
+}
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number)
{
@@ -819,7 +873,7 @@ NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
reg->LATCH = (1 << pin_number);
}
-#endif
+#endif // defined(NRF_GPIO_LATCH_PRESENT)
#if defined(GPIO_PIN_CNF_MCUSEL_Msk)
NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h
index ab09e71..8f3321d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h
index 33b8123..da71bc6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,13 @@ extern "C" {
* @brief Hardware access layer for managing the Inter-IC Sound (I2S) peripheral.
*/
+#if defined(I2S_CONFIG_CLKCONFIG_CLKSRC_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether clock source configuration is available. */
+#define NRF_I2S_HAS_CLKCONFIG 1
+#else
+#define NRF_I2S_HAS_CLKCONFIG 0
+#endif
+
/**
* @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set
* function call to specify that the given I2S signal (SDOUT, SDIN, or MCK)
@@ -63,17 +70,23 @@ typedef enum
/** @brief I2S events. */
typedef enum
{
- NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double buffers.
- NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double buffers.
- NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED) ///< I2S transfer stopped.
+ NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double buffers.
+ NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double buffers.
+ NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED), ///< I2S transfer stopped.
+#if defined(I2S_INTENSET_FRAMESTART_Msk) || defined(__NRFX_DOXYGEN_)
+ NRF_I2S_EVENT_FRAMESTART = offsetof(NRF_I2S_Type, EVENTS_FRAMESTART) ///< Frame start event, generated on the active edge of LRCK.
+#endif
} nrf_i2s_event_t;
/** @brief I2S interrupts. */
typedef enum
{
- NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event.
- NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event.
- NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk ///< Interrupt on STOPPED event.
+ NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event.
+ NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event.
+ NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
+#if defined(I2S_INTENSET_FRAMESTART_Msk) || defined(__NRFX_DOXYGEN_)
+ NRF_I2S_INT_FRAMESTART_MASK = I2S_INTENCLR_FRAMESTART_Msk ///< Interrupt on FRAMESTART event.
+#endif
} nrf_i2s_int_mask_t;
/** @brief I2S modes of operation. */
@@ -136,9 +149,24 @@ typedef enum
/** @brief I2S sample widths. */
typedef enum
{
- NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit.
- NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit.
- NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit ///< 24 bit.
+ NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit.
+ NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit.
+ NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit, ///< 24 bit.
+#if defined(I2S_CONFIG_SWIDTH_SWIDTH_32Bit) || defined(__NRFX_DOXYGEN__)
+ NRF_I2S_SWIDTH_32BIT = I2S_CONFIG_SWIDTH_SWIDTH_32Bit, ///< 32 bit.
+#endif
+#if defined(I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16) || defined(__NRFX_DOXYGEN__)
+ NRF_I2S_SWIDTH_8BIT_IN16BIT = I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16, ///< 8 bit sample in a 16-bit half-frame.
+#endif
+#if defined(I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32) || defined(__NRFX_DOXYGEN__)
+ NRF_I2S_SWIDTH_8BIT_IN32BIT = I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32, ///< 8 bit sample in a 32-bit half-frame.
+#endif
+#if defined(I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32) || defined(__NRFX_DOXYGEN__)
+ NRF_I2S_SWIDTH_16BIT_IN32BIT = I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32, ///< 16 bit sample in a 32-bit half-frame.
+#endif
+#if defined(I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32) || defined(__NRFX_DOXYGEN__)
+ NRF_I2S_SWIDTH_24BIT_IN32BIT = I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32, ///< 24 bit sample in a 32-bit half-frame.
+#endif
} nrf_i2s_swidth_t;
/** @brief I2S alignments of sample within a frame. */
@@ -163,6 +191,14 @@ typedef enum
NRF_I2S_CHANNELS_RIGHT = I2S_CONFIG_CHANNELS_CHANNELS_Right ///< Right only.
} nrf_i2s_channels_t;
+#if NRF_I2S_HAS_CLKCONFIG
+/** @brief I2S Clock source selection. */
+typedef enum
+{
+ NRF_I2S_CLKSRC_PCLK32M = I2S_CONFIG_CLKCONFIG_CLKSRC_PCLK32M, ///< 32MHz peripheral clock.
+ NRF_I2S_CLKSRC_ACLK = I2S_CONFIG_CLKCONFIG_CLKSRC_ACLK ///< Audio PLL clock.
+} nrf_i2s_clksrc_t;
+#endif
/**
* @brief Function for activating the specified I2S task.
@@ -408,6 +444,19 @@ NRF_STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_reg,
*/
NRF_STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_reg);
+#if NRF_I2S_HAS_CLKCONFIG
+/**
+ * @brief Function for configuring I2S Clock.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] clksrc I2S Clock source selection.
+ * @param[in] enable_bypass Bypass clock generator. MCK will be equal to source input.
+ * If bypass is enabled the MCKFREQ setting has no effect.
+ */
+NRF_STATIC_INLINE void nrf_i2s_clk_configure(NRF_I2S_Type * p_reg,
+ nrf_i2s_clksrc_t clksrc,
+ bool enable_bypass);
+#endif
#ifndef NRF_DECLARE_ONLY
@@ -598,6 +647,16 @@ NRF_STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_reg)
return (uint32_t *)(p_reg->TXD.PTR);
}
+#if NRF_I2S_HAS_CLKCONFIG
+NRF_STATIC_INLINE void nrf_i2s_clk_configure(NRF_I2S_Type * p_reg,
+ nrf_i2s_clksrc_t clksrc,
+ bool enable_bypass)
+{
+ p_reg->CONFIG.CLKCONFIG = ((uint32_t) clksrc << I2S_CONFIG_CLKCONFIG_CLKSRC_Pos) |
+ ((uint32_t) enable_bypass << I2S_CONFIG_CLKCONFIG_BYPASS_Pos);
+}
+#endif
+
#endif // NRF_DECLARE_ONLY
/** @} */
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ipc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ipc.h
index 44f6b83..dee5b10 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ipc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ipc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_kmu.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_kmu.h
index 6d51470..a026f4c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_kmu.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_kmu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h
index 30fe7a4..777f6ea 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mpu.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mpu.h
index 7eb8186..b4bbce2 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mpu.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mpu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -113,8 +113,7 @@ NRF_STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg
* NVM protection during debug is disabled by default.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] enable True if NVM protection during debug is to be enabled.
- * False if otherwise.
+ * @param[in] enable True if NVM protection during debug is to be enabled, false otherwise.
*/
NRF_STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,
bool enable);
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mutex.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mutex.h
index a2b9287..02e1a05 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mutex.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mutex.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mwu.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mwu.h
index 64ebf8b..4fbf445 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mwu.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mwu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h
index 01dcfd9..f03d01d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.h
index 9a71ba3..3f0ddfd 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2012 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -349,7 +349,23 @@ NRF_STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg,
NRF_STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg,
nrf_nvmc_icache_config_t config)
{
- p_reg->ICACHECNF = (uint32_t)config;
+#if defined(NRF5340_XXAA_NETWORK) || defined(NRF9160_XXAA)
+ // Apply workaround for the anomalies:
+ // - 6 for the nRF5340.
+ // - 21 for the nRF9160.
+ if (config == NRF_NVMC_ICACHE_DISABLE)
+ {
+ NRFX_CRITICAL_SECTION_ENTER();
+ __ISB();
+ p_reg->ICACHECNF = (uint32_t)NRF_NVMC_ICACHE_DISABLE;
+ __ISB();
+ NRFX_CRITICAL_SECTION_EXIT();
+ }
+ else
+#endif
+ {
+ p_reg->ICACHECNF = (uint32_t)config;
+ }
}
NRF_STATIC_INLINE bool nrf_nvmc_icache_enable_check(NRF_NVMC_Type const * p_reg)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_oscillators.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_oscillators.h
new file mode 100644
index 0000000..d17ac60
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_oscillators.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRF_OSCILLATORS_H__
+#define NRF_OSCILLATORS_H__
+
+#include <nrfx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_oscillators_hal OSCILLATORS HAL
+ * @{
+ * @ingroup nrf_clock
+ * @brief Hardware access layer for managing the OSCILLATORS peripheral.
+ */
+
+/** @brief Capacitors configuration for LFXO. */
+typedef enum
+{
+ NRF_OSCILLATORS_LFXO_CAP_EXTERNAL = OSCILLATORS_XOSC32KI_INTCAP_INTCAP_External, ///< Use external capacitors.
+ NRF_OSCILLATORS_LFXO_CAP_6PF = OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C6PF, ///< Use 6 pF internal capacitors.
+ NRF_OSCILLATORS_LFXO_CAP_7PF = OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C7PF, ///< Use 7 pF internal capacitors.
+ NRF_OSCILLATORS_LFXO_CAP_11PF = OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C11PF, ///< Use 11 pF internal capacitors.
+} nrf_oscillators_lfxo_cap_t;
+
+/**
+ * @brief Function for enabling or disabling the bypass of LFXO with external clock source.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] enable True if bypass is to be enabled (use with rail-to-rail external source).
+ * False if bypass is to be disabled (use with xtal or low-swing external source).
+ */
+NRF_STATIC_INLINE void nrf_oscillators_lfxo_bypass_set(NRF_OSCILLATORS_Type * p_reg, bool enable);
+
+/**
+ * @brief Function for configuring the internal capacitors of LFXO.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] cap Capacitors configuration.
+ */
+NRF_STATIC_INLINE void nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS_Type * p_reg,
+ nrf_oscillators_lfxo_cap_t cap);
+
+/**
+ * @brief Function for configuring the internal capacitors of HXFO.
+ *
+ * The capacitance of internal capacitors ranges from 7 pF to 20 pF in 0.5 pF steps.
+ * To calculate the correct @p cap_value, use the following equation:
+ * CAPVALUE = (1+FICR->XOSC32MTRIM.SLOPE/16) * (CAPACITANCE*2-14) + FICR->XOSC32MTRIM.OFFSET
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] enable True if internal capacitors are to be enabled, false otherwise.
+ * @param[in] cap_value Value representing capacitance, calculated using provided equation.
+ * Ignored when internal capacitors are disabled.
+ */
+NRF_STATIC_INLINE void nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS_Type * p_reg,
+ bool enable,
+ uint32_t cap_value);
+
+#ifndef NRF_DECLARE_ONLY
+NRF_STATIC_INLINE void nrf_oscillators_lfxo_bypass_set(NRF_OSCILLATORS_Type * p_reg, bool enable)
+{
+ p_reg->XOSC32KI.BYPASS = (enable ? OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Enabled :
+ OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Disabled);
+}
+
+NRF_STATIC_INLINE void nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS_Type * p_reg,
+ nrf_oscillators_lfxo_cap_t cap)
+{
+ p_reg->XOSC32KI.INTCAP = (uint32_t)cap;
+}
+
+NRF_STATIC_INLINE void nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS_Type * p_reg,
+ bool enable,
+ uint32_t cap_value)
+{
+ p_reg->XOSC32MCAPS =
+ (enable ? ((OSCILLATORS_XOSC32MCAPS_ENABLE_Enabled << OSCILLATORS_XOSC32MCAPS_ENABLE_Pos) |
+ (cap_value << OSCILLATORS_XOSC32MCAPS_CAPVALUE_Pos))
+ : (OSCILLATORS_XOSC32MCAPS_ENABLE_Disabled << OSCILLATORS_XOSC32MCAPS_ENABLE_Pos));
+}
+#endif // NRF_DECLARE_ONLY
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_OSCILLATORS_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h
index 9dea754..b8545ff 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,6 +37,10 @@
extern "C" {
#endif
+#ifndef NRF_PDM0
+#define NRF_PDM0 NRF_PDM
+#endif
+
/**
* @defgroup nrf_pdm_hal PDM HAL
* @{
@@ -44,6 +48,20 @@ extern "C" {
* @brief Hardware access layer for managing the Pulse Density Modulation (PDM) peripheral.
*/
+#if defined(PDM_MCLKCONFIG_SRC_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether master clock source configuration is available. */
+#define NRF_PDM_HAS_MCLKCONFIG 1
+#else
+#define NRF_PDM_HAS_MCLKCONFIG 0
+#endif
+
+#if defined(PDM_RATIO_RATIO_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether ratio configuration is available. */
+#define NRF_PDM_HAS_RATIO_CONFIG 1
+#else
+#define NRF_PDM_HAS_RATIO_CONFIG 0
+#endif
+
/** @brief Minimum value of PDM gain. */
#define NRF_PDM_GAIN_MINIMUM 0x00
/** @brief Default value of PDM gain. */
@@ -83,9 +101,28 @@ typedef enum
{
NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K, ///< PDM_CLK = 1.000 MHz.
NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default, ///< PDM_CLK = 1.032 MHz.
- NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K ///< PDM_CLK = 1.067 MHz.
+ NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K, ///< PDM_CLK = 1.067 MHz.
+#if defined(PDM_PDMCLKCTRL_FREQ_1231K) || defined(__NRFX_DOXYGEN__)
+ NRF_PDM_FREQ_1231K = PDM_PDMCLKCTRL_FREQ_1231K, ///< PDM_CLK = 1.231 MHz.
+#endif
+#if defined(PDM_PDMCLKCTRL_FREQ_1280K) || defined(__NRFX_DOXYGEN__)
+ NRF_PDM_FREQ_1280K = PDM_PDMCLKCTRL_FREQ_1280K, ///< PDM_CLK = 1.280 MHz.
+#endif
+#if defined(PDM_PDMCLKCTRL_FREQ_1333K) || defined(__NRFX_DOXYGEN__)
+ NRF_PDM_FREQ_1333K = PDM_PDMCLKCTRL_FREQ_1333K ///< PDM_CLK = 1.333 MHz.
+#endif
} nrf_pdm_freq_t;
+
+#if NRF_PDM_HAS_RATIO_CONFIG
+/** @brief PDM ratio between PDM_CLK and output sample rate. */
+typedef enum
+{
+ NRF_PDM_RATIO_64X = PDM_RATIO_RATIO_Ratio64, ///< Ratio of 64.
+ NRF_PDM_RATIO_80X = PDM_RATIO_RATIO_Ratio80 ///< Ratio of 80.
+} nrf_pdm_ratio_t;
+#endif
+
/** @brief PDM operation mode. */
typedef enum
{
@@ -100,6 +137,14 @@ typedef enum
NRF_PDM_EDGE_LEFTRISING = PDM_MODE_EDGE_LeftRising ///< Left (or mono) is sampled on rising edge of PDM_CLK.
} nrf_pdm_edge_t;
+#if NRF_PDM_HAS_MCLKCONFIG
+/** @brief PDM master clock source selection. */
+typedef enum
+{
+ NRF_PDM_MCLKSRC_PCLK32M = PDM_MCLKCONFIG_SRC_PCLK32M, ///< 32MHz peripheral clock.
+ NRF_PDM_MCLKSRC_ACLK = PDM_MCLKCONFIG_SRC_ACLK ///< Audio PLL clock.
+} nrf_pdm_mclksrc_t;
+#endif
/**
* @brief Function for triggering a PDM task.
@@ -347,6 +392,26 @@ NRF_STATIC_INLINE void nrf_pdm_buffer_set(NRF_PDM_Type * p_reg, uint32_t * p_buf
*/
NRF_STATIC_INLINE uint32_t * nrf_pdm_buffer_get(NRF_PDM_Type const * p_reg);
+#if NRF_PDM_HAS_RATIO_CONFIG
+/**
+ * @brief Function for setting ratio between PDM_CLK and output sample rate.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] ratio Ratio between PDM_CLK and output sample rate.
+ */
+NRF_STATIC_INLINE void nrf_pdm_ratio_set(NRF_PDM_Type * p_reg, nrf_pdm_ratio_t ratio);
+#endif
+
+#if NRF_PDM_HAS_MCLKCONFIG
+/**
+ * @brief Function for configuring PDM master clock source.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mclksrc Master Clock source selection.
+ */
+NRF_STATIC_INLINE void nrf_pdm_mclksrc_configure(NRF_PDM_Type * p_reg, nrf_pdm_mclksrc_t mclksrc);
+#endif
+
#ifndef NRF_DECLARE_ONLY
NRF_STATIC_INLINE void nrf_pdm_task_trigger(NRF_PDM_Type * p_reg, nrf_pdm_task_t task)
{
@@ -507,6 +572,20 @@ NRF_STATIC_INLINE uint32_t * nrf_pdm_buffer_get(NRF_PDM_Type const * p_reg)
return (uint32_t *)p_reg->SAMPLE.PTR;
}
+#if NRF_PDM_HAS_RATIO_CONFIG
+NRF_STATIC_INLINE void nrf_pdm_ratio_set(NRF_PDM_Type * p_reg, nrf_pdm_ratio_t ratio)
+{
+ p_reg->RATIO = ratio;
+}
+#endif
+
+#if NRF_PDM_HAS_MCLKCONFIG
+NRF_STATIC_INLINE void nrf_pdm_mclksrc_configure(NRF_PDM_Type * p_reg, nrf_pdm_mclksrc_t mclksrc)
+{
+ p_reg->MCLKCONFIG = mclksrc;
+}
+#endif
+
#endif // NRF_DECLARE_ONLY
/** @} */
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h
index f489ff5..830d0b5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -50,21 +50,14 @@ extern "C" {
#define NRF_POWER_HAS_SLEEPEVT 1
#else
#define NRF_POWER_HAS_SLEEPEVT 0
-#endif // defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__)
+#endif
#if defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__)
/** @brief Symbol indicating whether the POWER peripheral controls the USB regulator. */
#define NRF_POWER_HAS_USBREG 1
#else
#define NRF_POWER_HAS_USBREG 0
-#endif // defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__)
-
-#if defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
-/** @brief Symbol indicating whether VDDH is present. */
-#define NRF_POWER_HAS_VDDH 1
-#else
-#define NRF_POWER_HAS_VDDH 0
-#endif // defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
+#endif
#if defined(POWER_DCDCEN0_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
/** @brief Symbol indicating whether DCDCEN for REG0 is present. */
@@ -80,13 +73,27 @@ extern "C" {
#define NRF_POWER_HAS_DCDCEN 0
#endif
+#if defined(POWER_INTENSET_POFWARN_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether power failure event is present. */
+#define NRF_POWER_HAS_POFWARN 1
+#else
+#define NRF_POWER_HAS_POFWARN 0
+#endif
+
#if defined(POWER_POFCON_THRESHOLD_Msk) || defined(__NRFX_DOXYGEN__)
-/** @brief Symbol indicating whether POFCON is present. */
+/** @brief Symbol indicating whether power failure comparator is present. */
#define NRF_POWER_HAS_POFCON 1
#else
#define NRF_POWER_HAS_POFCON 0
#endif
+#if defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether power failure comparator for VDDH is present. */
+#define NRF_POWER_HAS_POFCON_VDDH 1
+#else
+#define NRF_POWER_HAS_POFCON_VDDH 0
+#endif
+
#if defined(POWER_RESETREAS_RESETPIN_Msk) || defined(__NRFX_DOXYGEN__)
/** @brief Auxiliary definition to mark the fact that RESETREAS register is present in POWER */
#define NRF_POWER_HAS_RESETREAS 1
@@ -94,6 +101,13 @@ extern "C" {
#define NRF_POWER_HAS_RESETREAS 0
#endif
+#if defined(POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether MAINREGSTATUS register is present. */
+#define NRF_POWER_HAS_MAINREGSTATUS 1
+#else
+#define NRF_POWER_HAS_MAINREGSTATUS 0
+#endif
+
/** @brief POWER tasks. */
typedef enum
{
@@ -104,7 +118,7 @@ typedef enum
/** @brief POWER events. */
typedef enum
{
-#if NRF_POWER_HAS_POFCON
+#if NRF_POWER_HAS_POFWARN
NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN ), /**< Power failure warning. */
#endif
#if NRF_POWER_HAS_SLEEPEVT
@@ -121,7 +135,7 @@ typedef enum
/** @brief POWER interrupts. */
typedef enum
{
-#if NRF_POWER_HAS_POFCON
+#if NRF_POWER_HAS_POFWARN
NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk , /**< Write '1' to Enable interrupt for POFWARN event. */
#endif
#if NRF_POWER_HAS_SLEEPEVT
@@ -258,7 +272,7 @@ typedef enum
} nrf_power_pof_thr_t;
#endif // NRF_POWER_HAS_POFCON
-#if NRF_POWER_HAS_VDDH
+#if NRF_POWER_HAS_POFCON_VDDH
/** @brief Power failure comparator thresholds for VDDH. */
typedef enum
{
@@ -279,15 +293,16 @@ typedef enum
NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1 V. */
NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2 V. */
} nrf_power_pof_thrvddh_t;
+#endif // NRF_POWER_HAS_POFCON_VDDH
+#if NRF_POWER_HAS_MAINREGSTATUS
/** @brief Main regulator status. */
typedef enum
{
NRF_POWER_MAINREGSTATUS_NORMAL = POWER_MAINREGSTATUS_MAINREGSTATUS_Normal, /**< Normal voltage mode. Voltage supplied on VDD. */
NRF_POWER_MAINREGSTATUS_HIGH = POWER_MAINREGSTATUS_MAINREGSTATUS_High /**< High voltage mode. Voltage supplied on VDDH. */
} nrf_power_mainregstatus_t;
-
-#endif // NRF_POWER_HAS_VDDH
+#endif
#if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
/**
@@ -588,18 +603,12 @@ NRF_STATIC_INLINE void nrf_power_system_off(NRF_POWER_Type * p_reg);
/**
* @brief Function for setting the power failure comparator configuration.
*
- * This function sets the power failure comparator threshold and enables or disables flag.
- *
- * @note If VDDH settings are present in the device, this function will
- * clear its settings (set to the lowest voltage).
- * Use @ref nrf_power_pofcon_vddh_set function to set new value.
- *
- * @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] enabled Sets to true if power failure comparator is to be enabled.
- * @param[in] thr Sets the voltage threshold value.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] enable True if the power failure comparator is to be enabled, false otherwise.
+ * @param[in] thr voltage threshold value.
*/
NRF_STATIC_INLINE void nrf_power_pofcon_set(NRF_POWER_Type * p_reg,
- bool enabled,
+ bool enable,
nrf_power_pof_thr_t thr);
/**
@@ -616,7 +625,7 @@ NRF_STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(NRF_POWER_Type const
bool * p_enabled);
#endif // NRF_POWER_HAS_POFCON
-#if NRF_POWER_HAS_VDDH
+#if NRF_POWER_HAS_POFCON_VDDH
/**
* @brief Function for setting the VDDH power failure comparator threshold.
*
@@ -634,7 +643,7 @@ NRF_STATIC_INLINE void nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,
* @return VDDH threshold currently configured.
*/
NRF_STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg);
-#endif // NRF_POWER_HAS_VDDH
+#endif // NRF_POWER_HAS_POFCON_VDDH
/**
* @brief Function for setting the general purpose retention register.
@@ -705,7 +714,7 @@ NRF_STATIC_INLINE void nrf_power_gpregret_ext_set(NRF_POWER_Type * p_reg,
* will relate to the converter on low voltage side (1.3 V output).
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] enable Set true to enable the DCDC converter or false to disable the DCDC converter.
+ * @param[in] enable True if DCDC converter is to be enabled, false otherwise.
*/
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable);
@@ -774,7 +783,7 @@ NRF_STATIC_INLINE uint32_t nrf_power_rampower_mask_get(NRF_POWER_Type const * p_
* @brief Function for enabling or disabling the DCDC converter on VDDH.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] enable Set true to enable the DCDC converter or false to disable the DCDC converter.
+ * @param[in] enable True if DCDC converter on VDDH is to be enabled, false otherwise.
*/
NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable);
@@ -789,7 +798,7 @@ NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool en
NRF_STATIC_INLINE bool nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg);
#endif // NRF_POWER_HAS_DCDCEN_VDDH
-#if NRF_POWER_HAS_VDDH
+#if NRF_POWER_HAS_MAINREGSTATUS
/**
* @brief Function for getting the main supply status.
*
@@ -799,7 +808,7 @@ NRF_STATIC_INLINE bool nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg);
*/
NRF_STATIC_INLINE
nrf_power_mainregstatus_t nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg);
-#endif // NRF_POWER_HAS_VDDH
+#endif // NRF_POWER_HAS_MAINREGSTATUS
#if NRF_POWER_HAS_USBREG
/**
@@ -978,23 +987,23 @@ NRF_STATIC_INLINE void nrf_power_system_off(NRF_POWER_Type * p_reg)
#if NRF_POWER_HAS_POFCON
NRF_STATIC_INLINE void nrf_power_pofcon_set(NRF_POWER_Type * p_reg,
- bool enabled,
+ bool enable,
nrf_power_pof_thr_t thr)
{
NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLD_Msk >> POWER_POFCON_THRESHOLD_Pos)));
-#if NRF_POWER_HAS_VDDH
+#if NRF_POWER_HAS_POFCON_VDDH
uint32_t pofcon = p_reg->POFCON;
pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
pofcon |=
-#else // NRF_POWER_HAS_VDDH
+#else // NRF_POWER_HAS_POFCON_VDDH
p_reg->POFCON =
#endif
(((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
- (enabled ?
+ (enable ?
(POWER_POFCON_POF_Enabled << POWER_POFCON_POF_Pos)
:
(POWER_POFCON_POF_Disabled << POWER_POFCON_POF_Pos));
-#if NRF_POWER_HAS_VDDH
+#if NRF_POWER_HAS_POFCON_VDDH
p_reg->POFCON = pofcon;
#endif
}
@@ -1013,7 +1022,7 @@ NRF_STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(NRF_POWER_Type const
}
#endif // NRF_POWER_HAS_POFCON
-#if NRF_POWER_HAS_VDDH
+#if NRF_POWER_HAS_POFCON_VDDH
NRF_STATIC_INLINE void nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,
nrf_power_pof_thrvddh_t thr)
{
@@ -1029,7 +1038,7 @@ NRF_STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(NRF_POWER_Ty
return (nrf_power_pof_thrvddh_t)((p_reg->POFCON & POWER_POFCON_THRESHOLDVDDH_Msk) >>
POWER_POFCON_THRESHOLDVDDH_Pos);
}
-#endif // NRF_POWER_HAS_VDDH
+#endif // NRF_POWER_HAS_POFCON_VDDH
NRF_STATIC_INLINE void nrf_power_gpregret_set(NRF_POWER_Type * p_reg, uint8_t val)
{
@@ -1127,7 +1136,7 @@ NRF_STATIC_INLINE uint32_t nrf_power_rampower_mask_get(NRF_POWER_Type const * p_
{
return p_reg->RAM[block].POWER;
}
-#endif /* defined(POWER_RAM_POWER_S0POWER_Msk) */
+#endif // defined(POWER_RAM_POWER_S0POWER_Msk)
#if NRF_POWER_HAS_DCDCEN_VDDH
NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable)
@@ -1144,7 +1153,7 @@ NRF_STATIC_INLINE bool nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg)
}
#endif // NRF_POWER_HAS_DCDCEN_VDDH
-#if NRF_POWER_HAS_VDDH
+#if NRF_POWER_HAS_MAINREGSTATUS
NRF_STATIC_INLINE
nrf_power_mainregstatus_t nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg)
{
@@ -1152,7 +1161,7 @@ nrf_power_mainregstatus_t nrf_power_mainregstatus_get(NRF_POWER_Type const * p_r
POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) >>
POWER_MAINREGSTATUS_MAINREGSTATUS_Pos);
}
-#endif // NRF_POWER_HAS_VDDH
+#endif // NRF_POWER_HAS_MAINREGSTATUS
#if NRF_POWER_HAS_USBREG
NRF_STATIC_INLINE uint32_t nrf_power_usbregstatus_get(NRF_POWER_Type const * p_reg)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h
index 14b401d..85fa32d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h
index c669c52..1f017d1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -219,7 +219,7 @@ typedef union {
* SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
* respectively) are ignored at the end of a complex sequence
* playback, indicated by the LOOPSDONE event.
- * See the @linkProductSpecification52 for more information.
+ * See the Product Specification for more information.
*/
typedef struct
{
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h
index 8da7ea9..8ae72f2 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h
index 838f2e1..69eca9a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,34 @@ extern "C" {
* @brief Hardware access layer for managing the QSPI peripheral.
*/
+#if defined(QSPI_XIPEN_XIPEN_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether XIP can be explicitly enabled or disabled via XIPEN register. */
+#define NRF_QSPI_HAS_XIPEN 1
+#else
+#define NRF_QSPI_HAS_XIPEN 0
+#endif
+
+#if defined(QSPI_XIP_ENC_ENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether encryption for XIP is present. */
+#define NRF_QSPI_HAS_XIP_ENC 1
+#else
+#define NRF_QSPI_HAS_XIP_ENC 0
+#endif
+
+#if defined(QSPI_DMA_ENC_ENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether encryption for EasyDMA is present. */
+#define NRF_QSPI_HAS_DMA_ENC 1
+#else
+#define NRF_QSPI_HAS_DMA_ENC 0
+#endif
+
+#if defined(NRF53_SERIES) || defined(__NRFX_DOXYGEN__)
+/** @brief Value representing QSPI base clock frequency. */
+#define NRF_QSPI_BASE_CLOCK_FREQ 96000000uL
+#else
+#define NRF_QSPI_BASE_CLOCK_FREQ 32000000uL
+#endif
+
/**
* @brief This value can be used as a parameter for the @ref nrf_qspi_pins_set
* function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3)
@@ -78,27 +106,47 @@ typedef enum
NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */
} nrf_qspi_int_mask_t;
-/** @brief QSPI frequency divider values. */
+/** @brief QSPI base clock frequency divider values. */
typedef enum
{
- NRF_QSPI_FREQ_32MDIV1, /**< 32.0 MHz. */
- NRF_QSPI_FREQ_32MDIV2, /**< 16.0 MHz. */
- NRF_QSPI_FREQ_32MDIV3, /**< 10.6 MHz. */
- NRF_QSPI_FREQ_32MDIV4, /**< 8.00 MHz. */
- NRF_QSPI_FREQ_32MDIV5, /**< 6.40 MHz. */
- NRF_QSPI_FREQ_32MDIV6, /**< 5.33 MHz. */
- NRF_QSPI_FREQ_32MDIV7, /**< 4.57 MHz. */
- NRF_QSPI_FREQ_32MDIV8, /**< 4.00 MHz. */
- NRF_QSPI_FREQ_32MDIV9, /**< 3.55 MHz. */
- NRF_QSPI_FREQ_32MDIV10, /**< 3.20 MHz. */
- NRF_QSPI_FREQ_32MDIV11, /**< 2.90 MHz. */
- NRF_QSPI_FREQ_32MDIV12, /**< 2.66 MHz. */
- NRF_QSPI_FREQ_32MDIV13, /**< 2.46 MHz. */
- NRF_QSPI_FREQ_32MDIV14, /**< 2.29 MHz. */
- NRF_QSPI_FREQ_32MDIV15, /**< 2.13 MHz. */
- NRF_QSPI_FREQ_32MDIV16, /**< 2.00 MHz. */
+ NRF_QSPI_FREQ_DIV1, /**< Divide by 1. */
+ NRF_QSPI_FREQ_DIV2, /**< Divide by 2. */
+ NRF_QSPI_FREQ_DIV3, /**< Divide by 3. */
+ NRF_QSPI_FREQ_DIV4, /**< Divide by 4. */
+ NRF_QSPI_FREQ_DIV5, /**< Divide by 5. */
+ NRF_QSPI_FREQ_DIV6, /**< Divide by 6. */
+ NRF_QSPI_FREQ_DIV7, /**< Divide by 7. */
+ NRF_QSPI_FREQ_DIV8, /**< Divide by 8. */
+ NRF_QSPI_FREQ_DIV9, /**< Divide by 9. */
+ NRF_QSPI_FREQ_DIV10, /**< Divide by 10. */
+ NRF_QSPI_FREQ_DIV11, /**< Divide by 11. */
+ NRF_QSPI_FREQ_DIV12, /**< Divide by 12. */
+ NRF_QSPI_FREQ_DIV13, /**< Divide by 13. */
+ NRF_QSPI_FREQ_DIV14, /**< Divide by 14. */
+ NRF_QSPI_FREQ_DIV15, /**< Divide by 15. */
+ NRF_QSPI_FREQ_DIV16, /**< Divide by 16. */
} nrf_qspi_frequency_t;
+#if defined(NRF52_SERIES)
+/** Symbols translation for backward compatibility. */
+#define NRF_QSPI_FREQ_32MDIV1 NRF_QSPI_FREQ_DIV1
+#define NRF_QSPI_FREQ_32MDIV2 NRF_QSPI_FREQ_DIV2
+#define NRF_QSPI_FREQ_32MDIV3 NRF_QSPI_FREQ_DIV3
+#define NRF_QSPI_FREQ_32MDIV4 NRF_QSPI_FREQ_DIV4
+#define NRF_QSPI_FREQ_32MDIV5 NRF_QSPI_FREQ_DIV5
+#define NRF_QSPI_FREQ_32MDIV6 NRF_QSPI_FREQ_DIV6
+#define NRF_QSPI_FREQ_32MDIV7 NRF_QSPI_FREQ_DIV7
+#define NRF_QSPI_FREQ_32MDIV8 NRF_QSPI_FREQ_DIV8
+#define NRF_QSPI_FREQ_32MDIV9 NRF_QSPI_FREQ_DIV9
+#define NRF_QSPI_FREQ_32MDIV10 NRF_QSPI_FREQ_DIV10
+#define NRF_QSPI_FREQ_32MDIV11 NRF_QSPI_FREQ_DIV11
+#define NRF_QSPI_FREQ_32MDIV12 NRF_QSPI_FREQ_DIV12
+#define NRF_QSPI_FREQ_32MDIV13 NRF_QSPI_FREQ_DIV13
+#define NRF_QSPI_FREQ_32MDIV14 NRF_QSPI_FREQ_DIV14
+#define NRF_QSPI_FREQ_32MDIV15 NRF_QSPI_FREQ_DIV15
+#define NRF_QSPI_FREQ_32MDIV16 NRF_QSPI_FREQ_DIV16
+#endif
+
/** @brief Interface configuration for a read operation. */
typedef enum
{
@@ -171,10 +219,10 @@ typedef struct
uint8_t io0_pin; /**< IO0/MOSI pin number. */
uint8_t io1_pin; /**< IO1/MISO pin number. */
uint8_t io2_pin; /**< IO2 pin number (optional).
- * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
+ * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
*/
uint8_t io3_pin; /**< IO3 pin number (optional).
- * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
+ * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
*/
} nrf_qspi_pins_t;
@@ -215,10 +263,27 @@ typedef struct
uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */
bool dpmen; /**< Enable the DPM feature. */
nrf_qspi_spi_mode_t spi_mode; /**< SPI phase and polarization. */
- nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as enum @ref nrf_qspi_frequency_t. */
+ nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as QSPI base clock frequency divider.
+ * To calculate @p sck_freq value corresponding to chosen frequency,
+ * use the following equation:
+ *
+ * sck_freq = (NRF_QSPI_BASE_CLOCK_FREQ / frequency) - 1
+ *
+ * @note Achievable frequencies are determined by available
+ * divider values and QSPI base clock frequency.
+ */
} nrf_qspi_phy_conf_t;
+#if NRF_QSPI_HAS_XIP_ENC || NRF_QSPI_HAS_DMA_ENC
+/** @brief QSPI encryption settings for XIP and DMA transfers. */
+typedef struct
+{
+ uint32_t key[4]; /**< AES 128-bit key, stored on 4 32-bit words. */
+ uint32_t nonce[3]; /**< AES 96-bit nonce, stored on 3 32-bit words. */
+} nrf_qspi_encryption_t;
+#endif
+
/**
* @brief Function for activating the specified QSPI task.
*
@@ -499,6 +564,56 @@ NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type *
nrf_qspi_cinstr_len_t length,
bool finalize);
+#if NRF_QSPI_HAS_XIPEN
+/**
+ * @brief Function for enabling or disabling Execute in Place (XIP) operation.
+ *
+ * @note XIP can be enabled after reset. See Product Specification.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] enable True if XIP is to be enabled, false otherwise.
+ */
+NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type * p_reg, bool enable);
+#endif
+
+#if NRF_QSPI_HAS_XIP_ENC
+/**
+ * @brief Function for configuring the XIP encryption.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_cfg Pointer to encryption configuration structure.
+ */
+NRF_STATIC_INLINE void nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,
+ nrf_qspi_encryption_t const * p_cfg);
+
+/**
+ * @brief Function for enabling or disabling the XIP encryption.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] enable True if XIP encryption is to be enabled, false otherwise.
+ */
+NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg, bool enable);
+#endif
+
+#if NRF_QSPI_HAS_DMA_ENC
+/**
+ * @brief Function for configuring the EasyDMA encryption.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_cfg Pointer to encryption configuration structure.
+ */
+NRF_STATIC_INLINE void nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,
+ nrf_qspi_encryption_t const * p_cfg);
+
+/**
+ * @brief Function for enabling or disabling the EasyDMA encryption.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] enable True if EasyDMA encryption is to be enabled, false otherwise.
+ */
+NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable);
+#endif
+
#ifndef NRF_DECLARE_ONLY
NRF_STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task)
@@ -779,6 +894,55 @@ NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type *
p_reg->CINSTRCONF = mask;
}
+#if NRF_QSPI_HAS_XIPEN
+NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type * p_reg, bool enable)
+{
+ p_reg->XIPEN = (enable ? QSPI_XIPEN_XIPEN_Enable << QSPI_XIPEN_XIPEN_Pos
+ : QSPI_XIPEN_XIPEN_Disable << QSPI_XIPEN_XIPEN_Pos);
+}
+#endif
+
+#if NRF_QSPI_HAS_XIP_ENC
+NRF_STATIC_INLINE void nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,
+ nrf_qspi_encryption_t const * p_cfg)
+{
+ p_reg->XIP_ENC.KEY0 = p_cfg->key[0];
+ p_reg->XIP_ENC.KEY1 = p_cfg->key[1];
+ p_reg->XIP_ENC.KEY2 = p_cfg->key[2];
+ p_reg->XIP_ENC.KEY3 = p_cfg->key[3];
+ p_reg->XIP_ENC.NONCE0 = p_cfg->nonce[0];
+ p_reg->XIP_ENC.NONCE1 = p_cfg->nonce[1];
+ p_reg->XIP_ENC.NONCE2 = p_cfg->nonce[2];
+}
+
+NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg, bool enable)
+{
+ p_reg->XIP_ENC.ENABLE =
+ (enable ? QSPI_XIP_ENC_ENABLE_ENABLE_Enabled << QSPI_XIP_ENC_ENABLE_ENABLE_Pos
+ : QSPI_XIP_ENC_ENABLE_ENABLE_Disabled << QSPI_XIP_ENC_ENABLE_ENABLE_Pos);
+}
+#endif
+
+#if NRF_QSPI_HAS_DMA_ENC
+NRF_STATIC_INLINE void nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,
+ nrf_qspi_encryption_t const * p_cfg)
+{
+ p_reg->DMA_ENC.KEY0 = p_cfg->key[0];
+ p_reg->DMA_ENC.KEY1 = p_cfg->key[1];
+ p_reg->DMA_ENC.KEY2 = p_cfg->key[2];
+ p_reg->DMA_ENC.KEY3 = p_cfg->key[3];
+ p_reg->DMA_ENC.NONCE0 = p_cfg->nonce[0];
+ p_reg->DMA_ENC.NONCE1 = p_cfg->nonce[1];
+ p_reg->DMA_ENC.NONCE2 = p_cfg->nonce[2];
+}
+
+NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable)
+{
+ p_reg->DMA_ENC.ENABLE =
+ (enable ? QSPI_DMA_ENC_ENABLE_ENABLE_Enabled << QSPI_DMA_ENC_ENABLE_ENABLE_Pos
+ : QSPI_DMA_ENC_ENABLE_ENABLE_Disabled << QSPI_DMA_ENC_ENABLE_ENABLE_Pos);
+}
+#endif
#endif // NRF_DECLARE_ONLY
/** @} */
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h
index c661bdf..d3e087d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -124,6 +124,11 @@ typedef enum
and BleIeee802154_250Kbit modes when last
bit is sent on the air. */
#endif
+#if defined(RADIO_INTENSET_SYNC_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_SYNC = offsetof(NRF_RADIO_Type, EVENTS_SYNC), /**< Generated in Ble_LR125Kbit, Ble_LR500Kbit
+ and BleIeee802154_250Kbit modes when possible
+ preamble has been received. */
+#endif
} nrf_radio_event_t;
/** @brief RADIO interrupts. */
@@ -177,6 +182,9 @@ typedef enum
#if defined(RADIO_INTENSET_PHYEND_Msk) || defined(__NRFX_DOXYGEN__)
NRF_RADIO_INT_PHYEND_MASK = RADIO_INTENSET_PHYEND_Msk, /**< Interrupt on PHYEND event. */
#endif
+#if defined(RADIO_INTENSET_SYNC_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_SYNC_MASK = RADIO_INTENSET_SYNC_Msk, /**< Interrupt on SYNC event. */
+#endif
} nrf_radio_int_mask_t;
/** @brief RADIO shortcuts. */
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_regulators.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_regulators.h
index 1c10406..3efb462 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_regulators.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_regulators.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,11 +45,95 @@ extern "C" {
* @brief Hardware access layer for managing the REGULATORS peripheral.
*/
+#if defined(REGULATORS_MAINREGSTATUS_VREGH_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether MAINREGSTATUS register is present. */
+#define NRF_REGULATORS_HAS_MAINREGSTATUS 1
+#else
+#define NRF_REGULATORS_HAS_MAINREGSTATUS 0
+#endif
+
+#if defined(REGULATORS_POFCON_POF_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether power failure comparator is present. */
+#define NRF_REGULATORS_HAS_POFCON 1
+#else
+#define NRF_REGULATORS_HAS_POFCON 0
+#endif
+
+#if defined(REGULATORS_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether power failure comparator for VDDH is present. */
+#define NRF_REGULATORS_HAS_POFCON_VDDH 1
+#else
+#define NRF_REGULATORS_HAS_POFCON_VDDH 0
+#endif
+
+#if defined(REGULATORS_VREGH_DCDCEN_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether high voltage regulator is present. */
+#define NRF_REGULATORS_HAS_DCDCEN_VDDH 1
+#else
+#define NRF_REGULATORS_HAS_DCDCEN_VDDH 0
+#endif
+
+#if defined(REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether radio regulator is present. */
+#define NRF_REGULATORS_HAS_DCDCEN_RADIO 1
+#else
+#define NRF_REGULATORS_HAS_DCDCEN_RADIO 0
+#endif
+
+#if NRF_REGULATORS_HAS_MAINREGSTATUS
+/** @brief Main regulator status. */
+typedef enum
+{
+ NRF_REGULATORS_MAINREGSTATUS_NORMAL = REGULATORS_MAINREGSTATUS_VREGH_Inactive, /**< Normal voltage mode. Voltage supplied on VDD and VDDH. */
+ NRF_REGULATORS_MAINREGSTATUS_HIGH = REGULATORS_MAINREGSTATUS_VREGH_Active /**< High voltage mode. Voltage supplied on VDDH. */
+} nrf_regulators_mainregstatus_t;
+#endif
+
+#if NRF_REGULATORS_HAS_POFCON
+/** @brief Power failure comparator thresholds. */
+typedef enum
+{
+ NRF_REGULATORS_POFTHR_V19 = REGULATORS_POFCON_THRESHOLD_V19, /**< Set threshold to 1.9 V. */
+ NRF_REGULATORS_POFTHR_V20 = REGULATORS_POFCON_THRESHOLD_V20, /**< Set threshold to 2.0 V. */
+ NRF_REGULATORS_POFTHR_V21 = REGULATORS_POFCON_THRESHOLD_V21, /**< Set threshold to 2.1 V. */
+ NRF_REGULATORS_POFTHR_V22 = REGULATORS_POFCON_THRESHOLD_V22, /**< Set threshold to 2.2 V. */
+ NRF_REGULATORS_POFTHR_V23 = REGULATORS_POFCON_THRESHOLD_V23, /**< Set threshold to 2.3 V. */
+ NRF_REGULATORS_POFTHR_V24 = REGULATORS_POFCON_THRESHOLD_V24, /**< Set threshold to 2.4 V. */
+ NRF_REGULATORS_POFTHR_V25 = REGULATORS_POFCON_THRESHOLD_V25, /**< Set threshold to 2.5 V. */
+ NRF_REGULATORS_POFTHR_V26 = REGULATORS_POFCON_THRESHOLD_V26, /**< Set threshold to 2.6 V. */
+ NRF_REGULATORS_POFTHR_V27 = REGULATORS_POFCON_THRESHOLD_V27, /**< Set threshold to 2.7 V. */
+ NRF_REGULATORS_POFTHR_V28 = REGULATORS_POFCON_THRESHOLD_V28, /**< Set threshold to 2.8 V. */
+} nrf_regulators_pof_thr_t;
+#endif
+
+#if NRF_REGULATORS_HAS_POFCON_VDDH
+/** @brief Power failure comparator thresholds for VDDH. */
+typedef enum
+{
+ NRF_REGULATORS_POFTHRVDDH_V27 = REGULATORS_POFCON_THRESHOLDVDDH_V27, /**< Set threshold to 2.7 V. */
+ NRF_REGULATORS_POFTHRVDDH_V28 = REGULATORS_POFCON_THRESHOLDVDDH_V28, /**< Set threshold to 2.8 V. */
+ NRF_REGULATORS_POFTHRVDDH_V29 = REGULATORS_POFCON_THRESHOLDVDDH_V29, /**< Set threshold to 2.9 V. */
+ NRF_REGULATORS_POFTHRVDDH_V30 = REGULATORS_POFCON_THRESHOLDVDDH_V30, /**< Set threshold to 3.0 V. */
+ NRF_REGULATORS_POFTHRVDDH_V31 = REGULATORS_POFCON_THRESHOLDVDDH_V31, /**< Set threshold to 3.1 V. */
+ NRF_REGULATORS_POFTHRVDDH_V32 = REGULATORS_POFCON_THRESHOLDVDDH_V32, /**< Set threshold to 3.2 V. */
+ NRF_REGULATORS_POFTHRVDDH_V33 = REGULATORS_POFCON_THRESHOLDVDDH_V33, /**< Set threshold to 3.3 V. */
+ NRF_REGULATORS_POFTHRVDDH_V34 = REGULATORS_POFCON_THRESHOLDVDDH_V34, /**< Set threshold to 3.4 V. */
+ NRF_REGULATORS_POFTHRVDDH_V35 = REGULATORS_POFCON_THRESHOLDVDDH_V35, /**< Set threshold to 3.5 V. */
+ NRF_REGULATORS_POFTHRVDDH_V36 = REGULATORS_POFCON_THRESHOLDVDDH_V36, /**< Set threshold to 3.6 V. */
+ NRF_REGULATORS_POFTHRVDDH_V37 = REGULATORS_POFCON_THRESHOLDVDDH_V37, /**< Set threshold to 3.7 V. */
+ NRF_REGULATORS_POFTHRVDDH_V38 = REGULATORS_POFCON_THRESHOLDVDDH_V38, /**< Set threshold to 3.8 V. */
+ NRF_REGULATORS_POFTHRVDDH_V39 = REGULATORS_POFCON_THRESHOLDVDDH_V39, /**< Set threshold to 3.9 V. */
+ NRF_REGULATORS_POFTHRVDDH_V40 = REGULATORS_POFCON_THRESHOLDVDDH_V40, /**< Set threshold to 4.0 V. */
+ NRF_REGULATORS_POFTHRVDDH_V41 = REGULATORS_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1 V. */
+ NRF_REGULATORS_POFTHRVDDH_V42 = REGULATORS_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2 V. */
+} nrf_regulators_pof_thrvddh_t;
+#endif
+
/**
* @brief Function for enabling or disabling DCDC converter.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] enable Set true to enable or false to disable DCDC converter.
+ * @param[in] enable True if DCDC converter is to be enabled, false otherwise.
*/
NRF_STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool enable);
@@ -65,6 +149,86 @@ NRF_STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bo
*/
NRF_STATIC_INLINE void nrf_regulators_system_off(NRF_REGULATORS_Type * p_reg);
+#if NRF_REGULATORS_HAS_MAINREGSTATUS
+/**
+ * @brief Function for getting the main supply status.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return The current main supply status.
+ */
+NRF_STATIC_INLINE
+nrf_regulators_mainregstatus_t nrf_regulators_mainregstatus_get(NRF_REGULATORS_Type const * p_reg);
+#endif
+
+#if NRF_REGULATORS_HAS_POFCON
+/**
+ * @brief Function for setting the power failure comparator configuration.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] enable True if power failure comparator is to be enabled, false otherwise.
+ * @param[in] thr Voltage threshold value.
+ */
+NRF_STATIC_INLINE void nrf_regulators_pofcon_set(NRF_REGULATORS_Type * p_reg,
+ bool enable,
+ nrf_regulators_pof_thr_t thr);
+
+/**
+ * @brief Function for getting the power failure comparator configuration.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[out] p_enabled Function sets this boolean variable to true
+ * if power failure comparator is enabled.
+ * The pointer can be NULL if we do not need this information.
+ *
+ * @return Threshold setting for power failure comparator.
+ */
+NRF_STATIC_INLINE
+nrf_regulators_pof_thr_t nrf_regulators_pofcon_get(NRF_REGULATORS_Type const * p_reg,
+ bool * p_enabled);
+#endif // NRF_REGULATORS_HAS_POFCON
+
+#if NRF_REGULATORS_HAS_POFCON_VDDH
+/**
+ * @brief Function for setting the VDDH power failure comparator threshold.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] thr Threshold to be set.
+ */
+NRF_STATIC_INLINE void nrf_regulators_pofcon_vddh_set(NRF_REGULATORS_Type * p_reg,
+ nrf_regulators_pof_thrvddh_t thr);
+
+/**
+ * @brief Function for getting the VDDH regulators failure comparator threshold.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Threshold setting for regulators failure comparator.
+ */
+NRF_STATIC_INLINE
+nrf_regulators_pof_thrvddh_t nrf_regulators_pofcon_vddh_get(NRF_REGULATORS_Type const * p_reg);
+#endif // NRF_REGULATORS_HAS_POFCON_VDDH
+
+#if NRF_REGULATORS_HAS_DCDCEN_VDDH
+/**
+ * @brief Function for enabling or disabling the high voltage regulator.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] enable True if the high voltage regulator is to be enabled, false otherwise.
+ */
+NRF_STATIC_INLINE void nrf_regulators_dcdcen_vddh_set(NRF_REGULATORS_Type * p_reg, bool enable);
+#endif
+
+#if NRF_REGULATORS_HAS_DCDCEN_RADIO
+/**
+ * @brief Function for enabling or disabling the radio regulator.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] enable True if the radio regulator is to be enabled, false otherwise.
+ */
+NRF_STATIC_INLINE void nrf_regulators_dcdcen_radio_set(NRF_REGULATORS_Type * p_reg, bool enable);
+#endif
+
#ifndef NRF_DECLARE_ONLY
NRF_STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool enable)
@@ -88,6 +252,85 @@ NRF_STATIC_INLINE void nrf_regulators_system_off(NRF_REGULATORS_Type * p_reg)
}
}
+#if NRF_REGULATORS_HAS_MAINREGSTATUS
+NRF_STATIC_INLINE
+nrf_regulators_mainregstatus_t nrf_regulators_mainregstatus_get(NRF_REGULATORS_Type const * p_reg)
+{
+ return (nrf_regulators_mainregstatus_t)p_reg->MAINREGSTATUS;
+}
+#endif
+
+#if NRF_REGULATORS_HAS_POFCON
+NRF_STATIC_INLINE void nrf_regulators_pofcon_set(NRF_REGULATORS_Type * p_reg,
+ bool enable,
+ nrf_regulators_pof_thr_t thr)
+{
+#if NRF_REGULATORS_HAS_POFCON_VDDH
+ uint32_t pofcon = p_reg->POFCON;
+ pofcon &= ~(REGULATORS_POFCON_THRESHOLD_Msk | REGULATORS_POFCON_POF_Msk);
+ pofcon |=
+#else // NRF_REGULATORS_HAS_POFCON_VDDH
+ p_reg->POFCON =
+#endif
+ (((uint32_t)thr) << REGULATORS_POFCON_THRESHOLD_Pos) |
+ (enable ?
+ (REGULATORS_POFCON_POF_Enabled << REGULATORS_POFCON_POF_Pos)
+ :
+ (REGULATORS_POFCON_POF_Disabled << REGULATORS_POFCON_POF_Pos));
+#if NRF_REGULATORS_HAS_POFCON_VDDH
+ p_reg->POFCON = pofcon;
+#endif
+}
+
+NRF_STATIC_INLINE
+nrf_regulators_pof_thr_t nrf_regulators_pofcon_get(NRF_REGULATORS_Type const * p_reg,
+ bool * p_enabled)
+{
+ uint32_t pofcon = p_reg->POFCON;
+ if (NULL != p_enabled)
+ {
+ (*p_enabled) = ((pofcon & REGULATORS_POFCON_POF_Msk) >> REGULATORS_POFCON_POF_Pos)
+ == REGULATORS_POFCON_POF_Enabled;
+ }
+ return (nrf_regulators_pof_thr_t)((pofcon & REGULATORS_POFCON_THRESHOLD_Msk) >>
+ REGULATORS_POFCON_THRESHOLD_Pos);
+}
+#endif // NRF_REGULATORS_HAS_POFCON
+
+#if NRF_REGULATORS_HAS_POFCON_VDDH
+NRF_STATIC_INLINE void nrf_regulators_pofcon_vddh_set(NRF_REGULATORS_Type * p_reg,
+ nrf_regulators_pof_thrvddh_t thr)
+{
+ uint32_t pofcon = p_reg->POFCON;
+ pofcon &= ~REGULATORS_POFCON_THRESHOLDVDDH_Msk;
+ pofcon |= (((uint32_t)thr) << REGULATORS_POFCON_THRESHOLDVDDH_Pos);
+ p_reg->POFCON = pofcon;
+}
+
+NRF_STATIC_INLINE
+nrf_regulators_pof_thrvddh_t nrf_regulators_pofcon_vddh_get(NRF_REGULATORS_Type const * p_reg)
+{
+ return (nrf_regulators_pof_thrvddh_t)((p_reg->POFCON & REGULATORS_POFCON_THRESHOLDVDDH_Msk) >>
+ REGULATORS_POFCON_THRESHOLDVDDH_Pos);
+}
+#endif // NRF_REGULATORS_HAS_POFCON_VDDH
+
+#if NRF_REGULATORS_HAS_DCDCEN_VDDH
+NRF_STATIC_INLINE void nrf_regulators_dcdcen_vddh_set(NRF_REGULATORS_Type * p_reg, bool enable)
+{
+ p_reg->VREGH.DCDCEN = (enable) ? REGULATORS_VREGH_DCDCEN_DCDCEN_Enabled :
+ REGULATORS_VREGH_DCDCEN_DCDCEN_Disabled;
+}
+#endif
+
+#if NRF_REGULATORS_HAS_DCDCEN_RADIO
+NRF_STATIC_INLINE void nrf_regulators_dcdcen_radio_set(NRF_REGULATORS_Type * p_reg, bool enable)
+{
+ p_reg->VREGRADIO.DCDCEN = (enable) ? REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Enabled :
+ REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Disabled;
+}
+#endif
+
#endif // NRF_DECLARE_ONLY
/** @} */
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_reset.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_reset.h
index 438dedf..b9292c0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_reset.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_reset.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h
index 27de21e..26698e0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h
index ab1c4b7..710b943 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h
index 3757413..fef39a3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -66,7 +66,10 @@ typedef enum
NRF_SAADC_INPUT_AIN5 = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5).
NRF_SAADC_INPUT_AIN6 = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6).
NRF_SAADC_INPUT_AIN7 = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7).
- NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD ///< VDD as input.
+ NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD, ///< VDD as input.
+#if defined(SAADC_CH_PSELP_PSELP_VDDHDIV5) || defined(__NRFX_DOXYGEN__)
+ NRF_SAADC_INPUT_VDDHDIV5 = SAADC_CH_PSELP_PSELP_VDDHDIV5 ///< VDDH/5 as input.
+#endif
} nrf_saadc_input_t;
/** @brief Analog-to-digital converter oversampling mode. */
@@ -254,7 +257,7 @@ NRF_STATIC_INLINE uint32_t nrf_saadc_task_address_get(NRF_SAADC_Type const * p_r
nrf_saadc_task_t task);
/**
- * @brief Function for retrieving the state of the UARTE event.
+ * @brief Function for retrieving the state of the SAADC event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to be checked.
@@ -380,6 +383,14 @@ NRF_STATIC_INLINE void nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,
int16_t high);
/**
+ * @brief Function for setting the configuration of SAADC interrupts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Interrupts configuration to be set.
+ */
+NRF_STATIC_INLINE void nrf_saadc_int_set(NRF_SAADC_Type * p_reg, uint32_t mask);
+
+/**
* @brief Function for enabling specified SAADC interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -718,6 +729,11 @@ NRF_STATIC_INLINE void nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,
| (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk));
}
+NRF_STATIC_INLINE void nrf_saadc_int_set(NRF_SAADC_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTEN = mask;
+}
+
NRF_STATIC_INLINE void nrf_saadc_int_enable(NRF_SAADC_Type * p_reg, uint32_t mask)
{
p_reg->INTENSET = mask;
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h
index bb5d034..95df3d2 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h
index 0ce3a1f..a644f3e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -57,21 +57,24 @@ extern "C" {
(NRFX_CHECK(SPIM0_FEATURE_HARDWARE_CSN_PRESENT) || \
NRFX_CHECK(SPIM1_FEATURE_HARDWARE_CSN_PRESENT) || \
NRFX_CHECK(SPIM2_FEATURE_HARDWARE_CSN_PRESENT) || \
- NRFX_CHECK(SPIM3_FEATURE_HARDWARE_CSN_PRESENT))
+ NRFX_CHECK(SPIM3_FEATURE_HARDWARE_CSN_PRESENT) || \
+ NRFX_CHECK(SPIM4_FEATURE_HARDWARE_CSN_PRESENT))
/** @brief Macro for checking if the DCX pin control is available. */
#define NRF_SPIM_DCX_PRESENT \
(NRFX_CHECK(SPIM0_FEATURE_DCX_PRESENT) || \
NRFX_CHECK(SPIM1_FEATURE_DCX_PRESENT) || \
NRFX_CHECK(SPIM2_FEATURE_DCX_PRESENT) || \
- NRFX_CHECK(SPIM3_FEATURE_DCX_PRESENT))
+ NRFX_CHECK(SPIM3_FEATURE_DCX_PRESENT) || \
+ NRFX_CHECK(SPIM4_FEATURE_DCX_PRESENT))
/** @brief Macro for checking if the RXDELAY function is available. */
#define NRF_SPIM_RXDELAY_PRESENT \
(NRFX_CHECK(SPIM0_FEATURE_RXDELAY_PRESENT) || \
NRFX_CHECK(SPIM1_FEATURE_RXDELAY_PRESENT) || \
NRFX_CHECK(SPIM2_FEATURE_RXDELAY_PRESENT) || \
- NRFX_CHECK(SPIM3_FEATURE_RXDELAY_PRESENT))
+ NRFX_CHECK(SPIM3_FEATURE_RXDELAY_PRESENT) || \
+ NRFX_CHECK(SPIM4_FEATURE_RXDELAY_PRESENT))
#if defined(NRF_SPIM_DCX_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h
index cacb815..7819b6b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spu.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spu.h
index 62b6b4d..847068a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spu.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_systick.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_systick.h
index 483a749..8269854 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_systick.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_systick.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h
index 67dbdba..56e1d43 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2012 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h
index 2ffe5cd..d3cc5d6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h
index 1ffd531..5e37048 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h
index 50b4ed4..04d7555 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -104,9 +104,12 @@ typedef enum
/** @brief TWIM master clock frequency. */
typedef enum
{
- NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
- NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
- NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400 ///< 400 kbps.
+ NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
+ NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
+ NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400, ///< 400 kbps.
+#if defined(TWIM_FREQUENCY_FREQUENCY_K1000) || defined(__NRFX_DOXYGEN__)
+ NRF_TWIM_FREQ_1000K = TWIM_FREQUENCY_FREQUENCY_K1000 ///< 1000 kbps.
+#endif
} nrf_twim_frequency_t;
/** @brief TWIM error source. */
@@ -350,6 +353,15 @@ NRF_STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
uint32_t mask);
/**
+ * @brief Function for getting the shortcut setting.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Current shortcut configuration.
+ */
+NRF_STATIC_INLINE uint32_t nrf_twim_shorts_get(NRF_TWIM_Type const * p_reg);
+
+/**
* @brief Function for getting the amount of transmitted bytes.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -553,6 +565,11 @@ NRF_STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
p_reg->SHORTS = mask;
}
+NRF_STATIC_INLINE uint32_t nrf_twim_shorts_get(NRF_TWIM_Type const * p_reg)
+{
+ return p_reg->SHORTS;
+}
+
NRF_STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type const * p_reg)
{
return p_reg->TXD.AMOUNT;
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h
index 55d6684..2dffdaf 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h
index 8512cbd..2acc9e9 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h
index 06c5960..ba79304 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbd.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbd.h
index 9759c72..71c56c2 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbd.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbd.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -1086,15 +1086,6 @@ NRF_STATIC_INLINE uint32_t nrf_usbd_ep_amount_get(NRF_USBD_Type const * p_reg, u
NRF_STATIC_INLINE void nrf_usbd_enable(NRF_USBD_Type * p_reg)
{
-#ifdef NRF_FPGA_IMPLEMENTATION
- *(volatile uint32_t *)0x400005F4 = 3;
- __ISB();
- __DSB();
- *(volatile uint32_t *)0x400005F0 = 3;
- __ISB();
- __DSB();
-#endif
-
p_reg->ENABLE = USBD_ENABLE_ENABLE_Enabled << USBD_ENABLE_ENABLE_Pos;
(void) p_reg->ENABLE;
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbreg.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbreg.h
new file mode 100644
index 0000000..be811e1
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbreg.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRF_USBREG_H__
+#define NRF_USBREG_H__
+
+#include <nrfx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_usbreg_hal USBREG HAL
+ * @{
+ * @ingroup nrf_usbd
+ * @ingroup nrf_power
+ * @brief Hardware access layer for managing the USB regulator peripheral.
+ */
+
+/** @brief USBREG events. */
+typedef enum
+{
+ NRF_USBREG_EVENT_USBDETECTED = offsetof(NRF_USBREG_Type, EVENTS_USBDETECTED), /**< Voltage supply detected on VBUS. */
+ NRF_USBREG_EVENT_USBREMOVED = offsetof(NRF_USBREG_Type, EVENTS_USBREMOVED), /**< Voltage supply removed from VBUS. */
+ NRF_USBREG_EVENT_USBPWRRDY = offsetof(NRF_USBREG_Type, EVENTS_USBPWRRDY) /**< USB 3.3 V supply ready. */
+} nrf_usbreg_event_t;
+
+/** @brief USBREG interrupts. */
+typedef enum
+{
+ NRF_USBREG_INT_USBDETECTED = USBREG_INTEN_USBDETECTED_Msk, /**< Interrupt on USBDETECTED. */
+ NRF_USBREG_INT_USBREMOVED = USBREG_INTEN_USBREMOVED_Msk, /**< Interrupt on USBREMOVED. */
+ NRF_USBREG_INT_USBPWRRDY = USBREG_INTEN_USBPWRRDY_Msk /**< Interrupt on USBPWRRDY. */
+} nrf_usbreg_int_mask_t;
+
+/** @brief USBREGSTATUS register bit masks. */
+typedef enum
+{
+ NRF_USBREG_STATUS_VBUSDETECT_MASK = USBREG_USBREGSTATUS_VBUSDETECT_Msk, /**< USB detected or removed. */
+ NRF_USBREG_STATUS_OUTPUTRDY_MASK = USBREG_USBREGSTATUS_OUTPUTRDY_Msk /**< USB 3.3 V supply ready. */
+} nrf_usbreg_status_mask_t;
+
+/**
+ * @brief Function for clearing the specified USBREG event.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be cleared.
+ */
+NRF_STATIC_INLINE void nrf_usbreg_event_clear(NRF_USBREG_Type * p_reg,
+ nrf_usbreg_event_t event);
+
+/**
+ * @brief Function for retrieving the state of the USBREG event.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
+ *
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
+ */
+NRF_STATIC_INLINE bool nrf_usbreg_event_check(NRF_USBREG_Type const * p_reg,
+ nrf_usbreg_event_t event);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
+ */
+NRF_STATIC_INLINE void nrf_usbreg_int_enable(NRF_USBREG_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
+ */
+NRF_STATIC_INLINE void nrf_usbreg_int_disable(NRF_USBREG_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for checking if the specified interrupts are enabled.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be checked.
+ *
+ * @return Mask of enabled interrupts.
+ */
+NRF_STATIC_INLINE uint32_t nrf_usbreg_int_enable_check(NRF_USBREG_Type const * p_reg,
+ uint32_t mask);
+
+/**
+ * @brief Function for getting the whole USBREGSTATUS register.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return The USBREGSTATUS register value.
+ * Use @ref nrf_usbreg_status_mask_t values for bit masking.
+ */
+NRF_STATIC_INLINE uint32_t nrf_usbreg_status_get(NRF_USBREG_Type const * p_reg);
+
+#ifndef NRF_DECLARE_ONLY
+
+NRF_STATIC_INLINE void nrf_usbreg_event_clear(NRF_USBREG_Type * p_reg,
+ nrf_usbreg_event_t event)
+{
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+}
+
+NRF_STATIC_INLINE bool nrf_usbreg_event_check(NRF_USBREG_Type const * p_reg,
+ nrf_usbreg_event_t event)
+{
+ return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+NRF_STATIC_INLINE void nrf_usbreg_int_enable(NRF_USBREG_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTENSET = mask;
+}
+
+NRF_STATIC_INLINE void nrf_usbreg_int_disable(NRF_USBREG_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTENCLR = mask;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_usbreg_int_enable_check(NRF_USBREG_Type const * p_reg,
+ uint32_t mask)
+{
+ return p_reg->INTENSET & mask;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_usbreg_status_get(NRF_USBREG_Type const * p_reg)
+{
+ return p_reg->USBREGSTATUS;
+}
+
+#endif // NRF_DECLARE_ONLY
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_USBREG_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_vmc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_vmc.h
index a1d54e4..add75ef 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_vmc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_vmc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_regulators.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_vreqctrl.h
similarity index 59%
copy from hw/mcu/nordic/src/ext/nrfx/hal/nrf_regulators.h
copy to hw/mcu/nordic/src/ext/nrfx/hal/nrf_vreqctrl.h
index 1c10406..be9d2e5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_regulators.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_vreqctrl.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,8 +29,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef NRF_REGULATORS_H__
-#define NRF_REGULATORS_H__
+#ifndef NRF_VREQCTRL_H__
+#define NRF_VREQCTRL_H__
#include <nrfx.h>
@@ -39,53 +39,41 @@ extern "C" {
#endif
/**
- * @defgroup nrf_regulators_hal REGULATORS HAL
+ * @defgroup nrf_vreqctrl_hal VREQCTRL HAL
* @{
* @ingroup nrf_power
- * @brief Hardware access layer for managing the REGULATORS peripheral.
+ * @brief Hardware access layer for managing the VREQCTRL peripheral.
*/
/**
- * @brief Function for enabling or disabling DCDC converter.
+ * @brief Function for requesting high voltage on RADIO, to increase its output power by 3 dBm.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] enable Set true to enable or false to disable DCDC converter.
+ * @param[in] enable True if high voltage on RADIO is to be enabled, false otherwise.
*/
-NRF_STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool enable);
+NRF_STATIC_INLINE void nrf_vreqctrl_radio_high_voltage_set(NRF_VREQCTRL_Type * p_reg, bool enable);
/**
- * @brief Function for putting CPU in system OFF mode.
- *
- * This function puts the CPU into system off mode.
- * The only way to wake up the CPU is by reset.
- *
- * @note This function never returns.
+ * @brief Function for checking if high voltage on RADIO is ready.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval true The high voltage is ready.
+ * @retval false The high voltage is not ready.
*/
-NRF_STATIC_INLINE void nrf_regulators_system_off(NRF_REGULATORS_Type * p_reg);
+NRF_STATIC_INLINE bool nrf_vreqctrl_radio_high_voltage_check(NRF_VREQCTRL_Type const * p_reg);
#ifndef NRF_DECLARE_ONLY
-NRF_STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool enable)
+NRF_STATIC_INLINE void nrf_vreqctrl_radio_high_voltage_set(NRF_VREQCTRL_Type * p_reg, bool enable)
{
-#if defined(REGULATORS_DCDCEN_DCDCEN_Msk)
- p_reg->DCDCEN = (enable ? REGULATORS_DCDCEN_DCDCEN_Msk : 0);
-#else
- p_reg->VREGMAIN.DCDCEN = (enable ? REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Msk : 0);
-#endif
+ p_reg->VREGRADIO.VREQH =
+ (enable ? VREQCTRL_VREGRADIO_VREQH_VREQH_Enabled : VREQCTRL_VREGRADIO_VREQH_VREQH_Disabled);
}
-NRF_STATIC_INLINE void nrf_regulators_system_off(NRF_REGULATORS_Type * p_reg)
+NRF_STATIC_INLINE bool nrf_vreqctrl_radio_high_voltage_check(NRF_VREQCTRL_Type const * p_reg)
{
- p_reg->SYSTEMOFF = REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk;
- __DSB();
-
- /* Solution for simulated System OFF in debug mode */
- while (true)
- {
- __WFE();
- }
+ return (bool)(p_reg->VREGRADIO.VREQHREADY & VREQCTRL_VREGRADIO_VREQHREADY_READY_Msk);
}
#endif // NRF_DECLARE_ONLY
@@ -96,4 +84,4 @@ NRF_STATIC_INLINE void nrf_regulators_system_off(NRF_REGULATORS_Type * p_reg)
}
#endif
-#endif // NRF_REGULATORS_H__
+#endif // NRF_VREQCTRL_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h
index e572fd9..79f866c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -38,6 +38,10 @@
extern "C" {
#endif
+#ifndef NRF_WDT0
+#define NRF_WDT0 NRF_WDT
+#endif
+
/**
* @defgroup nrf_wdt_hal WDT HAL
* @{
diff --git a/hw/mcu/nordic/src/ext/nrfx/helpers/nrfx_gppi.h b/hw/mcu/nordic/src/ext/nrfx/helpers/nrfx_gppi.h
index 1c7e2fb..eb8b600 100644
--- a/hw/mcu/nordic/src/ext/nrfx/helpers/nrfx_gppi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/helpers/nrfx_gppi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_application.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_application.s
index 4152a8c..d9eb6eb 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_application.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_application.s
@@ -94,9 +94,9 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD 0 ; Reserved
DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
DCD SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
- DCD SPIM2_IRQHandler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD SPIM4_IRQHandler
+ DCD SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
+ DCD SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
DCD GPIOTE0_IRQHandler
DCD SAADC_IRQHandler
DCD TIMER0_IRQHandler
@@ -120,7 +120,7 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD PWM0_IRQHandler
DCD PWM1_IRQHandler
DCD PWM2_IRQHandler
- DCD 0 ; Reserved
+ DCD PWM3_IRQHandler
DCD 0 ; Reserved
DCD PDM0_IRQHandler
DCD 0 ; Reserved
@@ -135,8 +135,8 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
- DCD QDEC_IRQHandler
- DCD 0 ; Reserved
+ DCD QDEC0_IRQHandler
+ DCD QDEC1_IRQHandler
DCD 0 ; Reserved
DCD USBD_IRQHandler
DCD USBREGULATOR_IRQHandler
@@ -403,7 +403,9 @@ Default_Handler PROC
EXPORT CLOCK_POWER_IRQHandler [WEAK]
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler [WEAK]
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler [WEAK]
- EXPORT SPIM2_IRQHandler [WEAK]
+ EXPORT SPIM4_IRQHandler [WEAK]
+ EXPORT SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler [WEAK]
+ EXPORT SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler [WEAK]
EXPORT GPIOTE0_IRQHandler [WEAK]
EXPORT SAADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
@@ -423,13 +425,15 @@ Default_Handler PROC
EXPORT PWM0_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT PWM2_IRQHandler [WEAK]
+ EXPORT PWM3_IRQHandler [WEAK]
EXPORT PDM0_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT IPC_IRQHandler [WEAK]
EXPORT QSPI_IRQHandler [WEAK]
EXPORT NFCT_IRQHandler [WEAK]
EXPORT GPIOTE1_IRQHandler [WEAK]
- EXPORT QDEC_IRQHandler [WEAK]
+ EXPORT QDEC0_IRQHandler [WEAK]
+ EXPORT QDEC1_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
EXPORT USBREGULATOR_IRQHandler [WEAK]
EXPORT KMU_IRQHandler [WEAK]
@@ -440,7 +444,9 @@ SPU_IRQHandler
CLOCK_POWER_IRQHandler
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
-SPIM2_IRQHandler
+SPIM4_IRQHandler
+SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
+SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
GPIOTE0_IRQHandler
SAADC_IRQHandler
TIMER0_IRQHandler
@@ -460,13 +466,15 @@ EGU5_IRQHandler
PWM0_IRQHandler
PWM1_IRQHandler
PWM2_IRQHandler
+PWM3_IRQHandler
PDM0_IRQHandler
I2S0_IRQHandler
IPC_IRQHandler
QSPI_IRQHandler
NFCT_IRQHandler
GPIOTE1_IRQHandler
-QDEC_IRQHandler
+QDEC0_IRQHandler
+QDEC1_IRQHandler
USBD_IRQHandler
USBREGULATOR_IRQHandler
KMU_IRQHandler
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S
index 9ecb0ff..162db0c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S
@@ -68,7 +68,7 @@ __HeapBase:
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
- .section .isr_vector
+ .section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S
index dfc79ee..9e97163 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S
@@ -68,7 +68,7 @@ __HeapBase:
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
- .section .isr_vector
+ .section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52805.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52805.S
index d725622..3e314c7 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52805.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52805.S
@@ -68,7 +68,7 @@ __HeapBase:
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
- .section .isr_vector
+ .section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S
index 4980201..5bca5cd 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S
@@ -68,7 +68,7 @@ __HeapBase:
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
- .section .isr_vector
+ .section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S
index 0a1a1e4..ac7fd29 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S
@@ -68,7 +68,7 @@ __HeapBase:
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
- .section .isr_vector
+ .section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52833.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52833.S
index e781779..042b0c3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52833.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52833.S
@@ -68,7 +68,7 @@ __HeapBase:
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
- .section .isr_vector
+ .section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S
index 0de37bb..187a08d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S
@@ -68,7 +68,7 @@ __HeapBase:
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
- .section .isr_vector
+ .section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_application.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_application.S
index e89588a..1b05d92 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_application.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_application.S
@@ -68,7 +68,7 @@ __HeapBase:
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
- .section .isr_vector
+ .section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
@@ -100,9 +100,9 @@ __isr_vector:
.long 0 /*Reserved */
.long SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
.long SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
- .long SPIM2_IRQHandler
- .long 0 /*Reserved */
- .long 0 /*Reserved */
+ .long SPIM4_IRQHandler
+ .long SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
+ .long SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
.long GPIOTE0_IRQHandler
.long SAADC_IRQHandler
.long TIMER0_IRQHandler
@@ -126,7 +126,7 @@ __isr_vector:
.long PWM0_IRQHandler
.long PWM1_IRQHandler
.long PWM2_IRQHandler
- .long 0 /*Reserved */
+ .long PWM3_IRQHandler
.long 0 /*Reserved */
.long PDM0_IRQHandler
.long 0 /*Reserved */
@@ -141,8 +141,8 @@ __isr_vector:
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
- .long QDEC_IRQHandler
- .long 0 /*Reserved */
+ .long QDEC0_IRQHandler
+ .long QDEC1_IRQHandler
.long 0 /*Reserved */
.long USBD_IRQHandler
.long USBREGULATOR_IRQHandler
@@ -504,7 +504,9 @@ Default_Handler:
IRQ CLOCK_POWER_IRQHandler
IRQ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
IRQ SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
- IRQ SPIM2_IRQHandler
+ IRQ SPIM4_IRQHandler
+ IRQ SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
+ IRQ SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
IRQ GPIOTE0_IRQHandler
IRQ SAADC_IRQHandler
IRQ TIMER0_IRQHandler
@@ -524,13 +526,15 @@ Default_Handler:
IRQ PWM0_IRQHandler
IRQ PWM1_IRQHandler
IRQ PWM2_IRQHandler
+ IRQ PWM3_IRQHandler
IRQ PDM0_IRQHandler
IRQ I2S0_IRQHandler
IRQ IPC_IRQHandler
IRQ QSPI_IRQHandler
IRQ NFCT_IRQHandler
IRQ GPIOTE1_IRQHandler
- IRQ QDEC_IRQHandler
+ IRQ QDEC0_IRQHandler
+ IRQ QDEC1_IRQHandler
IRQ USBD_IRQHandler
IRQ USBREGULATOR_IRQHandler
IRQ KMU_IRQHandler
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_network.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_network.S
index 836c37e..e8aa81e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_network.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_network.S
@@ -68,7 +68,7 @@ __HeapBase:
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
- .section .isr_vector
+ .section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf9160.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf9160.S
index bf44dd7..d8b9893 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf9160.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf9160.S
@@ -68,7 +68,7 @@ __HeapBase:
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
- .section .isr_vector
+ .section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_application.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_application.s
index 4fce0f3..32106ed 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_application.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_application.s
@@ -95,9 +95,9 @@ __vector_table
DCD 0 ; Reserved
DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
DCD SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
- DCD SPIM2_IRQHandler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD SPIM4_IRQHandler
+ DCD SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
+ DCD SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
DCD GPIOTE0_IRQHandler
DCD SAADC_IRQHandler
DCD TIMER0_IRQHandler
@@ -121,7 +121,7 @@ __vector_table
DCD PWM0_IRQHandler
DCD PWM1_IRQHandler
DCD PWM2_IRQHandler
- DCD 0 ; Reserved
+ DCD PWM3_IRQHandler
DCD 0 ; Reserved
DCD PDM0_IRQHandler
DCD 0 ; Reserved
@@ -136,8 +136,8 @@ __vector_table
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
- DCD QDEC_IRQHandler
- DCD 0 ; Reserved
+ DCD QDEC0_IRQHandler
+ DCD QDEC1_IRQHandler
DCD 0 ; Reserved
DCD USBD_IRQHandler
DCD USBREGULATOR_IRQHandler
@@ -429,9 +429,19 @@ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
B .
- PUBWEAK SPIM2_IRQHandler
+ PUBWEAK SPIM4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPIM4_IRQHandler
+ B .
+
+ PUBWEAK SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
+ B .
+
+ PUBWEAK SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-SPIM2_IRQHandler
+SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
B .
PUBWEAK GPIOTE0_IRQHandler
@@ -529,6 +539,11 @@ PWM1_IRQHandler
PWM2_IRQHandler
B .
+ PUBWEAK PWM3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PWM3_IRQHandler
+ B .
+
PUBWEAK PDM0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PDM0_IRQHandler
@@ -559,9 +574,14 @@ NFCT_IRQHandler
GPIOTE1_IRQHandler
B .
- PUBWEAK QDEC_IRQHandler
+ PUBWEAK QDEC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+QDEC0_IRQHandler
+ B .
+
+ PUBWEAK QDEC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-QDEC_IRQHandler
+QDEC1_IRQHandler
B .
PUBWEAK USBD_IRQHandler
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h
index 289ab23..f36d5e7 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h
@@ -35,8 +35,8 @@ POSSIBILITY OF SUCH DAMAGE.
/* MDK version */
#define MDK_MAJOR_VERSION 8
-#define MDK_MINOR_VERSION 29
-#define MDK_MICRO_VERSION 0
+#define MDK_MINOR_VERSION 30
+#define MDK_MICRO_VERSION 2
/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */
#if defined (NRF51) ||\
@@ -85,6 +85,18 @@ POSSIBILITY OF SUCH DAMAGE.
#endif
#endif
+/* Define coprocessor domains */
+#if defined (NRF5340_XXAA_APPLICATION)
+ #ifndef NRF_APPLICATION
+ #define NRF_APPLICATION
+ #endif
+#endif
+#if defined (NRF5340_XXAA_NETWORK)
+ #ifndef NRF_NETWORK
+ #define NRF_NETWORK
+ #endif
+#endif
+
#if defined(_WIN32)
/* Do not include nrf specific files when building for PC host */
#elif defined(__unix)
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h
index 27baec4..5da3cea 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h
@@ -30,10 +30,10 @@
* @file nrf51.h
* @brief CMSIS HeaderFile
* @version 522
- * @date 25. October 2019
- * @note Generated by SVDConv V3.3.25 on Friday, 25.10.2019 09:35:33
+ * @date 17. January 2020
+ * @note Generated by SVDConv V3.3.25 on Friday, 17.01.2020 17:08:30
* from File 'nrf51.svd',
- * last modified on Friday, 25.10.2019 07:35:24
+ * last modified on Friday, 17.01.2020 16:08:22
*/
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_erratas.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_erratas.h
deleted file mode 100644
index 0f296a5..0000000
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_erratas.h
+++ /dev/null
@@ -1,2579 +0,0 @@
-#ifndef NRF51422_ERRATAS_H
-#define NRF51422_ERRATAS_H
-
-/*
-
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
-2. Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
-3. Neither the name of Nordic Semiconductor ASA nor the names of its
- contributors may be used to endorse or promote products derived from this
- software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-
-*/
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "compiler_abstraction.h"
-
-static bool errata_1(void) __UNUSED;
-static bool errata_2(void) __UNUSED;
-static bool errata_3(void) __UNUSED;
-static bool errata_4(void) __UNUSED;
-static bool errata_5(void) __UNUSED;
-static bool errata_6(void) __UNUSED;
-static bool errata_7(void) __UNUSED;
-static bool errata_8(void) __UNUSED;
-static bool errata_9(void) __UNUSED;
-static bool errata_10(void) __UNUSED;
-static bool errata_11(void) __UNUSED;
-static bool errata_12(void) __UNUSED;
-static bool errata_13(void) __UNUSED;
-static bool errata_14(void) __UNUSED;
-static bool errata_15(void) __UNUSED;
-static bool errata_16(void) __UNUSED;
-static bool errata_17(void) __UNUSED;
-static bool errata_18(void) __UNUSED;
-static bool errata_19(void) __UNUSED;
-static bool errata_20(void) __UNUSED;
-static bool errata_21(void) __UNUSED;
-static bool errata_22(void) __UNUSED;
-static bool errata_23(void) __UNUSED;
-static bool errata_24(void) __UNUSED;
-static bool errata_25(void) __UNUSED;
-static bool errata_26(void) __UNUSED;
-static bool errata_27(void) __UNUSED;
-static bool errata_28(void) __UNUSED;
-static bool errata_29(void) __UNUSED;
-static bool errata_30(void) __UNUSED;
-static bool errata_31(void) __UNUSED;
-static bool errata_32(void) __UNUSED;
-static bool errata_33(void) __UNUSED;
-static bool errata_34(void) __UNUSED;
-static bool errata_35(void) __UNUSED;
-static bool errata_36(void) __UNUSED;
-static bool errata_37(void) __UNUSED;
-static bool errata_38(void) __UNUSED;
-static bool errata_39(void) __UNUSED;
-static bool errata_40(void) __UNUSED;
-static bool errata_41(void) __UNUSED;
-static bool errata_42(void) __UNUSED;
-static bool errata_43(void) __UNUSED;
-static bool errata_44(void) __UNUSED;
-static bool errata_45(void) __UNUSED;
-static bool errata_46(void) __UNUSED;
-static bool errata_47(void) __UNUSED;
-static bool errata_48(void) __UNUSED;
-static bool errata_49(void) __UNUSED;
-static bool errata_50(void) __UNUSED;
-static bool errata_51(void) __UNUSED;
-static bool errata_52(void) __UNUSED;
-static bool errata_53(void) __UNUSED;
-static bool errata_54(void) __UNUSED;
-static bool errata_55(void) __UNUSED;
-static bool errata_56(void) __UNUSED;
-static bool errata_57(void) __UNUSED;
-static bool errata_58(void) __UNUSED;
-static bool errata_59(void) __UNUSED;
-static bool errata_60(void) __UNUSED;
-static bool errata_61(void) __UNUSED;
-static bool errata_62(void) __UNUSED;
-static bool errata_63(void) __UNUSED;
-static bool errata_64(void) __UNUSED;
-static bool errata_65(void) __UNUSED;
-static bool errata_66(void) __UNUSED;
-static bool errata_67(void) __UNUSED;
-static bool errata_68(void) __UNUSED;
-static bool errata_69(void) __UNUSED;
-static bool errata_70(void) __UNUSED;
-static bool errata_71(void) __UNUSED;
-static bool errata_72(void) __UNUSED;
-static bool errata_73(void) __UNUSED;
-static bool errata_74(void) __UNUSED;
-static bool errata_75(void) __UNUSED;
-static bool errata_76(void) __UNUSED;
-static bool errata_77(void) __UNUSED;
-static bool errata_78(void) __UNUSED;
-
-static bool errata_1(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_2(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_3(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_4(void)
-{
- return false;
-}
-
-static bool errata_5(void)
-{
- return false;
-}
-
-static bool errata_6(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_7(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_8(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_9(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_10(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_11(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_12(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_13(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_14(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_15(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_16(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_17(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_18(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_19(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_20(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_21(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_22(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_23(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_24(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_25(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_26(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_27(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_28(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_29(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_30(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_31(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_32(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
- }
- break;
-
- }
-
- return false;
-}
-
-static bool errata_33(void)
-{
- uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
- uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
-
- switch(var1)
- {
- case 0x01:
- switch(var2)
- {
- case 0x00ul:
- return true;
- case 0x01ul:
- return true;
- case 0x02ul:
- return false;
- case 0x04ul:
- return false;
- case 0x07ul:
- return false;
- case 0x08ul:
- return false;
- case 0x09ul:
- return false;
- default:
- return false;
- break;
... 47859 lines suppressed ...