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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/08/06 07:31:38 UTC

[incubator-nuttx] 09/10: imrt102x:ENET Match Data sheet Naming

This is an automated email from the ASF dual-hosted git repository.

xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git

commit b9a6b01e6cf696aa22e4b0e4499a5d80b8dc41bc
Author: David Sidrane <Da...@NscDg.com>
AuthorDate: Fri Aug 5 09:48:51 2022 -0700

    imrt102x:ENET Match Data sheet Naming
---
 arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h    | 18 +++++++++---------
 arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h |  2 +-
 arch/arm/src/imxrt/imxrt_clockconfig.c                |  4 ++--
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h
index a99630dd09..4eed2f4e0f 100644
--- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h
+++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h
@@ -838,19 +838,19 @@
 
 /* Analog ENET PLL Control Register */
 
-#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT      (0)       /* Bits 0-1:    Controls the frequency of the ethernet0 reference clock */
-#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK       (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
-#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ    ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
-#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ    ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
-#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ   ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
-#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ   ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT      (0)       /* Bits 0-1:    Controls the frequency of the ethernet0 reference clock */
+#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK       (0x3 << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_25MHZ    ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ    ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_100MHZ   ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_125MHZ   ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
 
 /*                                                                 Bits 2-11:
  *                                                                   Reserved
  */
-#define CCM_ANALOG_PLL_ENET_POWERDOWN                   (1 << 12) /* Bit 12:     Powers down the PLL */
-#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN               (1 << 13) /* Bit 13:     Enable the PLL providing the ENET1 125 MHz reference clock */
-#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT       (14)       /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_ENET_POWERDOWN                  (1 << 12) /* Bit 12:     Powers down the PLL */
+#define CCM_ANALOG_PLL_ENET_ENABLE                     (1 << 13) /* Bit 13:     Enable the PLL providing the ENET1 125 MHz reference clock */
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT       (14)      /* Bits 14-15: Determines the bypass source */
 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK        (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)
 #  define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M   ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
 
diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h
index 50d281d902..094f9513dc 100644
--- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h
+++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h
@@ -993,7 +993,7 @@
 #define GPR_GPR1_GINT                                           (1 << 12)
 #define GPR_GPR1_ENET1_CLK_SEL                                  (1 << 13)
 #define GPR_GPR1_USB_EXP_MODE_EN                                (1 << 15)
-#define GPR_GPR1_ENET1_TX_CLK_OUT_EN                            (1 << 17)
+#define GPR_GPR1_ENET1_TX_DIR_OUT                               (1 << 17)
 #define GPR_GPR1_SAI1_MCLK_DIR_IN                               (0 << 19)
 #define GPR_GPR1_SAI1_MCLK_DIR_OUT                              (1 << 19)
 #define GPR_GPR1_SAI2_MCLK_DIR_IN                               (0 << 20)
diff --git a/arch/arm/src/imxrt/imxrt_clockconfig.c b/arch/arm/src/imxrt/imxrt_clockconfig.c
index d415582d3a..10454a13d6 100644
--- a/arch/arm/src/imxrt/imxrt_clockconfig.c
+++ b/arch/arm/src/imxrt/imxrt_clockconfig.c
@@ -358,8 +358,8 @@ static void imxrt_pllsetup(void)
 
   /* Init ENET PLL6 */
 
-  reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ |
-        CCM_ANALOG_PLL_ENET_ENET1_125M_EN          |
+  reg = CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ |
+        CCM_ANALOG_PLL_ENET_ENABLE                 |
         CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN        |
         CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN;