Re: [I] [FEATURE] STM32H5 OTP word read/write (and eFuse driver) [nuttx]

["darrylring (via GitHub)" <gi...@apache.org>]

darrylring commented on issue #20188:
URL: https://github.com/apache/nuttx/issues/20188#issuecomment-5937385077

   Actually, there's some overlap with another feature I am working on, which is connecting the high-cycle flash region (EDATA) to an MTD driver. Both need to deal with the double ECC errors.
   
   There are three approaches to take here:
   
   1. Attach an NMI handler in `stm32h563xx_flash.c` that can share some state with the read functions to check what address is read accessed and act accordingly.
   2. Mask the flash double ECC error NMI before each read.
   3. Mask the flash double ECC error NMI at initialization.
   
   I'm leaning toward #2 as the least invasive option.
   
   Both also need to deal with the ICACHE issue: they must either be marked as non-cacheable with the MPU, or be read with the ICACHE disabled. The closest precedent I can find is that `stm32_get_uniqueid` disables the ICACHE before reading the unique ID (which is in the same region as the OTP).
   
   I'm looking for feedback. Maybe I'm overthinking this, but quietly eating up two MPU regions (if both features are enabled) seems less desirable than just toggling the ICACHE off before a read.


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