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Posted to commits@mynewt.apache.org by st...@apache.org on 2016/07/27 23:13:49 UTC
[20/51] [partial] incubator-mynewt-core git commit: add stm32 and
nordic sdks based on new structure
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/fstorage/fstorage_internal_defs.h
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diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/fstorage/fstorage_internal_defs.h b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/fstorage/fstorage_internal_defs.h
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+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#ifndef FSTORAGE_INTERNAL_DEFS_H__
+#define FSTORAGE_INTERNAL_DEFS_H__
+
+#include "nrf.h"
+
+
+#define FS_FLAG_INITIALIZED (1 << 0) // The module has been initialized.
+#define FS_FLAG_PROCESSING (1 << 1) // The module is processing flash operations.
+// The module is waiting for a flash operation initiated by another module to complete.
+#define FS_FLAG_FLASH_REQ_PENDING (1 << 2)
+
+#define FS_ERASED_WORD (0xFFFFFFFF)
+
+// Helper macros for section variables.
+#define FS_SECTION_VARS_GET(i) NRF_SECTION_VARS_GET((i), fs_config_t, fs_data)
+#define FS_SECTION_VARS_COUNT NRF_SECTION_VARS_COUNT(fs_config_t, fs_data)
+#define FS_SECTION_VARS_START_ADDR NRF_SECTION_VARS_START_ADDR(fs_data)
+#define FS_SECTION_VARS_END_ADDR NRF_SECTION_VARS_END_ADDR(fs_data)
+
+
+// Register the section 'fs_data'.
+//lint -save -e19
+NRF_SECTION_VARS_REGISTER_SECTION(fs_data);
+//lint -restore
+
+// Declare symbols into the 'fs_data' section.
+NRF_SECTION_VARS_REGISTER_SYMBOLS(fs_config_t, fs_data);
+//lint -esym(526,fs_dataBase)
+//lint -esym(526,fs_dataLimit)
+
+
+// fstorage op-codes.
+typedef enum
+{
+ FS_OP_NONE, // No operation.
+ FS_OP_STORE, // Store data.
+ FS_OP_ERASE // Erase one or more flash pages.
+} fs_op_code_t;
+
+
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ // anonymous unions are enabled by default.
+#endif
+
+// fstorage operation.
+// Encapsulates details of a flash operation to be executed by this module.
+typedef struct
+{
+ fs_config_t const * p_config; // Application-specific fstorage configuration.
+ fs_op_code_t op_code; // ID of the operation.
+ union
+ {
+ struct
+ {
+ uint32_t const * p_src; // Pointer to the data to be written to flash.
+ uint32_t const * p_dest; // Destination of the data in flash.
+ uint16_t length_words; // Length of the data to be written, in words.
+ uint16_t offset; // Write offset.
+ } store;
+ struct
+ {
+ uint16_t page;
+ uint16_t pages_erased;
+ uint16_t pages_to_erase;
+ } erase;
+ };
+} fs_op_t;
+
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ // leave anonymous unions enabled.
+#elif defined(__GNUC__)
+ // anonymous unions are enabled by default.
+#endif
+
+
+// Queue of requested operations.
+// This queue holds flash operations requested to the module.
+// The data to be written to flash must be kept in memory until the write operation
+// is completed, i.e., an event indicating completion is received.
+typedef struct
+{
+ fs_op_t op[FS_QUEUE_SIZE]; // Queue elements.
+ uint32_t rp; // Index of the operation being processed.
+ uint32_t count; // Number of elements in the queue.
+} fs_op_queue_t;
+
+
+// Size of a flash page in bytes.
+#if defined (NRF51)
+ #define FS_PAGE_SIZE (1024)
+#elif defined (NRF52)
+ #define FS_PAGE_SIZE (4096)
+#endif
+
+
+// Size of a flash page in words.
+#define FS_PAGE_SIZE_WORDS (FS_PAGE_SIZE / sizeof(uint32_t))
+
+
+// Function to obtain the end of the flash space available to fstorage.
+static uint32_t const * fs_flash_page_end_addr()
+{
+ uint32_t const bootloader_addr = NRF_UICR->NRFFW[0];
+
+ return (uint32_t*)((bootloader_addr != FS_ERASED_WORD) ? bootloader_addr :
+ NRF_FICR->CODESIZE * FS_PAGE_SIZE);
+}
+
+
+// Macro to obtain the address of the last page.
+// If there is a bootloader present the bootloader address read from UICR
+// will act as the page beyond the end of the available flash storage.
+#define FS_PAGE_END_ADDR (fs_flash_page_end_addr())
+
+
+#endif //__FSTORAGE_INTERNAL_DEFS_H
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/fstorage/fstorage_nosd.c
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diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/fstorage/fstorage_nosd.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/fstorage/fstorage_nosd.c
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http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote.c
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diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote.c
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+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote.c
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+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#include "app_gpiote.h"
+#include "nrf_drv_gpiote.h"
+#include "sdk_common.h"
+
+
+/**@brief GPIOTE user type. */
+typedef struct
+{
+ uint32_t pins_mask; /**< Mask defining which pins user wants to monitor. */
+ uint32_t pins_low_to_high_mask; /**< Mask defining which pins will generate events to this user when toggling low->high. */
+ uint32_t pins_high_to_low_mask; /**< Mask defining which pins will generate events to this user when toggling high->low. */
+ uint32_t sense_high_pins; /**< Mask defining which pins are configured to generate GPIOTE interrupt on transition to high level. */
+ app_gpiote_event_handler_t event_handler; /**< Pointer to function to be executed when an event occurs. */
+ bool enabled; /**< Flag indicating whether user is enabled. */
+} gpiote_user_t;
+
+STATIC_ASSERT(sizeof(gpiote_user_t) <= GPIOTE_USER_NODE_SIZE);
+STATIC_ASSERT(sizeof(gpiote_user_t) % 4 == 0);
+
+static uint8_t m_user_array_size; /**< Size of user array. */
+static uint8_t m_user_count; /**< Number of registered users. */
+static gpiote_user_t * mp_users = NULL; /**< Array of GPIOTE users. */
+static uint32_t m_pins; /**< Mask of initialized pins. */
+static uint32_t m_last_pins_state; /**< Most recent state of pins. */
+
+#define MODULE_INITIALIZED (mp_users != NULL)
+#include "sdk_macros.h"
+
+void gpiote_handler(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action)
+{
+ int i;
+ uint32_t pin_mask = 1 << pin;
+ bool hitolo = (m_last_pins_state & pin_mask) ? true : false;
+ m_last_pins_state = nrf_gpio_pins_read();
+
+ for (i = 0; i < m_user_count; i++)
+ {
+ if (mp_users[i].enabled && (pin_mask & mp_users[i].pins_mask))
+ {
+ if ((pin_mask & mp_users[i].pins_high_to_low_mask) && hitolo)
+ {
+ mp_users[i].event_handler(0,pin_mask);
+ }
+ else if ((pin_mask & mp_users[i].pins_low_to_high_mask) && !hitolo)
+ {
+ mp_users[i].event_handler(pin_mask,0);
+ }
+ }
+ }
+}
+
+uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer)
+{
+ uint32_t ret_code = NRF_SUCCESS;
+
+ if (p_buffer == NULL)
+ {
+ return NRF_ERROR_INVALID_PARAM;
+ }
+
+ // Check that buffer is correctly aligned.
+ if (!is_word_aligned(p_buffer))
+ {
+ return NRF_ERROR_INVALID_PARAM;
+ }
+
+ // Initialize file globals.
+ mp_users = (gpiote_user_t *)p_buffer;
+ m_user_array_size = max_users;
+ m_user_count = 0;
+ m_pins = 0;
+
+ memset(mp_users, 0, m_user_array_size * sizeof(gpiote_user_t));
+
+ if (nrf_drv_gpiote_is_init()==false)
+ {
+ ret_code = nrf_drv_gpiote_init();
+ }
+
+ return ret_code;
+}
+
+uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id,
+ uint32_t pins_low_to_high_mask,
+ uint32_t pins_high_to_low_mask,
+ app_gpiote_event_handler_t event_handler)
+{
+ uint32_t user_pin_mask;
+ uint32_t ret_val = NRF_SUCCESS;
+
+ // Check state and parameters.
+ VERIFY_MODULE_INITIALIZED();
+
+ if (event_handler == NULL)
+ {
+ return NRF_ERROR_INVALID_PARAM;
+ }
+ if (m_user_count >= m_user_array_size)
+ {
+ return NRF_ERROR_NO_MEM;
+ }
+
+ user_pin_mask = pins_low_to_high_mask | pins_high_to_low_mask;
+ // Allocate new user.
+ mp_users[m_user_count].pins_mask = user_pin_mask;
+ mp_users[m_user_count].pins_low_to_high_mask = pins_low_to_high_mask;
+ mp_users[m_user_count].pins_high_to_low_mask = pins_high_to_low_mask;
+ mp_users[m_user_count].event_handler = event_handler;
+ mp_users[m_user_count].enabled = false;
+
+ *p_user_id = m_user_count++;
+
+ uint32_t mask = 1;
+ uint32_t i;
+ const nrf_drv_gpiote_in_config_t config = GPIOTE_CONFIG_IN_SENSE_TOGGLE(false);
+ for (i = 0; i < 32; i++)
+ {
+ if ((mask & user_pin_mask) & ~m_pins)
+ {
+ ret_val = nrf_drv_gpiote_in_init(i, &config, gpiote_handler);
+ VERIFY_SUCCESS(ret_val);
+ m_pins |= mask;
+ }
+ mask <<= 1;
+ }
+ return ret_val;
+}
+
+__STATIC_INLINE uint32_t error_check(app_gpiote_user_id_t user_id)
+{
+ // Check state and parameters.
+ VERIFY_MODULE_INITIALIZED();
+
+ if (user_id >= m_user_count)
+ {
+ return NRF_ERROR_INVALID_PARAM;
+ }
+ return NRF_SUCCESS;
+}
+/**
+ * @brief Function for enabling event on pin (if not yet enabled) or disabling the event if no other
+ * user requires it.
+ *
+ * @param pin Pin to enable
+ * @param enable If true function will attempt to enable the pin else it will attempt to disable it.
+ */
+static void pin_event_enable(uint32_t pin, bool enable)
+{
+ uint32_t i;
+ uint32_t pin_mask = 1UL << pin;
+ bool enabled = false;
+ //search if any user already enabled given pin
+ for (i = 0; i < m_user_count; i++)
+ {
+ if (mp_users[i].enabled && (mp_users[i].pins_mask & pin_mask))
+ {
+ enabled = true;
+ break;
+ }
+ }
+ if (!enabled)
+ {
+ if (enable)
+ {
+ m_last_pins_state = nrf_gpio_pins_read();
+ nrf_drv_gpiote_in_event_enable(pin, true);
+ }
+ else
+ {
+ nrf_drv_gpiote_in_event_disable(pin);
+ }
+ }
+}
+
+/**
+ * @brief Function for enabling or disabling events for pins used by the user.
+ *
+ * Function will enable pin events only if they are not yet enabled. Function will disable pin
+ * events only if there is no other enabled user that is using them.
+ *
+ * @param user_id User id.
+ * @param enable If true function will attempt to enable the pin else it will attempt to disable it.
+ */
+static uint32_t user_enable(app_gpiote_user_id_t user_id, bool enable)
+{
+ uint32_t ret_code = error_check(user_id);
+
+ if (ret_code == NRF_SUCCESS)
+ {
+ uint32_t i;
+ uint32_t mask = 1UL;
+ for (i = 0; i < 32; i++)
+ {
+ if (mp_users[user_id].pins_mask & mask)
+ {
+ pin_event_enable(i, enable);
+ }
+ mask <<= 1;
+ }
+ }
+ return ret_code;
+}
+
+uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id)
+{
+ uint32_t ret_code = NRF_SUCCESS;
+
+ if (mp_users[user_id].enabled == false)
+ {
+ ret_code = user_enable(user_id, true);
+ VERIFY_SUCCESS(ret_code);
+
+ mp_users[user_id].enabled = true;
+ return ret_code;
+ }
+ else
+ {
+ return ret_code;
+ }
+}
+
+uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id)
+{
+ uint32_t ret_code = NRF_SUCCESS;
+
+ if (mp_users[user_id].enabled)
+ {
+ mp_users[user_id].enabled = false;
+ ret_code = user_enable(user_id, false);
+ }
+
+ return ret_code;
+}
+
+uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins)
+{
+ gpiote_user_t * p_user;
+ uint32_t ret_code = error_check(user_id);
+
+ if (ret_code == NRF_SUCCESS)
+ {
+ p_user = &mp_users[user_id];
+ // Get pins.
+ *p_pins = nrf_gpio_pins_read() & p_user->pins_mask;
+
+ }
+ return ret_code;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote.h
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diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote.h b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote.h
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+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_gpiote GPIOTE Handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief GPIOTE handler module.
+ *
+ * @details The GPIOTE handler allows several modules ("users") to share the GPIOTE interrupt,
+ * each user defining a set of pins able to generate events to the user.
+ * When a GPIOTE interrupt occurs, the GPIOTE interrupt handler will call the event handler
+ * of each user for which at least one of the pins generated an event.
+ *
+ * The GPIOTE users are responsible for configuring all their corresponding pins, except
+ * the SENSE field, which should be initialized to GPIO_PIN_CNF_SENSE_Disabled.
+ * The SENSE field will be updated by the GPIOTE module when it is enabled or disabled,
+ * and also while it is enabled.
+ *
+ * The module specifies on which pins events should be generated if the pin(s) goes
+ * from low->high or high->low or both directions.
+ *
+ * @note Even if the application is using the @ref app_scheduler, the GPIOTE event handlers will
+ * be called directly from the GPIOTE interrupt handler.
+ *
+ * @warning If multiple users registers for the same pins the behavior for those pins are undefined.
+ */
+
+#ifndef APP_GPIOTE_H__
+#define APP_GPIOTE_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "app_error.h"
+#include "app_util.h"
+
+#define GPIOTE_USER_NODE_SIZE 24 /**< Size of app_gpiote.gpiote_user_t (only for use inside APP_GPIOTE_BUF_SIZE()). */
+#define NO_OF_PINS 32 /**< Number of GPIO pins on the \nRFXX chip. */
+
+/**@brief Compute number of bytes required to hold the GPIOTE data structures.
+ *
+ * @param[in] MAX_USERS Maximum number of GPIOTE users.
+ *
+ * @retval Required buffer size (in bytes).
+ */
+#define APP_GPIOTE_BUF_SIZE(MAX_USERS) ((MAX_USERS) * GPIOTE_USER_NODE_SIZE)
+
+typedef uint8_t app_gpiote_user_id_t;
+
+/**@brief GPIOTE event handler type. */
+typedef void (*app_gpiote_event_handler_t)(uint32_t event_pins_low_to_high,
+ uint32_t event_pins_high_to_low);
+
+/**@brief GPIOTE input event handler type. */
+typedef void (*app_gpiote_input_event_handler_t)(void);
+
+/**@brief Macro for initializing the GPIOTE module.
+ *
+ * @details It will handle dimensioning and allocation of the memory buffer required by the module,
+ * making sure that the buffer is correctly aligned.
+ *
+ * @param[in] MAX_USERS Maximum number of GPIOTE users.
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+/*lint -emacro(506, APP_GPIOTE_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_GPIOTE_INIT(MAX_USERS) \
+ do \
+ { \
+ static uint32_t app_gpiote_buf[CEIL_DIV(APP_GPIOTE_BUF_SIZE(MAX_USERS), sizeof(uint32_t))];\
+ uint32_t ERR_CODE = app_gpiote_init((MAX_USERS), app_gpiote_buf); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the GPIOTE module.
+ *
+ * @note Normally initialization should be done using the APP_GPIOTE_INIT() macro, as that will
+ * allocate the buffer needed by the GPIOTE module (including aligning the buffer correctly).
+ *
+ * @param[in] max_users Maximum number of GPIOTE users.
+ * @param[in] p_buffer Pointer to memory buffer for internal use in the app_gpiote
+ * module. The size of the buffer can be computed using the
+ * APP_GPIOTE_BUF_SIZE() macro. The buffer must be aligned to
+ * a 4 byte boundary.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary).
+ */
+uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer);
+
+/**@brief Function for registering a GPIOTE user.
+ *
+ * @param[out] p_user_id Id for the new GPIOTE user.
+ * @param[in] pins_low_to_high_mask Mask defining which pins will generate events to this user
+ * when state is changed from low->high.
+ * @param[in] pins_high_to_low_mask Mask defining which pins will generate events to this user
+ * when state is changed from high->low.
+ * @param[in] event_handler Pointer to function to be executed when an event occurs.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte boundary).
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ * @retval NRF_ERROR_NO_MEM Returned if the application tries to register more users
+ * than defined when the GPIOTE module was initialized in
+ * @ref app_gpiote_init.
+ */
+uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id,
+ uint32_t pins_low_to_high_mask,
+ uint32_t pins_high_to_low_mask,
+ app_gpiote_event_handler_t event_handler);
+
+/**@brief Function for informing the GPIOTE module that the specified user wants to use the GPIOTE module.
+ *
+ * @param[in] user_id Id of user to enable.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id);
+
+/**@brief Function for informing the GPIOTE module that the specified user is done using the GPIOTE module.
+ *
+ * @param[in] user_id Id of user to enable.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id);
+
+/**@brief Function for getting the state of the pins which are registered for the specified user.
+ *
+ * @param[in] user_id Id of user to check.
+ * @param[out] p_pins Bit mask corresponding to the pins configured to generate events to
+ * the specified user. All bits corresponding to pins in the state
+ * 'high' will have value '1', all others will have value '0'.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins);
+
+/**@brief Function for registering event handlers for GPIOTE IN events.
+ *
+ * @param[in] channel GPIOTE channel [0..3].
+ * @param[in] pin Pins associated with GPIOTE channel. Changes on following pins will generate events.
+ * @param[in] polarity Specify operation on input that shall trigger IN event.
+ * @param[in] event_handler Event handler invoked on the IN event in the GPIOTE interrupt.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid channel or pin number.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_input_event_handler_register(const uint8_t channel,
+ const uint32_t pin,
+ const uint32_t polarity,
+ app_gpiote_input_event_handler_t event_handler);
+
+/**@brief Function for unregistering event handlers for GPIOTE IN events.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_input_event_handler_unregister(const uint8_t channel);
+
+/**@brief Function for registering event handler invoked at the end of a GPIOTE interrupt.
+ *
+ * @param[in] event_handler Event handler invoked at the end of the GPIOTE interrupt.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_end_irq_event_handler_register(app_gpiote_input_event_handler_t event_handler);
+
+/**@brief Function for unregistering event handler invoked at the end of a GPIOTE interrupt.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_end_irq_event_handler_unregister(void);
+
+/**@brief Function for enabling interrupts in the GPIOTE driver.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support.
+ */
+uint32_t app_gpiote_enable_interrupts(void);
+
+/**@brief Function for disabling interrupts in the GPIOTE driver.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support.
+ */
+uint32_t app_gpiote_disable_interrupts(void);
+
+
+#endif // APP_GPIOTE_H__
+
+/** @} */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote_fast_detect.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote_fast_detect.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote_fast_detect.c
new file mode 100644
index 0000000..88b3dc2
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/gpiote/app_gpiote_fast_detect.c
@@ -0,0 +1,527 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#include "app_gpiote.h"
+#include <stdlib.h>
+#include "app_util_platform.h"
+#include "nrf_gpio.h"
+#include "sdk_common.h"
+
+#define NRF51_GPIOTE_CHANNEL 4
+#define NRF51_PINS 31
+
+#ifdef NRF51
+#define SWI_IRQHandler SWI1_IRQHandler
+#define SWI_IRQn SWI1_IRQn
+#elif defined NRF52
+#define SWI_IRQHandler SWI1_EGU1_IRQHAndler
+#define SWI_IRQn SWI1_EGU1_IRQn
+#endif
+
+/**@brief GPIOTE user type. */
+typedef struct
+{
+ uint32_t pins_mask; /**< Mask defining which pins user wants to monitor. */
+ uint32_t pins_low_to_high_mask; /**< Mask defining which pins will generate events to this user when toggling low->high. */
+ uint32_t pins_high_to_low_mask; /**< Mask defining which pins will generate events to this user when toggling high->low. */
+ uint32_t sense_high_pins; /**< Mask defining which pins are configured to generate GPIOTE interrupt on transition to high level. */
+ app_gpiote_event_handler_t event_handler; /**< Pointer to function to be executed when an event occurs. */
+} gpiote_user_t;
+
+STATIC_ASSERT(sizeof (gpiote_user_t) <= GPIOTE_USER_NODE_SIZE);
+STATIC_ASSERT(sizeof (gpiote_user_t) % 4 == 0);
+
+static uint32_t m_enabled_users_mask; /**< Mask for tracking which users are enabled. */
+static uint8_t m_user_array_size; /**< Size of user array. */
+static uint8_t m_user_count; /**< Number of registered users. */
+static gpiote_user_t * mp_users = NULL; /**< Array of GPIOTE users. */
+
+#define MODULE_INITIALIZED (mp_users != NULL)
+#include "sdk_macros.h"
+
+static app_gpiote_input_event_handler_t m_app_gpiote_input_event_handlers[4] = {0};
+
+static app_gpiote_input_event_handler_t m_app_gpiote_end_irq_event_handler = NULL;
+
+/**@brief Function for toggling sense level for specified pins.
+ *
+ * @param[in] p_user Pointer to user structure.
+ * @param[in] pins Bitmask specifying for which pins the sense level is to be toggled.
+ */
+static void sense_level_toggle(gpiote_user_t * p_user, uint32_t pins)
+{
+ uint32_t pin_no;
+
+ for (pin_no = 0; pin_no < NO_OF_PINS; pin_no++)
+ {
+ uint32_t pin_mask = (1 << pin_no);
+
+ if ((pins & pin_mask) != 0)
+ {
+ uint32_t sense;
+
+ //Invert sensing.
+ if ((p_user->sense_high_pins & pin_mask) == 0)
+ {
+ sense = GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos;
+ p_user->sense_high_pins |= pin_mask;
+ }
+ else
+ {
+ sense = GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos;
+ p_user->sense_high_pins &= ~pin_mask;
+ }
+
+ NRF_GPIO->PIN_CNF[pin_no] &= ~GPIO_PIN_CNF_SENSE_Msk;
+ NRF_GPIO->PIN_CNF[pin_no] |= sense;
+ }
+ }
+}
+
+
+/**@brief Function for handling the GPIOTE interrupt.
+ */
+void GPIOTE_IRQHandler(void)
+{
+ bool gpiote_in_evt = false;
+ bool gpiote_port_evt = false;
+
+ if ((NRF_GPIOTE->EVENTS_IN[0] == 1) && (NRF_GPIOTE->INTENSET & GPIOTE_INTENSET_IN0_Msk))
+ {
+ NRF_GPIOTE->EVENTS_IN[0] = 0;
+ gpiote_in_evt = true;
+
+ if (m_app_gpiote_input_event_handlers[0])
+ {
+ m_app_gpiote_input_event_handlers[0]();
+ }
+ }
+
+ if ((NRF_GPIOTE->EVENTS_IN[1] == 1) && (NRF_GPIOTE->INTENSET & GPIOTE_INTENSET_IN1_Msk))
+ {
+ NRF_GPIOTE->EVENTS_IN[1] = 0;
+ gpiote_in_evt = true;
+
+ if (m_app_gpiote_input_event_handlers[1])
+ {
+ m_app_gpiote_input_event_handlers[1]();
+ }
+ }
+
+ if ((NRF_GPIOTE->EVENTS_IN[2] == 1) && (NRF_GPIOTE->INTENSET & GPIOTE_INTENSET_IN2_Msk))
+ {
+ NRF_GPIOTE->EVENTS_IN[2] = 0;
+ gpiote_in_evt = true;
+
+ if (m_app_gpiote_input_event_handlers[2])
+ {
+ m_app_gpiote_input_event_handlers[2]();
+ }
+ }
+
+ if ((NRF_GPIOTE->EVENTS_IN[3] == 1) && (NRF_GPIOTE->INTENSET & GPIOTE_INTENSET_IN3_Msk))
+ {
+ NRF_GPIOTE->EVENTS_IN[3] = 0;
+ gpiote_in_evt = true;
+
+ if (m_app_gpiote_input_event_handlers[3])
+ {
+ m_app_gpiote_input_event_handlers[3]();
+ }
+ }
+
+ if ((NRF_GPIOTE->EVENTS_PORT == 1) && (NRF_GPIOTE->INTENSET & GPIOTE_INTENSET_PORT_Msk))
+ {
+ //Clear event.
+ NRF_GPIOTE->EVENTS_PORT = 0;
+
+ gpiote_port_evt = true;
+ }
+
+ if (m_app_gpiote_end_irq_event_handler && gpiote_in_evt)
+ {
+ m_app_gpiote_end_irq_event_handler();
+ }
+
+ if (gpiote_port_evt)
+ {
+ NVIC_SetPendingIRQ(SWI_IRQn);
+ }
+}
+
+
+/**@brief Function for handling the SWI1 interrupt.
+ */
+void SWI_IRQHandler(void)
+{
+ uint8_t i;
+ uint32_t pins_changed;
+ uint32_t pins_state = NRF_GPIO->IN;
+
+ //Check all users.
+ for (i = 0; i < m_user_count; i++)
+ {
+ gpiote_user_t * p_user = &mp_users[i];
+
+ //Check if user is enabled.
+ if (((1 << i) & m_enabled_users_mask) != 0)
+ {
+ uint32_t transition_pins;
+ uint32_t event_low_to_high;
+ uint32_t event_high_to_low;
+
+ //Find set of pins on which there has been a transition.
+ transition_pins = (pins_state ^ ~p_user->sense_high_pins) & p_user->pins_mask;
+
+ //Toggle SENSE level for all pins that have changed state.
+ sense_level_toggle(p_user, transition_pins);
+
+ //Second read after setting sense.
+ //Check if any pins have changed while serving this interrupt.
+ pins_changed = NRF_GPIO->IN ^ pins_state;
+
+ if (pins_changed)
+ {
+ //Transition pins detected in late stage.
+ uint32_t late_transition_pins;
+
+ pins_state |= pins_changed;
+
+ //Find set of pins on which there has been a transition.
+ late_transition_pins = (pins_state ^ ~p_user->sense_high_pins) & p_user->pins_mask;
+
+ //Toggle SENSE level for all pins that have changed state in last phase.
+ sense_level_toggle(p_user, late_transition_pins);
+
+ //Update pins that has changed state since the interrupt occurred.
+ transition_pins |= late_transition_pins;
+ }
+
+ //Call user event handler if an event has occurred.
+ event_high_to_low = (~pins_state & p_user->pins_high_to_low_mask) & transition_pins;
+ event_low_to_high = (pins_state & p_user->pins_low_to_high_mask) & transition_pins;
+
+ if ((event_low_to_high | event_high_to_low) != 0)
+ {
+ p_user->event_handler(event_low_to_high, event_high_to_low);
+ }
+ }
+ }
+}
+
+
+/**@brief Function for enabling interrupt SWI1.
+ */
+static void app_gpiote_swi1_enable_irq(void)
+{
+ NVIC_ClearPendingIRQ(SWI_IRQn);
+ NVIC_SetPriority(SWI_IRQn, APP_IRQ_PRIORITY_LOW);
+ NVIC_EnableIRQ(SWI_IRQn);
+}
+
+/**@brief Function for disabling interrupt SWI1.
+ */
+static void app_gpiote_swi1_disable_irq(void)
+{
+ NVIC_DisableIRQ(SWI_IRQn);
+}
+
+/**@brief Function for sense disabling for all pins for specified user.
+ *
+ * @param[in] user_id User id.
+ */
+static void pins_sense_disable(app_gpiote_user_id_t user_id)
+{
+ uint32_t pin_no;
+
+ for (pin_no = 0; pin_no < 32; pin_no++)
+ {
+ if ((mp_users[user_id].pins_mask & (1 << pin_no)) != 0)
+ {
+ NRF_GPIO->PIN_CNF[pin_no] &= ~GPIO_PIN_CNF_SENSE_Msk;
+ NRF_GPIO->PIN_CNF[pin_no] |= GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos;
+ }
+ }
+}
+
+
+uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer)
+{
+ if (p_buffer == NULL)
+ {
+ return NRF_ERROR_INVALID_PARAM;
+ }
+
+ //Check that buffer is correctly aligned.
+ if (!is_word_aligned(p_buffer))
+ {
+ return NRF_ERROR_INVALID_PARAM;
+ }
+
+ //Initialize file globals.
+ mp_users = (gpiote_user_t *)p_buffer;
+ m_user_array_size = max_users;
+ m_user_count = 0;
+ m_enabled_users_mask = 0;
+
+ memset(mp_users, 0, m_user_array_size * sizeof (gpiote_user_t));
+
+ (void)app_gpiote_enable_interrupts();
+
+ return NRF_SUCCESS;
+}
+
+uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id,
+ uint32_t pins_low_to_high_mask,
+ uint32_t pins_high_to_low_mask,
+ app_gpiote_event_handler_t event_handler)
+{
+ //Check state and parameters.
+ VERIFY_MODULE_INITIALIZED();
+
+ if (event_handler == NULL)
+ {
+ return NRF_ERROR_INVALID_PARAM;
+ }
+
+ if (m_user_count >= m_user_array_size)
+ {
+ return NRF_ERROR_NO_MEM;
+ }
+
+ //Allocate new user.
+ mp_users[m_user_count].pins_mask = pins_low_to_high_mask | pins_high_to_low_mask;
+ mp_users[m_user_count].pins_low_to_high_mask = pins_low_to_high_mask;
+ mp_users[m_user_count].pins_high_to_low_mask = pins_high_to_low_mask;
+ mp_users[m_user_count].event_handler = event_handler;
+
+ *p_user_id = m_user_count++;
+
+ //Make sure SENSE is disabled for all pins.
+ pins_sense_disable(*p_user_id);
+
+ return NRF_SUCCESS;
+}
+
+uint32_t app_gpiote_enable_interrupts(void)
+{
+ NVIC_ClearPendingIRQ(GPIOTE_IRQn);
+ NVIC_SetPriority(GPIOTE_IRQn, APP_IRQ_PRIORITY_HIGH);
+ NVIC_EnableIRQ(GPIOTE_IRQn);
+
+ //Enable interrupt SWI1.
+ app_gpiote_swi1_enable_irq();
+
+ return NRF_SUCCESS;
+}
+
+uint32_t app_gpiote_disable_interrupts(void)
+{
+ NVIC_DisableIRQ(GPIOTE_IRQn);
+
+ //Disable interrupt SWI1.
+ app_gpiote_swi1_disable_irq();
+
+ return NRF_SUCCESS;
+}
+
+uint32_t app_gpiote_input_event_handler_register(const uint8_t channel,
+ const uint32_t pin,
+ const uint32_t polarity,
+ app_gpiote_input_event_handler_t event_handler)
+{
+ if (channel < NRF51_GPIOTE_CHANNEL && pin < NRF51_PINS)
+ {
+ NRF_GPIOTE->CONFIG[channel] = (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) |
+ (pin << GPIOTE_CONFIG_PSEL_Pos) |
+ (polarity << GPIOTE_CONFIG_POLARITY_Pos);
+
+ switch (channel)
+ {
+ case 0:
+ NRF_GPIOTE->INTENSET |= (GPIOTE_INTENSET_IN0_Enabled << GPIOTE_INTENSET_IN0_Pos);
+ break;
+
+ case 1:
+ NRF_GPIOTE->INTENSET |= (GPIOTE_INTENSET_IN1_Enabled << GPIOTE_INTENSET_IN1_Pos);
+ break;
+
+ case 2:
+ NRF_GPIOTE->INTENSET |= (GPIOTE_INTENSET_IN2_Enabled << GPIOTE_INTENSET_IN2_Pos);
+ break;
+
+ case 3:
+ NRF_GPIOTE->INTENSET |= (GPIOTE_INTENSET_IN3_Enabled << GPIOTE_INTENSET_IN3_Pos);
+ break;
+
+ default:
+ break;
+ }
+
+ m_app_gpiote_input_event_handlers[channel] = event_handler;
+
+ return NRF_SUCCESS;
+ }
+
+ return NRF_ERROR_INVALID_PARAM;
+}
+
+uint32_t app_gpiote_input_event_handler_unregister(const uint8_t channel)
+{
+ if (channel < NRF51_GPIOTE_CHANNEL)
+ {
+ const uint32_t pin_not_connected = 31UL;
+
+ NRF_GPIOTE->CONFIG[channel] = (GPIOTE_CONFIG_MODE_Disabled << GPIOTE_CONFIG_MODE_Pos) |
+ (pin_not_connected << GPIOTE_CONFIG_PSEL_Pos) |
+ (GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
+
+ switch (channel)
+ {
+ case 0:
+ NRF_GPIOTE->INTENSET |= (GPIOTE_INTENSET_IN0_Disabled << GPIOTE_INTENSET_IN0_Pos);
+ break;
+
+ case 1:
+ NRF_GPIOTE->INTENSET |= (GPIOTE_INTENSET_IN1_Disabled << GPIOTE_INTENSET_IN1_Pos);
+ break;
+
+ case 2:
+ NRF_GPIOTE->INTENSET |= (GPIOTE_INTENSET_IN2_Disabled << GPIOTE_INTENSET_IN2_Pos);
+ break;
+
+ case 3:
+ NRF_GPIOTE->INTENSET |= (GPIOTE_INTENSET_IN3_Disabled << GPIOTE_INTENSET_IN3_Pos);
+ break;
+
+ default:
+ break;
+ }
+
+ m_app_gpiote_input_event_handlers[channel] = NULL;
+
+ return NRF_SUCCESS;
+ }
+
+ return NRF_ERROR_INVALID_PARAM;
+}
+
+uint32_t app_gpiote_end_irq_event_handler_register(app_gpiote_input_event_handler_t event_handler)
+{
+ m_app_gpiote_end_irq_event_handler = event_handler;
+ return NRF_SUCCESS;
+}
+
+uint32_t app_gpiote_end_irq_event_handler_unregister(void)
+{
+ m_app_gpiote_end_irq_event_handler = NULL;
+ return NRF_SUCCESS;
+}
+
+uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id)
+{
+ uint32_t pin_no;
+ uint32_t pins_state;
+
+ //Check state and parameters.
+ VERIFY_MODULE_INITIALIZED();
+
+ if (user_id >= m_user_count)
+ {
+ return NRF_ERROR_INVALID_PARAM;
+ }
+
+ //Clear any pending event.
+ NRF_GPIOTE->EVENTS_PORT = 0;
+ pins_state = NRF_GPIO->IN;
+
+ //Enable user.
+ if (m_enabled_users_mask == 0)
+ {
+ NRF_GPIOTE->INTENSET = GPIOTE_INTENSET_PORT_Msk;
+ }
+ m_enabled_users_mask |= (1 << user_id);
+
+ //Enable sensing for all pins for specified user.
+ mp_users[user_id].sense_high_pins = 0;
+
+ for (pin_no = 0; pin_no < 32; pin_no++)
+ {
+ uint32_t pin_mask = (1 << pin_no);
+
+ if ((mp_users[user_id].pins_mask & pin_mask) != 0)
+ {
+ uint32_t sense;
+
+ if ((pins_state & pin_mask) != 0)
+ {
+ sense = GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos;
+ }
+ else
+ {
+ sense = GPIO_PIN_CNF_SENSE_High <<
+ GPIO_PIN_CNF_SENSE_Pos;
+ mp_users[user_id].sense_high_pins |= pin_mask;
+ }
+
+ NRF_GPIO->PIN_CNF[pin_no] &= ~GPIO_PIN_CNF_SENSE_Msk;
+ NRF_GPIO->PIN_CNF[pin_no] |= sense;
+ }
+ }
+
+ return NRF_SUCCESS;
+}
+
+
+uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id)
+{
+ //Check state and parameters.
+ VERIFY_MODULE_INITIALIZED();
+
+ if (user_id >= m_user_count)
+ {
+ return NRF_ERROR_INVALID_PARAM;
+ }
+
+ //Disable sensing for all pins for specified user.
+ pins_sense_disable(user_id);
+
+ //Disable user.
+ m_enabled_users_mask &= ~(1UL << user_id);
+
+ if (m_enabled_users_mask == 0)
+ {
+ NRF_GPIOTE->INTENCLR = GPIOTE_INTENSET_PORT_Msk;
+ }
+
+ return NRF_SUCCESS;
+}
+
+
+uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins)
+{
+ gpiote_user_t * p_user;
+
+ //Check state and parameters.
+ VERIFY_MODULE_INITIALIZED();
+
+ if (user_id >= m_user_count)
+ {
+ return NRF_ERROR_INVALID_PARAM;
+ }
+
+ //Get pins.
+ p_user = &mp_users[user_id];
+ *p_pins = NRF_GPIO->IN & p_user->pins_mask;
+
+ return NRF_SUCCESS;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault.h
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault.h b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault.h
new file mode 100644
index 0000000..3cb099a
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault.h
@@ -0,0 +1,60 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+#ifndef HARFAULT_H__
+#define HARFAULT_H__
+#include <stdint.h>
+#include <stddef.h>
+/**
+ * @defgroup hardfault_default HardFault exception
+ * @{
+ * @brief Default HardFault exception implementation.
+ * @ingroup app_common
+ */
+
+/**
+ * @brief Contents of the stack.
+ *
+ * This structure is used to re-create the stack layout after a HardFault exception was raised.
+ */
+typedef struct HardFault_stack
+{
+ uint32_t r0; ///< R0 register.
+ uint32_t r1; ///< R1 register.
+ uint32_t r2; ///< R2 register.
+ uint32_t r3; ///< R3 register.
+ uint32_t r12; ///< R12 register.
+ uint32_t lr; ///< Link register.
+ uint32_t pc; ///< Program counter.
+ uint32_t psr; ///< Program status register.
+}HardFault_stack_t;
+
+/**
+ * @brief Function for processing HardFault exceptions.
+ *
+ * An application that needs to process HardFault exceptions should provide an implementation of this function.
+ * It will be called from the HardFault handler.
+ * If no implementation is provided, the library uses a default one, which just restarts the MCU.
+ *
+ * @note If the DEBUG_NRF macro is defined, the software breakpoint is set just before the call
+ * to this function.
+ *
+ * @param p_stack Pointer to the stack bottom.
+ * This pointer might be NULL if the HardFault was called when the main stack was
+ * the active stack and a stack overrun is detected.
+ * In such a situation, the stack pointer is reinitialized to the default position,
+ * and the stack content is lost.
+ */
+void HardFault_process(HardFault_stack_t *p_stack);
+
+/** @} */
+#endif /* HARFAULT_H__ */
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault_implementation.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault_implementation.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault_implementation.c
new file mode 100644
index 0000000..0a5fee8
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/hardfault_implementation.c
@@ -0,0 +1,47 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+#include "hardfault.h"
+#include "nrf.h"
+#include "compiler_abstraction.h"
+#include "nordic_common.h"
+#ifdef SOFTDEVICE_PRESENT
+#include "nrf_soc.h"
+#endif
+
+#if defined(DEBUG_NRF)
+/**
+ * @brief Pointer to the last received stack pointer.
+ *
+ * This pointer is set in the debug version of the HardFault handler.
+ * It helps to debug HardFault reasons.
+ */
+volatile HardFault_stack_t *HardFault_p_stack;
+#endif
+
+/*lint -save -e14 */
+__WEAK void HardFault_process(HardFault_stack_t *p_stack)
+{
+ // Restart the system by default
+ NVIC_SystemReset();
+}
+/*lint -restore */
+
+void HardFault_c_handler( uint32_t *p_stack_address )
+{
+#if defined(DEBUG_NRF)
+ HardFault_p_stack = (HardFault_stack_t*)p_stack_address;
+ /* Generate breakpoint if debugger is connected */
+ __BKPT(0);
+#endif
+
+ HardFault_process((HardFault_stack_t*)p_stack_address);
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_gcc.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_gcc.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_gcc.c
new file mode 100644
index 0000000..e29b6c0
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_gcc.c
@@ -0,0 +1,52 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+#include <stdint.h>
+
+void HardFault_Handler(void) __attribute__(( naked ));
+
+void HardFault_Handler(void)
+{
+ __asm volatile(
+ " .syntax unified \n"
+
+ " ldr r0, =0xFFFFFFFD \n"
+ " cmp r0, lr \n"
+ " bne HardFault_Handler_ChooseMSP \n"
+ /* Reading PSP into R0 */
+ " mrs r0, PSP \n"
+ " b HardFault_Handler_Continue \n"
+ "HardFault_Handler_ChooseMSP: \n"
+ /* Reading MSP into R0 */
+ " mrs r0, MSP \n"
+ /* -----------------------------------------------------------------
+ * If we have selected MSP check if we may use stack safetly.
+ * If not - reset the stack to the initial value. */
+ " ldr r1, =__StackTop \n"
+ " ldr r2, =__StackLimit \n"
+
+ /* MSP is in the range of <__StackTop, __StackLimit) */
+ " cmp r0, r1 \n"
+ " bhi HardFault_MoveSP \n"
+ " cmp r0, r2 \n"
+ " bhi HardFault_Handler_Continue \n"
+ /* ----------------------------------------------------------------- */
+ "HardFault_MoveSP: \n"
+ " mov SP, r1 \n"
+ " movs r0, #0 \n"
+
+ "HardFault_Handler_Continue: \n"
+ " ldr r3, =HardFault_c_handler \n"
+ " bx r3 \n"
+
+ " .align \n"
+ );
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_iar.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_iar.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_iar.c
new file mode 100644
index 0000000..cfd341b
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_iar.c
@@ -0,0 +1,65 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+#include <stdint.h>
+
+#pragma section = "CSTACK"
+extern void HardFault_c_handler( uint32_t * );
+
+__stackless void HardFault_Handler(void);
+
+__stackless void HardFault_Handler(void)
+{
+ __asm volatile(
+ " ldr r0, 100f \n"
+ " cmp r0, lr \n"
+ " bne 1f \n"
+ /* Reading PSP into R0 */
+ " mrs r0, PSP \n"
+ " b 3f \n"
+ "1: \n"
+ /* Reading MSP into R0 */
+ " mrs r0, MSP \n"
+ /* -----------------------------------------------------------------
+ * If we have selected MSP check if we may use stack safetly.
+ * If not - reset the stack to the initial value. */
+ " ldr r1, 101f \n"
+ " ldr r2, 102f \n"
+
+ /* MSP is in the range of <__StackTop, __StackLimit) */
+ " cmp r0, r1 \n"
+ " bhi 2f \n"
+ " cmp r0, r2 \n"
+ " bhi 3f \n"
+ /* ----------------------------------------------------------------- */
+ "2: \n"
+ " mov SP, r1 \n"
+ " movs r0, #0 \n"
+
+ "3: \n"
+ " ldr r3, 103f \n"
+ " bx r3 \n"
+
+ "100: \n"
+ " DC32 0xFFFFFFFD \n"
+ "101: \n"
+ " DC32 %c0 \n"
+ "102: \n"
+ " DC32 %c1 \n"
+ "103: \n"
+ " DC32 %c2 \n"
+ : /* Outputs */
+ : /* Inputs */
+ "i"(__section_end("CSTACK")),
+ "i"(__section_begin("CSTACK")),
+ "i"(&HardFault_c_handler)
+ );
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_keil.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_keil.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_keil.c
new file mode 100644
index 0000000..2b88df9
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf51/handler/hardfault_handler_keil.c
@@ -0,0 +1,61 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+#include <stdint.h>
+
+//lint -save -e27 -e10 -e19 -e40
+extern char STACK$$Base;
+
+/* This variable should be static but then it cannot be used in assembly code below.
+ * The problem here is that the address of the section can be archived by $$ operator
+ * that is not allowed in assembly code. */
+char const * HardFault_Handler_stack_bottom = &STACK$$Base;
+//lint -restore
+
+__asm void HardFault_Handler(void)
+{
+ PRESERVE8
+ EXTERN HardFault_c_handler
+ EXTERN __initial_sp
+ EXTERN HardFault_Handler_stack_bottom
+
+ ldr r0, =0xFFFFFFFD
+ cmp r0, lr
+ bne HardFault_Handler_ChooseMSP
+ /* Reading PSP into R0 */
+ mrs r0, PSP
+ b HardFault_Handler_Continue
+HardFault_Handler_ChooseMSP
+ /* Reading MSP into R0 */
+ mrs r0, MSP
+ /* -----------------------------------------------------------------
+ * If we have selected MSP, check if we may use stack safely.
+ * If not - reset the stack to the initial value. */
+ ldr r1, =__initial_sp
+ ldr r2, =HardFault_Handler_stack_bottom
+ ldr r2, [r2]
+
+ /* MSP is in the range of <__StackTop, __StackLimit) */
+ cmp r0, r1
+ bhi HardFault_MoveSP
+ cmp r0, r2
+ bhi HardFault_Handler_Continue
+ /* ----------------------------------------------------------------- */
+HardFault_MoveSP
+ mov SP, r1
+ movs r0, #0
+
+HardFault_Handler_Continue
+ ldr r3, =HardFault_c_handler
+ bx r3
+
+ ALIGN
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_gcc.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_gcc.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_gcc.c
new file mode 100644
index 0000000..8d2bb99
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_gcc.c
@@ -0,0 +1,49 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+#include <stdint.h>
+
+void HardFault_Handler(void) __attribute__(( naked ));
+
+void HardFault_Handler(void)
+{
+ __asm volatile(
+ " ldr r3, =HardFault_c_handler \n"
+ " tst lr, #4 \n"
+
+ /* PSP is quite simple and does not require additional handler */
+ " itt ne \n"
+ " mrsne r0, psp \n"
+ /* Jump to the handler, do not store LR - returning from handler just exits exception */
+ " bxne r3 \n"
+
+ /* Processing MSP requires stack checking */
+ " mrs r0, msp \n"
+
+ " ldr r1, =__StackTop \n"
+ " ldr r2, =__StackLimit \n"
+
+ /* MSP is in the range of <__StackTop, __StackLimit) */
+ " cmp r0, r1 \n"
+ " bhi HardFault_MoveSP \n"
+ " cmp r0, r2 \n"
+ " bhi HardFault_Handler_Continue \n"
+
+ "HardFault_MoveSP: \n"
+ " mov sp, r1 \n"
+ " mov r0, #0 \n"
+
+ "HardFault_Handler_Continue: \n"
+ " bx r3 \n"
+
+ " .align \n"
+ );
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_iar.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_iar.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_iar.c
new file mode 100644
index 0000000..d390c4a
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_iar.c
@@ -0,0 +1,64 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+#include <stdint.h>
+
+#pragma section = "CSTACK"
+extern void HardFault_c_handler( uint32_t * );
+
+__stackless void HardFault_Handler(void);
+
+__stackless void HardFault_Handler(void)
+{
+ __asm volatile(
+ " ldr.n r3, 103f \n"
+ " tst lr, #4 \n"
+
+ /* PSP is quite simple and does not require additional handler */
+ " itt ne \n"
+ " mrsne r0, psp \n"
+ /* Jump to the handler, do not store LR - returning from handler just exits exception */
+ " bxne r3 \n"
+
+ /* Processing MSP requires stack checking */
+ " mrs r0, msp \n"
+
+ " ldr.n r1, 101f \n"
+ " ldr.n r2, 102f \n"
+
+ /* MSP is in the range of <__StackTop, __StackLimit) */
+ " cmp r0, r1 \n"
+ " bhi.n 1f \n"
+ " cmp r0, r2 \n"
+ " bhi.n 2f \n"
+
+ "1: \n"
+ " mov sp, r1 \n"
+ " mov r0, #0 \n"
+
+ "2: \n"
+ " bx r3 \n"
+ /* Data alignment if required */
+ " nop \n"
+
+ "101: \n"
+ " DC32 %c0 \n"
+ "102: \n"
+ " DC32 %c1 \n"
+ "103: \n"
+ " DC32 %c2 \n"
+ : /* Outputs */
+ : /* Inputs */
+ "i"(__section_end("CSTACK")),
+ "i"(__section_begin("CSTACK")),
+ "i"(&HardFault_c_handler)
+ );
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_keil.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_keil.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_keil.c
new file mode 100644
index 0000000..ad9642c
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hardfault/nrf52/handler/hardfault_handler_keil.c
@@ -0,0 +1,60 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+#include <stdint.h>
+
+//lint -save -e27 -e10 -e19 -e40
+extern char STACK$$Base;
+
+/* This variable should be static but then it cannot be used in assembly code below.
+ * The problem here is that the address of the section can be archived by $$ operator
+ * that is not allowed in assembly code. */
+char const * HardFault_Handler_stack_bottom = &STACK$$Base;
+//lint -restore
+
+__asm void HardFault_Handler(void)
+{
+ PRESERVE8
+ EXTERN HardFault_c_handler
+ EXTERN __initial_sp
+ EXTERN HardFault_Handler_stack_bottom
+
+ ldr r3, =HardFault_c_handler
+ tst lr, #4
+
+ /* PSP is quite simple and does not require additional handler */
+ itt ne
+ mrsne r0, psp
+ /* Jump to the handler, do not store LR - returning from handler just exits exception */
+ bxne r3
+
+ /* Processing MSP requires stack checking */
+ mrs r0, msp
+
+ ldr r1, =__initial_sp
+ ldr r2, =HardFault_Handler_stack_bottom
+ ldr r2, [r2]
+
+ /* MSP is in the range of <__StackTop, __StackLimit) */
+ cmp r0, r1
+ bhi HardFault_MoveSP
+ cmp r0, r2
+ bhi HardFault_Handler_Continue
+
+HardFault_MoveSP
+ mov sp, r1
+ mov r0, #0
+
+HardFault_Handler_Continue
+ bx r3
+
+ ALIGN
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/config/hci_mem_pool_internal.h
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/config/hci_mem_pool_internal.h b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/config/hci_mem_pool_internal.h
new file mode 100644
index 0000000..2027710
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/config/hci_mem_pool_internal.h
@@ -0,0 +1,32 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup memory_pool_internal Memory Pool Internal
+ * @{
+ * @ingroup memory_pool
+ *
+ * @brief Memory pool internal definitions
+ */
+
+#ifndef MEM_POOL_INTERNAL_H__
+#define MEM_POOL_INTERNAL_H__
+
+#define TX_BUF_SIZE 600u /**< TX buffer size in bytes. */
+#define RX_BUF_SIZE TX_BUF_SIZE /**< RX buffer size in bytes. */
+
+#define RX_BUF_QUEUE_SIZE 4u /**< RX buffer element size. */
+
+#endif // MEM_POOL_INTERNAL_H__
+
+/** @} */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/config/hci_transport_config.h
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/config/hci_transport_config.h b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/config/hci_transport_config.h
new file mode 100644
index 0000000..7684615
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/config/hci_transport_config.h
@@ -0,0 +1,40 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @brief Definition of HCI Transport Layer configurable parameters
+ */
+
+#ifndef HCI_TRANSPORT_CFG_H__
+#define HCI_TRANSPORT_CFG_H__
+
+/** This section covers configurable parameters for the HCI Transport SLIP layer. */
+#define HCI_SLIP_UART_RX_PIN_NUMBER 1 /**< Defines the UART RX pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_TX_PIN_NUMBER 2 /**< Defines the UART TX pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_RTS_PIN_NUMBER 3 /**< Defines the UART RTS pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_CTS_PIN_NUMBER 4 /**< Defines the UART CTS pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_MODE APP_UART_FLOW_CONTROL_ENABLED /**< Defines the UART mode to be used. Use UART Low Power with Flow Control - Valid values are defined in \ref app_uart_flow_control_t. For further information on the UART Low Power mode, please refer to: \ref app_uart . */
+
+#define HCI_SLIP_UART_BAUDRATE UART_BAUDRATE_BAUDRATE_Baud38400 /**< Defines the UART Baud rate. Default is 38400 baud. */
+
+/** This section covers configurable parameters for the HCI Transport layer that are used for calculating correct value for the retransmission timer timeout. */
+#define MAX_PACKET_SIZE_IN_BITS 8000u /**< Maximum size of a single application packet in bits. */
+#define USED_BAUD_RATE 38400u /**< The used uart baudrate. */
+
+#endif // HCI_TRANSPORT_CFG_H__
+
+/** @} */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.c
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diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.c
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+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#include "hci_mem_pool.h"
+#include "hci_mem_pool_internal.h"
+#include <stdbool.h>
+#include <stdio.h>
+
+/**@brief RX buffer element instance structure.
+ */
+typedef struct
+{
+ uint8_t rx_buffer[RX_BUF_SIZE]; /**< RX buffer memory array. */
+ uint32_t length; /**< Length of the RX buffer memory array. */
+} rx_buffer_elem_t;
+
+/**@brief RX buffer queue element instance structure.
+ */
+typedef struct
+{
+ rx_buffer_elem_t * p_buffer; /**< Pointer to RX buffer element. */
+ uint32_t free_window_count; /**< Free space element count. */
+ uint32_t free_available_count; /**< Free area element count. */
+ uint32_t read_available_count; /**< Read area element count. */
+ uint32_t write_index; /**< Write position index. */
+ uint32_t read_index; /**< Read position index. */
+ uint32_t free_index; /**< Free position index. */
+} rx_buffer_queue_t;
+
+static bool m_is_tx_allocated; /**< Boolean value to determine if the TX buffer is allocated. */
+static rx_buffer_elem_t m_rx_buffer_elem_queue[RX_BUF_QUEUE_SIZE]; /**< RX buffer element instances. */
+static rx_buffer_queue_t m_rx_buffer_queue; /**< RX buffer queue element instance. */
+
+
+uint32_t hci_mem_pool_open(void)
+{
+ m_is_tx_allocated = false;
+ m_rx_buffer_queue.p_buffer = m_rx_buffer_elem_queue;
+ m_rx_buffer_queue.free_window_count = RX_BUF_QUEUE_SIZE;
+ m_rx_buffer_queue.free_available_count = 0;
+ m_rx_buffer_queue.read_available_count = 0;
+ m_rx_buffer_queue.write_index = 0;
+ m_rx_buffer_queue.read_index = 0;
+ m_rx_buffer_queue.free_index = 0;
+
+ return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_close(void)
+{
+ return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer)
+{
+ static uint8_t tx_buffer[TX_BUF_SIZE];
+
+ uint32_t err_code;
+
+ if (pp_buffer == NULL)
+ {
+ return NRF_ERROR_NULL;
+ }
+
+ if (!m_is_tx_allocated)
+ {
+ m_is_tx_allocated = true;
+ *pp_buffer = tx_buffer;
+ err_code = NRF_SUCCESS;
+ }
+ else
+ {
+ err_code = NRF_ERROR_NO_MEM;
+ }
+
+ return err_code;
+}
+
+
+uint32_t hci_mem_pool_tx_free(void)
+{
+ m_is_tx_allocated = false;
+
+ return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer)
+{
+ uint32_t err_code;
+
+ if (pp_buffer == NULL)
+ {
+ return NRF_ERROR_NULL;
+ }
+ *pp_buffer = NULL;
+
+ if (m_rx_buffer_queue.free_window_count != 0)
+ {
+ if (length <= RX_BUF_SIZE)
+ {
+ --(m_rx_buffer_queue.free_window_count);
+ ++(m_rx_buffer_queue.read_available_count);
+
+ *pp_buffer =
+ m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.write_index].rx_buffer;
+
+ m_rx_buffer_queue.free_index |= (1u << m_rx_buffer_queue.write_index);
+
+ // @note: Adjust the write_index making use of the fact that the buffer size is of
+ // power of two and two's complement arithmetic. For details refer example to book
+ // "Making embedded systems: Elicia White".
+ m_rx_buffer_queue.write_index =
+ (m_rx_buffer_queue.write_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
+
+ err_code = NRF_SUCCESS;
+ }
+ else
+ {
+ err_code = NRF_ERROR_DATA_SIZE;
+ }
+ }
+ else
+ {
+ err_code = NRF_ERROR_NO_MEM;
+ }
+
+ return err_code;
+}
+
+
+uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer)
+{
+ uint32_t err_code;
+ uint32_t consume_index;
+ uint32_t start_index;
+
+ if (m_rx_buffer_queue.free_available_count != 0)
+ {
+ // Find the buffer that has been freed -
+ // Start at read_index minus free_available_count and then increment until read index.
+ err_code = NRF_ERROR_INVALID_ADDR;
+ consume_index = (m_rx_buffer_queue.read_index - m_rx_buffer_queue.free_available_count) &
+ (RX_BUF_QUEUE_SIZE - 1u);
+ start_index = consume_index;
+
+ do
+ {
+ if (m_rx_buffer_queue.p_buffer[consume_index].rx_buffer == p_buffer)
+ {
+ m_rx_buffer_queue.free_index ^= (1u << consume_index);
+ err_code = NRF_SUCCESS;
+ break;
+ }
+ else
+ {
+ consume_index = (consume_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
+ }
+ }
+ while (consume_index != m_rx_buffer_queue.read_index);
+
+ while (!(m_rx_buffer_queue.free_index & (1 << start_index)) &&
+ (m_rx_buffer_queue.free_available_count != 0))
+ {
+ --(m_rx_buffer_queue.free_available_count);
+ ++(m_rx_buffer_queue.free_window_count);
+ start_index = (consume_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
+ }
+ }
+ else
+ {
+ err_code = NRF_ERROR_NO_MEM;
+ }
+
+ return err_code;
+}
+
+
+uint32_t hci_mem_pool_rx_data_size_set(uint32_t length)
+{
+ // @note: Adjust the write_index making use of the fact that the buffer size is of power
+ // of two and two's complement arithmetic. For details refer example to book
+ // "Making embedded systems: Elicia White".
+ const uint32_t index = (m_rx_buffer_queue.write_index - 1u) & (RX_BUF_QUEUE_SIZE - 1u);
+ m_rx_buffer_queue.p_buffer[index].length = length;
+
+ return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length)
+{
+ uint32_t err_code;
+
+ if ((pp_buffer == NULL) || (p_length == NULL))
+ {
+ return NRF_ERROR_NULL;
+ }
+
+ if (m_rx_buffer_queue.read_available_count != 0)
+ {
+ --(m_rx_buffer_queue.read_available_count);
+ ++(m_rx_buffer_queue.free_available_count);
+
+ *pp_buffer =
+ m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].rx_buffer;
+ *p_length =
+ m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].length;
+
+ // @note: Adjust the write_index making use of the fact that the buffer size is of power
+ // of two and two's complement arithmetic. For details refer example to book
+ // "Making embedded systems: Elicia White".
+ m_rx_buffer_queue.read_index =
+ (m_rx_buffer_queue.read_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
+
+ err_code = NRF_SUCCESS;
+ }
+ else
+ {
+ err_code = NRF_ERROR_NO_MEM;
+ }
+
+ return err_code;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f06c2d2b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.h
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diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.h b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.h
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+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/libraries/hci/hci_mem_pool.h
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+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup memory_pool Memory pool
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Memory pool implementation
+ *
+ * Memory pool implementation, based on circular buffer data structure, which supports asynchronous
+ * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers.
+ * The memory managed by the pool is allocated from static storage instead of heap. The internal
+ * design of the circular buffer implementing the RX memory layout is illustrated in the picture
+ * below.
+ *
+ * @image html memory_pool.png "Circular buffer design"
+ *
+ * The expected call order for the RX APIs is as follows:
+ * - hci_mem_pool_rx_produce
+ * - hci_mem_pool_rx_data_size_set
+ * - hci_mem_pool_rx_extract
+ * - hci_mem_pool_rx_consume
+ *
+ * @warning If the above mentioned expected call order is violated the end result can be undefined.
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available to suit various implementations:
+ * - TX_BUF_SIZE TX buffer size in bytes.
+ * - RX_BUF_SIZE RX buffer size in bytes.
+ * - RX_BUF_QUEUE_SIZE RX buffer element size.
+ */
+
+#ifndef HCI_MEM_POOL_H__
+#define HCI_MEM_POOL_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**@brief Function for opening the module.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_mem_pool_open(void);
+
+/**@brief Function for closing the module.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_mem_pool_close(void);
+
+/**@brief Function for allocating requested amount of TX memory.
+ *
+ * @param[out] pp_buffer Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available for allocation.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer);
+
+/**@brief Function for freeing previously allocated TX memory.
+ *
+ * @note Memory management follows the FIFO principle meaning that free() order must match the
+ * alloc(...) order, which is the reason for omitting exact memory block identifier as an
+ * input parameter.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_mem_pool_tx_free(void);
+
+/**@brief Function for producing a free RX memory block for usage.
+ *
+ * @note Upon produce request amount being 0, NRF_SUCCESS is returned.
+ *
+ * @param[in] length Amount, in bytes, of free memory to be produced.
+ * @param[out] pp_buffer Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS Operation success. Free RX memory block produced.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No suitable memory available for allocation.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Request size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer);
+
+/**@brief Function for setting the length of the last produced RX memory block.
+ *
+ * @warning If call to this API is omitted the end result is that the following call to
+ * mem_pool_rx_extract will return incorrect data in the p_length output parameter.
+ *
+ * @param[in] length Amount, in bytes, of actual memory used.
+ *
+ * @retval NRF_SUCCESS Operation success. Length was set.
+ */
+uint32_t hci_mem_pool_rx_data_size_set(uint32_t length);
+
+/**@brief Function for extracting a packet, which has been filled with read data, for further
+ * processing.
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+
+/**@brief Function for freeing previously extracted packet, which has been filled with read data.
+ *
+ * @param[in] p_buffer Pointer to consumed buffer.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to free.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer);
+
+#endif // HCI_MEM_POOL_H__
+
+/** @} */