You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/04/15 14:55:35 UTC
[incubator-nuttx] 03/05: arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller included into Kconfig.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 6ec86361a867d84063d1e6a74540f5914100a34c
Author: Jan Charvat <ja...@gmail.com>
AuthorDate: Wed Apr 6 12:15:04 2022 +0200
arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller included into Kconfig.
Signed-off-by: Jan Charvat <ja...@gmail.com>
---
arch/risc-v/src/esp32c3/Kconfig | 62 +++++++++++++++++++++++++++++++++++++++
arch/risc-v/src/esp32c3/Make.defs | 4 +++
2 files changed, 66 insertions(+)
diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig
index 9ce6bf95c8..92b9e1cba6 100644
--- a/arch/risc-v/src/esp32c3/Kconfig
+++ b/arch/risc-v/src/esp32c3/Kconfig
@@ -197,6 +197,11 @@ config ESP32C3_I2C
bool
default n
+config ESP32C3_TWAI
+ bool
+ default n
+ select CAN
+
config ESP32C3_TIMER
bool
default n
@@ -252,6 +257,11 @@ config ESP32C3_I2C0
default n
select ESP32C3_I2C
+config ESP32C3_TWAI0
+ bool "TWAI (CAN) 0"
+ default n
+ select ESP32C3_TWAI
+
config ESP32C3_RNG
bool "Random Number Generator (RNG)"
default n
@@ -408,6 +418,58 @@ config ESP32C3_I2CTIMEOMS
endmenu # I2C configuration
+menu "TWAI driver options"
+ depends on ESP32C3_TWAI
+
+if ESP32C3_TWAI0
+
+config ESP32C3_TWAI0_TXPIN
+ int "TWAI0 TX Pin"
+ default 2
+
+config ESP32C3_TWAI0_RXPIN
+ int "TWAI0 RX Pin"
+ default 3
+
+config ESP32C3_TWAI0_BITRATE
+ int "TWAI0 bitrate"
+ default 1000000
+ ---help---
+ TWAI0 bit rate. Required if ESP32C3_TWAI0 is defined.
+
+config ESP32C3_TWAI0_SAMPLEP
+ int "TWAI0 sample point"
+ default 80
+ ---help---
+ TWAI0 sample point location as a percent value. Required
+ if ESP32C3_TWAI0 is defined.
+
+config ESP32C3_TWAI0_SJW
+ int "TWAI0 synchronization jump width"
+ default 3
+ ---help---
+ SJW limits the number of Time Quanta corrections during bit
+ Resynchronization. Default: 3
+
+config ESP32C3_TWAI0_SAM
+ bool "TWAI0 sampling"
+ default n
+ ---help---
+ The bus is sampled 3 times (recommended for low to medium speed buses
+ to spikes on the bus-line).
+
+endif # ESP32C3_TWAI0
+
+config ESP32C3_TWAI_REGDEBUG
+ bool "TWAI register level debug"
+ depends on DEBUG_CAN_INFO
+ default n
+ ---help---
+ Output detailed register-level TWAI debug information. Requires also
+ CONFIG_DEBUG_CAN_INFO.
+
+endmenu #ESP32C3_TWAI
+
menu "SPI configuration"
depends on ESP32C3_SPI
diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs
index fe9c76a8c2..c9d611a818 100644
--- a/arch/risc-v/src/esp32c3/Make.defs
+++ b/arch/risc-v/src/esp32c3/Make.defs
@@ -81,6 +81,10 @@ ifeq ($(CONFIG_ESP32C3_I2C),y)
CHIP_CSRCS += esp32c3_i2c.c
endif
+ifeq ($(CONFIG_ESP32C3_TWAI),y)
+CHIP_CSRCS += esp32c3_twai.c
+endif
+
ifeq ($(CONFIG_ESP32C3_SPI),y)
CHIP_CSRCS += esp32c3_spi.c
ifeq ($(CONFIG_SPI_SLAVE),y)