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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2021/03/27 14:43:38 UTC
[GitHub] [incubator-nuttx] hotislandn opened a new pull request #3203: arch:rv64:c906:add risc-v PMP and change mem map for protect build.
hotislandn opened a new pull request #3203:
URL: https://github.com/apache/incubator-nuttx/pull/3203
Signed-off-by: hotislandn <ho...@hotmail.com>
## Summary
This patch adds a simple PMP setting for the C906 protect build.
With this patch, the userspace code can not access memory out of its code and ram regions.
## Impact
All configurations for the board: smartl-c906.
## Testing
All configurations for smartl-c906 have been built and verified on QEMU.
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[GitHub] [incubator-nuttx] xiaoxiang781216 merged pull request #3203: arch:rv64:c906:add risc-v PMP and change mem map for protect build.
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 merged pull request #3203:
URL: https://github.com/apache/incubator-nuttx/pull/3203
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[GitHub] [incubator-nuttx] hotislandn commented on a change in pull request #3203: arch:rv64:c906:add risc-v PMP and change mem map for protect build.
Posted by GitBox <gi...@apache.org>.
hotislandn commented on a change in pull request #3203:
URL: https://github.com/apache/incubator-nuttx/pull/3203#discussion_r602818550
##########
File path: arch/risc-v/src/common/riscv_pmp.c
##########
@@ -0,0 +1,206 @@
+/****************************************************************************
+ * arch/risc-v/src/common/riscv_pmp.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+
+#include "riscv_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PMP_CFG_BITS_CNT (8)
+#define PMP_CFG_FLAG_MASK (0xFF)
+
+#define PMP_CFG_CNT_IN_REG (__riscv_xlen / PMP_CFG_BITS_CNT)
+
+#define PMP_MASK_SET_ONE_REGION(region, attr, reg) \
+ do { \
+ uintptr_t offset = region % PMP_CFG_CNT_IN_REG; \
+ reg &= ~(PMP_CFG_FLAG_MASK << (offset * PMP_CFG_BITS_CNT)); \
+ reg |= attr << (offset * PMP_CFG_BITS_CNT); \
+ } while(0);
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: riscv_config_pmp_region
+ *
+ * Description:
+ * This function will set the specific PMP region with the desired cfg.
+ *
+ * Input Parameters:
+ * region - The region index number.
+ * attr - The region configurations.
+ * base - The base address of the region.
+ * size - The memory length of the region.
+ * For the NAPOT mode, the base address must aligned to the size boundary,
+ * and the size must be power-of-two according to the the PMP spec.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
+ uintptr_t base, uintptr_t size)
+{
+ uintptr_t addr = 0;
+ uintptr_t cfg = 0;
+
+ /* TODO: check the base address alignment and size */
+
+ addr = base >> 2;
+ if (PMPCFG_A_NAPOT == (attr & PMPCFG_A_MASK))
+ {
+ addr |= (size - 1) >> 3;
+ }
+
+ switch (region)
+ {
+ case 0:
+ __asm volatile("csrw pmpaddr0, %0" : :"r"(addr));
Review comment:
OK，let me update them all.Thx.
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #3203: arch:rv64:c906:add risc-v PMP and change mem map for protect build.
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on a change in pull request #3203:
URL: https://github.com/apache/incubator-nuttx/pull/3203#discussion_r602732490
##########
File path: arch/risc-v/src/common/riscv_pmp.c
##########
@@ -0,0 +1,206 @@
+/****************************************************************************
+ * arch/risc-v/src/common/riscv_pmp.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+
+#include "riscv_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PMP_CFG_BITS_CNT (8)
+#define PMP_CFG_FLAG_MASK (0xFF)
+
+#define PMP_CFG_CNT_IN_REG (__riscv_xlen / PMP_CFG_BITS_CNT)
+
+#define PMP_MASK_SET_ONE_REGION(region, attr, reg) \
+ do { \
+ uintptr_t offset = region % PMP_CFG_CNT_IN_REG; \
+ reg &= ~(PMP_CFG_FLAG_MASK << (offset * PMP_CFG_BITS_CNT)); \
+ reg |= attr << (offset * PMP_CFG_BITS_CNT); \
+ } while(0);
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: riscv_config_pmp_region
+ *
+ * Description:
+ * This function will set the specific PMP region with the desired cfg.
+ *
+ * Input Parameters:
+ * region - The region index number.
+ * attr - The region configurations.
+ * base - The base address of the region.
+ * size - The memory length of the region.
+ * For the NAPOT mode, the base address must aligned to the size boundary,
+ * and the size must be power-of-two according to the the PMP spec.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
+ uintptr_t base, uintptr_t size)
+{
+ uintptr_t addr = 0;
+ uintptr_t cfg = 0;
+
+ /* TODO: check the base address alignment and size */
+
+ addr = base >> 2;
+ if (PMPCFG_A_NAPOT == (attr & PMPCFG_A_MASK))
+ {
+ addr |= (size - 1) >> 3;
+ }
+
+ switch (region)
+ {
+ case 0:
+ __asm volatile("csrw pmpaddr0, %0" : :"r"(addr));
Review comment:
change all csrw and csrr to WRITE_CSR and READ_CSR?
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