[GitHub] [nuttx] TimJTi commented on a diff in pull request #7691: GD25Q 4 byte read status issue

[GitBox <gi...@apache.org>]

TimJTi commented on code in PR #7691:
URL: https://github.com/apache/nuttx/pull/7691#discussion_r1032386682


##########
drivers/mtd/gd25.c:
##########
@@ -107,6 +107,7 @@
 #define GD25_SR_WIP                 (1 << 0)  /* Bit 0: Write in Progress */
 #define GD25_SR_WEL                 (1 << 1)  /* Bit 1: Write Enable Latch */
 #define GD25_SR1_EN4B               (1 << 3)  /* Bit 3: Enable 4byte address */
+#define GD25Q_SR1_EN4B              (1 << 0)  /* Bit 0: Enable 4byte address GD25Q memories */

Review Comment:
   Apologies, perhaps what you wrote was ambiguous and I misunderstood - but that is not the bit that is read (it reads the second status reg to get S11 - or S8 with this change) BUT it will not be read for a 32Mbit device anyway. The driver will never attempt to place this device into 4 byte read mode, so it is not a problem:
   
         if (priv->nsectors > GD25_NSECTORS_128MBIT)
           {          
              if (!gd25_4ben(priv))
                {
                  ferr("ERROR: capacity %02x: Can't enable 4-byte mode!\n", capacity);
                  ... etc



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