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Posted to commits@nuttx.apache.org by xi...@apache.org on 2020/10/31 17:40:53 UTC
[incubator-nuttx] 04/04: arch: spi: fix typos and run nxstyle
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit a01a01ab4558f2dc25996f7c095d894467b58909
Author: Juha Niskanen <ju...@haltian.com>
AuthorDate: Sat Oct 31 17:47:57 2020 +0200
arch: spi: fix typos and run nxstyle
Signed-off-by: Juha Niskanen <ju...@haltian.com>
---
arch/arm/src/efm32/efm32_spi.c | 8 ++++----
arch/arm/src/kinetis/kinetis_spi.c | 2 +-
arch/arm/src/kl/kl_spi.c | 6 ++++--
arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c | 14 +++++++++-----
arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c | 20 ++++++++++++++------
arch/arm/src/lpc2378/lpc23xx_spi.c | 16 +++++++++++-----
arch/arm/src/lpc43xx/lpc43_spi.c | 16 +++++++++++-----
arch/arm/src/lpc43xx/lpc43_ssp.c | 18 +++++++++++++-----
arch/arm/src/max326xx/max32660/max32660_spim.c | 14 +++++++++-----
arch/arm/src/samv7/sam_qspi.c | 6 +++---
arch/arm/src/samv7/sam_spi_slave.c | 6 +++---
arch/arm/src/stm32/stm32_spi.c | 6 +++---
arch/arm/src/stm32f0l0g0/stm32_spi.c | 16 ++++++++++++----
arch/arm/src/tiva/common/tiva_ssi.c | 2 +-
arch/avr/src/avr/up_spi.c | 4 ++--
arch/mips/src/pic32mz/pic32mz_spi.c | 6 +++---
arch/xtensa/src/esp32/esp32_spi.c | 8 +++-----
arch/z16/src/z16f/z16f_espi.c | 4 ++--
18 files changed, 108 insertions(+), 64 deletions(-)
diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c
index d4f783f..f5e181c 100644
--- a/arch/arm/src/efm32/efm32_spi.c
+++ b/arch/arm/src/efm32/efm32_spi.c
@@ -1044,8 +1044,8 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
regval |= setting;
spi_putreg(config, EFM32_USART_FRAME_OFFSET, regval);
- /* Save the selection so the subsequence re-configurations will be
- * faster
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
*/
priv->nbits = nbits;
@@ -1105,8 +1105,8 @@ static int spi_hwfeatures(FAR struct spi_dev_s *dev,
spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval);
- /* Save the selection so the subsequence re-configurations will be
- * faster
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
*/
priv->lsbfirst = lsbfirst;
diff --git a/arch/arm/src/kinetis/kinetis_spi.c b/arch/arm/src/kinetis/kinetis_spi.c
index 12aa9d9..eba7bfb 100644
--- a/arch/arm/src/kinetis/kinetis_spi.c
+++ b/arch/arm/src/kinetis/kinetis_spi.c
@@ -813,7 +813,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= SPI_CTARM_FMSZ(nbits - 1);
spi_putreg(priv, priv->ctarsel, regval);
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so that subsequent re-configurations will be faster. */
priv->nbits = nbits;
}
diff --git a/arch/arm/src/kl/kl_spi.c b/arch/arm/src/kl/kl_spi.c
index 4aef68c..3b81e90 100644
--- a/arch/arm/src/kl/kl_spi.c
+++ b/arch/arm/src/kl/kl_spi.c
@@ -284,7 +284,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
unsigned int spr;
unsigned int sppr;
- /* Check if the requested frequence is the same as the frequency selection */
+ /* Check if the requested frequence is the same as the frequency
+ * selection.
+ */
if (priv->frequency == frequency)
{
@@ -410,7 +412,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
spi_putreg(priv, KL_SPI_C1_OFFSET, regval);
- /* Save the mode so that subsequent re-configuratins will be faster */
+ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode;
}
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
index 3514112..9b76047 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
@@ -228,10 +228,12 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t divisor;
uint32_t actual;
- /* Check if the requested frequence is the same as the frequency selection */
-
DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2);
+ /* Check if the requested frequence is the same as the frequency
+ * selection.
+ */
+
if (priv->frequency == frequency)
{
/* We are already at this frequency. Return the actual. */
@@ -328,7 +330,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
putreg32(regval, LPC17_40_SPI_CR);
- /* Save the mode so that subsequent re-configuratins will be faster */
+ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode;
}
@@ -342,7 +344,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
*
* Input Parameters:
* dev - Device-specific state data
- * nbits - The number of bits requests
+ * nbits - The number of bits requested
*
* Returned Value:
* none
@@ -368,7 +370,9 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= SPI_CR_BITENABLE;
regval = getreg32(LPC17_40_SPI_CR);
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
+ */
priv->nbits = nbits;
}
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
index 1ac23cc..5a080ef 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
@@ -385,10 +385,12 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev,
uint32_t regval;
uint32_t actual;
- /* Check if the requested frequency is the same as the frequency selection */
-
DEBUGASSERT(priv && frequency <= SSP_CLOCK / 2);
+ /* Check if the requested frequency is the same as the frequency
+ * selection.
+ */
+
if (priv->frequency == frequency)
{
/* We are already at this frequency. Return the actual. */
@@ -533,7 +535,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
*
* Input Parameters:
* dev - Device-specific state data
- * nbits - The number of bits requests
+ * nbits - The number of bits requested
*
* Returned Value:
* none
@@ -558,7 +560,9 @@ static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= ((nbits - 1) << SSP_CR0_DSS_SHIFT);
ssp_putreg(priv, LPC17_40_SSP_CR0_OFFSET, regval);
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
+ */
priv->nbits = nbits;
}
@@ -731,7 +735,9 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
uint32_t data;
uint32_t rxpending = 0;
- /* While there is remaining to be sent (and no synchronization error has occurred) */
+ /* While there is remaining to be sent (and no synchronization error
+ * has occurred)
+ */
spiinfo("nwords: %d\n", nwords);
u.pv = buffer;
@@ -752,7 +758,9 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
rxpending++;
}
- /* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
+ /* Now, read the RX data from the RX FIFO while the RX FIFO is
+ * not empty.
+ */
spiinfo("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_RNE)
diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.c b/arch/arm/src/lpc2378/lpc23xx_spi.c
index af8a042..3539841 100644
--- a/arch/arm/src/lpc2378/lpc23xx_spi.c
+++ b/arch/arm/src/lpc2378/lpc23xx_spi.c
@@ -234,7 +234,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
DEBUGASSERT(frequency <= SPI_CLOCK / 2);
- /* Check if the requested frequency is the same as the frequency selection */
+ /* Check if the requested frequency is the same as the frequency
+ * selection.
+ */
DEBUGASSERT(priv != NULL);
if (priv->frequency == frequency)
@@ -248,7 +250,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
divisor = SPI_CLOCK / frequency;
- /* The SPI CCR register must contain an even number greater than or equal to 8. */
+ /* The SPI CCR register must contain an even number greater than or equal
+ * to 8.
+ */
if (divisor < 8)
{
@@ -332,7 +336,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
putreg32(regval, SPI_CR);
- /* Save the mode so that subsequent re-configuratins will be faster */
+ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode;
}
@@ -346,7 +350,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
*
* Input Parameters:
* dev - Device-specific state data
- * nbits - The number of bits requests
+ * nbits - The number of bits requested
*
* Returned Value:
* none
@@ -373,7 +377,9 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= SPI_CR_BITENABLE;
putreg32(regval, SPI_CR);
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
+ */
priv->nbits = nbits;
}
diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c
index 00e6fb9..3269bbb 100644
--- a/arch/arm/src/lpc43xx/lpc43_spi.c
+++ b/arch/arm/src/lpc43xx/lpc43_spi.c
@@ -219,7 +219,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t divisor;
uint32_t actual;
- /* Check if the requested frequence is the same as the frequency selection */
+ /* Check if the requested frequence is the same as the frequency
+ * selection.
+ */
DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2);
@@ -234,7 +236,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
divisor = SPI_CLOCK / frequency;
- /* The SPI CCR register must contain an even number greater than or equal to 8. */
+ /* The SPI CCR register must contain an even number greater than or equal
+ * to 8.
+ */
if (divisor < 8)
{
@@ -317,7 +321,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
putreg32(regval, LPC43_SPI_CR);
- /* Save the mode so that subsequent re-configuratins will be faster */
+ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode;
}
@@ -331,7 +335,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
*
* Input Parameters:
* dev - Device-specific state data
- * nbits - The number of bits requests
+ * nbits - The number of bits requested
*
* Returned Value:
* none
@@ -357,7 +361,9 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= SPI_CR_BITENABLE;
regval = getreg32(LPC43_SPI_CR);
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
+ */
priv->nbits = nbits;
}
diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c
index a003097..fc1d53c 100644
--- a/arch/arm/src/lpc43xx/lpc43_ssp.c
+++ b/arch/arm/src/lpc43xx/lpc43_ssp.c
@@ -432,7 +432,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
*
* Input Parameters:
* dev - Device-specific state data
- * nbits - The number of bits requests
+ * nbits - The number of bits requested
*
* Returned Value:
* none
@@ -461,7 +461,9 @@ static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits)
spiinfo("SSP Control Register 0 (CR0) after setting"
"DSS: 0x%08X.\n", regval);
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
+ */
priv->nbits = nbits;
}
@@ -550,7 +552,9 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
uint32_t datadummy = (priv->nbits > 8) ? 0xffff : 0xff;
uint32_t rxpending = 0;
- /* While there is remaining to be sent (and no synchronization error has occurred) */
+ /* While there is remaining to be sent (and no synchronization error
+ * has occurred)
+ */
spiinfo("nwords: %d\n", nwords);
@@ -585,7 +589,9 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
rxpending++;
}
- /* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
+ /* Now, read the RX data from the RX FIFO while the RX FIFO is not
+ * empty.
+ */
spiinfo("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE)
@@ -759,7 +765,9 @@ static inline FAR struct lpc43_sspdev_s *lpc43_ssp1initialize(void)
/* Pins configuration */
#ifdef PINCONF_SSP1_SCK
- /* It is possible this is not configured if CLK0 is being used for clocking SPI */
+ /* It is possible this is not configured if CLK0 is being used for
+ * clocking SPI.
+ */
lpc43_pin_config(PINCONF_SSP1_SCK);
#endif
diff --git a/arch/arm/src/max326xx/max32660/max32660_spim.c b/arch/arm/src/max326xx/max32660/max32660_spim.c
index 6e16189..0188897 100644
--- a/arch/arm/src/max326xx/max32660/max32660_spim.c
+++ b/arch/arm/src/max326xx/max32660/max32660_spim.c
@@ -708,7 +708,9 @@ static int spi_poll(struct max326_spidev_s *priv)
inten |= SPI_INT_RXLEVEL;
}
- /* Break out if we've received all the bytes and we're not transmitting */
+ /* Break out if we've received all the bytes and we're not
+ * transmitting.
+ */
if (priv->txbuffer == NULL && priv->rxbytes == length)
{
@@ -716,7 +718,7 @@ static int spi_poll(struct max326_spidev_s *priv)
}
}
- /* Break out once we've transmitted and received all of the data */
+ /* Break out once we've transmitted and received all of the data. */
if (priv->rxbytes == length && priv->txbytes == length)
{
@@ -1080,7 +1082,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
spi_modify_ctrl2(priv, setbits, clrbits);
- /* Save the mode so that subsequent re-configurations will be faster */
+ /* Save the mode so that subsequent re-configurations will be
+ * faster.
+ */
priv->mode = mode;
}
@@ -1121,8 +1125,8 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
priv->data16 = (nbits > 8);
- /* Save the selection so the subsequence re-configurations will be
- * faster
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
*/
priv->nbits = nbits;
diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c
index 61439f7..d77e87c 100644
--- a/arch/arm/src/samv7/sam_qspi.c
+++ b/arch/arm/src/samv7/sam_qspi.c
@@ -1281,7 +1281,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode)
*
* Input Parameters:
* dev - Device-specific state data
- * nbits - The number of bits requests
+ * nbits - The number of bits requested
*
* Returned Value:
* none
@@ -1310,8 +1310,8 @@ static void qspi_setbits(struct qspi_dev_s *dev, int nbits)
spiinfo("MR=%08x\n", regval);
- /* Save the selection so the subsequence re-configurations will be
- * faster
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
*/
priv->nbits = nbits;
diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c
index 9197756..a950dbf 100644
--- a/arch/arm/src/samv7/sam_spi_slave.c
+++ b/arch/arm/src/samv7/sam_spi_slave.c
@@ -703,7 +703,7 @@ static void spi_setmode(struct sam_spidev_s *priv, enum spi_smode_e mode)
*
* Input Parameters:
* priv - SPI device data structure
- * nbits - The number of bits requests
+ * nbits - The number of bits requested
*
* Returned Value:
* none
@@ -730,8 +730,8 @@ static void spi_setbits(struct sam_spidev_s *priv, int nbits)
spiinfo("csr0=%08x\n", regval);
- /* Save the selection so the subsequence re-configurations will be
- * faster
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
*/
priv->nbits = nbits;
diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c
index 2048286..5fb79c4 100644
--- a/arch/arm/src/stm32/stm32_spi.c
+++ b/arch/arm/src/stm32/stm32_spi.c
@@ -1520,7 +1520,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
spi_modifycr1(priv, setbits, clrbits);
spi_modifycr1(priv, SPI_CR1_SPE, 0);
#endif
- /* Save the selection so the subsequence re-configurations will be faster */
+ /* Save the selection so that subsequent re-configurations will be faster. */
priv->nbits = nbits;
}
@@ -1818,10 +1818,10 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
/* If this bus uses a in driver buffers we will incur 2 copies,
* The copy cost is << less the non DMA transfer time and having
- * the buffer in the driver ensures DMA can be used. This is bacause
+ * the buffer in the driver ensures DMA can be used. This is because
* the API does not support passing the buffer extent so the only
* extent is buffer + the transfer size. These can sizes be less than
- * the cache line size, and not aligned and tyicaly greater then 4
+ * the cache line size, and not aligned and typically greater then 4
* bytes, which is about the break even point for the DMA IO overhead.
*/
diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c
index 2a5a555..d842760 100644
--- a/arch/arm/src/stm32f0l0g0/stm32_spi.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c
@@ -1068,7 +1068,9 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits);
spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
- /* Save the mode so that subsequent re-configurations will be faster */
+ /* Save the mode so that subsequent re-configurations will be
+ * faster.
+ */
priv->mode = mode;
}
@@ -1156,7 +1158,9 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
#endif
- /* Save the selection so that subsequent re-configurations will be faster. */
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
+ */
priv->nbits = nbits;
}
@@ -1256,7 +1260,9 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd)
spi_writeword(priv, (uint16_t)(wd & 0xffff));
ret = (uint32_t)spi_readword(priv);
- /* Check and clear any error flags (Reading from the SR clears the error flags) */
+ /* Check and clear any error flags (Reading from the SR clears the error
+ * flags)
+ */
regval = spi_getreg(priv, STM32_SPI_SR_OFFSET);
@@ -1618,7 +1624,9 @@ static int spi_pm_prepare(FAR struct pm_callback_s *cb, int domain,
if (sval <= 0)
{
- /* Exclusive lock is held, do not allow entry to deeper PM states. */
+ /* Exclusive lock is held, do not allow entry to deeper PM
+ * states.
+ */
return -EBUSY;
}
diff --git a/arch/arm/src/tiva/common/tiva_ssi.c b/arch/arm/src/tiva/common/tiva_ssi.c
index 941209e..3c1e0d6 100644
--- a/arch/arm/src/tiva/common/tiva_ssi.c
+++ b/arch/arm/src/tiva/common/tiva_ssi.c
@@ -1277,7 +1277,7 @@ static void ssi_setmodeinternal(struct tiva_ssidev_s *priv,
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, regval);
spiinfo("CR0: %08x\n", regval);
- /* Save the mode so that subsequent re-configuratins will be faster */
+ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode;
}
diff --git a/arch/avr/src/avr/up_spi.c b/arch/avr/src/avr/up_spi.c
index 09334ad..7caa2bc 100644
--- a/arch/avr/src/avr/up_spi.c
+++ b/arch/avr/src/avr/up_spi.c
@@ -308,7 +308,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
SPSR = regval;
- /* Save the mode so that subsequent re-configuratins will be faster */
+ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode;
}
@@ -322,7 +322,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
*
* Input Parameters:
* dev - Device-specific state data
- * nbits - The number of bits requests (only nbits == 8 is supported)
+ * nbits - The number of bits requested (only nbits == 8 is supported)
*
* Returned Value:
* none
diff --git a/arch/mips/src/pic32mz/pic32mz_spi.c b/arch/mips/src/pic32mz/pic32mz_spi.c
index 1643b0a..2daaadf 100644
--- a/arch/mips/src/pic32mz/pic32mz_spi.c
+++ b/arch/mips/src/pic32mz/pic32mz_spi.c
@@ -1368,7 +1368,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
*
* Input Parameters:
* dev - Device-specific state data
- * nbits - The number of bits requests
+ * nbits - The number of bits requested
*
* Returned Value:
* none
@@ -1411,8 +1411,8 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= setting;
spi_putreg(priv, PIC32MZ_SPI_CON_OFFSET, regval);
- /* Save the selection so the subsequence re-configurations will be
- * faster
+ /* Save the selection so that subsequent re-configurations will be
+ * faster.
*/
priv->nbits = nbits;
diff --git a/arch/xtensa/src/esp32/esp32_spi.c b/arch/xtensa/src/esp32/esp32_spi.c
index f1f71b3..fa38e99 100644
--- a/arch/xtensa/src/esp32/esp32_spi.c
+++ b/arch/xtensa/src/esp32/esp32_spi.c
@@ -791,16 +791,14 @@ static void esp32_spi_setbits(FAR struct spi_dev_s *dev, int nbits)
if (nbits != priv->nbits)
{
- /**
- * Save the selection so the subsequence re-configurations
+ /* Save the selection so that subsequent re-configurations
* will be faster.
*/
priv->nbits = nbits;
- /**
- * Each DMA transmission will set these value according to
- * calculate buffer length.
+ /* Each DMA transmission will set these value according to
+ * calculated buffer length.
*/
if (!priv->dma_chan)
diff --git a/arch/z16/src/z16f/z16f_espi.c b/arch/z16/src/z16f/z16f_espi.c
index 4415c4b..12c619b 100644
--- a/arch/z16/src/z16f/z16f_espi.c
+++ b/arch/z16/src/z16f/z16f_espi.c
@@ -514,7 +514,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
*
* Input Parameters:
* dev - Device-specific state data
- * nbits - The number of bits requests
+ * nbits - The number of bits requested
*
* Returned Value:
* none
@@ -548,7 +548,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
spi_putreg8(priv, regval, Z16F_ESPI_MODE);
spiinfo("ESPI MODE: %02x\n", regval);
- /* Save the selection so the subsequence re-configurations will be
+ /* Save the selection so that subsequent re-configurations will be
* faster.
*/