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Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2022/06/08 12:39:26 UTC
[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2848: mcu/nrf52: Handle APROTECT
apache-mynewt-bot commented on PR #2848:
URL: https://github.com/apache/mynewt-core/pull/2848#issuecomment-1149861673
<!-- style-bot -->
## Style check summary
### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
#### hw/mcu/nordic/nrf52xxx/src/system_nrf52.c
<details>
```diff
@@ -355,138 +373,155 @@
/* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://www.nordicsemi.com/DocLib */
- if (errata_108()){
+ if (errata_108()) {
*(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F;
}
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
for your device located at https://www.nordicsemi.com/DocLib */
- if (errata_136()){
- if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
- NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
+ if (errata_136()) {
+ if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk) {
+ NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
}
}
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
- defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
- reserved for PinReset and not available as normal GPIO. */
+ defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+ reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
#define RESET_PIN 21
- if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
- ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
- NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NRF_UICR->PSELRESET[0] = RESET_PIN;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NRF_UICR->PSELRESET[1] = RESET_PIN;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NVIC_SystemReset();
- }
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
+ (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) !=
+ (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) {
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NRF_UICR->PSELRESET[0] = RESET_PIN;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NRF_UICR->PSELRESET[1] = RESET_PIN;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NVIC_SystemReset();
+ }
#endif
#endif
#ifdef NRF52840_XXAA
- /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
- for your device located at https://infocenter.nordicsemi.com/ */
- if (errata_36()){
- NRF_CLOCK->EVENTS_DONE = 0;
- NRF_CLOCK->EVENTS_CTTO = 0;
- NRF_CLOCK->CTIV = 0;
- }
-
- /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
- for your device located at https://infocenter.nordicsemi.com/ */
- if (errata_98()){
- *(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
- }
-
- /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
- for your device located at https://infocenter.nordicsemi.com/ */
- if (errata_103()){
- NRF_CCM->MAXPACKETSIZE = 0xFBul;
- }
-
- /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
- for your device located at https://infocenter.nordicsemi.com/ */
- if (errata_115()){
- *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
- }
-
- /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
- for your device located at https://infocenter.nordicsemi.com/ */
- if (errata_120()){
- *(volatile uint32_t *)0x40029640ul = 0x200ul;
- }
-
- /* Workaround for Errata 120 "QSPI: Second read and long read commands fail" found at the Errata document
- for your device located at https://infocenter.nordicsemi.com/ */
- if (errata_121()){
- *(volatile uint32_t *)0x40029600ul = 0x00040400ul;
- }
-
- /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
- * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
- * operations are not used in your code. */
+ /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_36()) {
+ NRF_CLOCK->EVENTS_DONE = 0;
+ NRF_CLOCK->EVENTS_CTTO = 0;
+ NRF_CLOCK->CTIV = 0;
+ }
+
+ /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_98()) {
+ *(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
+ }
+
+ /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_103()) {
+ NRF_CCM->MAXPACKETSIZE = 0xFBul;
+ }
+
+ /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_115()) {
+ *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) |
+ (*(uint32_t *)0x10000258 & 0x0000000F);
+ }
+
+ /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_120()) {
+ *(volatile uint32_t *)0x40029640ul = 0x200ul;
+ }
+
+ /* Workaround for Errata 120 "QSPI: Second read and long read commands fail" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_121()) {
+ *(volatile uint32_t *)0x40029600ul = 0x00040400ul;
+ }
+
+ /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+ * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+ * operations are not used in your code. */
#if (__FPU_USED == 1)
- SCB->CPACR |= (3UL << 20) | (3UL << 22);
- __DSB();
- __ISB();
+ SCB->CPACR |= (3UL << 20) | (3UL << 22);
+ __DSB();
+ __ISB();
#endif
- /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
- two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
- normal GPIOs. */
+ /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+ two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+ normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
- if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
- NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NVIC_SystemReset();
- }
+ if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) {
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NVIC_SystemReset();
+ }
#endif
- /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
- defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
- reserved for PinReset and not available as normal GPIO. */
+ /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+ defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+ reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
- if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
- ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
- NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NRF_UICR->PSELRESET[0] = 18;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NRF_UICR->PSELRESET[1] = 18;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NVIC_SystemReset();
- }
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
+ (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) !=
+ (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) {
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NRF_UICR->PSELRESET[0] = 18;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NRF_UICR->PSELRESET[1] = 18;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}
+ NVIC_SystemReset();
+ }
#endif
- /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
- Specification to see which one). */
+ /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+ Specification to see which one). */
#if defined (ENABLE_SWO)
- CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
- NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
- NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+ NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
- /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
- Specification to see which ones). */
+ /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+ Specification to see which ones). */
#if defined (ENABLE_TRACE)
- CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
- NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
- NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
- NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
- NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
- NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
- NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+ NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
+ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
+ (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
#endif
nrf52_handle_approtect();
```
</details>
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