[GitHub] [tvm] tqchen commented on a change in pull request #7923: [TensorIR][PASS][M1c] CompactBufferAllocation

[GitBox <gi...@apache.org>]

tqchen commented on a change in pull request #7923:
URL: https://github.com/apache/tvm/pull/7923#discussion_r621136104



##########
File path: python/tvm/tir/transform/transform.py
##########
@@ -560,3 +560,53 @@ def PlanAndUpdateBufferAllocationLocation():
         The result pass
     """
     return _ffi_api.PlanAndUpdateBufferAllocationLocation()
+
+
+def ConvertBlocksToOpaque():
+    """Substitute all the block vars with the PrimExprs they are bound to, indicated by
+    the corresponding iter_values in BlockRealize, and then convert the blocks into
+    opaque ones by removing all the iter_values in BlockRealize and iter_vars in Block.
+
+    Returns
+    -------
+    fpass : tvm.transform.Pass
+        The result pass
+    """
+    return _ffi_api.ConvertBlocksToOpaque()
+
+
+def CompactBufferAllocation():

Review comment:
       Yes, the functionality should be similar, except that infer bound needs to walk through the schedule tree, while in this case the split/reorder already updated the index, so the impl should be simpler




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