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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/06/15 12:29:23 UTC
[incubator-nuttx] 01/02: stm32wl5: add support for internal FLASH
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 5490f8964f02cb66af9c8afd17c8355c0328f90d
Author: Michał Łyszczek <mi...@bofc.pl>
AuthorDate: Tue Jun 14 00:32:11 2022 +0200
stm32wl5: add support for internal FLASH
This patch adds corrected implementation of FLASH memory to be used
with progmem driver for use with mtd filesystems like nxffs or smartfs.
Signed-off-by: Michał Łyszczek <mi...@bofc.pl>
---
Documentation/platforms/arm/stm32wl5/index.rst | 10 +
arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h | 250 ++++++++++++------------
arch/arm/src/stm32wl5/stm32wl5_flash.c | 166 +++++++++-------
arch/arm/src/stm32wl5/stm32wl5_flash.h | 8 +-
4 files changed, 234 insertions(+), 200 deletions(-)
diff --git a/Documentation/platforms/arm/stm32wl5/index.rst b/Documentation/platforms/arm/stm32wl5/index.rst
index 3099ebaa8f..798114e211 100644
--- a/Documentation/platforms/arm/stm32wl5/index.rst
+++ b/Documentation/platforms/arm/stm32wl5/index.rst
@@ -40,6 +40,7 @@ RCC Yes All registers defined, not all peripherals enabled
SYSCFG Yes All registers defined, GPIO EXTI works, remapping not tested
USART Yes
LPUART Yes full speed with HSE works, low power mode with LSE not implemented
+FLASH Yes Progmem imlementation - mtd filesystems like smartfs or nxffs work
DMA No
SRAM2 No
SPI No
@@ -133,6 +134,15 @@ interrupt first goes through EXTI and is then forwarded to main NVIC.
EXTI for gpio can be enabled via `stm32wl5_gpiosetevent` function.
+FLASH
+-----
+
+Place where program code lives. Part of flash can also be used to create
+small filesystems like nxffs or smartfs to hold persistant data between
+reboots without the need of attaching external flash or mmc card. Since
+flash has limited number of erases (writes) it's best to hold there only
+data that is no frequently updated (so, configuration is ok, logs are not).
+
Supported Boards
================
diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h
index 757f7e689a..26ca718fe4 100644
--- a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h
+++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h
@@ -45,8 +45,6 @@
* STM32WL5xxx has only single bank flash and page size 2KiB
*/
-#define _K(x) ((x)*1024)
-
#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32WL5_FLASH_OVERRIDE_8) && \
!defined(CONFIG_STM32WL5_FLASH_OVERRIDE_B) && \
@@ -104,7 +102,7 @@
# error "unknown flash configuration!"
#endif
-#define STM32WL5_FLASH_SIZE (STM32WL5_FLASH_NPAGES * STM32WL5_FLASH_PAGESIZE)
+#define STM32WL5_FLASH_SIZE (STM32WL5_FLASH_NPAGES * STM32WL5_FLASH_PAGESIZE)
/* Register Offsets *********************************************************/
@@ -131,114 +129,114 @@
/* Register Addresses *******************************************************/
-#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET)
-#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET)
-#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET)
-#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET)
-#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET)
-#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET)
-#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET)
-#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET)
-#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET)
-#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET)
-#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET)
-#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET)
-#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET)
-#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET)
-#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET)
-#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET)
-#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET)
-#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET)
-#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET)
-#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET)
+#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET)
+#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET)
+#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET)
+#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET)
+#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET)
+#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET)
+#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET)
+#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET)
+#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET)
+#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET)
+#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET)
+#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET)
+#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET)
+#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET)
+#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET)
+#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET)
+#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET)
+#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET)
+#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET)
+#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Flash Access Control Register (ACR) */
-#define FLASH_ACR_LATENCY_SHIFT (0)
-#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
-# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 1 and 2. */
-# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */
-# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */
-# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */
-
-#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */
-#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
-#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
-#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */
-#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */
-#define FLASH_ACR_PES (1 << 15) /* Bit 15: Suspend flash program */
-#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Is user flash empty */
+#define FLASH_ACR_LATENCY_SHIFT (0)
+#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
+# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, for Vcore range 1 and 2. */
+# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */
+# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */
+# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */
+
+#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */
+#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
+#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
+#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */
+#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */
+#define FLASH_ACR_PES (1 << 15) /* Bit 15: Suspend flash program */
+#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Is user flash empty */
/* Flash Access Control Register 2 (ACR2) */
-#define FLASH_ACR2_PRIVMODE (1 << 0) /* Bit 0: Enable flash priviliged access mode */
-#define FLASH_ACR2_HDPADIS (1 << 1) /* Bit 1: Disable user flash hide protection area access */
-#define FLASH_ACR2_C2SWDBGEN (1 << 2) /* Bit 2: Enable cpu2 debug access */
+#define FLASH_ACR2_PRIVMODE (1 << 0) /* Bit 0: Enable flash priviliged access mode */
+#define FLASH_ACR2_HDPADIS (1 << 1) /* Bit 1: Disable user flash hide protection area access */
+#define FLASH_ACR2_C2SWDBGEN (1 << 2) /* Bit 2: Enable cpu2 debug access */
/* Flash Status Register (SR) */
-#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
-#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
-#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */
-#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
-#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
-#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */
-#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
-#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */
-#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */
-#define FLASH_SR_OPTNV (1 << 13) /* Bit 13: User option OPTVAL indication */
-#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */
-#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */
-#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
-#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Program or erase configuration busy */
-#define FLASH_SR_PESD (1 << 19) /* Bit 19: Program or erase operation suspended */
+#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
+#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
+#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */
+#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
+#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
+#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */
+#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
+#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */
+#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */
+#define FLASH_SR_OPTNV (1 << 13) /* Bit 13: User option OPTVAL indication */
+#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */
+#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */
+#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
+#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Program or erase configuration busy */
+#define FLASH_SR_PESD (1 << 19) /* Bit 19: Program or erase operation suspended */
/* Flash Control Register (CR) */
-#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */
-#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */
-#define FLASH_CR_MER (1 << 2) /* Bit 2 : Mass Erase */
+#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */
+#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */
+#define FLASH_CR_MER (1 << 2) /* Bit 2 : Mass Erase */
-#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */
-#define FLASH_CR_PNB_MASK (0x7F << FLASH_CR_PNB_SHIFT)
-#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n, n=0..127 */
+#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */
+#define FLASH_CR_PNB_MASK (0x7F << FLASH_CR_PNB_SHIFT)
+#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n, n=0..127 */
-#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */
-#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */
-#define FLASH_CR_FSTPG (1 << 23) /* Bit 23: Fast programming */
-#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
-#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
-#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */
-#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */
-#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */
-#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
+#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */
+#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */
+#define FLASH_CR_FSTPG (1 << 18) /* Bit 18: Fast programming */
+#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
+#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
+#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */
+#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */
+#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */
+#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
/* Flash ECC Register (ECCR) */
-#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-15: Read protect */
-# define FLASH_ECCR_ADDR_ECC_MASK (0xffff << FLASH_ECCR_ADDR_ECC_SHIFT)
-#define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */
-#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */
-#define FLASH_ECCR_CPUID_SHIFT (26)
-# define FLASH_ECCR_CPUID_MASK (0x7 << FLASH_ECCR_CPUID_SHIFT)
-# define FLASH_ECCR_CPUID_CPU1 (0x0 << FLASH_ECCR_CPUID_SHIFT) /* 000: cpu1 access caused ECC failure */
-# define FLASH_ECCR_CPUID_CPU2 (0x1 << FLASH_ECCR_CPUID_SHIFT) /* 001: cpu2 access caused ECC failure */
+#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-16: ECC fail address */
+# define FLASH_ECCR_ADDR_ECC_MASK (0x1ffff << FLASH_ECCR_ADDR_ECC_SHIFT)
+#define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */
+#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */
+#define FLASH_ECCR_CPUID_SHIFT (26)
+# define FLASH_ECCR_CPUID_MASK (0x7 << FLASH_ECCR_CPUID_SHIFT)
+# define FLASH_ECCR_CPUID_CPU1 (0x0 << FLASH_ECCR_CPUID_SHIFT) /* 000: cpu1 access caused ECC failure */
+# define FLASH_ECCR_CPUID_CPU2 (0x1 << FLASH_ECCR_CPUID_SHIFT) /* 001: cpu2 access caused ECC failure */
-#define FLASH_ECCR_ECCC (1 << 30) /* Bit 30: ECC correction */
-#define FLASH_ECCR_ECCD (1 << 31) /* Bit 31: ECC detection */
+#define FLASH_ECCR_ECCC (1 << 30) /* Bit 30: ECC correction */
+#define FLASH_ECCR_ECCD (1 << 31) /* Bit 31: ECC detection */
/* Flash Option Register (OPTR) */
-#define FLASH_OPTR_RDP_SHIFT (0) /* Bits 0-7: Read Protection Level */
+#define FLASH_OPTR_RDP_SHIFT (0) /* Bits 0-7: Read Protection Level */
#define FLASH_OPTR_RDP_MASK (0xFF << FLASH_OPTR_RDP_SHIFT)
#define FLASH_OPTR_RDP_NONE (0xAA << FLASH_OPTR_RDP_SHIFT)
#define FLASH_OPTR_RDP_CHIP (0xCC << FLASH_OPTR_RDP_SHIFT) /* WARNING, CANNOT BE REVERSED !! */
-#define FLASH_OPTR_ESE (1 << 8) /* Bit 8: System security flag */
+#define FLASH_OPTR_ESE (1 << 8) /* Bit 8: System security flag */
-#define FLASH_OPTR_BORLEV_SHIFT (9) /* Bits 9-11: BOR reset Level */
+#define FLASH_OPTR_BORLEV_SHIFT (9) /* Bits 9-11: BOR reset Level */
#define FLASH_OPTR_BORLEV_MASK (7 << FLASH_OPTR_BORLEV_SHIFT)
#define FLASH_OPTR_VBOR0 (0 << FLASH_OPTR_BORLEV_SHIFT) /* 000: BOR Level 0 (1.7 V) */
#define FLASH_OPTR_VBOR1 (1 << FLASH_OPTR_BORLEV_SHIFT) /* 001: BOR Level 1 (2.0 V) */
@@ -246,59 +244,59 @@
#define FLASH_OPTR_VBOR3 (3 << FLASH_OPTR_BORLEV_SHIFT) /* 011: BOR Level 3 (2.5 V) */
#define FLASH_OPTR_VBOR4 (4 << FLASH_OPTR_BORLEV_SHIFT) /* 100: BOR Level 4 (2.8 V) */
-#define FLASH_OPTR_NRST_STOP (1 << 12) /* Bit 12: Generate reset when entering the Stop mode */
-#define FLASH_OPTR_NRST_STDBY (1 << 13) /* Bit 13: Generate reset when entering the Standby mode */
-#define FLASH_OPTR_NRST_SHDW (1 << 14) /* Bit 14: Generate reset when entering the Shutdown mode */
-#define FLASH_OPTR_IWDG_SW (1 << 16) /* Bit 16: Independent watchdog selection */
-#define FLASH_OPTR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */
-#define FLASH_OPTR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/
-#define FLASH_OPTR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */
-#define FLASH_OPTR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */
-#define FLASH_OPTR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */
-#define FLASH_OPTR_SRAM_RST (1 << 25) /* Bit 25: SRAM1/2 Erase when system reset */
-#define FLASH_OPTR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */
-#define FLASH_OPTR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */
-
-#define FLASH_OPTR_C1BOOT_LOCK (1 << 30) /* Bit 30: Enable cpu1 boot lock */
-#define FLASH_OPTR_C2BOOT_LOCK (1 << 31) /* Bit 31: Enable cpu2 boot lock */
+#define FLASH_OPTR_NRST_STOP (1 << 12) /* Bit 12: Generate reset when entering the Stop mode */
+#define FLASH_OPTR_NRST_STDBY (1 << 13) /* Bit 13: Generate reset when entering the Standby mode */
+#define FLASH_OPTR_NRST_SHDW (1 << 14) /* Bit 14: Generate reset when entering the Shutdown mode */
+#define FLASH_OPTR_IWDG_SW (1 << 16) /* Bit 16: Independent watchdog selection */
+#define FLASH_OPTR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */
+#define FLASH_OPTR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/
+#define FLASH_OPTR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */
+#define FLASH_OPTR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */
+#define FLASH_OPTR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */
+#define FLASH_OPTR_SRAM_RST (1 << 25) /* Bit 25: SRAM1/2 Erase when system reset */
+#define FLASH_OPTR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */
+#define FLASH_OPTR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */
+
+#define FLASH_OPTR_C1BOOT_LOCK (1 << 30) /* Bit 30: Enable cpu1 boot lock */
+#define FLASH_OPTR_C2BOOT_LOCK (1 << 31) /* Bit 31: Enable cpu2 boot lock */
/* Flash CPU2 Access Control Register (C2ACR) */
-#define FLASH_C2ACR_PRFTEN (1 << 8) /* Bit 8: Enable cpu2 prefetch */
-#define FLASH_C2ACR_ICEN (1 << 9) /* Bit 9: Enable cpu2 instruction cache */
-#define FLASH_C2ACR_ICRST (1 << 11) /* Bit 11: Reset cpu2 instruction cache */
-#define FLASH_C2ACR_PES (1 << 15) /* Bit 15: Suspend cpu2 flash program/erase */
+#define FLASH_C2ACR_PRFTEN (1 << 8) /* Bit 8: Enable cpu2 prefetch */
+#define FLASH_C2ACR_ICEN (1 << 9) /* Bit 9: Enable cpu2 instruction cache */
+#define FLASH_C2ACR_ICRST (1 << 11) /* Bit 11: Reset cpu2 instruction cache */
+#define FLASH_C2ACR_PES (1 << 15) /* Bit 15: Suspend cpu2 flash program/erase */
/* Flash CPU2 Status Register (C2SR) */
-#define FLASH_C2SR_EOP (1 << 0) /* Bit 0: End of operation flag */
-#define FLASH_C2SR_OPERR (1 << 1) /* Bit 1: Operation */
-#define FLASH_C2SR_PROGERR (1 << 3) /* Bit 3: Programming */
-#define FLASH_C2SR_WRPERR (1 << 4) /* Bit 4: Write protection */
-#define FLASH_C2SR_PGAERR (1 << 5) /* Bit 5: Programming alignment */
-#define FLASH_C2SR_SIZERR (1 << 6) /* Bit 6: Size */
-#define FLASH_C2SR_PGSERR (1 << 7) /* Bit 7: Programming sequence */
-#define FLASH_C2SR_MISSERR (1 << 8) /* Bit 8: Fast programming data miss */
-#define FLASH_C2SR_FASTERR (1 << 9) /* Bit 9: Fast programming */
-#define FLASH_C2SR_RDERR (1 << 14) /* Bit 14: PCROP read */
-#define FLASH_C2SR_BSY (1 << 16) /* Bit 16: Busy flag */
-#define FLASH_C2SR_CFGBSY (1 << 18) /* Bit 18: Program or erase configuration busy */
-#define FLASH_C2SR_PESD (1 << 19) /* Bit 19: Program/erase operation suspended */
+#define FLASH_C2SR_EOP (1 << 0) /* Bit 0: End of operation flag */
+#define FLASH_C2SR_OPERR (1 << 1) /* Bit 1: Operation */
+#define FLASH_C2SR_PROGERR (1 << 3) /* Bit 3: Programming */
+#define FLASH_C2SR_WRPERR (1 << 4) /* Bit 4: Write protection */
+#define FLASH_C2SR_PGAERR (1 << 5) /* Bit 5: Programming alignment */
+#define FLASH_C2SR_SIZERR (1 << 6) /* Bit 6: Size */
+#define FLASH_C2SR_PGSERR (1 << 7) /* Bit 7: Programming sequence */
+#define FLASH_C2SR_MISSERR (1 << 8) /* Bit 8: Fast programming data miss */
+#define FLASH_C2SR_FASTERR (1 << 9) /* Bit 9: Fast programming */
+#define FLASH_C2SR_RDERR (1 << 14) /* Bit 14: PCROP read */
+#define FLASH_C2SR_BSY (1 << 16) /* Bit 16: Busy flag */
+#define FLASH_C2SR_CFGBSY (1 << 18) /* Bit 18: Program or erase configuration busy */
+#define FLASH_C2SR_PESD (1 << 19) /* Bit 19: Program/erase operation suspended */
/* Flash CPU2 Control Register (C2CR) */
-#define FLASH_C2CR_PG (1 << 0) /* Bit 0 : Program Page */
-#define FLASH_C2CR_PER (1 << 1) /* Bit 1 : Page Erase */
-#define FLASH_C2CR_MER (1 << 2) /* Bit 2 : Mass Erase */
+#define FLASH_C2CR_PG (1 << 0) /* Bit 0 : Program Page */
+#define FLASH_C2CR_PER (1 << 1) /* Bit 1 : Page Erase */
+#define FLASH_C2CR_MER (1 << 2) /* Bit 2 : Mass Erase */
-#define FLASH_C2CR_PNB_SHIFT (3) /* Bits 3-9: Page number */
-#define FLASH_C2CR_PNB_MASK (0x7F << FLASH_C2CR_PNB_SHIFT)
-#define FLASH_C2CR_PNB(n) ((n) << FLASH_C2CR_PNB_SHIFT) /* Page n, n=0..127 */
+#define FLASH_C2CR_PNB_SHIFT (3) /* Bits 3-9: Page number */
+#define FLASH_C2CR_PNB_MASK (0x7F << FLASH_C2CR_PNB_SHIFT)
+#define FLASH_C2CR_PNB(n) ((n) << FLASH_C2CR_PNB_SHIFT) /* Page n, n=0..127 */
-#define FLASH_C2CR_START (1 << 16) /* Bit 16: Start Erase */
-#define FLASH_C2CR_FSTPG (1 << 18) /* Bit 23: Fast programming */
-#define FLASH_C2CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
-#define FLASH_C2CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
-#define FLASH_C2CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */
+#define FLASH_C2CR_START (1 << 16) /* Bit 16: Start Erase */
+#define FLASH_C2CR_FSTPG (1 << 18) /* Bit 23: Fast programming */
+#define FLASH_C2CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
+#define FLASH_C2CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
+#define FLASH_C2CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */
#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_FLASH_H */
diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.c b/arch/arm/src/stm32wl5/stm32wl5_flash.c
index d79a8e3adf..7fff2d309c 100644
--- a/arch/arm/src/stm32wl5/stm32wl5_flash.c
+++ b/arch/arm/src/stm32wl5/stm32wl5_flash.c
@@ -34,17 +34,17 @@
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/progmem.h>
+#include <nuttx/semaphore.h>
-#include <semaphore.h>
#include <assert.h>
#include <debug.h>
#include <errno.h>
+#include <inttypes.h>
#include <string.h>
#include "stm32wl5_rcc.h"
#include "stm32wl5_waste.h"
#include "stm32wl5_flash.h"
-
#include "arm_internal.h"
#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT)
@@ -57,6 +57,7 @@
#define FLASH_KEY1 0x45670123
#define FLASH_KEY2 0xCDEF89AB
+#define FLASH_ERASEDVALUE 0xffu
#define OPTBYTES_KEY1 0x08192A3B
#define OPTBYTES_KEY2 0x4C5D6E7F
@@ -64,15 +65,7 @@
#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE
#define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4)
#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
-#if FLASH_PAGE_SIZE == 2048
-# define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */
-#elif FLASH_PAGE_SIZE == 4096
-# define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */
-#elif FLASH_PAGE_SIZE == 8192
-# define FLASH_PAGE_SHIFT (13) /* 2**13 = 8192B */
-#else
-# error Unsupported STM32WL5_FLASH_PAGESIZE
-#endif
+#define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */
#define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT)
#define FLASH_CR_PAGE_ERASE FLASH_CR_PER
@@ -99,23 +92,9 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS];
* Private Functions
****************************************************************************/
-static inline void sem_lock(void)
+static inline int sem_lock(void)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&g_sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ return nxsem_wait_uninterruptible(&g_sem);
}
static inline void sem_unlock(void)
@@ -168,10 +147,11 @@ static inline void flash_optbytes_lock(void)
static inline void flash_erase(size_t page)
{
- finfo("erase page %u\n", page);
+ finfo("erase page %u\n", (unsigned int)page);
modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PAGE_ERASE);
- modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page));
+ modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PNB_MASK,
+ FLASH_CR_PNB(page & 0xff));
modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_START);
while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY)
@@ -186,18 +166,36 @@ static inline void flash_erase(size_t page)
* Public Functions
****************************************************************************/
-void stm32wl5_flash_unlock(void)
+int stm32wl5_flash_unlock(void)
{
- sem_lock();
+ int ret;
+
+ ret = sem_lock();
+ if (ret < 0)
+ {
+ return ret;
+ }
+
flash_unlock();
sem_unlock();
+
+ return ret;
}
-void stm32wl5_flash_lock(void)
+int stm32wl5_flash_lock(void)
{
- sem_lock();
+ int ret;
+
+ ret = sem_lock();
+ if (ret < 0)
+ {
+ return ret;
+ }
+
flash_lock();
sem_unlock();
+
+ return ret;
}
/****************************************************************************
@@ -220,6 +218,7 @@ void stm32wl5_flash_lock(void)
uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
{
uint32_t regval;
+ int ret;
/* To avoid accidents, do not allow setting RDP via this function.
* Remove these asserts if want to enable changing the protection level.
@@ -229,19 +228,24 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
DEBUGASSERT((clrbits & FLASH_OPTR_RDP_MASK) == 0);
DEBUGASSERT((setbits & FLASH_OPTR_RDP_MASK) == 0);
- sem_lock();
+ ret = sem_lock();
+ if (ret < 0)
+ {
+ return 0;
+ }
+
flash_optbytes_unlock();
/* Modify Option Bytes in register. */
regval = getreg32(STM32WL5_FLASH_OPTR);
- finfo("Flash option bytes before: 0x%x\n", (unsigned)regval);
+ finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval);
regval = (regval & ~clrbits) | setbits;
putreg32(regval, STM32WL5_FLASH_OPTR);
- finfo("Flash option bytes after: 0x%x\n", (unsigned)regval);
+ finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval);
/* Start Option Bytes programming and wait for completion. */
@@ -260,13 +264,11 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
size_t up_progmem_pagesize(size_t page)
{
- (void)page;
return STM32WL5_FLASH_PAGESIZE;
}
size_t up_progmem_erasesize(size_t block)
{
- (void)block;
return STM32WL5_FLASH_PAGESIZE;
}
@@ -305,41 +307,23 @@ bool up_progmem_isuniform(void)
return true;
}
-ssize_t up_progmem_ispageerased(size_t page)
+ssize_t up_progmem_eraseblock(size_t block)
{
- size_t addr;
- size_t count;
- size_t bwritten = 0;
+ int ret;
- if (page >= STM32WL5_FLASH_NPAGES)
+ if (block >= STM32WL5_FLASH_NPAGES)
{
return -EFAULT;
}
- /* Verify */
-
- for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page);
- count; count--, addr++)
- {
- if (getreg8(addr) != 0xff)
- {
- bwritten++;
- }
- }
-
- return bwritten;
-}
+ /* Erase single block */
-ssize_t up_progmem_eraseblock(size_t block)
-{
- if (block >= STM32WL5_FLASH_NPAGES)
+ ret = sem_lock();
+ if (ret < 0)
{
- return -EFAULT;
+ return (ssize_t)ret;
}
- /* Erase single block */
-
- sem_lock();
flash_unlock();
flash_erase(block);
@@ -359,6 +343,31 @@ ssize_t up_progmem_eraseblock(size_t block)
}
}
+ssize_t up_progmem_ispageerased(size_t page)
+{
+ size_t addr;
+ size_t count;
+ size_t bwritten = 0;
+
+ if (page >= STM32WL5_FLASH_NPAGES)
+ {
+ return -EFAULT;
+ }
+
+ /* Verify */
+
+ for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page);
+ count; count--, addr++)
+ {
+ if (getreg8(addr) != FLASH_ERASEDVALUE)
+ {
+ bwritten++;
+ }
+ }
+
+ return bwritten;
+}
+
ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
{
uint32_t *dest;
@@ -367,6 +376,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
size_t xfrsize;
size_t offset;
size_t page;
+ bool set_pg_bit = false;
int i;
int ret = OK;
@@ -393,7 +403,11 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
dest = (uint32_t *)((uint8_t *)addr - offset);
written = 0;
- sem_lock();
+ ret = sem_lock();
+ if (ret < 0)
+ {
+ return (ssize_t)ret;
+ }
/* Get flash ready and begin flashing. */
@@ -445,6 +459,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
/* Write the page. Must be with double-words. */
modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PG);
+ set_pg_bit = true;
for (i = 0; i < FLASH_PAGE_WORDS; i += 2)
{
@@ -460,7 +475,6 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
if (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR)
{
- modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0);
ret = -EROFS;
goto out;
}
@@ -468,13 +482,13 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
if (getreg32(dest - 1) != *(src - 1) ||
getreg32(dest - 2) != *(src - 2))
{
- modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0);
ret = -EIO;
goto out;
}
}
modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0);
+ set_pg_bit = false;
/* Adjust pointers and counts for the next time through the loop */
@@ -487,15 +501,20 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
}
out:
- /* If there was an error, clear all error flags in status
- * register (rc_w1 register so do this by writing the
- * error bits).
+ if (set_pg_bit)
+ {
+ modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0);
+ }
+
+ /* If there was an error, clear all error flags in status register (rc_w1
+ * register so do this by writing the error bits).
*/
if (ret != OK)
{
- ferr("flash write error: %d, status: 0x%x\n", ret,
- (unsigned)getreg32(STM32WL5_FLASH_SR));
+ ferr("flash write error: %d, status: 0x%" PRIx32 "\n",
+ ret, getreg32(STM32WL5_FLASH_SR));
+
modifyreg32(STM32WL5_FLASH_SR, 0, FLASH_SR_ALLERRS);
}
@@ -503,3 +522,8 @@ out:
sem_unlock();
return (ret == OK) ? written : ret;
}
+
+uint8_t up_progmem_erasestate(void)
+{
+ return FLASH_ERASEDVALUE;
+}
diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.h b/arch/arm/src/stm32wl5/stm32wl5_flash.h
index 9978309d59..a4f70df674 100644
--- a/arch/arm/src/stm32wl5/stm32wl5_flash.h
+++ b/arch/arm/src/stm32wl5/stm32wl5_flash.h
@@ -26,14 +26,16 @@
****************************************************************************/
#include <nuttx/config.h>
+#include <stdint.h>
+
#include "hardware/stm32wl5_flash.h"
/****************************************************************************
- * Public Function Prototypes
+ * Public Functions Prototypes
****************************************************************************/
-void stm32wl5_flash_lock(void);
-void stm32wl5_flash_unlock(void);
+int stm32wl5_flash_lock(void);
+int stm32wl5_flash_unlock(void);
/****************************************************************************
* Name: stm32wl5_flash_user_optbytes