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Posted to commits@tvm.apache.org by GitBox <gi...@apache.org> on 2020/03/04 20:08:32 UTC
[GitHub] [incubator-tvm] pasqoc opened a new pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
pasqoc opened a new pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986
This PR provides fixes to the VTA Chisel implementation, as well as support and enhancements for the tsim and de10nano targets.
With fixes in, the deploy classification tutorial now runs correctly on the de10nano for Resnet18 and Resnet34 workloads, matching the results obtained when running with cpu, fsim, and tsim targets.
A summary of the PR contributions is reported below, more details can be found in the individual commits.
Bug fixes:
* Corrupted DRAM stores and loads when crossing page boundaries.
* Mismatched LoadUop state and output FSM logic.
Enhancements:
* Added de10nano host FPGA programming.
* Enabled de10nano user defined target frequency, tested at 100MHz.
* Improved FSIM/TSIM/FPGA xref debug.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388402428
##########
File path: vta/src/de10nano/de10nano_mgr.h
##########
@@ -0,0 +1,554 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ *
+ * \file de10nano_mgr.h
+ * \brief DE10-Nano fpga manager.
+ */
+
+#ifndef VTA_DE10NANO_DE10NANO_MGR_H_
+#define VTA_DE10NANO_DE10NANO_MGR_H_
+
+extern "C" {
+ #include <fcntl.h>
+ #include <unistd.h>
+ #include <stddef.h>
+ #include <stdint.h>
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <sys/mman.h>
+ #include <sys/types.h>
+ #include <sys/time.h>
+}
+
+// Register definition and address map taken from cv_5v4.pdf,
+// Cyclone V Hard Processor System Technical Reference Manual,
+// chapter 5: FPGA Manager.
+struct de10nano_mgr {
Review comment:
Sure, I don't mind either way.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389284600
##########
File path: vta/python/vta/testing/util.py
##########
@@ -59,8 +59,8 @@ def run(run_func):
tracker_port = os.environ.get("TVM_TRACKER_PORT", None)
# Otherwise, we can set the variables below to directly
# obtain a remote from a test device
- pynq_host = os.environ.get("VTA_PYNQ_RPC_HOST", None)
- pynq_port = os.environ.get("VTA_PYNQ_RPC_PORT", None)
+ pynq_host = os.environ.get("VTA_RPC_HOST", None)
Review comment:
I thought @tmoreau89 requested these changes.
@tmoreau89, @liangfu, @vegaluisjose, please make a collective decision and let me know.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595994939
I have put the linter back in, BTW, so the new linter should not gate this PR.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595991392
Just created Issue #5003 .
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595869658
I suggest changing the timer object to avoid performing the "warming run" job and enable running a single job.
This is also what you may want to do if you add resnet18 tsim to CI and don't want the test to run for ages.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595504375
Any chance the docker image maybe using python2 instead of python3.
Not running docker so not able to reproduce, but it seems the f string is not recognized.
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595967041
I see, if this affects the behavior of the de10nano runs then it's probably a bug on the hardware side (things are not being re-initialized properly)?
The bug fix can be followed up in a subsequent PR, but adding a corner case check to bypass the timer, with a FIXME, or TODO to mention that timer breaks correctness on DE10nano is a way to make sure it's documented and will be followed up on.
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388051460
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -32,16 +32,19 @@ ifeq (, $(VERILATOR_INC_DIR))
endif
endif
-CONFIG = DefaultPynqConfig
+CONFIG = DefaultDe10Config
TOP = VTA
TOP_TEST = Test
BUILD_NAME = build
USE_TRACE = 0
+USE_TRACE_FST = 0
Review comment:
I think we might need a comment here, to notify future users that `USE_TRACE` would default to use VCD as output, and `USE_TRACE_FST` would not take effect if `USE_TRACE` is not enabled.
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389453718
##########
File path: vta/src/de10nano/cma_api.h
##########
@@ -27,6 +27,8 @@
extern "C" {
#endif
+#include <stddef.h>
Review comment:
Thanks, that make total sense.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388575975
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
I really don't mind if lint stays or not.
Given your preference I am going to put it back.
But there is definitely a bug in either scalafmt or the way sbt calls it.
I tried to change the scalafmt configuration to fix the indentation but without success...
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595992450
Nice, thanks! So we'll wait for @liangfu 's linter PR to merge, land that so we can re-enable the linter in your PR.
Seems like we have the Chisel design passing in hardware, and sims; including the CI tests passing.
@liangfu @vegaluisjose can you approve the PR if your comments have been addressed?
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389279439
##########
File path: vta/hardware/intel/scripts/soc_system.tcl
##########
@@ -88,34 +237,486 @@ set_instance_parameter_value hps_0 {MEM_VENDOR} {Other}
set_instance_parameter_value hps_0 {MEM_VERBOSE} {1}
set_instance_parameter_value hps_0 {MEM_VOLTAGE} {1.5V DDR3}
set_instance_parameter_value hps_0 {MEM_WTCL} {7}
-set_instance_parameter_value hps_0 {F2SCLK_COLDRST_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_DBGRST_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_PERIPHCLK_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_SDRAMCLK_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_WARMRST_Enable} {0}
-set_instance_parameter_value hps_0 {LWH2F_Enable} {true}
-set_instance_parameter_value hps_0 {S2F_Width} {0}
-set_instance_parameter_value hps_0 {F2SDRAM_Type} {}
-set_instance_parameter_value hps_0 {F2SDRAM_Width} {}
set_instance_parameter_value hps_0 {MPU_EVENTS_Enable} {0}
+set_instance_parameter_value hps_0 {MRS_MIRROR_PING_PONG_ATSO} {0}
+set_instance_parameter_value hps_0 {MULTICAST_EN} {0}
+set_instance_parameter_value hps_0 {NAND_Mode} {N/A}
+set_instance_parameter_value hps_0 {NAND_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {NEXTGEN} {1}
+set_instance_parameter_value hps_0 {NIOS_ROM_DATA_WIDTH} {32}
+set_instance_parameter_value hps_0 {NUM_DLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {NUM_EXTRA_REPORT_PATH} {10}
+set_instance_parameter_value hps_0 {NUM_OCT_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {NUM_OF_PORTS} {1}
+set_instance_parameter_value hps_0 {NUM_PLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {OCT_SHARING_MODE} {None}
+set_instance_parameter_value hps_0 {P2C_READ_CLOCK_ADD_PHASE} {0.0}
+set_instance_parameter_value hps_0 {PACKAGE_DESKEW} {0}
+set_instance_parameter_value hps_0 {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM} {}
+set_instance_parameter_value hps_0 {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {PHY_CSR_CONNECTION} {INTERNAL_JTAG}
+set_instance_parameter_value hps_0 {PHY_CSR_ENABLED} {0}
+set_instance_parameter_value hps_0 {PHY_ONLY} {0}
+set_instance_parameter_value hps_0 {PINGPONGPHY_EN} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_CLK_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_LOCATION} {Top_Bottom}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_SHARING_MODE} {None}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {POWER_OF_TWO_BUS} {0}
+set_instance_parameter_value hps_0 {PRIORITY_PORT} {1 1 1 1 1 1}
+set_instance_parameter_value hps_0 {QSPI_Mode} {N/A}
+set_instance_parameter_value hps_0 {QSPI_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {RATE} {Full}
+set_instance_parameter_value hps_0 {RDIMM_CONFIG} {0000000000000000}
+set_instance_parameter_value hps_0 {READ_DQ_DQS_CLOCK_SOURCE} {INVERTED_DQS_BUS}
+set_instance_parameter_value hps_0 {READ_FIFO_SIZE} {8}
+set_instance_parameter_value hps_0 {REFRESH_BURST_VALIDATION} {0}
+set_instance_parameter_value hps_0 {REFRESH_INTERVAL} {15000}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ} {125.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_MAX_PARAM} {0.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_MIN_PARAM} {0.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {S2FCLK_COLDRST_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_PENDINGRST_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER0CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER1CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER1CLK_FREQ} {100.0}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK} {5}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK_FREQ} {100.0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CAN_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CLOCKPERIPHERAL_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CTI_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_DMA_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_EMAC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_FPGAMANAGER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_GPIO_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_I2CEMAC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_I2CPERIPHERAL_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_L4TIMER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_NAND_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_OSCTIMER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_QSPI_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SDMMC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SPIMASTER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SPISLAVE_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_UART_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_USB_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_WATCHDOG_Enable} {0}
+set_instance_parameter_value hps_0 {S2F_Width} {0}
+set_instance_parameter_value hps_0 {SDIO_Mode} {N/A}
+set_instance_parameter_value hps_0 {SDIO_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SEQUENCER_TYPE} {NIOS}
+set_instance_parameter_value hps_0 {SEQ_MODE} {0}
+set_instance_parameter_value hps_0 {SKIP_MEM_INIT} {1}
+set_instance_parameter_value hps_0 {SOPC_COMPAT_RESET} {0}
+set_instance_parameter_value hps_0 {SPEED_GRADE} {7}
+set_instance_parameter_value hps_0 {SPIM0_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIM0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIM1_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIM1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIS0_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIS0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIS1_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIS1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {STARVE_LIMIT} {10}
+set_instance_parameter_value hps_0 {STM_Enable} {0}
+set_instance_parameter_value hps_0 {TEST_Enable} {0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_EYE_REDUCTION_H} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_EYE_REDUCTION_SU} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_SKEW} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_SLEW_RATE} {1.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_CK_CKN_SLEW_RATE} {2.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DERATE_METHOD} {AUTO}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQS_DQSN_SLEW_RATE} {2.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_SLEW_RATE} {1.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_ISI_METHOD} {AUTO}
+set_instance_parameter_value hps_0 {TIMING_BOARD_MAX_CK_DELAY} {0.6}
+set_instance_parameter_value hps_0 {TIMING_BOARD_MAX_DQS_DELAY} {0.6}
+set_instance_parameter_value hps_0 {TIMING_BOARD_READ_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_BETWEEN_DIMMS} {0.05}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.01}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {-0.01}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_WITHIN_DQS} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TDH} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TDS} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TIH} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TIS} {0.0}
+set_instance_parameter_value hps_0 {TIMING_TDH} {125}
+set_instance_parameter_value hps_0 {TIMING_TDQSCK} {400}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDL} {1200}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDM} {900}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDS} {450}
+set_instance_parameter_value hps_0 {TIMING_TDQSH} {0.35}
+set_instance_parameter_value hps_0 {TIMING_TDQSQ} {120}
+set_instance_parameter_value hps_0 {TIMING_TDQSS} {0.25}
+set_instance_parameter_value hps_0 {TIMING_TDS} {50}
+set_instance_parameter_value hps_0 {TIMING_TDSH} {0.2}
+set_instance_parameter_value hps_0 {TIMING_TDSS} {0.2}
+set_instance_parameter_value hps_0 {TIMING_TIH} {250}
+set_instance_parameter_value hps_0 {TIMING_TIS} {175}
+set_instance_parameter_value hps_0 {TIMING_TQH} {0.38}
+set_instance_parameter_value hps_0 {TIMING_TQHS} {300}
+set_instance_parameter_value hps_0 {TIMING_TQSH} {0.38}
+set_instance_parameter_value hps_0 {TPIUFPGA_Enable} {0}
+set_instance_parameter_value hps_0 {TPIUFPGA_alt} {0}
+set_instance_parameter_value hps_0 {TRACE_Mode} {N/A}
+set_instance_parameter_value hps_0 {TRACE_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {TRACKING_ERROR_TEST} {0}
+set_instance_parameter_value hps_0 {TRACKING_WATCH_TEST} {0}
+set_instance_parameter_value hps_0 {TREFI} {35100}
+set_instance_parameter_value hps_0 {TRFC} {350}
+set_instance_parameter_value hps_0 {UART0_Mode} {N/A}
+set_instance_parameter_value hps_0 {UART0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {UART1_Mode} {N/A}
+set_instance_parameter_value hps_0 {UART1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USB0_Mode} {N/A}
+set_instance_parameter_value hps_0 {USB0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USB1_Mode} {N/A}
+set_instance_parameter_value hps_0 {USB1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USER_DEBUG_LEVEL} {1}
+set_instance_parameter_value hps_0 {USE_AXI_ADAPTOR} {0}
+set_instance_parameter_value hps_0 {USE_FAKE_PHY} {0}
+set_instance_parameter_value hps_0 {USE_MEM_CLK_FREQ} {0}
+set_instance_parameter_value hps_0 {USE_MM_ADAPTOR} {1}
+set_instance_parameter_value hps_0 {USE_SEQUENCER_BFM} {0}
+set_instance_parameter_value hps_0 {WEIGHT_PORT} {0 0 0 0 0 0}
+set_instance_parameter_value hps_0 {WRBUFFER_ADDR_WIDTH} {6}
+set_instance_parameter_value hps_0 {can0_clk_div} {1}
+set_instance_parameter_value hps_0 {can1_clk_div} {1}
+set_instance_parameter_value hps_0 {configure_advanced_parameters} {0}
+set_instance_parameter_value hps_0 {customize_device_pll_info} {0}
+set_instance_parameter_value hps_0 {dbctrl_stayosc1} {1}
+set_instance_parameter_value hps_0 {dbg_at_clk_div} {0}
+set_instance_parameter_value hps_0 {dbg_clk_div} {1}
+set_instance_parameter_value hps_0 {dbg_trace_clk_div} {0}
+set_instance_parameter_value hps_0 {desired_can0_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_can1_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_cfg_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_emac0_clk_mhz} {250.0}
+set_instance_parameter_value hps_0 {desired_emac1_clk_mhz} {250.0}
+set_instance_parameter_value hps_0 {desired_gpio_db_clk_hz} {32000}
+set_instance_parameter_value hps_0 {desired_l4_mp_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_l4_sp_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_mpu_clk_mhz} {800.0}
+set_instance_parameter_value hps_0 {desired_nand_clk_mhz} {12.5}
+set_instance_parameter_value hps_0 {desired_qspi_clk_mhz} {400.0}
+set_instance_parameter_value hps_0 {desired_sdmmc_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {desired_spi_m_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {desired_usb_mp_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {device_pll_info_manual} {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}}
+set_instance_parameter_value hps_0 {eosc1_clk_mhz} {25.0}
+set_instance_parameter_value hps_0 {eosc2_clk_mhz} {25.0}
+set_instance_parameter_value hps_0 {gpio_db_clk_div} {6249}
+set_instance_parameter_value hps_0 {l3_mp_clk_div} {1}
+set_instance_parameter_value hps_0 {l3_sp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_mp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_mp_clk_source} {1}
+set_instance_parameter_value hps_0 {l4_sp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_sp_clk_source} {1}
+set_instance_parameter_value hps_0 {main_pll_c3} {3}
+set_instance_parameter_value hps_0 {main_pll_c4} {3}
+set_instance_parameter_value hps_0 {main_pll_c5} {15}
+set_instance_parameter_value hps_0 {main_pll_m} {63}
+set_instance_parameter_value hps_0 {main_pll_n} {0}
+set_instance_parameter_value hps_0 {nand_clk_source} {2}
+set_instance_parameter_value hps_0 {periph_pll_c0} {3}
+set_instance_parameter_value hps_0 {periph_pll_c1} {3}
+set_instance_parameter_value hps_0 {periph_pll_c2} {1}
+set_instance_parameter_value hps_0 {periph_pll_c3} {19}
+set_instance_parameter_value hps_0 {periph_pll_c4} {4}
+set_instance_parameter_value hps_0 {periph_pll_c5} {9}
+set_instance_parameter_value hps_0 {periph_pll_m} {79}
+set_instance_parameter_value hps_0 {periph_pll_n} {1}
+set_instance_parameter_value hps_0 {periph_pll_source} {0}
+set_instance_parameter_value hps_0 {qspi_clk_source} {1}
+set_instance_parameter_value hps_0 {sdmmc_clk_source} {2}
+set_instance_parameter_value hps_0 {show_advanced_parameters} {0}
+set_instance_parameter_value hps_0 {show_debug_info_as_warning_msg} {0}
+set_instance_parameter_value hps_0 {show_warning_as_error_msg} {0}
+set_instance_parameter_value hps_0 {spi_m_clk_div} {0}
+set_instance_parameter_value hps_0 {usb_mp_clk_div} {0}
+set_instance_parameter_value hps_0 {use_default_mpu_clk} {1}
-add_instance vta_0 vta 1.0
-
-# connections and connection parameters
-add_connection clk_0.clk hps_0.f2h_axi_clock clock
-add_connection clk_0.clk hps_0.h2f_lw_axi_clock clock
-add_connection clk_0.clk vta_0.clock clock
-add_connection clk_0.clk_reset vta_0.reset reset
-
-add_connection hps_0.h2f_lw_axi_master vta_0.s_axi_control avalon
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control arbitrationPriority {1}
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control baseAddress {0x00020000}
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control defaultConnection {0}
+add_instance pll_0 altera_pll 18.1
+set_instance_parameter_value pll_0 {debug_print_output} {0}
+set_instance_parameter_value pll_0 {debug_use_rbc_taf_method} {0}
+set_instance_parameter_value pll_0 {gui_active_clk} {0}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency0} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency1} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency10} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency11} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency12} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency13} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency14} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency15} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency16} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency17} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency2} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency3} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency4} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency5} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency6} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency7} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency8} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency9} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift0} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift1} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift10} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift11} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift12} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift13} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift14} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift15} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift16} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift17} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift2} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift3} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift4} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift5} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift6} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift7} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift8} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift9} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter0} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter1} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter10} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter11} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter12} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter13} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter14} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter15} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter16} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter17} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter2} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter3} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter4} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter5} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter6} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter7} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter8} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter9} {0}
+set_instance_parameter_value pll_0 {gui_cascade_outclk_index} {0}
+set_instance_parameter_value pll_0 {gui_channel_spacing} {0.0}
+set_instance_parameter_value pll_0 {gui_clk_bad} {0}
+set_instance_parameter_value pll_0 {gui_device_speed_grade} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c0} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c1} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c10} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c11} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c12} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c13} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c14} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c15} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c16} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c17} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c2} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c3} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c4} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c5} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c6} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c7} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c8} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c9} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_n} {1}
+set_instance_parameter_value pll_0 {gui_dps_cntr} {C0}
+set_instance_parameter_value pll_0 {gui_dps_dir} {Positive}
+set_instance_parameter_value pll_0 {gui_dps_num} {1}
+set_instance_parameter_value pll_0 {gui_dsm_out_sel} {1st_order}
+set_instance_parameter_value pll_0 {gui_duty_cycle0} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle1} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle10} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle11} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle12} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle13} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle14} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle15} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle16} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle17} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle2} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle3} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle4} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle5} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle6} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle7} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle8} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle9} {50}
+set_instance_parameter_value pll_0 {gui_en_adv_params} {0}
+set_instance_parameter_value pll_0 {gui_en_dps_ports} {0}
+set_instance_parameter_value pll_0 {gui_en_phout_ports} {0}
+set_instance_parameter_value pll_0 {gui_en_reconf} {0}
+set_instance_parameter_value pll_0 {gui_enable_cascade_in} {0}
+set_instance_parameter_value pll_0 {gui_enable_cascade_out} {0}
+set_instance_parameter_value pll_0 {gui_enable_mif_dps} {0}
+set_instance_parameter_value pll_0 {gui_feedback_clock} {Global Clock}
+set_instance_parameter_value pll_0 {gui_frac_multiply_factor} {1.0}
+set_instance_parameter_value pll_0 {gui_fractional_cout} {32}
+set_instance_parameter_value pll_0 {gui_mif_generate} {0}
+set_instance_parameter_value pll_0 {gui_multiply_factor} {1}
+set_instance_parameter_value pll_0 {gui_number_of_clocks} {1}
+set_instance_parameter_value pll_0 {gui_operation_mode} {normal}
+set_instance_parameter_value pll_0 {gui_output_clock_frequency0} $FREQ_MHZ
+set_instance_parameter_value pll_0 {gui_output_clock_frequency1} {100.0}
Review comment:
No, only output 0 of the PLL is used to feed clock to VTA.
All other outputs are unused.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388629955
##########
File path: vta/tutorials/matrix_multiply.py
##########
@@ -52,7 +52,7 @@
# We configure both the bitstream and the runtime system on the Pynq
# to match the VTA configuration specified by the vta_config.json file.
-if env.TARGET == "pynq":
+if env.TARGET == "pynq" or env.TARGET == "de10nano":
Review comment:
I would prefer to decouple it in a follow up PR, since I have everything tested at this point, if you don't mind.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595502268
Right now the build is failing in runtime.cc, not sure why.
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388021612
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -32,16 +32,19 @@ ifeq (, $(VERILATOR_INC_DIR))
endif
endif
-CONFIG = DefaultPynqConfig
+CONFIG = DefaultDe10Config
Review comment:
If we're going to set the default to DE10, has the PynqConfig been tested in simulation as well in this PR?
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388042452
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
With `--test` argument in `sbt scalafmt`, the linter would not change the code base, see PR #4555 .
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389477855
##########
File path: vta/hardware/intel/scripts/soc_system.tcl
##########
@@ -33,7 +33,156 @@ set_instance_parameter_value clk_0 {clockFrequencyKnown} {1}
set_instance_parameter_value clk_0 {resetSynchronousEdges} {NONE}
add_instance hps_0 altera_hps 18.1
+set_instance_parameter_value hps_0 {ABSTRACT_REAL_COMPARE_TEST} {0}
Review comment:
The size of this generated script increased from 7 KB to 47 KB. What's your opinion on this @tmoreau89 ?
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389453645
##########
File path: vta/python/vta/testing/util.py
##########
@@ -59,8 +59,8 @@ def run(run_func):
tracker_port = os.environ.get("TVM_TRACKER_PORT", None)
# Otherwise, we can set the variables below to directly
# obtain a remote from a test device
- pynq_host = os.environ.get("VTA_PYNQ_RPC_HOST", None)
- pynq_port = os.environ.get("VTA_PYNQ_RPC_PORT", None)
+ pynq_host = os.environ.get("VTA_RPC_HOST", None)
Review comment:
I don't have strong opinion on this, and it's fine to do a separate PR.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388434267
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
But unfortunately it does not work, I invite you to try yourself.
sbt scalafmt --test does change the code.
In my case it changes 6 scala files, for instance:
```diff
diff --git a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala
index 31e0b56bd..f99ac4948 100644
--- a/vta/hardware/chisel/src/main/scala/core/LoadUop.scala
+++ b/vta/hardware/chisel/src/main/scala/core/LoadUop.scala
@@ -118,12 +118,11 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
state := sReadCmd
xlen := xrem
xrem := 0.U
- }
- .otherwise {
- state := sReadCmd
- xlen := xmax - 1.U
- xrem := xrem - xmax
- }
+ }.otherwise {
+ state := sReadCmd
+ xlen := xmax - 1.U
+ xrem := xrem - xmax
+ }
}
}
}
```
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389246425
##########
File path: vta/src/de10nano/cma_api.h
##########
@@ -27,6 +27,8 @@
extern "C" {
#endif
+#include <stddef.h>
Review comment:
Why do we need to add this header file here?
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595390387
Last commit address previous comments.
sbt scalafmt --test is still open since it changes code.
Please let me know what you think.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595985613
For pynq I use a locally generated HLS bitstream.
But I do not get consistent results with pynq.
With m.run() always works, with timer() sometimes it works.
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595593538
Agree with @vegaluisjose on the separate PR; if you submit it, we'll work to merge it quickly so you can rebase against master and get those changes in
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389810505
##########
File path: vta/hardware/intel/scripts/soc_system.tcl
##########
@@ -33,7 +33,156 @@ set_instance_parameter_value clk_0 {clockFrequencyKnown} {1}
set_instance_parameter_value clk_0 {resetSynchronousEdges} {NONE}
add_instance hps_0 altera_hps 18.1
+set_instance_parameter_value hps_0 {ABSTRACT_REAL_COMPARE_TEST} {0}
Review comment:
This file is 760 lines of generated code with a few local modifications, it is not large by any standard and perfectly suitable for github. Apart from the very little return on investment in reducing it if one puts such a high value to file size, doing it seems counter productive. As in the case of this PR, next time one regenerates the script a whole manual diff needs to be done and different versions of the generating tool or even different runs with new components will change the layout of the file. It is no trivial to figure out what is needed and what not and any modifications need to be tested with full spins of bitstream generation and testing. Actually, a robust and agile way for doing this would be to save both the original untouched generated file and the applied patch, so that the patch can be quickly reapplied when the base script is regenerated. Modifying the generated script every time comparing to a manually reduced version has the potential of adding oversights that may be difficult to catch. So all in all, I do not see the benefits of reducing the file size maybe to 10KB? Especially since there are already so many other files larger than this one in the repo.
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389245910
##########
File path: vta/hardware/intel/scripts/soc_system.tcl
##########
@@ -33,7 +33,156 @@ set_instance_parameter_value clk_0 {clockFrequencyKnown} {1}
set_instance_parameter_value clk_0 {resetSynchronousEdges} {NONE}
add_instance hps_0 altera_hps 18.1
+set_instance_parameter_value hps_0 {ABSTRACT_REAL_COMPARE_TEST} {0}
Review comment:
Can we reduce the generated code to a minimal number while preserve this is all functional?
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-596126498
Thanks against for pushing this PR through @pasqoc this work is hugely appreciated by the TVM community!
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-594916203
@vegaluisjose can you also review this PR?
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[GitHub] [incubator-tvm] vegaluisjose commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
vegaluisjose commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389057566
##########
File path: vta/hardware/chisel/src/main/scala/core/TensorStore.scala
##########
@@ -62,20 +62,40 @@ class TensorStore(tensorType: String = "none", debug: Boolean = false)(
val tag = Reg(UInt(8.W))
val set = Reg(UInt(8.W))
+ // Dynamically adjust the size of DMA transfers to avoid crossing page boundaries.
+ final val ADAPTIVE_DMA_XFER_ENABLE = true
Review comment:
Just curious -- is there a way this is false?. If this is fixing the wraparound AXI bug, then we should make it default and update all the code that depend on it. For example:
```
val xfer_init_bytes = if (ADAPTIVE_DMA_XFER_ENABLE) xmax_bytes - xfer_init_addr % xmax_bytes else xmax_bytes
```
will be replaced by
```
val xfer_init_bytes = xmax_bytes - xfer_init_addr % xmax_bytes
```
Same in `TensorUtil.scala`
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389073911
##########
File path: vta/hardware/chisel/src/main/scala/core/TensorStore.scala
##########
@@ -62,20 +62,40 @@ class TensorStore(tensorType: String = "none", debug: Boolean = false)(
val tag = Reg(UInt(8.W))
val set = Reg(UInt(8.W))
+ // Dynamically adjust the size of DMA transfers to avoid crossing page boundaries.
+ final val ADAPTIVE_DMA_XFER_ENABLE = true
Review comment:
Well, this is a limitation, not a feature though, unless you are talking about bug backward compatibility.
Indeed, you may very well have this limitation removed in future versions of AXI or maybe be using other interconnects that do not have it, and you may choose to take advantage of better performance.
That said, I don't mind taking it out, it will save two lines of scala code ;-)
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-596323516
Rebased and made small changes after running new linter.
New linter works great, thanks @liangfu !
Thanks @tmoreau89 , happy to contribute to such an awesome project!
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388057224
##########
File path: vta/tests/python/de10nano/test_program_rpc.py
##########
@@ -0,0 +1,45 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+import sys, os
+import tvm
+from tvm import rpc
+from vta import get_bitstream_path, download_bitstream, program_fpga, reconfig_runtime
+
+host = os.environ.get("VTA_PYNQ_RPC_HOST", "de10nano")
Review comment:
@tmoreau89 Shall we rename this environment variable for targets other than PYNQ?
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595976611
Hi @tmoreau89, actually I observe the same problem with pynq as well, just tried.
If I use m.run() everything works (see results in table), every time, but when I use timer() everything breaks.
When was the last time you testes deploy_classification with pynq?
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-596126449
@liangfu I just merged @liangfu 's scala linter fix: https://github.com/apache/incubator-tvm/pull/4998
If @pasqoc you could rebase against master and make sure that lint passes, that'll be great. You may have to resolve merge conflicts but these may just be linting ones.
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[GitHub] [incubator-tvm] vegaluisjose commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
vegaluisjose commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595512678
I was running into the same issue with the `f-strings` in your code. I think the problem is that we are running `python2` in the [cmake](https://github.com/apache/incubator-tvm/blob/master/cmake/modules/VTA.cmake#L19-L28) maybe @tmoreau89 ?
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595984335
@pasqoc I haven't run the full test recently, but I can do it on my end. Are you using a bitstream generated from Chisel or generated from HLS (e.g. the default one that ships with the example)?
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388056496
##########
File path: vta/src/de10nano/de10nano_mgr.h
##########
@@ -0,0 +1,554 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ *
+ * \file de10nano_mgr.h
+ * \brief DE10-Nano fpga manager.
+ */
+
+#ifndef VTA_DE10NANO_DE10NANO_MGR_H_
+#define VTA_DE10NANO_DE10NANO_MGR_H_
+
+extern "C" {
+ #include <fcntl.h>
+ #include <unistd.h>
+ #include <stddef.h>
+ #include <stdint.h>
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <sys/mman.h>
+ #include <sys/types.h>
+ #include <sys/time.h>
+}
+
+// Register definition and address map taken from cv_5v4.pdf,
+// Cyclone V Hard Processor System Technical Reference Manual,
+// chapter 5: FPGA Manager.
+struct de10nano_mgr {
Review comment:
Please take `CamelCase` for class names.
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-594973729
@vegaluisjose @liangfu this makes me realize that we may want to run CI testing for different FPGA parameterizations in TSIM, e.g. DE10Nano, Pynq, F1. This might consume quite a bit of compute cycles, so they would just be done on unit tests.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388400268
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -32,16 +32,19 @@ ifeq (, $(VERILATOR_INC_DIR))
endif
endif
-CONFIG = DefaultPynqConfig
+CONFIG = DefaultDe10Config
TOP = VTA
TOP_TEST = Test
BUILD_NAME = build
USE_TRACE = 0
+USE_TRACE_FST = 0
Review comment:
Makes sense, although the logic is fairly simple and self-explanatory.
I did not see any comments in the Makefile for any of the configuration variables so I did not want to start adding ones.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389090920
##########
File path: vta/tests/python/de10nano/test_program_rpc.py
##########
@@ -0,0 +1,45 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+import sys, os
+import tvm
+from tvm import rpc
+from vta import get_bitstream_path, download_bitstream, program_fpga, reconfig_runtime
+
+host = os.environ.get("VTA_PYNQ_RPC_HOST", "de10nano")
Review comment:
Agree!
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-596110493
@liangfu, @tmoreau89, for the linter changes I thought we had decided to do them in a different PR. The linter line in Makefile is now unmodified in this PR.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388398027
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
Yes, this is the right way to go.
With --test the user is left to do the actual edits.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-594816587
Hi @tmoreau89, @liangfu, please review the PR and let me know of anything.
Finally deploy classification returns a cat on the de10-nano ... ;-)
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389279439
##########
File path: vta/hardware/intel/scripts/soc_system.tcl
##########
@@ -88,34 +237,486 @@ set_instance_parameter_value hps_0 {MEM_VENDOR} {Other}
set_instance_parameter_value hps_0 {MEM_VERBOSE} {1}
set_instance_parameter_value hps_0 {MEM_VOLTAGE} {1.5V DDR3}
set_instance_parameter_value hps_0 {MEM_WTCL} {7}
-set_instance_parameter_value hps_0 {F2SCLK_COLDRST_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_DBGRST_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_PERIPHCLK_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_SDRAMCLK_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_WARMRST_Enable} {0}
-set_instance_parameter_value hps_0 {LWH2F_Enable} {true}
-set_instance_parameter_value hps_0 {S2F_Width} {0}
-set_instance_parameter_value hps_0 {F2SDRAM_Type} {}
-set_instance_parameter_value hps_0 {F2SDRAM_Width} {}
set_instance_parameter_value hps_0 {MPU_EVENTS_Enable} {0}
+set_instance_parameter_value hps_0 {MRS_MIRROR_PING_PONG_ATSO} {0}
+set_instance_parameter_value hps_0 {MULTICAST_EN} {0}
+set_instance_parameter_value hps_0 {NAND_Mode} {N/A}
+set_instance_parameter_value hps_0 {NAND_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {NEXTGEN} {1}
+set_instance_parameter_value hps_0 {NIOS_ROM_DATA_WIDTH} {32}
+set_instance_parameter_value hps_0 {NUM_DLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {NUM_EXTRA_REPORT_PATH} {10}
+set_instance_parameter_value hps_0 {NUM_OCT_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {NUM_OF_PORTS} {1}
+set_instance_parameter_value hps_0 {NUM_PLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {OCT_SHARING_MODE} {None}
+set_instance_parameter_value hps_0 {P2C_READ_CLOCK_ADD_PHASE} {0.0}
+set_instance_parameter_value hps_0 {PACKAGE_DESKEW} {0}
+set_instance_parameter_value hps_0 {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM} {}
+set_instance_parameter_value hps_0 {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {PHY_CSR_CONNECTION} {INTERNAL_JTAG}
+set_instance_parameter_value hps_0 {PHY_CSR_ENABLED} {0}
+set_instance_parameter_value hps_0 {PHY_ONLY} {0}
+set_instance_parameter_value hps_0 {PINGPONGPHY_EN} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_CLK_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_LOCATION} {Top_Bottom}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_SHARING_MODE} {None}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {POWER_OF_TWO_BUS} {0}
+set_instance_parameter_value hps_0 {PRIORITY_PORT} {1 1 1 1 1 1}
+set_instance_parameter_value hps_0 {QSPI_Mode} {N/A}
+set_instance_parameter_value hps_0 {QSPI_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {RATE} {Full}
+set_instance_parameter_value hps_0 {RDIMM_CONFIG} {0000000000000000}
+set_instance_parameter_value hps_0 {READ_DQ_DQS_CLOCK_SOURCE} {INVERTED_DQS_BUS}
+set_instance_parameter_value hps_0 {READ_FIFO_SIZE} {8}
+set_instance_parameter_value hps_0 {REFRESH_BURST_VALIDATION} {0}
+set_instance_parameter_value hps_0 {REFRESH_INTERVAL} {15000}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ} {125.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_MAX_PARAM} {0.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_MIN_PARAM} {0.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {S2FCLK_COLDRST_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_PENDINGRST_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER0CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER1CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER1CLK_FREQ} {100.0}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK} {5}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK_FREQ} {100.0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CAN_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CLOCKPERIPHERAL_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CTI_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_DMA_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_EMAC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_FPGAMANAGER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_GPIO_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_I2CEMAC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_I2CPERIPHERAL_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_L4TIMER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_NAND_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_OSCTIMER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_QSPI_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SDMMC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SPIMASTER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SPISLAVE_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_UART_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_USB_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_WATCHDOG_Enable} {0}
+set_instance_parameter_value hps_0 {S2F_Width} {0}
+set_instance_parameter_value hps_0 {SDIO_Mode} {N/A}
+set_instance_parameter_value hps_0 {SDIO_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SEQUENCER_TYPE} {NIOS}
+set_instance_parameter_value hps_0 {SEQ_MODE} {0}
+set_instance_parameter_value hps_0 {SKIP_MEM_INIT} {1}
+set_instance_parameter_value hps_0 {SOPC_COMPAT_RESET} {0}
+set_instance_parameter_value hps_0 {SPEED_GRADE} {7}
+set_instance_parameter_value hps_0 {SPIM0_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIM0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIM1_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIM1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIS0_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIS0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIS1_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIS1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {STARVE_LIMIT} {10}
+set_instance_parameter_value hps_0 {STM_Enable} {0}
+set_instance_parameter_value hps_0 {TEST_Enable} {0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_EYE_REDUCTION_H} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_EYE_REDUCTION_SU} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_SKEW} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_SLEW_RATE} {1.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_CK_CKN_SLEW_RATE} {2.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DERATE_METHOD} {AUTO}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQS_DQSN_SLEW_RATE} {2.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_SLEW_RATE} {1.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_ISI_METHOD} {AUTO}
+set_instance_parameter_value hps_0 {TIMING_BOARD_MAX_CK_DELAY} {0.6}
+set_instance_parameter_value hps_0 {TIMING_BOARD_MAX_DQS_DELAY} {0.6}
+set_instance_parameter_value hps_0 {TIMING_BOARD_READ_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_BETWEEN_DIMMS} {0.05}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.01}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {-0.01}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_WITHIN_DQS} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TDH} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TDS} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TIH} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TIS} {0.0}
+set_instance_parameter_value hps_0 {TIMING_TDH} {125}
+set_instance_parameter_value hps_0 {TIMING_TDQSCK} {400}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDL} {1200}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDM} {900}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDS} {450}
+set_instance_parameter_value hps_0 {TIMING_TDQSH} {0.35}
+set_instance_parameter_value hps_0 {TIMING_TDQSQ} {120}
+set_instance_parameter_value hps_0 {TIMING_TDQSS} {0.25}
+set_instance_parameter_value hps_0 {TIMING_TDS} {50}
+set_instance_parameter_value hps_0 {TIMING_TDSH} {0.2}
+set_instance_parameter_value hps_0 {TIMING_TDSS} {0.2}
+set_instance_parameter_value hps_0 {TIMING_TIH} {250}
+set_instance_parameter_value hps_0 {TIMING_TIS} {175}
+set_instance_parameter_value hps_0 {TIMING_TQH} {0.38}
+set_instance_parameter_value hps_0 {TIMING_TQHS} {300}
+set_instance_parameter_value hps_0 {TIMING_TQSH} {0.38}
+set_instance_parameter_value hps_0 {TPIUFPGA_Enable} {0}
+set_instance_parameter_value hps_0 {TPIUFPGA_alt} {0}
+set_instance_parameter_value hps_0 {TRACE_Mode} {N/A}
+set_instance_parameter_value hps_0 {TRACE_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {TRACKING_ERROR_TEST} {0}
+set_instance_parameter_value hps_0 {TRACKING_WATCH_TEST} {0}
+set_instance_parameter_value hps_0 {TREFI} {35100}
+set_instance_parameter_value hps_0 {TRFC} {350}
+set_instance_parameter_value hps_0 {UART0_Mode} {N/A}
+set_instance_parameter_value hps_0 {UART0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {UART1_Mode} {N/A}
+set_instance_parameter_value hps_0 {UART1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USB0_Mode} {N/A}
+set_instance_parameter_value hps_0 {USB0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USB1_Mode} {N/A}
+set_instance_parameter_value hps_0 {USB1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USER_DEBUG_LEVEL} {1}
+set_instance_parameter_value hps_0 {USE_AXI_ADAPTOR} {0}
+set_instance_parameter_value hps_0 {USE_FAKE_PHY} {0}
+set_instance_parameter_value hps_0 {USE_MEM_CLK_FREQ} {0}
+set_instance_parameter_value hps_0 {USE_MM_ADAPTOR} {1}
+set_instance_parameter_value hps_0 {USE_SEQUENCER_BFM} {0}
+set_instance_parameter_value hps_0 {WEIGHT_PORT} {0 0 0 0 0 0}
+set_instance_parameter_value hps_0 {WRBUFFER_ADDR_WIDTH} {6}
+set_instance_parameter_value hps_0 {can0_clk_div} {1}
+set_instance_parameter_value hps_0 {can1_clk_div} {1}
+set_instance_parameter_value hps_0 {configure_advanced_parameters} {0}
+set_instance_parameter_value hps_0 {customize_device_pll_info} {0}
+set_instance_parameter_value hps_0 {dbctrl_stayosc1} {1}
+set_instance_parameter_value hps_0 {dbg_at_clk_div} {0}
+set_instance_parameter_value hps_0 {dbg_clk_div} {1}
+set_instance_parameter_value hps_0 {dbg_trace_clk_div} {0}
+set_instance_parameter_value hps_0 {desired_can0_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_can1_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_cfg_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_emac0_clk_mhz} {250.0}
+set_instance_parameter_value hps_0 {desired_emac1_clk_mhz} {250.0}
+set_instance_parameter_value hps_0 {desired_gpio_db_clk_hz} {32000}
+set_instance_parameter_value hps_0 {desired_l4_mp_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_l4_sp_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_mpu_clk_mhz} {800.0}
+set_instance_parameter_value hps_0 {desired_nand_clk_mhz} {12.5}
+set_instance_parameter_value hps_0 {desired_qspi_clk_mhz} {400.0}
+set_instance_parameter_value hps_0 {desired_sdmmc_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {desired_spi_m_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {desired_usb_mp_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {device_pll_info_manual} {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}}
+set_instance_parameter_value hps_0 {eosc1_clk_mhz} {25.0}
+set_instance_parameter_value hps_0 {eosc2_clk_mhz} {25.0}
+set_instance_parameter_value hps_0 {gpio_db_clk_div} {6249}
+set_instance_parameter_value hps_0 {l3_mp_clk_div} {1}
+set_instance_parameter_value hps_0 {l3_sp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_mp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_mp_clk_source} {1}
+set_instance_parameter_value hps_0 {l4_sp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_sp_clk_source} {1}
+set_instance_parameter_value hps_0 {main_pll_c3} {3}
+set_instance_parameter_value hps_0 {main_pll_c4} {3}
+set_instance_parameter_value hps_0 {main_pll_c5} {15}
+set_instance_parameter_value hps_0 {main_pll_m} {63}
+set_instance_parameter_value hps_0 {main_pll_n} {0}
+set_instance_parameter_value hps_0 {nand_clk_source} {2}
+set_instance_parameter_value hps_0 {periph_pll_c0} {3}
+set_instance_parameter_value hps_0 {periph_pll_c1} {3}
+set_instance_parameter_value hps_0 {periph_pll_c2} {1}
+set_instance_parameter_value hps_0 {periph_pll_c3} {19}
+set_instance_parameter_value hps_0 {periph_pll_c4} {4}
+set_instance_parameter_value hps_0 {periph_pll_c5} {9}
+set_instance_parameter_value hps_0 {periph_pll_m} {79}
+set_instance_parameter_value hps_0 {periph_pll_n} {1}
+set_instance_parameter_value hps_0 {periph_pll_source} {0}
+set_instance_parameter_value hps_0 {qspi_clk_source} {1}
+set_instance_parameter_value hps_0 {sdmmc_clk_source} {2}
+set_instance_parameter_value hps_0 {show_advanced_parameters} {0}
+set_instance_parameter_value hps_0 {show_debug_info_as_warning_msg} {0}
+set_instance_parameter_value hps_0 {show_warning_as_error_msg} {0}
+set_instance_parameter_value hps_0 {spi_m_clk_div} {0}
+set_instance_parameter_value hps_0 {usb_mp_clk_div} {0}
+set_instance_parameter_value hps_0 {use_default_mpu_clk} {1}
-add_instance vta_0 vta 1.0
-
-# connections and connection parameters
-add_connection clk_0.clk hps_0.f2h_axi_clock clock
-add_connection clk_0.clk hps_0.h2f_lw_axi_clock clock
-add_connection clk_0.clk vta_0.clock clock
-add_connection clk_0.clk_reset vta_0.reset reset
-
-add_connection hps_0.h2f_lw_axi_master vta_0.s_axi_control avalon
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control arbitrationPriority {1}
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control baseAddress {0x00020000}
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control defaultConnection {0}
+add_instance pll_0 altera_pll 18.1
+set_instance_parameter_value pll_0 {debug_print_output} {0}
+set_instance_parameter_value pll_0 {debug_use_rbc_taf_method} {0}
+set_instance_parameter_value pll_0 {gui_active_clk} {0}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency0} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency1} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency10} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency11} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency12} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency13} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency14} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency15} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency16} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency17} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency2} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency3} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency4} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency5} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency6} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency7} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency8} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency9} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift0} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift1} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift10} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift11} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift12} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift13} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift14} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift15} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift16} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift17} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift2} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift3} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift4} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift5} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift6} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift7} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift8} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift9} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter0} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter1} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter10} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter11} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter12} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter13} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter14} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter15} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter16} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter17} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter2} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter3} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter4} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter5} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter6} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter7} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter8} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter9} {0}
+set_instance_parameter_value pll_0 {gui_cascade_outclk_index} {0}
+set_instance_parameter_value pll_0 {gui_channel_spacing} {0.0}
+set_instance_parameter_value pll_0 {gui_clk_bad} {0}
+set_instance_parameter_value pll_0 {gui_device_speed_grade} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c0} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c1} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c10} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c11} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c12} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c13} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c14} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c15} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c16} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c17} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c2} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c3} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c4} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c5} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c6} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c7} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c8} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c9} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_n} {1}
+set_instance_parameter_value pll_0 {gui_dps_cntr} {C0}
+set_instance_parameter_value pll_0 {gui_dps_dir} {Positive}
+set_instance_parameter_value pll_0 {gui_dps_num} {1}
+set_instance_parameter_value pll_0 {gui_dsm_out_sel} {1st_order}
+set_instance_parameter_value pll_0 {gui_duty_cycle0} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle1} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle10} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle11} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle12} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle13} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle14} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle15} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle16} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle17} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle2} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle3} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle4} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle5} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle6} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle7} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle8} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle9} {50}
+set_instance_parameter_value pll_0 {gui_en_adv_params} {0}
+set_instance_parameter_value pll_0 {gui_en_dps_ports} {0}
+set_instance_parameter_value pll_0 {gui_en_phout_ports} {0}
+set_instance_parameter_value pll_0 {gui_en_reconf} {0}
+set_instance_parameter_value pll_0 {gui_enable_cascade_in} {0}
+set_instance_parameter_value pll_0 {gui_enable_cascade_out} {0}
+set_instance_parameter_value pll_0 {gui_enable_mif_dps} {0}
+set_instance_parameter_value pll_0 {gui_feedback_clock} {Global Clock}
+set_instance_parameter_value pll_0 {gui_frac_multiply_factor} {1.0}
+set_instance_parameter_value pll_0 {gui_fractional_cout} {32}
+set_instance_parameter_value pll_0 {gui_mif_generate} {0}
+set_instance_parameter_value pll_0 {gui_multiply_factor} {1}
+set_instance_parameter_value pll_0 {gui_number_of_clocks} {1}
+set_instance_parameter_value pll_0 {gui_operation_mode} {normal}
+set_instance_parameter_value pll_0 {gui_output_clock_frequency0} $FREQ_MHZ
+set_instance_parameter_value pll_0 {gui_output_clock_frequency1} {100.0}
Review comment:
No, only output 0 of the PLL is used to feed clock to VTA.
All other output are unused.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389294713
##########
File path: vta/src/de10nano/cma_api.h
##########
@@ -27,6 +27,8 @@
extern "C" {
#endif
+#include <stddef.h>
Review comment:
GCC 7.4.0, the default in my UBUNTU 18.04.3 distro on the DE10-Nano exits with error without it because of undefined **size_t** type.
You may be using an older version that is more lenient in allowing not specifying required headers.
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[GitHub] [incubator-tvm] pasqoc edited a comment on issue #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc edited a comment on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595390387
Last commit addresses previous comments.
sbt scalafmt --test is still open since it changes code.
Please let me know what you think.
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[GitHub] [incubator-tvm] liangfu commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-594992227
> This makes me realize that we may want to run CI testing for different FPGA parameterizations in TSIM, e.g. DE10Nano, Pynq, F1. This might consume quite a bit of compute cycles, so they would just be done on unit tests.
Agree, as long as we preserve at least one TSIM based integration test in the CI.
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595991256
It's possible that some failed experiments left the pynq in a stale state. The CMA drivers that perform pinned page allocation can have a stale state if processes exit without a cleanup / freeing of those pinned pages. It causes subsequent experiments to fail and therefore require a power cycle.
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595995212
> I have put the linter back in, BTW, so the new linter should not gate this PR.
ack
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595969480
It happens with both TSIM and DE10 so most likely it is a runtime issue with Chisel based targets.
I just have not had the time to look into it, this PR only took me already a long time ...
So FIXME needs to be documented for both TSIM and DE10.
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388597868
##########
File path: vta/tutorials/matrix_multiply.py
##########
@@ -52,7 +52,7 @@
# We configure both the bitstream and the runtime system on the Pynq
# to match the VTA configuration specified by the vta_config.json file.
-if env.TARGET == "pynq":
+if env.TARGET == "pynq" or env.TARGET == "de10nano":
Review comment:
Perhaps in this PR I would add a couple methods to the `Environment` class in this file: https://github.com/apache/incubator-tvm/blob/master/vta/python/vta/environment.py
and then call it from these unit tests.
That would help keep the code nice and easy to maintain! If you'd rather not do it, I can do a follow up PR
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-594917196
Thank you @pasqoc for this awesome PR, and extensive fixes to the Chisel codebase. @liangfu , @vegaluisjose and I will help review the PR.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388027401
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
I don't mind if you leave it there.
I personally do make lib only but then I forget, type make and indentation goes berserk, just annoying :-)
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388025042
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -32,16 +32,19 @@ ifeq (, $(VERILATOR_INC_DIR))
endif
endif
-CONFIG = DefaultPynqConfig
+CONFIG = DefaultDe10Config
Review comment:
I was not aware that pynq was also used as a target for Chisel.
Have not tested in simulation, so I would use De10 as the working one.
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388021044
##########
File path: cmake/modules/VTA.cmake
##########
@@ -101,7 +101,9 @@ elseif(PYTHON)
${VTA_TARGET} STREQUAL "ultra96")
target_link_libraries(vta ${__cma_lib})
elseif(${VTA_TARGET} STREQUAL "de10nano") # DE10-Nano rules
- target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21)
+ #target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21)
Review comment:
cleanup?
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388056182
##########
File path: vta/src/de10nano/de10nano_mgr.h
##########
@@ -0,0 +1,554 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ *
+ * \file de10nano_mgr.h
+ * \brief DE10-Nano fpga manager.
+ */
+
+#ifndef VTA_DE10NANO_DE10NANO_MGR_H_
+#define VTA_DE10NANO_DE10NANO_MGR_H_
+
+extern "C" {
Review comment:
I suggest taking the following format
```c
#ifdef __cplusplus
extern "C" {
#endif
// ...
#ifdef __cplusplus
}
#endif
```
In addition, I think this is a C++ header file (please correct me if I understood), it's better to include C++ variant of the standard library, like `#include <cstdint>`
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[GitHub] [incubator-tvm] tmoreau89 merged pull request #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 merged pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389086191
##########
File path: vta/tests/python/de10nano/test_program_rpc.py
##########
@@ -0,0 +1,45 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+import sys, os
+import tvm
+from tvm import rpc
+from vta import get_bitstream_path, download_bitstream, program_fpga, reconfig_runtime
+
+host = os.environ.get("VTA_PYNQ_RPC_HOST", "de10nano")
Review comment:
I see; upon second though it would be cleaner to use `VTA_RPC_HOST` environment variables given that some of our unit tests assume that we're targeting the pynq boards.
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388533974
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
It is indeed an odd indentation choice, but I would be in favor of enabling lint even if the output is odd to have uniformity/consistency across the Chisel codebase. @liangfu @vegaluisjose any input on why the indentation of the `}` looks funky?
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389292372
##########
File path: vta/hardware/intel/scripts/soc_system.tcl
##########
@@ -88,34 +237,486 @@ set_instance_parameter_value hps_0 {MEM_VENDOR} {Other}
set_instance_parameter_value hps_0 {MEM_VERBOSE} {1}
set_instance_parameter_value hps_0 {MEM_VOLTAGE} {1.5V DDR3}
set_instance_parameter_value hps_0 {MEM_WTCL} {7}
-set_instance_parameter_value hps_0 {F2SCLK_COLDRST_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_DBGRST_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_PERIPHCLK_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_SDRAMCLK_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_WARMRST_Enable} {0}
-set_instance_parameter_value hps_0 {LWH2F_Enable} {true}
-set_instance_parameter_value hps_0 {S2F_Width} {0}
-set_instance_parameter_value hps_0 {F2SDRAM_Type} {}
-set_instance_parameter_value hps_0 {F2SDRAM_Width} {}
set_instance_parameter_value hps_0 {MPU_EVENTS_Enable} {0}
+set_instance_parameter_value hps_0 {MRS_MIRROR_PING_PONG_ATSO} {0}
+set_instance_parameter_value hps_0 {MULTICAST_EN} {0}
+set_instance_parameter_value hps_0 {NAND_Mode} {N/A}
+set_instance_parameter_value hps_0 {NAND_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {NEXTGEN} {1}
+set_instance_parameter_value hps_0 {NIOS_ROM_DATA_WIDTH} {32}
+set_instance_parameter_value hps_0 {NUM_DLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {NUM_EXTRA_REPORT_PATH} {10}
+set_instance_parameter_value hps_0 {NUM_OCT_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {NUM_OF_PORTS} {1}
+set_instance_parameter_value hps_0 {NUM_PLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {OCT_SHARING_MODE} {None}
+set_instance_parameter_value hps_0 {P2C_READ_CLOCK_ADD_PHASE} {0.0}
+set_instance_parameter_value hps_0 {PACKAGE_DESKEW} {0}
+set_instance_parameter_value hps_0 {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM} {}
+set_instance_parameter_value hps_0 {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {PHY_CSR_CONNECTION} {INTERNAL_JTAG}
+set_instance_parameter_value hps_0 {PHY_CSR_ENABLED} {0}
+set_instance_parameter_value hps_0 {PHY_ONLY} {0}
+set_instance_parameter_value hps_0 {PINGPONGPHY_EN} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_CLK_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_LOCATION} {Top_Bottom}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_SHARING_MODE} {None}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {POWER_OF_TWO_BUS} {0}
+set_instance_parameter_value hps_0 {PRIORITY_PORT} {1 1 1 1 1 1}
+set_instance_parameter_value hps_0 {QSPI_Mode} {N/A}
+set_instance_parameter_value hps_0 {QSPI_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {RATE} {Full}
+set_instance_parameter_value hps_0 {RDIMM_CONFIG} {0000000000000000}
+set_instance_parameter_value hps_0 {READ_DQ_DQS_CLOCK_SOURCE} {INVERTED_DQS_BUS}
+set_instance_parameter_value hps_0 {READ_FIFO_SIZE} {8}
+set_instance_parameter_value hps_0 {REFRESH_BURST_VALIDATION} {0}
+set_instance_parameter_value hps_0 {REFRESH_INTERVAL} {15000}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ} {125.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_MAX_PARAM} {0.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_MIN_PARAM} {0.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {S2FCLK_COLDRST_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_PENDINGRST_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER0CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER1CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER1CLK_FREQ} {100.0}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK} {5}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK_FREQ} {100.0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CAN_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CLOCKPERIPHERAL_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CTI_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_DMA_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_EMAC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_FPGAMANAGER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_GPIO_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_I2CEMAC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_I2CPERIPHERAL_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_L4TIMER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_NAND_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_OSCTIMER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_QSPI_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SDMMC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SPIMASTER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SPISLAVE_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_UART_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_USB_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_WATCHDOG_Enable} {0}
+set_instance_parameter_value hps_0 {S2F_Width} {0}
+set_instance_parameter_value hps_0 {SDIO_Mode} {N/A}
+set_instance_parameter_value hps_0 {SDIO_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SEQUENCER_TYPE} {NIOS}
+set_instance_parameter_value hps_0 {SEQ_MODE} {0}
+set_instance_parameter_value hps_0 {SKIP_MEM_INIT} {1}
+set_instance_parameter_value hps_0 {SOPC_COMPAT_RESET} {0}
+set_instance_parameter_value hps_0 {SPEED_GRADE} {7}
+set_instance_parameter_value hps_0 {SPIM0_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIM0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIM1_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIM1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIS0_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIS0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIS1_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIS1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {STARVE_LIMIT} {10}
+set_instance_parameter_value hps_0 {STM_Enable} {0}
+set_instance_parameter_value hps_0 {TEST_Enable} {0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_EYE_REDUCTION_H} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_EYE_REDUCTION_SU} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_SKEW} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_SLEW_RATE} {1.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_CK_CKN_SLEW_RATE} {2.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DERATE_METHOD} {AUTO}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQS_DQSN_SLEW_RATE} {2.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_SLEW_RATE} {1.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_ISI_METHOD} {AUTO}
+set_instance_parameter_value hps_0 {TIMING_BOARD_MAX_CK_DELAY} {0.6}
+set_instance_parameter_value hps_0 {TIMING_BOARD_MAX_DQS_DELAY} {0.6}
+set_instance_parameter_value hps_0 {TIMING_BOARD_READ_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_BETWEEN_DIMMS} {0.05}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.01}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {-0.01}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_WITHIN_DQS} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TDH} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TDS} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TIH} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TIS} {0.0}
+set_instance_parameter_value hps_0 {TIMING_TDH} {125}
+set_instance_parameter_value hps_0 {TIMING_TDQSCK} {400}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDL} {1200}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDM} {900}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDS} {450}
+set_instance_parameter_value hps_0 {TIMING_TDQSH} {0.35}
+set_instance_parameter_value hps_0 {TIMING_TDQSQ} {120}
+set_instance_parameter_value hps_0 {TIMING_TDQSS} {0.25}
+set_instance_parameter_value hps_0 {TIMING_TDS} {50}
+set_instance_parameter_value hps_0 {TIMING_TDSH} {0.2}
+set_instance_parameter_value hps_0 {TIMING_TDSS} {0.2}
+set_instance_parameter_value hps_0 {TIMING_TIH} {250}
+set_instance_parameter_value hps_0 {TIMING_TIS} {175}
+set_instance_parameter_value hps_0 {TIMING_TQH} {0.38}
+set_instance_parameter_value hps_0 {TIMING_TQHS} {300}
+set_instance_parameter_value hps_0 {TIMING_TQSH} {0.38}
+set_instance_parameter_value hps_0 {TPIUFPGA_Enable} {0}
+set_instance_parameter_value hps_0 {TPIUFPGA_alt} {0}
+set_instance_parameter_value hps_0 {TRACE_Mode} {N/A}
+set_instance_parameter_value hps_0 {TRACE_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {TRACKING_ERROR_TEST} {0}
+set_instance_parameter_value hps_0 {TRACKING_WATCH_TEST} {0}
+set_instance_parameter_value hps_0 {TREFI} {35100}
+set_instance_parameter_value hps_0 {TRFC} {350}
+set_instance_parameter_value hps_0 {UART0_Mode} {N/A}
+set_instance_parameter_value hps_0 {UART0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {UART1_Mode} {N/A}
+set_instance_parameter_value hps_0 {UART1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USB0_Mode} {N/A}
+set_instance_parameter_value hps_0 {USB0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USB1_Mode} {N/A}
+set_instance_parameter_value hps_0 {USB1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USER_DEBUG_LEVEL} {1}
+set_instance_parameter_value hps_0 {USE_AXI_ADAPTOR} {0}
+set_instance_parameter_value hps_0 {USE_FAKE_PHY} {0}
+set_instance_parameter_value hps_0 {USE_MEM_CLK_FREQ} {0}
+set_instance_parameter_value hps_0 {USE_MM_ADAPTOR} {1}
+set_instance_parameter_value hps_0 {USE_SEQUENCER_BFM} {0}
+set_instance_parameter_value hps_0 {WEIGHT_PORT} {0 0 0 0 0 0}
+set_instance_parameter_value hps_0 {WRBUFFER_ADDR_WIDTH} {6}
+set_instance_parameter_value hps_0 {can0_clk_div} {1}
+set_instance_parameter_value hps_0 {can1_clk_div} {1}
+set_instance_parameter_value hps_0 {configure_advanced_parameters} {0}
+set_instance_parameter_value hps_0 {customize_device_pll_info} {0}
+set_instance_parameter_value hps_0 {dbctrl_stayosc1} {1}
+set_instance_parameter_value hps_0 {dbg_at_clk_div} {0}
+set_instance_parameter_value hps_0 {dbg_clk_div} {1}
+set_instance_parameter_value hps_0 {dbg_trace_clk_div} {0}
+set_instance_parameter_value hps_0 {desired_can0_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_can1_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_cfg_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_emac0_clk_mhz} {250.0}
+set_instance_parameter_value hps_0 {desired_emac1_clk_mhz} {250.0}
+set_instance_parameter_value hps_0 {desired_gpio_db_clk_hz} {32000}
+set_instance_parameter_value hps_0 {desired_l4_mp_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_l4_sp_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_mpu_clk_mhz} {800.0}
+set_instance_parameter_value hps_0 {desired_nand_clk_mhz} {12.5}
+set_instance_parameter_value hps_0 {desired_qspi_clk_mhz} {400.0}
+set_instance_parameter_value hps_0 {desired_sdmmc_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {desired_spi_m_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {desired_usb_mp_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {device_pll_info_manual} {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}}
+set_instance_parameter_value hps_0 {eosc1_clk_mhz} {25.0}
+set_instance_parameter_value hps_0 {eosc2_clk_mhz} {25.0}
+set_instance_parameter_value hps_0 {gpio_db_clk_div} {6249}
+set_instance_parameter_value hps_0 {l3_mp_clk_div} {1}
+set_instance_parameter_value hps_0 {l3_sp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_mp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_mp_clk_source} {1}
+set_instance_parameter_value hps_0 {l4_sp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_sp_clk_source} {1}
+set_instance_parameter_value hps_0 {main_pll_c3} {3}
+set_instance_parameter_value hps_0 {main_pll_c4} {3}
+set_instance_parameter_value hps_0 {main_pll_c5} {15}
+set_instance_parameter_value hps_0 {main_pll_m} {63}
+set_instance_parameter_value hps_0 {main_pll_n} {0}
+set_instance_parameter_value hps_0 {nand_clk_source} {2}
+set_instance_parameter_value hps_0 {periph_pll_c0} {3}
+set_instance_parameter_value hps_0 {periph_pll_c1} {3}
+set_instance_parameter_value hps_0 {periph_pll_c2} {1}
+set_instance_parameter_value hps_0 {periph_pll_c3} {19}
+set_instance_parameter_value hps_0 {periph_pll_c4} {4}
+set_instance_parameter_value hps_0 {periph_pll_c5} {9}
+set_instance_parameter_value hps_0 {periph_pll_m} {79}
+set_instance_parameter_value hps_0 {periph_pll_n} {1}
+set_instance_parameter_value hps_0 {periph_pll_source} {0}
+set_instance_parameter_value hps_0 {qspi_clk_source} {1}
+set_instance_parameter_value hps_0 {sdmmc_clk_source} {2}
+set_instance_parameter_value hps_0 {show_advanced_parameters} {0}
+set_instance_parameter_value hps_0 {show_debug_info_as_warning_msg} {0}
+set_instance_parameter_value hps_0 {show_warning_as_error_msg} {0}
+set_instance_parameter_value hps_0 {spi_m_clk_div} {0}
+set_instance_parameter_value hps_0 {usb_mp_clk_div} {0}
+set_instance_parameter_value hps_0 {use_default_mpu_clk} {1}
-add_instance vta_0 vta 1.0
-
-# connections and connection parameters
-add_connection clk_0.clk hps_0.f2h_axi_clock clock
-add_connection clk_0.clk hps_0.h2f_lw_axi_clock clock
-add_connection clk_0.clk vta_0.clock clock
-add_connection clk_0.clk_reset vta_0.reset reset
-
-add_connection hps_0.h2f_lw_axi_master vta_0.s_axi_control avalon
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control arbitrationPriority {1}
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control baseAddress {0x00020000}
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control defaultConnection {0}
+add_instance pll_0 altera_pll 18.1
+set_instance_parameter_value pll_0 {debug_print_output} {0}
+set_instance_parameter_value pll_0 {debug_use_rbc_taf_method} {0}
+set_instance_parameter_value pll_0 {gui_active_clk} {0}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency0} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency1} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency10} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency11} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency12} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency13} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency14} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency15} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency16} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency17} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency2} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency3} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency4} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency5} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency6} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency7} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency8} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency9} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift0} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift1} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift10} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift11} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift12} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift13} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift14} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift15} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift16} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift17} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift2} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift3} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift4} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift5} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift6} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift7} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift8} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift9} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter0} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter1} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter10} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter11} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter12} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter13} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter14} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter15} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter16} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter17} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter2} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter3} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter4} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter5} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter6} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter7} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter8} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter9} {0}
+set_instance_parameter_value pll_0 {gui_cascade_outclk_index} {0}
+set_instance_parameter_value pll_0 {gui_channel_spacing} {0.0}
+set_instance_parameter_value pll_0 {gui_clk_bad} {0}
+set_instance_parameter_value pll_0 {gui_device_speed_grade} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c0} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c1} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c10} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c11} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c12} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c13} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c14} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c15} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c16} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c17} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c2} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c3} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c4} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c5} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c6} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c7} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c8} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c9} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_n} {1}
+set_instance_parameter_value pll_0 {gui_dps_cntr} {C0}
+set_instance_parameter_value pll_0 {gui_dps_dir} {Positive}
+set_instance_parameter_value pll_0 {gui_dps_num} {1}
+set_instance_parameter_value pll_0 {gui_dsm_out_sel} {1st_order}
+set_instance_parameter_value pll_0 {gui_duty_cycle0} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle1} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle10} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle11} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle12} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle13} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle14} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle15} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle16} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle17} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle2} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle3} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle4} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle5} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle6} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle7} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle8} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle9} {50}
+set_instance_parameter_value pll_0 {gui_en_adv_params} {0}
+set_instance_parameter_value pll_0 {gui_en_dps_ports} {0}
+set_instance_parameter_value pll_0 {gui_en_phout_ports} {0}
+set_instance_parameter_value pll_0 {gui_en_reconf} {0}
+set_instance_parameter_value pll_0 {gui_enable_cascade_in} {0}
+set_instance_parameter_value pll_0 {gui_enable_cascade_out} {0}
+set_instance_parameter_value pll_0 {gui_enable_mif_dps} {0}
+set_instance_parameter_value pll_0 {gui_feedback_clock} {Global Clock}
+set_instance_parameter_value pll_0 {gui_frac_multiply_factor} {1.0}
+set_instance_parameter_value pll_0 {gui_fractional_cout} {32}
+set_instance_parameter_value pll_0 {gui_mif_generate} {0}
+set_instance_parameter_value pll_0 {gui_multiply_factor} {1}
+set_instance_parameter_value pll_0 {gui_number_of_clocks} {1}
+set_instance_parameter_value pll_0 {gui_operation_mode} {normal}
+set_instance_parameter_value pll_0 {gui_output_clock_frequency0} $FREQ_MHZ
+set_instance_parameter_value pll_0 {gui_output_clock_frequency1} {100.0}
Review comment:
@liangfu, please take as long as you need to reproduce on your end.
Note that, as already discussed in the forum sometime ago, I am using an updated de10nano board image I have generated with UBUNTU 18.04.3, 512MB dedicated to CMA.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595517463
Do you want me to remove python from
find_program(PYTHON NAMES python python3 python3.6)
in cmake/modules/VTA.cmake?
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-594980581
I have produced the following table while testing the various targets under same workloads.
Where you see nan it typically means segfault (Resnet50 and Resnet101 and Pynq for Resnet34).
DE10-Nano has a total of 1GB of DRAM with 512MB dedicated to CMA.
Pynq uses the HLS build.
FSIM does computation.
Both DE10-Nano and Pynq run at 100MHz.
Can you explain the differences in match 4 and 5 and with cpu?
| | net | target | graph[s] | offload[s] | inference[s] | match 1 | match 2 | match 3 | match 4 | match 5 |
|----|--------------|----------|------------|--------------|----------------|--------------|--------------|--------------|-----------------|-----------------|
| 0 | resnet18_v1 | cpu | 37.51 | 7.47 | 0.16 | tabby cat | tiger cat | Egyptian cat | welcome mat | carton |
| 1 | resnet18_v1 | fsim | 14.94 | 1.58 | 1.01 | tabby cat | tiger cat | Egyptian cat | welcome mat | plastic bag |
| 2 | resnet18_v1 | tsim | 15.22 | 1.7 | 227.73 | tabby cat | tiger cat | Egyptian cat | welcome mat | plastic bag |
| 3 | resnet18_v1 | de10nano | 15.08 | 2.34 | 0.76 | tabby cat | tiger cat | Egyptian cat | welcome mat | plastic bag |
| 4 | resnet18_v1 | pynq | 15.93 | 2.45 | 0.61 | tabby cat | tiger cat | Egyptian cat | welcome mat | plastic bag |
| 5 | resnet18_v2 | cpu | 45.61 | 8.7 | 0.18 | tabby cat | tiger cat | Egyptian cat | radiator | plastic bag |
| 6 | resnet18_v2 | fsim | 16.6 | 1.95 | 1.08 | Egyptian cat | tabby cat | tiger cat | window screen | shower curtain |
| 7 | resnet18_v2 | tsim | 17.22 | 2.17 | 290.37 | Egyptian cat | tabby cat | tiger cat | window screen | shower curtain |
| 8 | resnet18_v2 | de10nano | 16.38 | 2.47 | 0.77 | Egyptian cat | tabby cat | tiger cat | window screen | shower curtain |
| 9 | resnet18_v2 | pynq | 16.52 | 2.56 | 0.63 | Egyptian cat | tabby cat | tiger cat | window screen | shower curtain |
| 10 | resnet34_v1 | cpu | 38.31 | 7.56 | 0.33 | tabby cat | Egyptian cat | tiger cat | welcome mat | carton |
| 11 | resnet34_v1 | fsim | 17.84 | 2.09 | 2.18 | tabby cat | tiger cat | Egyptian cat | window screen | carton |
| 12 | resnet34_v1 | tsim | 18.54 | 1.92 | 506.25 | tabby cat | tiger cat | Egyptian cat | window screen | carton |
| 13 | resnet34_v1 | de10nano | 18.26 | 2.97 | 1.13 | tabby cat | tiger cat | Egyptian cat | window screen | carton |
| 14 | resnet34_v1 | pynq | 20.27 | 3.03 | 0 | nan | nan | nan | nan | nan |
| 15 | resnet34_v2 | cpu | 42.49 | 8.42 | 0.32 | tabby cat | tiger cat | Egyptian cat | welcome mat | catamount |
| 16 | resnet34_v2 | fsim | 20.22 | 2.3 | 2.14 | tabby cat | Egyptian cat | tiger cat | bathroom tissue | paper towel |
| 17 | resnet34_v2 | tsim | 19.98 | 2.37 | 466.59 | tabby cat | Egyptian cat | tiger cat | paper towel | bathroom tissue |
| 18 | resnet34_v2 | de10nano | 19.67 | 3.21 | 1.13 | tabby cat | Egyptian cat | tiger cat | paper towel | wash-hand basin |
| 19 | resnet34_v2 | pynq | 21.75 | 3.32 | 0 | nan | nan | nan | nan | nan |
| 20 | resnet50_v2 | cpu | 27.34 | 6.45 | 0.41 | Egyptian cat | tabby cat | tiger cat | welcome mat | carton |
| 21 | resnet50_v2 | fsim | 0 | 0 | 0 | nan | nan | nan | nan | nan |
| 22 | resnet50_v2 | tsim | 0 | 0 | 0 | nan | nan | nan | nan | nan |
| 23 | resnet50_v2 | de10nano | 0 | 0 | 0 | nan | nan | nan | nan | nan |
| 24 | resnet50_v2 | pynq | 0 | 0 | 0 | nan | nan | nan | nan | nan |
| 25 | resnet101_v2 | cpu | 27.95 | 6.52 | 0.78 | tabby cat | tiger cat | Egyptian cat | carton | catamount |
| 26 | resnet101_v2 | fsim | 0 | 0 | 0 | nan | nan | nan | nan | nan |
| 27 | resnet101_v2 | tsim | 0 | 0 | 0 | nan | nan | nan | nan | nan |
| 28 | resnet101_v2 | de10nano | 0 | 0 | 0 | nan | nan | nan | nan | nan |
| 29 | resnet101_v2 | pynq | 0 | 0 | 0 | nan | nan | nan | nan | nan |
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-596658449
Thanks @pasqoc @liangfu @vegaluisjose for the work and the reviews; the PR has been merged!
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388021044
##########
File path: cmake/modules/VTA.cmake
##########
@@ -101,7 +101,9 @@ elseif(PYTHON)
${VTA_TARGET} STREQUAL "ultra96")
target_link_libraries(vta ${__cma_lib})
elseif(${VTA_TARGET} STREQUAL "de10nano") # DE10-Nano rules
- target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21)
+ #target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21)
Review comment:
should we remove the line?
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389245691
##########
File path: vta/hardware/intel/scripts/soc_system.tcl
##########
@@ -88,34 +237,486 @@ set_instance_parameter_value hps_0 {MEM_VENDOR} {Other}
set_instance_parameter_value hps_0 {MEM_VERBOSE} {1}
set_instance_parameter_value hps_0 {MEM_VOLTAGE} {1.5V DDR3}
set_instance_parameter_value hps_0 {MEM_WTCL} {7}
-set_instance_parameter_value hps_0 {F2SCLK_COLDRST_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_DBGRST_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_PERIPHCLK_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_SDRAMCLK_Enable} {0}
-set_instance_parameter_value hps_0 {F2SCLK_WARMRST_Enable} {0}
-set_instance_parameter_value hps_0 {LWH2F_Enable} {true}
-set_instance_parameter_value hps_0 {S2F_Width} {0}
-set_instance_parameter_value hps_0 {F2SDRAM_Type} {}
-set_instance_parameter_value hps_0 {F2SDRAM_Width} {}
set_instance_parameter_value hps_0 {MPU_EVENTS_Enable} {0}
+set_instance_parameter_value hps_0 {MRS_MIRROR_PING_PONG_ATSO} {0}
+set_instance_parameter_value hps_0 {MULTICAST_EN} {0}
+set_instance_parameter_value hps_0 {NAND_Mode} {N/A}
+set_instance_parameter_value hps_0 {NAND_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {NEXTGEN} {1}
+set_instance_parameter_value hps_0 {NIOS_ROM_DATA_WIDTH} {32}
+set_instance_parameter_value hps_0 {NUM_DLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {NUM_EXTRA_REPORT_PATH} {10}
+set_instance_parameter_value hps_0 {NUM_OCT_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {NUM_OF_PORTS} {1}
+set_instance_parameter_value hps_0 {NUM_PLL_SHARING_INTERFACES} {1}
+set_instance_parameter_value hps_0 {OCT_SHARING_MODE} {None}
+set_instance_parameter_value hps_0 {P2C_READ_CLOCK_ADD_PHASE} {0.0}
+set_instance_parameter_value hps_0 {PACKAGE_DESKEW} {0}
+set_instance_parameter_value hps_0 {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM} {}
+set_instance_parameter_value hps_0 {PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {PHY_CSR_CONNECTION} {INTERNAL_JTAG}
+set_instance_parameter_value hps_0 {PHY_CSR_ENABLED} {0}
+set_instance_parameter_value hps_0 {PHY_ONLY} {0}
+set_instance_parameter_value hps_0 {PINGPONGPHY_EN} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_CLK_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_LOCATION} {Top_Bottom}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_SHARING_MODE} {None}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_DIV_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_FREQ_PARAM} {0.0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_FREQ_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_MULT_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_PHASE_PS_PARAM} {0}
+set_instance_parameter_value hps_0 {PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM} {}
+set_instance_parameter_value hps_0 {POWER_OF_TWO_BUS} {0}
+set_instance_parameter_value hps_0 {PRIORITY_PORT} {1 1 1 1 1 1}
+set_instance_parameter_value hps_0 {QSPI_Mode} {N/A}
+set_instance_parameter_value hps_0 {QSPI_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {RATE} {Full}
+set_instance_parameter_value hps_0 {RDIMM_CONFIG} {0000000000000000}
+set_instance_parameter_value hps_0 {READ_DQ_DQS_CLOCK_SOURCE} {INVERTED_DQS_BUS}
+set_instance_parameter_value hps_0 {READ_FIFO_SIZE} {8}
+set_instance_parameter_value hps_0 {REFRESH_BURST_VALIDATION} {0}
+set_instance_parameter_value hps_0 {REFRESH_INTERVAL} {15000}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ} {125.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_MAX_PARAM} {0.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_MIN_PARAM} {0.0}
+set_instance_parameter_value hps_0 {REF_CLK_FREQ_PARAM_VALID} {0}
+set_instance_parameter_value hps_0 {S2FCLK_COLDRST_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_PENDINGRST_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER0CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER1CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER1CLK_FREQ} {100.0}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK} {5}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK_Enable} {0}
+set_instance_parameter_value hps_0 {S2FCLK_USER2CLK_FREQ} {100.0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CAN_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CLOCKPERIPHERAL_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_CTI_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_DMA_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_EMAC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_FPGAMANAGER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_GPIO_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_I2CEMAC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_I2CPERIPHERAL_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_L4TIMER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_NAND_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_OSCTIMER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_QSPI_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SDMMC_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SPIMASTER_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_SPISLAVE_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_UART_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_USB_Enable} {0}
+set_instance_parameter_value hps_0 {S2FINTERRUPT_WATCHDOG_Enable} {0}
+set_instance_parameter_value hps_0 {S2F_Width} {0}
+set_instance_parameter_value hps_0 {SDIO_Mode} {N/A}
+set_instance_parameter_value hps_0 {SDIO_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SEQUENCER_TYPE} {NIOS}
+set_instance_parameter_value hps_0 {SEQ_MODE} {0}
+set_instance_parameter_value hps_0 {SKIP_MEM_INIT} {1}
+set_instance_parameter_value hps_0 {SOPC_COMPAT_RESET} {0}
+set_instance_parameter_value hps_0 {SPEED_GRADE} {7}
+set_instance_parameter_value hps_0 {SPIM0_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIM0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIM1_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIM1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIS0_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIS0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {SPIS1_Mode} {N/A}
+set_instance_parameter_value hps_0 {SPIS1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {STARVE_LIMIT} {10}
+set_instance_parameter_value hps_0 {STM_Enable} {0}
+set_instance_parameter_value hps_0 {TEST_Enable} {0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_EYE_REDUCTION_H} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_EYE_REDUCTION_SU} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_SKEW} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_SLEW_RATE} {1.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_CK_CKN_SLEW_RATE} {2.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DERATE_METHOD} {AUTO}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQS_DQSN_SLEW_RATE} {2.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_SLEW_RATE} {1.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_ISI_METHOD} {AUTO}
+set_instance_parameter_value hps_0 {TIMING_BOARD_MAX_CK_DELAY} {0.6}
+set_instance_parameter_value hps_0 {TIMING_BOARD_MAX_DQS_DELAY} {0.6}
+set_instance_parameter_value hps_0 {TIMING_BOARD_READ_DQ_EYE_REDUCTION} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_BETWEEN_DIMMS} {0.05}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.01}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {-0.01}
+set_instance_parameter_value hps_0 {TIMING_BOARD_SKEW_WITHIN_DQS} {0.02}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TDH} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TDS} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TIH} {0.0}
+set_instance_parameter_value hps_0 {TIMING_BOARD_TIS} {0.0}
+set_instance_parameter_value hps_0 {TIMING_TDH} {125}
+set_instance_parameter_value hps_0 {TIMING_TDQSCK} {400}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDL} {1200}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDM} {900}
+set_instance_parameter_value hps_0 {TIMING_TDQSCKDS} {450}
+set_instance_parameter_value hps_0 {TIMING_TDQSH} {0.35}
+set_instance_parameter_value hps_0 {TIMING_TDQSQ} {120}
+set_instance_parameter_value hps_0 {TIMING_TDQSS} {0.25}
+set_instance_parameter_value hps_0 {TIMING_TDS} {50}
+set_instance_parameter_value hps_0 {TIMING_TDSH} {0.2}
+set_instance_parameter_value hps_0 {TIMING_TDSS} {0.2}
+set_instance_parameter_value hps_0 {TIMING_TIH} {250}
+set_instance_parameter_value hps_0 {TIMING_TIS} {175}
+set_instance_parameter_value hps_0 {TIMING_TQH} {0.38}
+set_instance_parameter_value hps_0 {TIMING_TQHS} {300}
+set_instance_parameter_value hps_0 {TIMING_TQSH} {0.38}
+set_instance_parameter_value hps_0 {TPIUFPGA_Enable} {0}
+set_instance_parameter_value hps_0 {TPIUFPGA_alt} {0}
+set_instance_parameter_value hps_0 {TRACE_Mode} {N/A}
+set_instance_parameter_value hps_0 {TRACE_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {TRACKING_ERROR_TEST} {0}
+set_instance_parameter_value hps_0 {TRACKING_WATCH_TEST} {0}
+set_instance_parameter_value hps_0 {TREFI} {35100}
+set_instance_parameter_value hps_0 {TRFC} {350}
+set_instance_parameter_value hps_0 {UART0_Mode} {N/A}
+set_instance_parameter_value hps_0 {UART0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {UART1_Mode} {N/A}
+set_instance_parameter_value hps_0 {UART1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USB0_Mode} {N/A}
+set_instance_parameter_value hps_0 {USB0_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USB1_Mode} {N/A}
+set_instance_parameter_value hps_0 {USB1_PinMuxing} {Unused}
+set_instance_parameter_value hps_0 {USER_DEBUG_LEVEL} {1}
+set_instance_parameter_value hps_0 {USE_AXI_ADAPTOR} {0}
+set_instance_parameter_value hps_0 {USE_FAKE_PHY} {0}
+set_instance_parameter_value hps_0 {USE_MEM_CLK_FREQ} {0}
+set_instance_parameter_value hps_0 {USE_MM_ADAPTOR} {1}
+set_instance_parameter_value hps_0 {USE_SEQUENCER_BFM} {0}
+set_instance_parameter_value hps_0 {WEIGHT_PORT} {0 0 0 0 0 0}
+set_instance_parameter_value hps_0 {WRBUFFER_ADDR_WIDTH} {6}
+set_instance_parameter_value hps_0 {can0_clk_div} {1}
+set_instance_parameter_value hps_0 {can1_clk_div} {1}
+set_instance_parameter_value hps_0 {configure_advanced_parameters} {0}
+set_instance_parameter_value hps_0 {customize_device_pll_info} {0}
+set_instance_parameter_value hps_0 {dbctrl_stayosc1} {1}
+set_instance_parameter_value hps_0 {dbg_at_clk_div} {0}
+set_instance_parameter_value hps_0 {dbg_clk_div} {1}
+set_instance_parameter_value hps_0 {dbg_trace_clk_div} {0}
+set_instance_parameter_value hps_0 {desired_can0_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_can1_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_cfg_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_emac0_clk_mhz} {250.0}
+set_instance_parameter_value hps_0 {desired_emac1_clk_mhz} {250.0}
+set_instance_parameter_value hps_0 {desired_gpio_db_clk_hz} {32000}
+set_instance_parameter_value hps_0 {desired_l4_mp_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_l4_sp_clk_mhz} {100.0}
+set_instance_parameter_value hps_0 {desired_mpu_clk_mhz} {800.0}
+set_instance_parameter_value hps_0 {desired_nand_clk_mhz} {12.5}
+set_instance_parameter_value hps_0 {desired_qspi_clk_mhz} {400.0}
+set_instance_parameter_value hps_0 {desired_sdmmc_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {desired_spi_m_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {desired_usb_mp_clk_mhz} {200.0}
+set_instance_parameter_value hps_0 {device_pll_info_manual} {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}}
+set_instance_parameter_value hps_0 {eosc1_clk_mhz} {25.0}
+set_instance_parameter_value hps_0 {eosc2_clk_mhz} {25.0}
+set_instance_parameter_value hps_0 {gpio_db_clk_div} {6249}
+set_instance_parameter_value hps_0 {l3_mp_clk_div} {1}
+set_instance_parameter_value hps_0 {l3_sp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_mp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_mp_clk_source} {1}
+set_instance_parameter_value hps_0 {l4_sp_clk_div} {1}
+set_instance_parameter_value hps_0 {l4_sp_clk_source} {1}
+set_instance_parameter_value hps_0 {main_pll_c3} {3}
+set_instance_parameter_value hps_0 {main_pll_c4} {3}
+set_instance_parameter_value hps_0 {main_pll_c5} {15}
+set_instance_parameter_value hps_0 {main_pll_m} {63}
+set_instance_parameter_value hps_0 {main_pll_n} {0}
+set_instance_parameter_value hps_0 {nand_clk_source} {2}
+set_instance_parameter_value hps_0 {periph_pll_c0} {3}
+set_instance_parameter_value hps_0 {periph_pll_c1} {3}
+set_instance_parameter_value hps_0 {periph_pll_c2} {1}
+set_instance_parameter_value hps_0 {periph_pll_c3} {19}
+set_instance_parameter_value hps_0 {periph_pll_c4} {4}
+set_instance_parameter_value hps_0 {periph_pll_c5} {9}
+set_instance_parameter_value hps_0 {periph_pll_m} {79}
+set_instance_parameter_value hps_0 {periph_pll_n} {1}
+set_instance_parameter_value hps_0 {periph_pll_source} {0}
+set_instance_parameter_value hps_0 {qspi_clk_source} {1}
+set_instance_parameter_value hps_0 {sdmmc_clk_source} {2}
+set_instance_parameter_value hps_0 {show_advanced_parameters} {0}
+set_instance_parameter_value hps_0 {show_debug_info_as_warning_msg} {0}
+set_instance_parameter_value hps_0 {show_warning_as_error_msg} {0}
+set_instance_parameter_value hps_0 {spi_m_clk_div} {0}
+set_instance_parameter_value hps_0 {usb_mp_clk_div} {0}
+set_instance_parameter_value hps_0 {use_default_mpu_clk} {1}
-add_instance vta_0 vta 1.0
-
-# connections and connection parameters
-add_connection clk_0.clk hps_0.f2h_axi_clock clock
-add_connection clk_0.clk hps_0.h2f_lw_axi_clock clock
-add_connection clk_0.clk vta_0.clock clock
-add_connection clk_0.clk_reset vta_0.reset reset
-
-add_connection hps_0.h2f_lw_axi_master vta_0.s_axi_control avalon
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control arbitrationPriority {1}
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control baseAddress {0x00020000}
-set_connection_parameter_value hps_0.h2f_lw_axi_master/vta_0.s_axi_control defaultConnection {0}
+add_instance pll_0 altera_pll 18.1
+set_instance_parameter_value pll_0 {debug_print_output} {0}
+set_instance_parameter_value pll_0 {debug_use_rbc_taf_method} {0}
+set_instance_parameter_value pll_0 {gui_active_clk} {0}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency0} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency1} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency10} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency11} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency12} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency13} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency14} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency15} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency16} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency17} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency2} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency3} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency4} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency5} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency6} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency7} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency8} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_output_clock_frequency9} {0 MHz}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift0} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift1} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift10} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift11} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift12} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift13} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift14} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift15} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift16} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift17} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift2} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift3} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift4} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift5} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift6} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift7} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift8} {0}
+set_instance_parameter_value pll_0 {gui_actual_phase_shift9} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter0} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter1} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter10} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter11} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter12} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter13} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter14} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter15} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter16} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter17} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter2} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter3} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter4} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter5} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter6} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter7} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter8} {0}
+set_instance_parameter_value pll_0 {gui_cascade_counter9} {0}
+set_instance_parameter_value pll_0 {gui_cascade_outclk_index} {0}
+set_instance_parameter_value pll_0 {gui_channel_spacing} {0.0}
+set_instance_parameter_value pll_0 {gui_clk_bad} {0}
+set_instance_parameter_value pll_0 {gui_device_speed_grade} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c0} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c1} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c10} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c11} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c12} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c13} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c14} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c15} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c16} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c17} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c2} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c3} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c4} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c5} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c6} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c7} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c8} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_c9} {1}
+set_instance_parameter_value pll_0 {gui_divide_factor_n} {1}
+set_instance_parameter_value pll_0 {gui_dps_cntr} {C0}
+set_instance_parameter_value pll_0 {gui_dps_dir} {Positive}
+set_instance_parameter_value pll_0 {gui_dps_num} {1}
+set_instance_parameter_value pll_0 {gui_dsm_out_sel} {1st_order}
+set_instance_parameter_value pll_0 {gui_duty_cycle0} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle1} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle10} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle11} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle12} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle13} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle14} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle15} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle16} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle17} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle2} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle3} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle4} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle5} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle6} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle7} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle8} {50}
+set_instance_parameter_value pll_0 {gui_duty_cycle9} {50}
+set_instance_parameter_value pll_0 {gui_en_adv_params} {0}
+set_instance_parameter_value pll_0 {gui_en_dps_ports} {0}
+set_instance_parameter_value pll_0 {gui_en_phout_ports} {0}
+set_instance_parameter_value pll_0 {gui_en_reconf} {0}
+set_instance_parameter_value pll_0 {gui_enable_cascade_in} {0}
+set_instance_parameter_value pll_0 {gui_enable_cascade_out} {0}
+set_instance_parameter_value pll_0 {gui_enable_mif_dps} {0}
+set_instance_parameter_value pll_0 {gui_feedback_clock} {Global Clock}
+set_instance_parameter_value pll_0 {gui_frac_multiply_factor} {1.0}
+set_instance_parameter_value pll_0 {gui_fractional_cout} {32}
+set_instance_parameter_value pll_0 {gui_mif_generate} {0}
+set_instance_parameter_value pll_0 {gui_multiply_factor} {1}
+set_instance_parameter_value pll_0 {gui_number_of_clocks} {1}
+set_instance_parameter_value pll_0 {gui_operation_mode} {normal}
+set_instance_parameter_value pll_0 {gui_output_clock_frequency0} $FREQ_MHZ
+set_instance_parameter_value pll_0 {gui_output_clock_frequency1} {100.0}
Review comment:
Should this be $FREQ_MHZ as well?
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595474164
It looks like at the moment the cpp lint test is failing: https://ci.tvm.ai/blue/organizations/jenkins/tvm/detail/PR-4986/5/pipeline
You may have to go in and address the lint errors in `vta/src/de10nano/de10nano_mgr.h`
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389246377
##########
File path: vta/python/vta/testing/util.py
##########
@@ -59,8 +59,8 @@ def run(run_func):
tracker_port = os.environ.get("TVM_TRACKER_PORT", None)
# Otherwise, we can set the variables below to directly
# obtain a remote from a test device
- pynq_host = os.environ.get("VTA_PYNQ_RPC_HOST", None)
- pynq_port = os.environ.get("VTA_PYNQ_RPC_PORT", None)
+ pynq_host = os.environ.get("VTA_RPC_HOST", None)
Review comment:
I think we should be careful when we make changes like this, since the tutorial pages in the document should be updated as well. As suggested by @tmoreau89 , this would be changed in a separate PR, would you please undo the changes to the environment variable?
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595971376
Sure, no problem.
I'll give it a stab if I have time anyway :-)
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389282347
##########
File path: vta/hardware/intel/scripts/soc_system.tcl
##########
@@ -33,7 +33,156 @@ set_instance_parameter_value clk_0 {clockFrequencyKnown} {1}
set_instance_parameter_value clk_0 {resetSynchronousEdges} {NONE}
add_instance hps_0 altera_hps 18.1
+set_instance_parameter_value hps_0 {ABSTRACT_REAL_COMPARE_TEST} {0}
Review comment:
I personally feel like this is unnecessary and not a good use of cognitive time and extra test time after the changes :-)
But if you want I don't mind you to remove the extra lines in a different PR.
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388688246
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
I think it's better to replace scala linter from `scalafmt` to `scalatyle`, the former focus on changing the code format to a predefined style (it removed --test argument lately I think), and the later focus on checking style errors with no intention in changing the code base. I can put an update to switch the linter for scala, if you would like @tmoreau89 @vegaluisjose .
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389088721
##########
File path: vta/hardware/chisel/src/main/scala/core/TensorStore.scala
##########
@@ -62,20 +62,40 @@ class TensorStore(tensorType: String = "none", debug: Boolean = false)(
val tag = Reg(UInt(8.W))
val set = Reg(UInt(8.W))
+ // Dynamically adjust the size of DMA transfers to avoid crossing page boundaries.
+ final val ADAPTIVE_DMA_XFER_ENABLE = true
Review comment:
Ok, will do shortly!
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389086618
##########
File path: vta/tutorials/matrix_multiply.py
##########
@@ -52,7 +52,7 @@
# We configure both the bitstream and the runtime system on the Pynq
# to match the VTA configuration specified by the vta_config.json file.
-if env.TARGET == "pynq":
+if env.TARGET == "pynq" or env.TARGET == "de10nano":
Review comment:
Ok, that is fair, thanks
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595919837
The same problem happens for de10nano as well, not just sim.
To make it simple we could add another option warm_up with default true to timer so you can just set timer in CI runs or other tests, without changing anything else.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595457508
General question.
I see the CI jenkins merge-hook build fails for reasons other than the PR itself (not right now, I need to change include order to pass lint after the last commit).
Is it a requirement to have this build pass?
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388572722
##########
File path: vta/tutorials/matrix_multiply.py
##########
@@ -52,7 +52,7 @@
# We configure both the bitstream and the runtime system on the Pynq
# to match the VTA configuration specified by the vta_config.json file.
-if env.TARGET == "pynq":
+if env.TARGET == "pynq" or env.TARGET == "de10nano":
Review comment:
Totally agree.
Do you want me to remove the de10nano check at this point.
I just wanted to document how to invoke a test with the de10nano target.
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389303551
##########
File path: vta/python/vta/testing/util.py
##########
@@ -59,8 +59,8 @@ def run(run_func):
tracker_port = os.environ.get("TVM_TRACKER_PORT", None)
# Otherwise, we can set the variables below to directly
# obtain a remote from a test device
- pynq_host = os.environ.get("VTA_PYNQ_RPC_HOST", None)
- pynq_port = os.environ.get("VTA_PYNQ_RPC_PORT", None)
+ pynq_host = os.environ.get("VTA_RPC_HOST", None)
Review comment:
I did indeed make the request, and grep for all occurrences of `VTA_PYNQ_RPC_HOST` to update documentation (including tutorials). I agree with @liangfu that documentation needs to be updated accordingly, but I think that for the sake of expediency, we can do it all in this PR. If you are strongly opposed to this @liangfu I think that we can go back to keeping the variables as `VTA_PYNQ_RPC_HOST` and modifying it in a subsequent PR. Please let @pasqoc how you'd like to proceed.
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[GitHub] [incubator-tvm] vegaluisjose commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
vegaluisjose commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388703764
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
Hey @liangfu ,
that sounds like a plan. Let's do it in a separate PR. I saw the chisel template is also using that.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-594935354
You are welcome!
Sorry I forgot to lint, doing next.
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388025984
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
Oh I just saw your newest commits. @vegaluisjose set up the Chisel linter, he can chime in on what the best course of action is moving forward. It would be nice to keep linting the code for future submissions.
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388021304
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
what was the reason for removing lint here?
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-594974692
I have tested unit tests, conv2d, and deploy classification for tsim and de10 for Chisel with De10Config only.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595993460
Let me commit the changes requested by @vegaluisjose.
I also have the VTA_PYNQ_* to VTA_* renamed variables tested.
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388532585
##########
File path: vta/tests/python/de10nano/test_program_rpc.py
##########
@@ -0,0 +1,45 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+import sys, os
+import tvm
+from tvm import rpc
+from vta import get_bitstream_path, download_bitstream, program_fpga, reconfig_runtime
+
+host = os.environ.get("VTA_PYNQ_RPC_HOST", "de10nano")
Review comment:
I think I've been using this variable to be able to target and program different FPGAs. For in that spririt, I would use `VTA_DE10_RPC_HOST` for this test. Your bashrc could contain multiple hosts including `VTA_PYNQ_RPC_HOST`, `VTA_DE10_RPC_HOST`, `VTA_ULTRA96_RPC_HOST` etc.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389060772
##########
File path: vta/hardware/chisel/src/main/scala/core/TensorStore.scala
##########
@@ -62,20 +62,40 @@ class TensorStore(tensorType: String = "none", debug: Boolean = false)(
val tag = Reg(UInt(8.W))
val set = Reg(UInt(8.W))
+ // Dynamically adjust the size of DMA transfers to avoid crossing page boundaries.
+ final val ADAPTIVE_DMA_XFER_ENABLE = true
Review comment:
There is small cost that the fix adds in terms of timing, which could be mitigated with a refactoring of the FSM.
I was not sure whether the wraparound problem is a systematic limitation or not so I decided to add it in a parametric way just in case another platform does no exhibits the issue.
I left the static constant there but one could drive it from the Configs.scala file if needed.
The idea is to turn it off when trying another platform and if successful set the parameter to false in a config file.
Does it make sense?
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595916237
@pasqoc I suggest that we change the script in the CI to not use the timer and just invoke `m.run()` for simulation based targets. The warmup round is needed for hardware targets for stable performance measurements. I think it's totally fine to use m.run for sim targets, and the timer for FPGA runs. I agree that we shouldn't run 12 rounds of simulation in the CI that's definitely overkill :)
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595876389
Resnet18_v1 should only take 31M cycles for one run and around 5 minutes, so you are running 12 jobs in around an hour.
Also if you want to cross reference the results reported on the table I have used a tabby cat image directly downloaded from ImageNet because I wanted to be sure to get the correct expected result.
Using the default cat image may give you a tiger cat instead ...
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595970177
That's a fair assessment, let's go with m.run() as default with a comment about timer causing failures on the Chisel based designs. It's fine if you choose not to address/investigate the bug; do you mind creating a Github issue for it? thanks
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595877573
I can add the changes to timer if you want me to, and then changing num = rep = 1 in deploy_classification.py should make the test pass.
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[GitHub] [incubator-tvm] vegaluisjose commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
vegaluisjose commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595590569
Hey @pasqoc ,
I just ran/build everything in both Linux/Mac but it seems to be failing consistently in `resnet18v1`. I am getting the following
```
[traced 408M cycles]
Execution statistics:
cycle_count : 31427003
resnet18_v1 prediction for sample 0
#1: grocery store, grocery, food market, market
#2: scale, weighing machine
#3: banana
#4: punching bag, punch bag, punching ball, punchball
#5: cleaver, meat cleaver, chopper
Traceback (most recent call last):
File "deploy_classification.py", line 290, in <module>
assert(cat_detected)
AssertionError
```
Perhaps I am missing something? I built everything directly from your `de10-nano` branch
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[GitHub] [incubator-tvm] vegaluisjose commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
vegaluisjose commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389079967
##########
File path: vta/hardware/chisel/src/main/scala/core/TensorStore.scala
##########
@@ -62,20 +62,40 @@ class TensorStore(tensorType: String = "none", debug: Boolean = false)(
val tag = Reg(UInt(8.W))
val set = Reg(UInt(8.W))
+ // Dynamically adjust the size of DMA transfers to avoid crossing page boundaries.
+ final val ADAPTIVE_DMA_XFER_ENABLE = true
Review comment:
Yeah, I think we can remove it here and in `TensorUtil.scala`.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388403925
##########
File path: vta/tests/python/de10nano/test_program_rpc.py
##########
@@ -0,0 +1,45 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+import sys, os
+import tvm
+from tvm import rpc
+from vta import get_bitstream_path, download_bitstream, program_fpga, reconfig_runtime
+
+host = os.environ.get("VTA_PYNQ_RPC_HOST", "de10nano")
Review comment:
I was also confused when I first browsed the code.
I would have expected something like:
VTA_RPC_HOST = {pynq|de10nano|ultra96|etc}
VTA_RPC_PORT = 9091
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388053279
##########
File path: vta/hardware/chisel/src/main/scala/core/TensorLoad.scala
##########
@@ -212,14 +212,16 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)(
when(state === sIdle) {
waddr_cur := dec.sram_offset
waddr_nxt := dec.sram_offset
- }.elsewhen((io.vme_rd.data
- .fire() || isZeroPad) && set === (tp.tensorLength - 1).U && tag === (tp.numMemBlock - 1).U) {
- waddr_cur := waddr_cur + 1.U
- }
- .elsewhen(dataCtrl.io.stride) {
- waddr_cur := waddr_nxt + dec.xsize
- waddr_nxt := waddr_nxt + dec.xsize
- }
+ }.elsewhen((io.vme_rd.data.fire() || isZeroPad) &&
+ set === (tp.tensorLength - 1).U &&
+ tag === (tp.numMemBlock - 1).U)
+ {
Review comment:
I think the linter might remind you to move the bracket to the previous line.
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388026025
##########
File path: cmake/modules/VTA.cmake
##########
@@ -101,7 +101,9 @@ elseif(PYTHON)
${VTA_TARGET} STREQUAL "ultra96")
target_link_libraries(vta ${__cma_lib})
elseif(${VTA_TARGET} STREQUAL "de10nano") # DE10-Nano rules
- target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21)
+ #target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21)
Review comment:
Great thanks!
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595993915
Once this PR lands, I'll add e2e unit testing in TSIM on a variant of the ResNet-18 tutorial
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388535249
##########
File path: vta/tutorials/matrix_multiply.py
##########
@@ -52,7 +52,7 @@
# We configure both the bitstream and the runtime system on the Pynq
# to match the VTA configuration specified by the vta_config.json file.
-if env.TARGET == "pynq":
+if env.TARGET == "pynq" or env.TARGET == "de10nano":
Review comment:
To keep the code maintainable as we scale the number of supported FPGAs, we should a function in the environment.py library that essentially checks the target against a list of FPGA target and used as such: `env.target_is_fpga()` for all of the FPGA delineations, and `env.target_is_sim()` for tsim, fsim
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595867732
One think I forgot to mention (and I did not change the deploy_classification.py code in the branch) is that currently you must avoid using the timer when doing inference.
There is some interaction I have not debugged yet that makes the runs started by timer subsequent to the first one fail for all chisel based targets.
Right now you must call the model once directly, i.e. disable the timer object and call m.run() instead of timer() on line 255.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388021605
##########
File path: cmake/modules/VTA.cmake
##########
@@ -101,7 +101,9 @@ elseif(PYTHON)
${VTA_TARGET} STREQUAL "ultra96")
target_link_libraries(vta ${__cma_lib})
elseif(${VTA_TARGET} STREQUAL "de10nano") # DE10-Nano rules
- target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21)
+ #target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21)
Review comment:
I only left the comment there for reference, I suppose it can go.
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[GitHub] [incubator-tvm] liangfu commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
liangfu commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389454356
##########
File path: vta/hardware/intel/scripts/soc_system.tcl
##########
@@ -33,7 +33,156 @@ set_instance_parameter_value clk_0 {clockFrequencyKnown} {1}
set_instance_parameter_value clk_0 {resetSynchronousEdges} {NONE}
add_instance hps_0 altera_hps 18.1
+set_instance_parameter_value hps_0 {ABSTRACT_REAL_COMPARE_TEST} {0}
Review comment:
Thanks again for pushing this through @pasqoc , I think it's fine to have follow-up PRs on this.
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[GitHub] [incubator-tvm] vegaluisjose commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
vegaluisjose commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595522233
I think it would be nice to do that in a separate PR.
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[GitHub] [incubator-tvm] tmoreau89 commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595986283
Does the default HLS generated bitstream produce the right results then? It could very well be a broader issue with the Chisel design and therefore may not even be DE10 specific.
If you create the issue, @liangfu , @vegaluisjose and I can look into it and investigate.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595989200
After restarting the pynq board both downloaded and local bitstreams seem to work now. I need to remember to power cycle the pynq after attempts to run Resnet34, 50, 101, by my benchmark script. That seems to break the pynq ..... But I am not entirely sure since I did not run the benchmarks recently and pynq was fine ... mmmh
I will create the issue, but you can already reproduce as @vegaluisjose has done with TSIM.
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[GitHub] [incubator-tvm] pasqoc commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595514049
Just removed them, but f strings are so much better .....
Any particular reason why python 2 is still used?
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[GitHub] [incubator-tvm] vegaluisjose commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
vegaluisjose commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595885814
Hey @pasqoc ,
You are right, that makes the test work. It works for me without changing the number of repetitions.
Thoughts on this `timer()` @tmoreau89 and @liangfu ?
Here is the trace
```
resnet18_v1 inference graph built in 8.82s!
File synset.txt exists, skip.
File cat.png exists, skip.
[traced 1M cycles]
[traced 2M cycles]
[traced 3M cycles]
[traced 4M cycles]
[traced 5M cycles]
[traced 6M cycles]
[traced 7M cycles]
[traced 8M cycles]
[traced 9M cycles]
[traced 10M cycles]
[traced 11M cycles]
[traced 12M cycles]
[traced 13M cycles]
[traced 14M cycles]
[traced 15M cycles]
[traced 16M cycles]
[traced 17M cycles]
[traced 18M cycles]
[traced 19M cycles]
[traced 20M cycles]
[traced 21M cycles]
[traced 22M cycles]
[traced 23M cycles]
[traced 24M cycles]
[traced 25M cycles]
[traced 26M cycles]
[traced 27M cycles]
[traced 28M cycles]
[traced 29M cycles]
[traced 30M cycles]
[traced 31M cycles]
Execution statistics:
cycle_count : 2417775
resnet18_v1 prediction for sample 0
#1: tiger cat
#2: Egyptian cat
#3: tabby, tabby cat
#4: lynx, catamount
#5: weasel
```
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388023813
##########
File path: vta/hardware/chisel/Makefile
##########
@@ -109,7 +133,7 @@ else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
-default: lint lib
Review comment:
As I explained in the commit message, currently lint messes up indentation and requires manual fixes.
It would be better in my opinion to perform lint manually after large code changes only.
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388572033
##########
File path: vta/tests/python/de10nano/test_program_rpc.py
##########
@@ -0,0 +1,45 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+import sys, os
+import tvm
+from tvm import rpc
+from vta import get_bitstream_path, download_bitstream, program_fpga, reconfig_runtime
+
+host = os.environ.get("VTA_PYNQ_RPC_HOST", "de10nano")
Review comment:
Makes perfect sense, perhaps coupled with your idea of folding fpga target specific info in environment.py.
Right now introducing VTA_DE10_RPC_HOST anywhere VTA_PYNQ_RPC_HOST, including matrix_multiply.py for instance would add a lot of boiler plate code.
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[GitHub] [incubator-tvm] pasqoc edited a comment on issue #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc edited a comment on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595976611
Hi @tmoreau89, actually I observe the same problem with pynq as well, just tried.
If I use m.run() everything works (see results in table), every time, but when I use timer() everything breaks.
When was the last time you tested deploy_classification with pynq?
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[GitHub] [incubator-tvm] tmoreau89 commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
tmoreau89 commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389086490
##########
File path: vta/tests/python/de10nano/test_program_rpc.py
##########
@@ -0,0 +1,45 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+import sys, os
+import tvm
+from tvm import rpc
+from vta import get_bitstream_path, download_bitstream, program_fpga, reconfig_runtime
+
+host = os.environ.get("VTA_PYNQ_RPC_HOST", "de10nano")
Review comment:
I think that's totally acceptable as long as we update documentation too to reflect that change in requirements. Grep-ing for `VTA_PYNQ_RPC_HOST` should do the trick
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[GitHub] [incubator-tvm] pasqoc commented on a change in pull request #4986:
[VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
pasqoc commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r388402066
##########
File path: vta/src/de10nano/de10nano_mgr.h
##########
@@ -0,0 +1,554 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ *
+ * \file de10nano_mgr.h
+ * \brief DE10-Nano fpga manager.
+ */
+
+#ifndef VTA_DE10NANO_DE10NANO_MGR_H_
+#define VTA_DE10NANO_DE10NANO_MGR_H_
+
+extern "C" {
Review comment:
This style is kind of nowadays redundant as the compiler knows already what to do.
You are right, this is a C++ header file and chances are it will not be used in a C only context.
I can make it pure C++ if you like.
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[GitHub] [incubator-tvm] vegaluisjose commented on issue #4986: [VTA][Chisel,
de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
vegaluisjose commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-595516892
This is an error on that cmake file actually because everything should be python3 by now. In fact, f-strings are used in other parts of the python codebase. This is a good find.
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[GitHub] [incubator-tvm] vegaluisjose commented on a change in pull request
#4986: [VTA][Chisel, de10nano] Chisel fixes and de10nano support
Posted by GitBox <gi...@apache.org>.
vegaluisjose commented on a change in pull request #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support
URL: https://github.com/apache/incubator-tvm/pull/4986#discussion_r389067200
##########
File path: vta/hardware/chisel/src/main/scala/core/TensorStore.scala
##########
@@ -62,20 +62,40 @@ class TensorStore(tensorType: String = "none", debug: Boolean = false)(
val tag = Reg(UInt(8.W))
val set = Reg(UInt(8.W))
+ // Dynamically adjust the size of DMA transfers to avoid crossing page boundaries.
+ final val ADAPTIVE_DMA_XFER_ENABLE = true
Review comment:
I see, AFAIK the problem is systematic across all platforms, so we might want to fix it right away. Also, I believe `de10-nano` is `AXI3`, therefore other platforms using `AXI4` should also work with this because AXI's _"backwards compatibility."_
Later, we can optimize for performance if we would like to.
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