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Posted to commits@nuttx.apache.org by xi...@apache.org on 2023/09/19 18:08:00 UTC
[nuttx] branch master updated: add Artery at32
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 1487aa267e add Artery at32
1487aa267e is described below
commit 1487aa267e3164cb851d07fd04a48c3906e072bc
Author: xiao <40...@qq.com>
AuthorDate: Sat Sep 16 18:11:01 2023 +0800
add Artery at32
check nxstyle
check nxstyle
---
arch/arm/Kconfig | 19 +
arch/arm/include/at32/at32f43xxx_irq.h | 184 +
arch/arm/include/at32/chip.h | 560 ++
arch/arm/include/at32/irq.h | 106 +
arch/arm/src/at32/Kconfig | 7683 ++++++++++++++++++++
arch/arm/src/at32/Make.defs | 181 +
arch/arm/src/at32/at32.h | 57 +
arch/arm/src/at32/at32_adc.c | 4433 +++++++++++
arch/arm/src/at32/at32_adc.h | 1368 ++++
arch/arm/src/at32/at32_allocateheap.c | 309 +
arch/arm/src/at32/at32_can.c | 2535 +++++++
arch/arm/src/at32/at32_can.h | 152 +
arch/arm/src/at32/at32_can_sock.c | 2484 +++++++
arch/arm/src/at32/at32_dbgmcu.h | 49 +
arch/arm/src/at32/at32_dma.c | 47 +
arch/arm/src/at32/at32_dma.h | 315 +
arch/arm/src/at32/at32_dma_v1mux.c | 1464 ++++
arch/arm/src/at32/at32_dumpgpio.c | 138 +
arch/arm/src/at32/at32_eth.c | 4030 ++++++++++
arch/arm/src/at32/at32_eth.h | 107 +
arch/arm/src/at32/at32_exti.h | 142 +
arch/arm/src/at32/at32_exti_alarm.c | 138 +
arch/arm/src/at32/at32_exti_gpio.c | 385 +
arch/arm/src/at32/at32_exti_pwr.c | 145 +
arch/arm/src/at32/at32_exti_pwr.h | 56 +
arch/arm/src/at32/at32_exti_wakeup.c | 137 +
arch/arm/src/at32/at32_flash.c | 41 +
arch/arm/src/at32/at32_flash.h | 90 +
arch/arm/src/at32/at32_gpio.c | 506 ++
arch/arm/src/at32/at32_gpio.h | 392 +
arch/arm/src/at32/at32_i2c.c | 2700 +++++++
arch/arm/src/at32/at32_i2c.h | 89 +
arch/arm/src/at32/at32_idle.c | 189 +
arch/arm/src/at32/at32_irq.c | 501 ++
arch/arm/src/at32/at32_iwdg.c | 696 ++
arch/arm/src/at32/at32_lowputc.c | 403 +
arch/arm/src/at32/at32_lowputc.h | 64 +
arch/arm/src/at32/at32_lse.c | 72 +
arch/arm/src/at32/at32_lsi.c | 84 +
arch/arm/src/at32/at32_mpuinit.c | 101 +
arch/arm/src/at32/at32_mpuinit.h | 75 +
arch/arm/src/at32/at32_otgfs.h | 104 +
arch/arm/src/at32/at32_otgfsdev.c | 5875 +++++++++++++++
arch/arm/src/at32/at32_otgfshost.c | 5467 ++++++++++++++
arch/arm/src/at32/at32_pm.h | 125 +
arch/arm/src/at32/at32_pminitialize.c | 62 +
arch/arm/src/at32/at32_pmsleep.c | 97 +
arch/arm/src/at32/at32_pmstandby.c | 96 +
arch/arm/src/at32/at32_pmstop.c | 107 +
arch/arm/src/at32/at32_pwm.c | 4505 ++++++++++++
arch/arm/src/at32/at32_pwm.h | 1147 +++
arch/arm/src/at32/at32_pwr.c | 345 +
arch/arm/src/at32/at32_pwr.h | 195 +
arch/arm/src/at32/at32_rcc.c | 228 +
arch/arm/src/at32/at32_rcc.h | 233 +
arch/arm/src/at32/at32_rtc.c | 42 +
arch/arm/src/at32/at32_rtc.h | 188 +
arch/arm/src/at32/at32_rtc_lowerhalf.c | 915 +++
arch/arm/src/at32/at32_sdio.c | 3177 ++++++++
arch/arm/src/at32/at32_sdio.h | 134 +
arch/arm/src/at32/at32_serial.c | 3049 ++++++++
arch/arm/src/at32/at32_spi.c | 1949 +++++
arch/arm/src/at32/at32_spi.h | 184 +
arch/arm/src/at32/at32_start.c | 201 +
arch/arm/src/at32/at32_start.h | 47 +
arch/arm/src/at32/at32_syscfg.h | 39 +
arch/arm/src/at32/at32_tim.c | 1819 +++++
arch/arm/src/at32/at32_tim.h | 219 +
arch/arm/src/at32/at32_tim_lowerhalf.c | 581 ++
arch/arm/src/at32/at32_timerisr.c | 153 +
arch/arm/src/at32/at32_uart.h | 592 ++
arch/arm/src/at32/at32_uid.c | 46 +
arch/arm/src/at32/at32_uid.h | 36 +
arch/arm/src/at32/at32_usbhost.c | 415 ++
arch/arm/src/at32/at32_usbhost.h | 280 +
arch/arm/src/at32/at32_userspace.c | 103 +
arch/arm/src/at32/at32_userspace.h | 61 +
arch/arm/src/at32/at32_waste.c | 42 +
arch/arm/src/at32/at32_waste.h | 64 +
arch/arm/src/at32/at32_wdg.h | 104 +
arch/arm/src/at32/at32_wwdg.c | 794 ++
arch/arm/src/at32/at32f43xx_flash.c | 410 ++
arch/arm/src/at32/at32f43xxx_alarm.h | 122 +
arch/arm/src/at32/at32f43xxx_rcc.c | 755 ++
arch/arm/src/at32/at32f43xxx_rtcc.c | 1626 +++++
arch/arm/src/at32/chip.h | 57 +
arch/arm/src/at32/hardware/at32_adc.h | 39 +
arch/arm/src/at32/hardware/at32_adc_v1.h | 633 ++
arch/arm/src/at32/hardware/at32_can.h | 469 ++
arch/arm/src/at32/hardware/at32_dbgmcu.h | 109 +
arch/arm/src/at32/hardware/at32_dma.h | 324 +
arch/arm/src/at32/hardware/at32_dmamux.h | 139 +
arch/arm/src/at32/hardware/at32_eth.h | 738 ++
arch/arm/src/at32/hardware/at32_exti.h | 113 +
arch/arm/src/at32/hardware/at32_flash.h | 226 +
arch/arm/src/at32/hardware/at32_i2c.h | 237 +
arch/arm/src/at32/hardware/at32_memorymap.h | 37 +
arch/arm/src/at32/hardware/at32_pinmap.h | 36 +
arch/arm/src/at32/hardware/at32_pwr.h | 87 +
arch/arm/src/at32/hardware/at32_rtcc.h | 365 +
arch/arm/src/at32/hardware/at32_sdio.h | 274 +
arch/arm/src/at32/hardware/at32_spi.h | 181 +
arch/arm/src/at32/hardware/at32_tim.h | 1057 +++
arch/arm/src/at32/hardware/at32_wdg.h | 140 +
arch/arm/src/at32/hardware/at32f43xxx_dmamux.h | 132 +
arch/arm/src/at32/hardware/at32f43xxx_gpio.h | 356 +
arch/arm/src/at32/hardware/at32f43xxx_memorymap.h | 217 +
arch/arm/src/at32/hardware/at32f43xxx_pinmap.h | 897 +++
arch/arm/src/at32/hardware/at32f43xxx_rcc.h | 568 ++
arch/arm/src/at32/hardware/at32f43xxx_syscfg.h | 288 +
arch/arm/src/at32/hardware/at32f43xxx_uart.h | 250 +
arch/arm/src/at32/hardware/at32fxxxxx_otgfs.h | 1221 ++++
boards/Kconfig | 11 +
boards/arm/at32/at32f437-mini/Kconfig | 13 +
boards/arm/at32/at32f437-mini/README.txt | 94 +
.../arm/at32/at32f437-mini/configs/adc/defconfig | 52 +
.../at32/at32f437-mini/configs/can_char/defconfig | 50 +
.../at32f437-mini/configs/can_socket/defconfig | 62 +
.../arm/at32/at32f437-mini/configs/eth/defconfig | 70 +
.../arm/at32/at32f437-mini/configs/msc/defconfig | 57 +
.../arm/at32/at32f437-mini/configs/nsh/defconfig | 48 +
.../arm/at32/at32f437-mini/configs/pwm/defconfig | 53 +
.../arm/at32/at32f437-mini/configs/rtc/defconfig | 51 +
.../at32/at32f437-mini/configs/sdcard/defconfig | 59 +
.../at32f437-mini/configs/systemview/defconfig | 57 +
.../at32/at32f437-mini/configs/usbnsh/defconfig | 53 +
.../at32/at32f437-mini/configs/usbserial/defconfig | 53 +
boards/arm/at32/at32f437-mini/include/board.h | 271 +
.../arm/at32/at32f437-mini/include/nsh_romfsimg.h | 111 +
boards/arm/at32/at32f437-mini/kernel/Makefile | 92 +
.../arm/at32/at32f437-mini/kernel/at32_userspace.c | 100 +
.../arm/at32/at32f437-mini/romfs/init.d/rc.sysinit | 15 +
boards/arm/at32/at32f437-mini/romfs/init.d/rcS | 2 +
.../romfs/sysconfig/network-scripts/ipcfg-eth0 | 5 +
boards/arm/at32/at32f437-mini/scripts/Make.defs | 54 +
.../arm/at32/at32f437-mini/scripts/kernel-space.ld | 96 +
boards/arm/at32/at32f437-mini/scripts/ld.script | 126 +
boards/arm/at32/at32f437-mini/scripts/memory.ld | 86 +
.../arm/at32/at32f437-mini/scripts/user-space.ld | 98 +
boards/arm/at32/at32f437-mini/src/Makefile | 83 +
boards/arm/at32/at32f437-mini/src/at32_adc.c | 235 +
boards/arm/at32/at32f437-mini/src/at32_appinit.c | 76 +
boards/arm/at32/at32f437-mini/src/at32_at24.c | 128 +
boards/arm/at32/at32f437-mini/src/at32_autoleds.c | 122 +
boards/arm/at32/at32f437-mini/src/at32_boot.c | 115 +
boards/arm/at32/at32f437-mini/src/at32_bringup.c | 231 +
boards/arm/at32/at32f437-mini/src/at32_can.c | 102 +
boards/arm/at32/at32f437-mini/src/at32_cansock.c | 58 +
boards/arm/at32/at32f437-mini/src/at32_ethernet.c | 240 +
boards/arm/at32/at32f437-mini/src/at32_gpio.c | 322 +
boards/arm/at32/at32f437-mini/src/at32_mmcsd.c | 109 +
boards/arm/at32/at32f437-mini/src/at32_pwm.c | 107 +
boards/arm/at32/at32f437-mini/src/at32_spi.c | 188 +
boards/arm/at32/at32f437-mini/src/at32_timer.c | 65 +
boards/arm/at32/at32f437-mini/src/at32_usb.c | 347 +
boards/arm/at32/at32f437-mini/src/at32_userleds.c | 215 +
boards/arm/at32/at32f437-mini/src/at32_w25.c | 281 +
boards/arm/at32/at32f437-mini/src/at32f437-mini.h | 458 ++
boards/arm/at32/at32f437-mini/tool/mkromfs.sh | 11 +
159 files changed, 84482 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e3384b26ad..f9495b6f35 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -659,6 +659,21 @@ config ARCH_CHIP_GOLDFISH_ARM
---help---
GOLDFISH virt platform (ARMv7a)
+config ARCH_CHIP_AT32
+ bool "Artery AT32 F4"
+ select ARCH_HAVE_MPU
+ select ARCH_HAVE_FETCHADD
+ select ARCH_HAVE_I2CRESET
+ select ARCH_HAVE_HEAPCHECK
+ select ARCH_HAVE_PROGMEM
+ select ARCH_HAVE_SPI_BITORDER
+ select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_TIMEKEEPING
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_HAVE_STACKCHECK
+ ---help---
+ Artery AT32 architectures (ARM Cortex-M4)
+
config ARCH_CHIP_ARM_CUSTOM
bool "Custom ARM chip"
select ARCH_CHIP_CUSTOM
@@ -1065,6 +1080,7 @@ config ARCH_CHIP
default "tlsr82" if ARCH_CHIP_TLSR82
default "qemu" if ARCH_CHIP_QEMU_ARM
default "goldfish" if ARCH_CHIP_GOLDFISH_ARM
+ default "at32" if ARCH_CHIP_AT32
config ARM_THUMB
bool "Thumb Mode"
@@ -1543,4 +1559,7 @@ endif
if ARCH_CHIP_GOLDFISH_ARM
source "arch/arm/src/goldfish/Kconfig"
endif
+if ARCH_CHIP_AT32
+source "arch/arm/src/at32/Kconfig"
+endif
endif # ARCH_ARM
diff --git a/arch/arm/include/at32/at32f43xxx_irq.h b/arch/arm/include/at32/at32f43xxx_irq.h
new file mode 100644
index 0000000000..aadf5c38e5
--- /dev/null
+++ b/arch/arm/include/at32/at32f43xxx_irq.h
@@ -0,0 +1,184 @@
+/****************************************************************************
+ * arch/arm/include/at32/at32f43xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_AT32_AT32F43XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_AT32_AT32F43XXX_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* IRQ numbers.
+ * The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC. This does, however, waste several words of memory in
+ * the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15). These common definitions can
+ * be found in nuttx/arch/arm/include/at32/irq.h
+ *
+ * External interrupts (vectors >= 16)
+ */
+
+#define AT32_IRQ_WWDG (AT32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define AT32_IRQ_PVD (AT32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define AT32_IRQ_TAMPER (AT32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
+#define AT32_IRQ_TIMESTAMP (AT32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
+#define AT32_IRQ_RTC_WKUP (AT32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define AT32_IRQ_FLASH (AT32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define AT32_IRQ_RCC (AT32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define AT32_IRQ_EXTI0 (AT32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define AT32_IRQ_EXTI1 (AT32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define AT32_IRQ_EXTI2 (AT32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
+#define AT32_IRQ_EXTI3 (AT32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+#define AT32_IRQ_EXTI4 (AT32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define AT32_IRQ_EDMAS1 (AT32_IRQ_FIRST+11) /* 11: EDMA Stream 1 global interrupt */
+#define AT32_IRQ_EDMAS2 (AT32_IRQ_FIRST+12) /* 12: EDMA Stream 2 global interrupt */
+#define AT32_IRQ_EDMAS3 (AT32_IRQ_FIRST+13) /* 13: EDMA Stream 3 global interrupt */
+#define AT32_IRQ_EDMAS4 (AT32_IRQ_FIRST+14) /* 14: EDMA Stream 4 global interrupt */
+#define AT32_IRQ_EDMAS5 (AT32_IRQ_FIRST+15) /* 15: EDMA Stream 5 global interrupt */
+#define AT32_IRQ_EDMAS6 (AT32_IRQ_FIRST+16) /* 16: EDMA Stream 6 global interrupt */
+#define AT32_IRQ_EDMAS7 (AT32_IRQ_FIRST+17) /* 17: EDMA Stream 7 global interrupt */
+#define AT32_IRQ_ADC (AT32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
+#define AT32_IRQ_CAN1TX (AT32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
+#define AT32_IRQ_CAN1RX0 (AT32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
+#define AT32_IRQ_CAN1RX1 (AT32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
+#define AT32_IRQ_CAN1SCE (AT32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
+#define AT32_IRQ_EXTI95 (AT32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define AT32_IRQ_TIM1BRK (AT32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
+#define AT32_IRQ_TIM9 (AT32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
+#define AT32_IRQ_TIM1UP (AT32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
+#define AT32_IRQ_TIM10 (AT32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
+#define AT32_IRQ_TIM1TRGCOM (AT32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
+#define AT32_IRQ_TIM11 (AT32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
+#define AT32_IRQ_TIM1CC (AT32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define AT32_IRQ_TIM2 (AT32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define AT32_IRQ_TIM3 (AT32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+#define AT32_IRQ_TIM4 (AT32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
+#define AT32_IRQ_I2C1EV (AT32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define AT32_IRQ_I2C1ER (AT32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define AT32_IRQ_I2C2EV (AT32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
+#define AT32_IRQ_I2C2ER (AT32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
+#define AT32_IRQ_SPI1 (AT32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define AT32_IRQ_SPI2 (AT32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
+#define AT32_IRQ_USART1 (AT32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define AT32_IRQ_USART2 (AT32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define AT32_IRQ_USART3 (AT32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+#define AT32_IRQ_EXTI1510 (AT32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define AT32_IRQ_RTCALRM (AT32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define AT32_IRQ_OTGFSWKUP (AT32_IRQ_FIRST+42) /* 42: USB On-The-Go FS1 Wakeup through EXTI line interrupt */
+#define AT32_IRQ_TIM8BRK (AT32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
+#define AT32_IRQ_TIM12 (AT32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
+#define AT32_IRQ_TIM8UP (AT32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
+#define AT32_IRQ_TIM13 (AT32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
+#define AT32_IRQ_TIM8TRGCOM (AT32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
+#define AT32_IRQ_TIM14 (AT32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
+#define AT32_IRQ_TIM8CC (AT32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
+#define AT32_IRQ_EDMAS8 (AT32_IRQ_FIRST+47) /* 47: EDMA Stream 8 global interrupt */
+#define AT32_IRQ_XSMC (AT32_IRQ_FIRST+48) /* 48: XSMC global interrupt */
+#define AT32_IRQ_SDIO (AT32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
+#define AT32_IRQ_TIM5 (AT32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
+#define AT32_IRQ_SPI3 (AT32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
+#define AT32_IRQ_UART4 (AT32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
+#define AT32_IRQ_UART5 (AT32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
+#define AT32_IRQ_TIM6 (AT32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
+#define AT32_IRQ_DAC (AT32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
+#define AT32_IRQ_TIM7 (AT32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
+#define AT32_IRQ_DMA1CH1 (AT32_IRQ_FIRST+56) /* 56: DMA1 Stream 1 global interrupt */
+#define AT32_IRQ_DMA1CH2 (AT32_IRQ_FIRST+57) /* 57: DMA1 Stream 2 global interrupt */
+#define AT32_IRQ_DMA1CH3 (AT32_IRQ_FIRST+58) /* 58: DMA1 Stream 3 global interrupt */
+#define AT32_IRQ_DMA1CH4 (AT32_IRQ_FIRST+59) /* 59: DMA1 Stream 4 global interrupt */
+#define AT32_IRQ_DMA1CH5 (AT32_IRQ_FIRST+60) /* 60: DMA1 Stream 5 global interrupt */
+#if defined(CONFIG_AT32_AT32F437)
+# define AT32_IRQ_ETH (AT32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
+# define AT32_IRQ_ETHWKUP (AT32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
+#endif
+#define AT32_IRQ_CAN2TX (AT32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
+#define AT32_IRQ_CAN2RX0 (AT32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
+#define AT32_IRQ_CAN2RX1 (AT32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
+#define AT32_IRQ_CAN2SCE (AT32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
+#define AT32_IRQ_OTGFS (AT32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
+#define AT32_IRQ_DMA1CH6 (AT32_IRQ_FIRST+68) /* 68: DMA1 Stream 6 global interrupt */
+#define AT32_IRQ_DMA1CH7 (AT32_IRQ_FIRST+69) /* 69: DMA1 Stream 7 global interrupt */
+#define AT32_IRQ_USART6 (AT32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
+#define AT32_IRQ_I2C3EV (AT32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
+#define AT32_IRQ_I2C3ER (AT32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
+#define AT32_IRQ_OTGFS2 (AT32_IRQ_FIRST+77) /* 77: USB On The Go FS2 global interrupt */
+#define AT32_IRQ_DVP (AT32_IRQ_FIRST+78) /* 78: DVP global interrupt */
+#define AT32_IRQ_FPU (AT32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+#define AT32_IRQ_UART7 (AT32_IRQ_FIRST+82) /* 82: UART7 interrupt */
+#define AT32_IRQ_UART8 (AT32_IRQ_FIRST+83) /* 83: UART8 interrupt */
+#define AT32_IRQ_SPI4 (AT32_IRQ_FIRST+84) /* 84: SPI4 interrupt */
+#define AT32_IRQ_QUADSPI2 (AT32_IRQ_FIRST+91) /* 91: SAI2 Global interrupt */
+#define AT32_IRQ_QUADSPI1 (AT32_IRQ_FIRST+92) /* 92: QuadSPI Global interrupt */
+#define AT32_IRQ_DMAMUX (AT32_IRQ_FIRST+94) /* DMAMUX over interrupt */
+#define AT32_IRQ_SDIO2 (AT32_IRQ_FIRST+102) /* SDIO2 interrupt */
+#define AT32_IRQ_ACC (AT32_IRQ_FIRST+103) /* ACC interrupt */
+#define AT32_IRQ_TIM20BRK (AT32_IRQ_FIRST+104) /* TIM20 break up interrupt */
+#define AT32_IRQ_TIM20UP (AT32_IRQ_FIRST+105) /* TIM20 over interrupt */
+#define AT32_IRQ_TIM20 (AT32_IRQ_FIRST+106) /* TIM20 global interrupt */
+#define AT32_IRQ_TIM20CC (AT32_IRQ_FIRST+107) /* TIM20 Capture Compare interrupt */
+#define AT32_IRQ_DMA2CH1 (AT32_IRQ_FIRST+108) /* DMA2 Stream 1 global interrupt */
+#define AT32_IRQ_DMA2CH2 (AT32_IRQ_FIRST+109) /* DMA2 Stream 2 global interrupt */
+#define AT32_IRQ_DMA2CH3 (AT32_IRQ_FIRST+110) /* DMA2 Stream 3 global interrupt */
+#define AT32_IRQ_DMA2CH4 (AT32_IRQ_FIRST+111) /* DMA2 Stream 4 global interrupt */
+#define AT32_IRQ_DMA2CH5 (AT32_IRQ_FIRST+112) /* DMA2 Stream 5 global interrupt */
+#define AT32_IRQ_DMA2CH6 (AT32_IRQ_FIRST+113) /* DMA2 Stream 6 global interrupt */
+#define AT32_IRQ_DMA2CH7 (AT32_IRQ_FIRST+114) /* DMA2 Stream 7 global interrupt */
+
+#if defined(CONFIG_AT32_AT32F435) || defined(CONFIG_AT32_AT32F437)
+# define AT32_IRQ_NEXTINT (115)
+# define NR_IRQS (AT32_IRQ_FIRST+115)
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_AT32_AT32F43XXX_IRQ_H */
\ No newline at end of file
diff --git a/arch/arm/include/at32/chip.h b/arch/arm/include/at32/chip.h
new file mode 100644
index 0000000000..46dc1093fa
--- /dev/null
+++ b/arch/arm/include/at32/chip.h
@@ -0,0 +1,560 @@
+/****************************************************************************
+ * arch/arm/include/at32/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_AT32_CHIP_H
+#define __ARCH_ARM_INCLUDE_AT32_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* Check the AT32 family configuration.
+ * It must be done in arch/arm/src/at32/Kconfig !
+ */
+
+#ifdef CONFIG_AT32_AT32F43XX
+# define __HAVE_F4 1
+#else
+# define __HAVE_F4 0
+#endif
+
+#if ((__HAVE_F1 + __HAVE_F2 + __HAVE_F30 + __HAVE_F33 + __HAVE_F37 + __HAVE_F4 + \
+ __HAVE_G4 + __HAVE_L1) != 1)
+# error "Only one AT32 family must be selected !"
+#endif
+
+#ifdef CONFIG_AT32_LOWDENSITY
+# define __HAVE_LD 1
+#else
+# define __HAVE_LD 0
+#endif
+#ifdef CONFIG_AT32_MEDIUMDENSITY
+# define __HAVE_MD 1
+#else
+# define __HAVE_MD 0
+#endif
+#ifdef CONFIG_AT32_MEDIUMPLUSDENSITY
+# define __HAVE_MPD 1
+#else
+# define __HAVE_MPD 0
+#endif
+#ifdef CONFIG_AT32_HIGHDENSITY
+# define __HAVE_HD 1
+#else
+# define __HAVE_HD 0
+#endif
+
+#if (__HAVE_LD +__HAVE_MD + __HAVE_MPD + __HAVE_HD) > 1
+# error "Up to one density configuration must be selected"
+#endif
+
+/* Get customizations for each supported chip and provide alternate function
+ * pin-mapping
+ *
+ * NOTE: Each GPIO pin may serve either for general purpose I/O or for a
+ * special alternate function (such as USART, CAN, USB, SDIO, etc.). That
+ * particular pin-mapping will depend on the package and AT32 family. If
+ * you are incorporating a new AT32 chip into NuttX, you will need to add
+ * the pin-mapping to a header file and to include that header file below.
+ * The chip-specific pin-mapping is defined in the chip datasheet.
+ */
+
+/* AT32 F4 Family ***********************************************************/
+#if defined(CONFIG_ARCH_CHIP_AT32F435RC) /* LQFP 64 10x10x1.4 256Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 0 /* No FSMC */
+# define AT32_NATIM 3 /* 3 advanced timers TIM1 and 8 */
+# define AT32_NGTIM 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 8 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* 2 basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 4 /* SPI1-4 */
+# define AT32_NI2S 4 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 8 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 2 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 2 /* USB OTG FS/HS */
+# define AT32_NGPIO 53 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 0 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F435RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 0 /* No FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 53 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F435RM) /* LQFP 64 10x10x1.4 4032Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 0 /* No FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 53 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F435VC) /* LQFP 100 14x14x1.4 256Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 84 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F435VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 84 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F435VM) /* LQFP 100 14x14x1.4 4032Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 84 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F435ZC) /* LQFP 144 20x20x1.4 256Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 116 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F435ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 116 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F435ZM) /* LQFP 144 20x20x1.4 4032Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 116 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F437RC) /* LQFP 64 10x10x1.4 256Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 0 /* No FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 53 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F437RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 0 /* No FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 53 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F437RM) /* LQFP 64 10x10x1.4 4032Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 0 /* No FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 53 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 0 /* No Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F437VC) /* LQFP-100 256Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 84 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F437VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 3 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 8 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 4 /* SPI1-3 */
+# define AT32_NI2S 4 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 8 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 2 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 2 /* USB OTG FS/HS */
+# define AT32_NGPIO 84 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 1 /* 12-bit DAC1, 1 channel */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
+# define AT32_NRNG 0 /* Random number generator (RNG) */
+# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F437VM) /* LQFP-100 14x14x1.4 4032Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 3 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 8 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 4 /* SPI1-3 */
+# define AT32_NI2S 4 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 8 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 2 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 2 /* USB OTG FS/HS */
+# define AT32_NGPIO 84 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define AT32_NDAC 1 /* 12-bit DAC1, 1 channel */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
+# define AT32_NRNG 0 /* Random number generator (RNG) */
+# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F437ZC) /* LQFP-144 256Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 116 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F437ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 116 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_AT32F437ZM) /* LQFP 144 20x20x1.4 4032Kb FLASH 384Kb SRAM */
+# define AT32_NFSMC 1 /* FSMC */
+# define AT32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define AT32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
+ * 32-bit general timers TIM2 and 5 with DMA */
+# define AT32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define AT32_NDMA 2 /* DMA1-2 */
+# define AT32_NSPI 3 /* SPI1-3 */
+# define AT32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define AT32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define AT32_NI2C 3 /* I2C1-3 */
+# define AT32_NCAN 2 /* CAN1-2 */
+# define AT32_NSDIO 1 /* SDIO */
+# define AT32_NLCD 0 /* No LCD */
+# define AT32_NUSBOTG 1 /* USB OTG FS/HS */
+# define AT32_NGPIO 116 /* GPIOA-I */
+# define AT32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define AT32_NDAC 2 /* 12-bit DAC1, 2 channels */
+# define AT32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define AT32_NCRC 1 /* CRC */
+# define AT32_NETHERNET 1 /* 100/100 Ethernet MAC */
+# define AT32_NRNG 1 /* Random number generator (RNG) */
+# define AT32_NDCMI 1 /* Digital camera interface (DCMI) */
+
+#else
+# error "Unsupported AT32 chip"
+#endif
+
+/* Peripheral IP versions ***************************************************/
+
+/* Peripheral IP versions are invariant and should be decided here, not in
+ * Kconfig.
+ *
+ * REVISIT: Currently only SPI IP version is handled here, with others being
+ * handled in Kconfig. Those others need to be gradually refactored
+ * and resolved here.
+ */
+
+#if defined(CONFIG_AT32_AT32F43XX)
+# define AT32_HAVE_IP_SPI_V2
+#else
+# error "Did not resolve peripheral IP versions!"
+#endif
+
+/* NVIC priority levels *****************************************************/
+
+#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
+
+#endif /* __ARCH_ARM_INCLUDE_AT32_CHIP_H */
diff --git a/arch/arm/include/at32/irq.h b/arch/arm/include/at32/irq.h
new file mode 100644
index 0000000000..adad8facf4
--- /dev/null
+++ b/arch/arm/include/at32/irq.h
@@ -0,0 +1,106 @@
+/****************************************************************************
+ * arch/arm/include/at32/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_AT32_IRQ_H
+#define __ARCH_ARM_INCLUDE_AT32_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include <arch/at32/chip.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* IRQ numbers.
+ * The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC. This does, however, waste several words of memory in
+ * the IRQ to handle mapping tables.
+ */
+
+/* Processor Exceptions (vectors 0-15) */
+
+#define AT32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
+ /* Vector 0: Reset stack pointer value */
+ /* Vector 1: Reset (not handler as an IRQ) */
+#define AT32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
+#define AT32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
+#define AT32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
+#define AT32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
+#define AT32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
+#define AT32_IRQ_SVCALL (11) /* Vector 11: SVC call */
+#define AT32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
+ /* Vector 13: Reserved */
+#define AT32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
+#define AT32_IRQ_SYSTICK (15) /* Vector 15: System tick */
+
+/* External interrupts (vectors >= 16).
+ * These definitions are chip-specific
+ */
+
+#define AT32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#if defined(CONFIG_AT32_AT32F43XX)
+# include <arch/at32/at32f43xxx_irq.h>
+
+#else
+# error "Unsupported AT32 chip"
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_AT32_IRQ_H */
diff --git a/arch/arm/src/at32/Kconfig b/arch/arm/src/at32/Kconfig
new file mode 100644
index 0000000000..9fd431b77e
--- /dev/null
+++ b/arch/arm/src/at32/Kconfig
@@ -0,0 +1,7683 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+comment "AT32 Configuration Options"
+
+choice
+ prompt "AT32 Chip Selection"
+ default ARCH_CHIP_AT32F437VM
+ depends on ARCH_CHIP_AT32
+
+
+config ARCH_CHIP_AT32F437VM
+ bool "AT32F437VM"
+ select AT32_AT32F43XX
+ select AT32_AT32F437
+ ---help---
+ AT32F43X 100-pin , 4032KB FLASH, 384KB SRAM
+
+config ARCH_CHIP_AT32F437RM
+ bool "AT32F437RM"
+ select AT32_AT32F43XX
+ select AT32_AT32F437
+ ---help---
+ AT32F43X 64-pin , 4032KB FLASH, 384KB SRAM
+
+config ARCH_CHIP_AT32F437VG
+ bool "AT32F437VG"
+ select AT32_AT32F43XX
+ select AT32_AT32F437
+ ---help---
+ AT32F43X 100-pin , 1024KB FLASH, 384KB SRAM
+
+config ARCH_CHIP_AT32F437RG
+ bool "AT32F437RG"
+ select AT32_AT32F43XX
+ select AT32_AT32F437
+ ---help---
+ AT32F43X 64-pin , 1024KB FLASH, 384KB SRAM
+
+config ARCH_CHIP_AT32F435VM
+ bool "AT32F435VM"
+ select AT32_AT32F43XX
+ select AT32_AT32F435
+ ---help---
+ AT32F43X 100-pin , 4032KB FLASH, 384KB SRAM
+
+config ARCH_CHIP_AT32F435RM
+ bool "AT32F435RM"
+ select AT32_AT32F43XX
+ select AT32_AT32F435
+ ---help---
+ AT32F43X 64-pin , 4032KB FLASH, 384KB SRAM
+
+config ARCH_CHIP_AT32F435VG
+ bool "AT32F435VG"
+ select AT32_AT32F43XX
+ select AT32_AT32F435
+ ---help---
+ AT32F43X 100-pin , 1024KB FLASH, 384KB SRAM
+
+config ARCH_CHIP_AT32F435RG
+ bool "AT32F435RG"
+ select AT32_AT32F43XX
+ select AT32_AT32F435
+ ---help---
+ AT32F43X 64-pin , 1024KB FLASH, 384KB SRAM
+
+endchoice
+
+choice
+ prompt "Override Flash Size Designator"
+ default AT32_FLASH_CONFIG_DEFAULT
+ depends on ARCH_CHIP_AT32
+ ---help---
+ AT32F series parts numbering (sans the package type)
+ ends with a number or letter that designates the FLASH size.
+
+ Designator Size in KiB
+ 8 64
+ B 128
+ C 256
+ E 512
+ G 1024
+ I 2048
+ M 4032
+
+ This configuration option defaults to using the configuration based
+ on that designator or the default smaller size if there is no last
+ character designator is present in the AT32 Chip Selection.
+
+ Examples:
+ If the AT32F437VM is chosen, the Flash configuration would be
+ 'M', if a variant of the part with a 4032 KiB Flash is released
+ in the future one could simply select the 'M' designator here.
+
+
+
+config AT32_FLASH_CONFIG_DEFAULT
+ bool "Default"
+
+config AT32_FLASH_CONFIG_8
+ bool "8 64KiB"
+
+config AT32_FLASH_CONFIG_B
+ bool "B 128KiB"
+
+config AT32_FLASH_CONFIG_C
+ bool "C 256KiB"
+
+config AT32_FLASH_CONFIG_E
+ bool "E 512KiB"
+
+config AT32_FLASH_CONFIG_G
+ bool "G 1024KiB"
+
+config AT32_FLASH_CONFIG_I
+ bool "I 2048KiB"
+
+config AT32_FLASH_CONFIG_M
+ bool "M 4032KiB"
+
+endchoice
+
+config AT32_AT32F43XX
+ bool
+ default n
+ select ARCH_CORTEXM4
+ select ARCH_HAVE_FPU
+ select AT32_HAVE_FLASH_ICACHE
+ select AT32_HAVE_FLASH_DCACHE
+ select AT32_HAVE_SPI2
+ select AT32_HAVE_I2C2
+ select AT32_HAVE_IOCOMPENSATION
+ select AT32_HAVE_IP_DBGMCU_V2
+ select AT32_HAVE_IP_TIMERS_V1
+ select AT32_HAVE_IP_ADC_V1
+ select AT32_HAVE_IP_DAC_V1
+ select AT32_HAVE_IP_DMA_V1
+ select AT32_HAVE_DMAMUX
+
+
+config AT32_AT32F435
+ bool
+ default n
+ select AT32_HAVE_FSMC
+ select AT32_HAVE_USART3
+ select AT32_HAVE_UART4
+ select AT32_HAVE_UART5
+ select AT32_HAVE_UART7
+ select AT32_HAVE_UART8
+ select AT32_HAVE_USART6
+ select AT32_HAVE_TIM1
+ select AT32_HAVE_TIM3
+ select AT32_HAVE_TIM4
+ select AT32_HAVE_TIM5
+ select AT32_HAVE_TIM6
+ select AT32_HAVE_TIM7
+ select AT32_HAVE_TIM8
+ select AT32_HAVE_TIM9
+ select AT32_HAVE_TIM10
+ select AT32_HAVE_TIM11
+ select AT32_HAVE_TIM12
+ select AT32_HAVE_TIM13
+ select AT32_HAVE_TIM14
+ select AT32_HAVE_TIM20
+ select AT32_HAVE_ADC2
+ select AT32_HAVE_ADC3
+ select AT32_HAVE_CAN1
+ select AT32_HAVE_CAN2
+ select AT32_HAVE_DAC1
+ select AT32_HAVE_DAC2
+ select AT32_HAVE_SPI3
+ select AT32_HAVE_I2S3
+ select AT32_HAVE_I2C3
+ select AT32_HAVE_OTGFS
+ select AT32_HAVE_OTGFS2
+
+config AT32_AT32F437
+ bool
+ default n
+ select AT32_HAVE_FSMC
+ select AT32_HAVE_USART3
+ select AT32_HAVE_UART4
+ select AT32_HAVE_UART5
+ select AT32_HAVE_USART6
+ select AT32_HAVE_UART7
+ select AT32_HAVE_UART8
+ select AT32_HAVE_TIM1
+ select AT32_HAVE_TIM2
+ select AT32_HAVE_TIM3
+ select AT32_HAVE_TIM4
+ select AT32_HAVE_TIM5
+ select AT32_HAVE_TIM6
+ select AT32_HAVE_TIM7
+ select AT32_HAVE_TIM8
+ select AT32_HAVE_TIM9
+ select AT32_HAVE_TIM10
+ select AT32_HAVE_TIM11
+ select AT32_HAVE_TIM12
+ select AT32_HAVE_TIM13
+ select AT32_HAVE_TIM14
+ select AT32_HAVE_TIM20
+ select AT32_HAVE_ADC2
+ select AT32_HAVE_ADC3
+ select AT32_HAVE_CAN1
+ select AT32_HAVE_CAN2
+ select AT32_HAVE_DAC1
+ select AT32_HAVE_SPI3
+ select AT32_HAVE_I2S3
+ select AT32_HAVE_I2C3
+ select AT32_HAVE_ETHMAC
+ select AT32_HAVE_OTGFS
+ select AT32_HAVE_OTGFS2
+ select AT32_HAVE_SDIO
+ select AT32_HAVE_SDIO2
+
+menu "AT32 Peripheral Support"
+
+# These "hidden" settings determine whether a peripheral option is available
+# for the selected MCU
+
+
+config AT32_HAVE_OVERDRIVE
+ bool
+ default n
+
+config AT32_HAVE_AES
+ bool
+ default n
+
+config AT32_HAVE_DMA1_CHAN8
+ bool
+ default n
+
+config AT32_HAVE_DMA2_CHAN678
+ bool
+ default n
+
+config AT32_HAVE_DMAMUX
+ bool
+ default n
+
+config AT32_HAVE_USBDEV
+ bool
+ default n
+
+config AT32_HAVE_USBFS
+ bool
+ default n
+
+config AT32_HAVE_OTGFS
+ bool
+ default n
+
+config AT32_HAVE_OTGFS2
+ bool
+ default n
+
+config AT32_HAVE_FMC
+ bool
+ default n
+
+config AT32_HAVE_FMAC
+ bool
+ default n
+
+config AT32_HAVE_FSMC
+ bool
+ default n
+
+config AT32_HAVE_USART3
+ bool
+ default n
+
+config AT32_HAVE_UART4
+ bool
+ default n
+
+config AT32_HAVE_UART5
+ bool
+ default n
+
+config AT32_HAVE_USART6
+ bool
+ default n
+
+config AT32_HAVE_UART7
+ bool
+ default n
+
+config AT32_HAVE_UART8
+ bool
+ default n
+
+config AT32_HAVE_TIM1
+ bool
+ default n
+
+config AT32_HAVE_TIM2
+ bool
+ default n
+
+config AT32_HAVE_TIM3
+ bool
+ default n
+
+config AT32_HAVE_TIM4
+ bool
+ default n
+
+config AT32_HAVE_TIM5
+ bool
+ default n
+
+config AT32_HAVE_TIM6
+ bool
+ default n
+
+config AT32_HAVE_TIM7
+ bool
+ default n
+
+config AT32_HAVE_TIM8
+ bool
+ default n
+
+config AT32_HAVE_TIM9
+ bool
+ default n
+
+config AT32_HAVE_TIM10
+ bool
+ default n
+
+config AT32_HAVE_TIM11
+ bool
+ default n
+
+config AT32_HAVE_TIM12
+ bool
+ default n
+
+config AT32_HAVE_TIM13
+ bool
+ default n
+
+config AT32_HAVE_TIM14
+ bool
+ default n
+
+config AT32_HAVE_TIM15
+ bool
+ default n
+
+config AT32_HAVE_TIM16
+ bool
+ default n
+
+config AT32_HAVE_TIM17
+ bool
+ default n
+
+config AT32_HAVE_TIM18
+ bool
+ default n
+
+config AT32_HAVE_TIM19
+ bool
+ default n
+
+config AT32_HAVE_TIM20
+ bool
+ default n
+
+config AT32_HAVE_ADC1
+ bool
+ default y
+
+config AT32_HAVE_ADC2
+ bool
+ default n
+
+config AT32_HAVE_ADC3
+ bool
+ default n
+
+config AT32_HAVE_ADC4
+ bool
+ default n
+
+config AT32_HAVE_ADC5
+ bool
+ default n
+
+config AT32_HAVE_ADC1_DMA
+ bool
+ default n
+
+config AT32_HAVE_ADC2_DMA
+ bool
+ default n
+
+config AT32_HAVE_ADC3_DMA
+ bool
+ default n
+
+config AT32_HAVE_ADC4_DMA
+ bool
+ default n
+
+config AT32_HAVE_ADC5_DMA
+ bool
+ default n
+
+config AT32_HAVE_CAN1
+ bool
+ default n
+
+config AT32_HAVE_CAN2
+ bool
+ default n
+
+config AT32_HAVE_DAC1
+ bool
+ default n
+
+config AT32_HAVE_DAC2
+ bool
+ default n
+
+config AT32_HAVE_DAC3
+ bool
+ default n
+
+config AT32_HAVE_DAC4
+ bool
+ default n
+
+config AT32_HAVE_QSPI
+ bool
+ default n
+
+config AT32_HAVE_ETHMAC
+ bool
+ default n
+
+config AT32_HAVE_I2C2
+ bool
+ default n
+
+config AT32_HAVE_I2C3
+ bool
+ default n
+
+config AT32_HAVE_SPI2
+ bool
+ default n
+
+config AT32_HAVE_SPI3
+ bool
+ default n
+
+config AT32_HAVE_I2S3
+ bool
+ default n
+
+config AT32_HAVE_SPI4
+ bool
+ default n
+
+config AT32_HAVE_I2SPLL
+ bool
+ default n
+
+# These are AT32 peripherals IP blocks
+
+config AT32_HAVE_IP_DBGMCU_V1
+ bool
+ default n
+
+config AT32_HAVE_IP_DBGMCU_V2
+ bool
+ default n
+
+config AT32_HAVE_IP_DBGMCU_V3
+ bool
+ default n
+
+config AT32_HAVE_IP_DMA_V1
+ bool
+ default n
+
+config AT32_HAVE_IP_DMA_V2
+ bool
+ default n
+
+config AT32_HAVE_IP_TIMERS_V1
+ bool
+ default n
+
+config AT32_HAVE_IP_TIMERS_V2
+ bool
+ default n
+
+config AT32_HAVE_IP_TIMERS_V3
+ bool
+ default n
+
+config AT32_HAVE_IP_ADC_V1
+ bool
+ default n
+
+config AT32_HAVE_IP_ADC_V1_BASIC
+ bool
+ default n
+ select AT32_HAVE_IP_ADC_V1
+
+config AT32_HAVE_IP_ADC_V2
+ bool
+ default n
+
+config AT32_HAVE_IP_ADC_V2_BASIC
+ bool
+ default n
+ select AT32_HAVE_IP_ADC_V2
+
+config AT32_HAVE_IP_DAC_V1
+ bool
+ default n
+
+config AT32_HAVE_IP_DAC_V2
+ bool
+ default n
+
+# These are the peripheral selections proper
+
+config AT32_ADC1
+ bool "ADC1"
+ default n
+ select AT32_ADC
+ select AT32_HAVE_ADC1_DMA if AT32_DMAMUX && (AT32_DMA1 || AT32_DMA2)
+
+config AT32_ADC2
+ bool "ADC2"
+ default n
+ select AT32_ADC
+ depends on AT32_HAVE_ADC2
+ select AT32_HAVE_ADC2_DMA if AT32_DMA2
+ select AT32_HAVE_ADC2_DMA if AT32_DMAMUX
+
+config AT32_ADC3
+ bool "ADC3"
+ default n
+ select AT32_ADC
+ depends on AT32_HAVE_ADC3
+ select AT32_HAVE_ADC3_DMA if AT32_DMA2
+ select AT32_HAVE_ADC3_DMA if AT32_DMAMUX
+
+config AT32_ADC4
+ bool "ADC4"
+ default n
+ select AT32_ADC
+ depends on AT32_HAVE_ADC4
+ select AT32_HAVE_ADC4_DMA if AT32_DMA2
+ select AT32_HAVE_ADC4_DMA if AT32_DMAMUX
+
+config AT32_ADC5
+ bool "ADC5"
+ default n
+ select AT32_ADC
+ depends on AT32_HAVE_ADC5
+ select AT32_HAVE_ADC5_DMA if AT32_DMA2
+ select AT32_HAVE_ADC5_DMA if AT32_DMAMUX
+
+config AT32_CAN1
+ bool "CAN1"
+ default n
+ select AT32_CAN
+ depends on AT32_HAVE_CAN1
+
+config AT32_CAN2
+ bool "CAN2"
+ default n
+ select AT32_CAN
+ depends on AT32_HAVE_CAN2
+
+config AT32_CCMDATARAM
+ bool "CMD/DATA RAM"
+ default n
+ depends on AT32_AT32F43XX
+
+config AT32_AES
+ bool "128-bit AES"
+ default n
+ depends on AT32_HAVE_AES
+ select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST
+ select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST
+
+config AT32_CEC
+ bool "CEC"
+ default n
+ depends on AT32_VALUELINE
+
+config AT32_CRC
+ bool "CRC"
+ default n
+
+config AT32_CRS
+ bool "CRS (Clock Recovery System)"
+ default n
+ depends on AT32_HAVE_CRS
+
+config AT32_DMA1
+ bool "DMA1"
+ default n
+ select AT32_DMA
+ select ARCH_DMA
+
+config AT32_DMA2
+ bool "DMA2"
+ default n
+ select AT32_DMA
+ select ARCH_DMA
+ depends on !AT32_VALUELINE || (AT32_VALUELINE && AT32_HIGHDENSITY)
+
+config AT32_DMAMUX1
+ bool "DMAMUX1"
+ default n
+ depends on AT32_HAVE_DMAMUX
+ select AT32_DMAMUX
+
+config AT32_DMAMUX2
+ bool "DMAMUX2"
+ default n
+ depends on AT32_HAVE_DMAMUX
+ select AT32_DMAMUX
+
+config AT32_DAC1
+ bool "DAC1"
+ default n
+ depends on AT32_HAVE_DAC1
+ select AT32_DAC
+
+if AT32_DAC1
+
+config AT32_DAC1CH1
+ bool "DAC1CH1"
+ default n
+
+config AT32_DAC1CH2
+ bool "DAC1CH2"
+ default n
+
+endif #AT32_DAC1
+
+config AT32_DAC2
+ bool "DAC2"
+ default n
+ depends on AT32_HAVE_DAC2
+ select AT32_DAC
+
+if AT32_DAC2
+
+config AT32_DAC2CH1
+ bool "DAC2CH1"
+ default n
+
+endif #AT32_DAC2
+
+config AT32_DAC3
+ bool "DAC3"
+ default n
+ depends on AT32_HAVE_DAC3
+ select AT32_DAC
+
+if AT32_DAC3
+
+config AT32_DAC3CH1
+ bool "DAC3CH1 Internal"
+ default n
+
+config AT32_DAC3CH2
+ bool "DAC3CH2 Internal"
+ default n
+
+endif #AT32_DAC3
+
+config AT32_DAC4
+ bool "DAC4"
+ default n
+ depends on AT32_HAVE_DAC4
+ select AT32_DAC
+
+if AT32_DAC4
+
+config AT32_DAC4CH1
+ bool "DAC4CH1 Internal"
+ default n
+
+config AT32_DAC4CH2
+ bool "DAC4CH2 Internal"
+ default n
+
+endif #AT32_DAC4
+
+config AT32_DCMI
+ bool "DCMI"
+ default n
+ depends on AT32_AT32F43XX
+
+config AT32_ETHMAC
+ bool "Ethernet MAC"
+ default n
+ depends on AT32_HAVE_ETHMAC
+ select NETDEVICES
+ select ARCH_HAVE_PHY
+
+config AT32_FSMC
+ bool "FSMC"
+ default n
+ depends on AT32_HAVE_FSMC
+
+config AT32_FMC
+ bool "FMC"
+ default n
+ depends on AT32_HAVE_FMC
+
+config AT32_FMAC
+ bool "FMAC (Filter Math Accelerator)"
+ default n
+ depends on AT32_HAVE_FMAC
+
+config AT32_I2C1
+ bool "I2C1"
+ default n
+ select AT32_I2C
+
+config AT32_I2C2
+ bool "I2C2"
+ default n
+ depends on AT32_HAVE_I2C2
+ select AT32_I2C
+
+config AT32_I2C3
+ bool "I2C3"
+ default n
+ depends on AT32_HAVE_I2C3
+ select AT32_I2C
+
+config AT32_RTC
+ bool "RTC"
+ default n
+ select RTC
+
+config AT32_OTGFS
+ bool "OTG FS"
+ default n
+ depends on AT32_HAVE_OTGFS
+ select USBHOST_HAVE_ASYNCH if AT32_USBHOST
+
+config AT32_OTGFS2
+ bool "OTG FS2"
+ default n
+ depends on AT32_AT32F43XX
+ select USBHOST_HAVE_ASYNCH if AT32_USBHOST
+
+config AT32_PWR
+ bool "PWR"
+ default n
+
+config AT32_QSPI
+ bool "QSPI (QUADSPI)"
+ depends on AT32_HAVE_QSPI
+ default n
+
+config AT32_SDIO
+ bool "SDIO"
+ default n
+ depends on !AT32_CONNECTIVITYLINE && !AT32_VALUELINE
+ select ARCH_HAVE_SDIO
+ select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
+ select ARCH_HAVE_SDIO_PREFLIGHT
+
+config AT32_SDIO2
+ bool "SDIO2"
+ default n
+ depends on !AT32_CONNECTIVITYLINE && !AT32_VALUELINE
+ select ARCH_HAVE_SDIO
+ select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
+ select ARCH_HAVE_SDIO_PREFLIGHT
+
+config AT32_SPI1
+ bool "SPI1"
+ default n
+ select SPI
+ select AT32_SPI
+
+config AT32_SPI2
+ bool "SPI2"
+ default n
+ depends on AT32_HAVE_SPI2
+ select SPI
+ select AT32_SPI
+
+config AT32_SPI3
+ bool "SPI3"
+ default n
+ depends on AT32_HAVE_SPI3
+ select SPI
+ select AT32_SPI
+
+config AT32_I2S3
+ bool "I2S3"
+ default n
+ depends on AT32_HAVE_I2S3
+ select I2S
+ select AT32_I2S
+
+config AT32_SPI4
+ bool "SPI4"
+ default n
+ depends on AT32_HAVE_SPI4
+ select SPI
+ select AT32_SPI
+
+config AT32_SYSCFG
+ bool "SYSCFG"
+ default y
+ depends on AT32_AT32F43XX || AT32_CONNECTIVITYLINE
+
+config AT32_TIM1
+ bool "TIM1"
+ default n
+ depends on AT32_HAVE_TIM1
+ select AT32_TIM
+
+config AT32_TIM2
+ bool "TIM2"
+ default n
+ select AT32_TIM
+
+config AT32_TIM3
+ bool "TIM3"
+ default n
+ depends on AT32_HAVE_TIM3
+ select AT32_TIM
+
+config AT32_TIM4
+ bool "TIM4"
+ default n
+ depends on AT32_HAVE_TIM4
+ select AT32_TIM
+
+config AT32_TIM5
+ bool "TIM5"
+ default n
+ depends on AT32_HAVE_TIM5
+ select AT32_TIM
+
+config AT32_TIM6
+ bool "TIM6"
+ default n
+ depends on AT32_HAVE_TIM6
+ select AT32_TIM
+
+config AT32_TIM7
+ bool "TIM7"
+ default n
+ depends on AT32_HAVE_TIM7
+ select AT32_TIM
+
+config AT32_TIM8
+ bool "TIM8"
+ default n
+ depends on AT32_HAVE_TIM8
+ select AT32_TIM
+
+config AT32_TIM9
+ bool "TIM9"
+ default n
+ depends on AT32_HAVE_TIM9
+ select AT32_TIM
+
+config AT32_TIM10
+ bool "TIM10"
+ default n
+ depends on AT32_HAVE_TIM10
+ select AT32_TIM
+
+config AT32_TIM11
+ bool "TIM11"
+ default n
+ depends on AT32_HAVE_TIM11
+ select AT32_TIM
+
+config AT32_TIM12
+ bool "TIM12"
+ default n
+ depends on AT32_HAVE_TIM12
+ select AT32_TIM
+
+config AT32_TIM13
+ bool "TIM13"
+ default n
+ depends on AT32_HAVE_TIM13
+ select AT32_TIM
+
+config AT32_TIM14
+ bool "TIM14"
+ default n
+ depends on AT32_HAVE_TIM14
+ select AT32_TIM
+
+config AT32_TIM15
+ bool "TIM15"
+ default n
+ depends on AT32_HAVE_TIM15
+ select AT32_TIM
+
+config AT32_TIM16
+ bool "TIM16"
+ default n
+ depends on AT32_HAVE_TIM16
+ select AT32_TIM
+
+config AT32_TIM17
+ bool "TIM17"
+ default n
+ depends on AT32_HAVE_TIM17
+ select AT32_TIM
+
+config AT32_TIM20
+ bool "TIM20"
+ default n
+ depends on AT32_HAVE_TIM20
+ select AT32_TIM
+
+config AT32_USART1
+ bool "USART1"
+ default n
+ select AT32_USART
+
+config AT32_USART2
+ bool "USART2"
+ default n
+ select AT32_USART
+
+config AT32_USART3
+ bool "USART3"
+ default n
+ depends on AT32_HAVE_USART3
+ select AT32_USART
+
+config AT32_UART4
+ bool "UART4"
+ default n
+ depends on AT32_HAVE_UART4
+ select AT32_USART
+
+config AT32_UART5
+ bool "UART5"
+ default n
+ depends on AT32_HAVE_UART5
+ select AT32_USART
+
+config AT32_USART6
+ bool "USART6"
+ default n
+ depends on AT32_HAVE_USART6
+ select AT32_USART
+
+config AT32_UART7
+ bool "UART7"
+ default n
+ depends on AT32_HAVE_UART7
+ select AT32_USART
+
+config AT32_UART8
+ bool "UART8"
+ default n
+ depends on AT32_HAVE_UART8
+ select AT32_USART
+
+config AT32_USB
+ bool "USB Device"
+ default n
+ depends on AT32_HAVE_USBDEV
+ select USBDEV
+
+config AT32_USBFS
+ bool "USB Full Speed Device"
+ default n
+ depends on AT32_HAVE_USBFS
+ select USBDEV
+
+config AT32_UCPD
+ bool "UCPD (USB Type C Power Delivery)"
+ default n
+ depends on AT32_HAVE_UCPD
+ select USBDEV
+
+config AT32_IWDG
+ bool "IWDG"
+ default n
+ select WATCHDOG
+
+config AT32_WWDG
+ bool "WWDG"
+ default n
+ select WATCHDOG
+
+endmenu
+
+config AT32_ADC
+ bool
+ default n
+
+config AT32_DAC
+ bool
+ default n
+
+config AT32_DMA
+ bool
+ default n
+
+config AT32_DMAMUX
+ bool
+ default n
+
+config AT32_SPI
+ bool
+ default n
+
+config AT32_SPI_DMA
+ bool
+ default n
+
+config AT32_I2S
+ bool
+ default n
+ select AT32_SPI_DMA
+
+config AT32_I2C
+ bool
+ default n
+
+config AT32_CAN
+ bool
+ default n
+
+config AT32_TIM
+ bool
+ default n
+
+config AT32_PWM
+ bool
+ default n
+ select ARCH_HAVE_PWM_PULSECOUNT
+
+config AT32_CAP
+ bool
+ default n
+
+config AT32_NOEXT_VECTORS
+ bool "Disable the ARMv7-M EXT vectors"
+ default n
+ ---help---
+ Sometimes you may not need any Vector support beyond SysTick
+ and wish to save memory. This applies only to ARMv7-M architectures.
+
+
+choice
+ prompt "JTAG Configuration"
+ default AT32_JTAG_DISABLE
+ ---help---
+ JTAG Enable settings (by default JTAG-DP and SW-DP are disabled)
+
+config AT32_JTAG_DISABLE
+ bool "Disable all JTAG clocking"
+
+config AT32_JTAG_FULL_ENABLE
+ bool "Enable full SWJ (JTAG-DP + SW-DP)"
+
+config AT32_JTAG_NOJNTRST_ENABLE
+ bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST"
+
+config AT32_JTAG_SW_ENABLE
+ bool "Set JTAG-DP disabled and SW-DP enabled"
+
+endchoice
+
+config AT32_DISABLE_IDLE_SLEEP_DURING_DEBUG
+ bool "Disable IDLE Sleep (WFI) in debug mode"
+ default n
+ ---help---
+ In debug configuration, disables the WFI instruction in the IDLE loop
+ to prevent the JTAG from disconnecting. With some JTAG debuggers, such
+ as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI
+ instruction, the debugger will disconnect, terminating the debug session.
+
+config AT32_FORCEPOWER
+ bool "Force power"
+ default n
+ ---help---
+ Timer and I2C devices may need to the following to force power to be applied
+ unconditionally at power up. (Otherwise, the device is powered when it is
+ initialized).
+
+config ARCH_BOARD_AT32_CUSTOM_CLOCKCONFIG
+ bool "Custom clock configuration"
+ default n
+ ---help---
+ Enables special, board-specific AT32 clock configuration.
+
+
+config AT32_DMACAPABLE
+ bool "Workaround non-DMA capable memory"
+ depends on ARCH_DMA
+ default y if AT32_AT32F43XX && !AT32_CCMEXCLUDE
+ ---help---
+ This option enables the DMA interface at32_dmacapable that can be
+ used to check if it is possible to do DMA from the selected address.
+ Drivers then may use this information to determine if they should
+ attempt the DMA or fall back to a different transfer method.
+
+config AT32_EXTERNAL_RAM
+ bool "External RAM on FSMC/FMC"
+ default n
+ depends on AT32_FSMC || AT32_FMC
+ select ARCH_HAVE_HEAP2
+ ---help---
+ In addition to internal SRAM, external RAM may be available through the FSMC/FMC.
+
+config AT32_TICKLESS_SYSTICK
+ bool "Tickless via SysTick"
+ default n
+ depends on SCHED_TICKLESS
+ ---help---
+ Use SysTick as Tickless clock.
+
+menu "Timer Configuration"
+ depends on AT32_TIM
+
+if SCHED_TICKLESS
+
+config AT32_TICKLESS_TIMER
+ int "Tickless hardware timer"
+ default 2
+ range 1 14
+ depends on !AT32_TICKLESS_SYSTICK
+ ---help---
+ If the Tickless OS feature is enabled, then one clock must be
+ assigned to provided the timer needed by the OS.
+
+config AT32_TICKLESS_CHANNEL
+ int "Tickless timer channel"
+ default 1
+ range 1 4
+ ---help---
+ If the Tickless OS feature is enabled, the one clock must be
+ assigned to provided the free-running timer needed by the OS
+ and one channel on that clock is needed to handle intervals.
+
+endif # SCHED_TICKLESS
+
+config AT32_ONESHOT
+ bool "TIM one-shot wrapper"
+ default n
+ ---help---
+ Enable a wrapper around the low level timer/counter functions to
+ support one-shot timer.
+
+config AT32_FREERUN
+ bool "TIM free-running wrapper"
+ default n
+ ---help---
+ Enable a wrapper around the low level timer/counter functions to
+ support a free-running timer.
+
+config AT32_ONESHOT_MAXTIMERS
+ int "Maximum number of oneshot timers"
+ default 1
+ range 1 8
+ depends on AT32_ONESHOT
+ ---help---
+ Determines the maximum number of oneshot timers that can be
+ supported. This setting pre-allocates some minimal support for each
+ of the timers and places an upper limit on the number of oneshot
+ timers that you can use.
+
+config AT32_PWM_LL_OPS
+ bool "PWM low-level operations"
+ default n
+ ---help---
+ Enable low-level PWM ops.
+
+config AT32_TIM1_PWM
+ bool "TIM1 PWM"
+ default n
+ depends on AT32_TIM1
+ select AT32_PWM
+ ---help---
+ Reserve timer 1 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM1
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM1_PWM
+
+config AT32_TIM1_MODE
+ int "TIM1 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+config AT32_TIM1_LOCK
+ int "TIM1 Lock Level Configuration"
+ default 0
+ range 0 3
+ ---help---
+ Timer 1 lock level configuration
+
+config AT32_TIM1_TDTS
+ int "TIM1 t_DTS Division"
+ default 0
+ range 0 2
+ ---help---
+ Timer 1 dead-time and sampling clock (t_DTS) division
+
+config AT32_TIM1_DEADTIME
+ int "TIM1 Initial Dead-time"
+ default 0
+ range 0 255
+ ---help---
+ Timer 1 initial dead-time
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM1_CHANNEL1
+ bool "TIM1 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM1_CHANNEL1
+
+config AT32_TIM1_CH1MODE
+ int "TIM1 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM1_CH1OUT
+ bool "TIM1 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+config AT32_TIM1_CH1NOUT
+ bool "TIM1 Channel 1 Complementary Output"
+ default n
+ ---help---
+ Enables channel 1 Complementary Output.
+
+endif # AT32_TIM1_CHANNEL1
+
+config AT32_TIM1_CHANNEL2
+ bool "TIM1 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if AT32_TIM1_CHANNEL2
+
+config AT32_TIM1_CH2MODE
+ int "TIM1 Channel 2 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM1_CH2OUT
+ bool "TIM1 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+config AT32_TIM1_CH2NOUT
+ bool "TIM1 Channel 2 Complementary Output"
+ default n
+ ---help---
+ Enables channel 2 Complementary Output.
+
+endif # AT32_TIM1_CHANNEL2
+
+config AT32_TIM1_CHANNEL3
+ bool "TIM1 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if AT32_TIM1_CHANNEL3
+
+config AT32_TIM1_CH3MODE
+ int "TIM1 Channel 3 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM1_CH3OUT
+ bool "TIM1 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+config AT32_TIM1_CH3NOUT
+ bool "TIM1 Channel 3 Complementary Output"
+ default n
+ ---help---
+ Enables channel 3 Complementary Output.
+
+endif # AT32_TIM1_CHANNEL3
+
+config AT32_TIM1_CHANNEL4
+ bool "TIM1 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if AT32_TIM1_CHANNEL4
+
+config AT32_TIM1_CH4MODE
+ int "TIM1 Channel 4 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM1_CH4OUT
+ bool "TIM1 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM1_CHANNEL4
+
+config AT32_TIM1_CHANNEL5
+ bool "TIM1 Channel 5 (internal)"
+ default n
+ depends on AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Enables channel 5 (not available externally)
+
+if AT32_TIM1_CHANNEL5
+
+config AT32_TIM1_CH5MODE
+ int "TIM1 Channel 5 Mode"
+ default 6
+ range 0 11
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM1_CH5OUT
+ bool "TIM1 Channel 5 Output"
+ default n
+ ---help---
+ Enables channel 5 output.
+
+endif # AT32_TIM1_CHANNEL5
+
+config AT32_TIM1_CHANNEL6
+ bool "TIM1 Channel 6 (internal)"
+ default n
+ depends on AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Enables channel 6 (not available externally)
+
+if AT32_TIM1_CHANNEL6
+
+config AT32_TIM1_CH6MODE
+ int "TIM1 Channel 6 Mode"
+ default 6
+ range 0 11
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM1_CH6OUT
+ bool "TIM1 Channel 6 Output"
+ default n
+ ---help---
+ Enables channel 6 output.
+
+endif # AT32_TIM1_CHANNEL6
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM1_CHANNEL
+ int "TIM1 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM1 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+if AT32_TIM1_CHANNEL = 1
+
+config AT32_TIM1_CH1OUT
+ bool "TIM1 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+config AT32_TIM1_CH1NOUT
+ bool "TIM1 Channel 1 Complementary Output"
+ default n
+ ---help---
+ Enables channel 1 Complementary Output.
+
+endif # AT32_TIM1_CHANNEL = 1
+
+if AT32_TIM1_CHANNEL = 2
+
+config AT32_TIM1_CH2OUT
+ bool "TIM1 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+config AT32_TIM1_CH2NOUT
+ bool "TIM1 Channel 2 Complementary Output"
+ default n
+ ---help---
+ Enables channel 2 Complementary Output.
+
+endif # AT32_TIM1_CHANNEL = 2
+
+if AT32_TIM1_CHANNEL = 3
+
+config AT32_TIM1_CH3OUT
+ bool "TIM1 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+config AT32_TIM1_CH3NOUT
+ bool "TIM1 Channel 3 Complementary Output"
+ default n
+ ---help---
+ Enables channel 3 Complementary Output.
+
+endif # AT32_TIM1_CHANNEL = 3
+
+if AT32_TIM1_CHANNEL = 4
+
+config AT32_TIM1_CH4OUT
+ bool "TIM1 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM1_CHANNEL = 4
+
+config AT32_TIM1_CHMODE
+ int "TIM1 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM1_PWM
+
+config AT32_TIM2_PWM
+ bool "TIM2 PWM"
+ default n
+ depends on AT32_TIM2
+ select AT32_PWM
+ ---help---
+ Reserve timer 2 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM2
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM2_PWM
+
+config AT32_TIM2_MODE
+ int "TIM2 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM2_CHANNEL1
+ bool "TIM2 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM2_CHANNEL1
+
+config AT32_TIM2_CH1MODE
+ int "TIM2 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM2_CH1OUT
+ bool "TIM2 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM2_CHANNEL1
+
+config AT32_TIM2_CHANNEL2
+ bool "TIM2 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if AT32_TIM2_CHANNEL2
+
+config AT32_TIM2_CH2MODE
+ int "TIM2 Channel 2 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM2_CH2OUT
+ bool "TIM2 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM2_CHANNEL2
+
+config AT32_TIM2_CHANNEL3
+ bool "TIM2 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if AT32_TIM2_CHANNEL3
+
+config AT32_TIM2_CH3MODE
+ int "TIM2 Channel 3 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM2_CH3OUT
+ bool "TIM2 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # AT32_TIM2_CHANNEL3
+
+config AT32_TIM2_CHANNEL4
+ bool "TIM2 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if AT32_TIM2_CHANNEL4
+
+config AT32_TIM2_CH4MODE
+ int "TIM2 Channel 4 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM2_CH4OUT
+ bool "TIM2 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM2_CHANNEL4
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM2_CHANNEL
+ int "TIM2 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM2 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+if AT32_TIM2_CHANNEL = 1
+
+config AT32_TIM2_CH1OUT
+ bool "TIM2 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM2_CHANNEL = 1
+
+if AT32_TIM2_CHANNEL = 2
+
+config AT32_TIM2_CH2OUT
+ bool "TIM2 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM2_CHANNEL = 2
+
+if AT32_TIM2_CHANNEL = 3
+
+config AT32_TIM2_CH3OUT
+ bool "TIM2 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # AT32_TIM2_CHANNEL = 3
+
+if AT32_TIM2_CHANNEL = 4
+
+config AT32_TIM2_CH4OUT
+ bool "TIM2 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM2_CHANNEL = 4
+
+config AT32_TIM2_CHMODE
+ int "TIM2 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM2_PWM
+
+config AT32_TIM3_PWM
+ bool "TIM3 PWM"
+ default n
+ depends on AT32_TIM3
+ select AT32_PWM
+ ---help---
+ Reserve timer 3 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM3
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM3_PWM
+
+config AT32_TIM3_MODE
+ int "TIM3 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM3_CHANNEL1
+ bool "TIM3 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM3_CHANNEL1
+
+config AT32_TIM3_CH1MODE
+ int "TIM3 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM3_CH1OUT
+ bool "TIM3 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM3_CHANNEL1
+
+config AT32_TIM3_CHANNEL2
+ bool "TIM3 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if AT32_TIM3_CHANNEL2
+
+config AT32_TIM3_CH2MODE
+ int "TIM3 Channel 2 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM3_CH2OUT
+ bool "TIM3 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM3_CHANNEL2
+
+config AT32_TIM3_CHANNEL3
+ bool "TIM3 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if AT32_TIM3_CHANNEL3
+
+config AT32_TIM3_CH3MODE
+ int "TIM3 Channel 3 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM3_CH3OUT
+ bool "TIM3 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # AT32_TIM3_CHANNEL3
+
+config AT32_TIM3_CHANNEL4
+ bool "TIM3 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if AT32_TIM3_CHANNEL4
+
+config AT32_TIM3_CH4MODE
+ int "TIM3 Channel 4 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM3_CH4OUT
+ bool "TIM3 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM3_CHANNEL4
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM3_CHANNEL
+ int "TIM3 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM3 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+if AT32_TIM3_CHANNEL = 1
+
+config AT32_TIM3_CH1OUT
+ bool "TIM3 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM3_CHANNEL = 1
+
+if AT32_TIM3_CHANNEL = 2
+
+config AT32_TIM3_CH2OUT
+ bool "TIM3 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM3_CHANNEL = 2
+
+if AT32_TIM3_CHANNEL = 3
+
+config AT32_TIM3_CH3OUT
+ bool "TIM3 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # AT32_TIM3_CHANNEL = 3
+
+if AT32_TIM3_CHANNEL = 4
+
+config AT32_TIM3_CH4OUT
+ bool "TIM3 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM3_CHANNEL = 4
+
+config AT32_TIM3_CHMODE
+ int "TIM3 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM3_PWM
+
+config AT32_TIM4_PWM
+ bool "TIM4 PWM"
+ default n
+ depends on AT32_TIM4
+ select AT32_PWM
+ ---help---
+ Reserve timer 4 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM4
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM4_PWM
+
+config AT32_TIM4_MODE
+ int "TIM4 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM4_CHANNEL1
+ bool "TIM4 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM4_CHANNEL1
+
+config AT32_TIM4_CH1MODE
+ int "TIM4 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM4_CH1OUT
+ bool "TIM4 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM4_CHANNEL1
+
+config AT32_TIM4_CHANNEL2
+ bool "TIM4 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if AT32_TIM4_CHANNEL2
+
+config AT32_TIM4_CH2MODE
+ int "TIM4 Channel 2 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM4_CH2OUT
+ bool "TIM4 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM4_CHANNEL2
+
+config AT32_TIM4_CHANNEL3
+ bool "TIM4 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if AT32_TIM4_CHANNEL3
+
+config AT32_TIM4_CH3MODE
+ int "TIM4 Channel 3 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM4_CH3OUT
+ bool "TIM4 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # AT32_TIM4_CHANNEL3
+
+config AT32_TIM4_CHANNEL4
+ bool "TIM4 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if AT32_TIM4_CHANNEL4
+
+config AT32_TIM4_CH4MODE
+ int "TIM4 Channel 4 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM4_CH4OUT
+ bool "TIM4 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM4_CHANNEL4
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM4_CHANNEL
+ int "TIM4 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM4 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+if AT32_TIM4_CHANNEL = 1
+
+config AT32_TIM4_CH1OUT
+ bool "TIM4 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM4_CHANNEL = 1
+
+if AT32_TIM4_CHANNEL = 2
+
+config AT32_TIM4_CH2OUT
+ bool "TIM4 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM4_CHANNEL = 2
+
+if AT32_TIM4_CHANNEL = 3
+
+config AT32_TIM4_CH3OUT
+ bool "TIM4 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # AT32_TIM4_CHANNEL = 3
+
+if AT32_TIM4_CHANNEL = 4
+
+config AT32_TIM4_CH4OUT
+ bool "TIM4 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM4_CHANNEL = 4
+
+config AT32_TIM4_CHMODE
+ int "TIM4 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM4_PWM
+
+config AT32_TIM5_PWM
+ bool "TIM5 PWM"
+ default n
+ depends on AT32_TIM5
+ select AT32_PWM
+ ---help---
+ Reserve timer 5 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM5
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM5_PWM
+
+config AT32_TIM5_MODE
+ int "TIM5 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM5_CHANNEL1
+ bool "TIM5 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM5_CHANNEL1
+
+config AT32_TIM5_CH1MODE
+ int "TIM5 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM5_CH1OUT
+ bool "TIM5 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM5_CHANNEL1
+
+config AT32_TIM5_CHANNEL2
+ bool "TIM5 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if AT32_TIM5_CHANNEL2
+
+config AT32_TIM5_CH2MODE
+ int "TIM5 Channel 2 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM5_CH2OUT
+ bool "TIM5 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM5_CHANNEL2
+
+config AT32_TIM5_CHANNEL3
+ bool "TIM5 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if AT32_TIM5_CHANNEL3
+
+config AT32_TIM5_CH3MODE
+ int "TIM5 Channel 3 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM5_CH3OUT
+ bool "TIM5 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # AT32_TIM5_CHANNEL3
+
+config AT32_TIM5_CHANNEL4
+ bool "TIM5 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if AT32_TIM5_CHANNEL4
+
+config AT32_TIM5_CH4MODE
+ int "TIM5 Channel 4 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM5_CH4OUT
+ bool "TIM5 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM5_CHANNEL4
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM5_CHANNEL
+ int "TIM5 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM5 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+if AT32_TIM5_CHANNEL = 1
+
+config AT32_TIM5_CH1OUT
+ bool "TIM5 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM5_CHANNEL = 1
+
+if AT32_TIM5_CHANNEL = 2
+
+config AT32_TIM5_CH2OUT
+ bool "TIM5 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM5_CHANNEL = 2
+
+if AT32_TIM5_CHANNEL = 3
+
+config AT32_TIM5_CH3OUT
+ bool "TIM5 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+endif # AT32_TIM5_CHANNEL = 3
+
+if AT32_TIM5_CHANNEL = 4
+
+config AT32_TIM5_CH4OUT
+ bool "TIM5 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM5_CHANNEL = 4
+
+config AT32_TIM5_CHMODE
+ int "TIM5 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM5_PWM
+
+config AT32_TIM8_PWM
+ bool "TIM8 PWM"
+ default n
+ depends on AT32_TIM8
+ select AT32_PWM
+ ---help---
+ Reserve timer 8 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM8
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM8_PWM
+
+config AT32_TIM8_MODE
+ int "TIM8 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+config AT32_TIM8_LOCK
+ int "TIM8 Lock Level Configuration"
+ default 0
+ range 0 3
+ ---help---
+ Timer 8 lock level configuration
+
+config AT32_TIM8_DEADTIME
+ int "TIM8 Initial Dead-time"
+ default 0
+ range 0 255
+ ---help---
+ Timer 8 initial dead-time
+
+config AT32_TIM8_TDTS
+ int "TIM8 t_DTS Division"
+ default 0
+ range 0 2
+ ---help---
+ Timer 8 dead-time and sampling clock (t_DTS) division
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM8_CHANNEL1
+ bool "TIM8 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM8_CHANNEL1
+
+config AT32_TIM8_CH1MODE
+ int "TIM8 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM8_CH1OUT
+ bool "TIM8 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+config AT32_TIM8_CH1NOUT
+ bool "TIM8 Channel 1 Complementary Output"
+ default n
+ ---help---
+ Enables channel 1 Complementary Output.
+
+endif # AT32_TIM8_CHANNEL1
+
+config AT32_TIM8_CHANNEL2
+ bool "TIM8 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if AT32_TIM8_CHANNEL2
+
+config AT32_TIM8_CH2MODE
+ int "TIM8 Channel 2 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM8_CH2OUT
+ bool "TIM8 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+config AT32_TIM8_CH2NOUT
+ bool "TIM8 Channel 2 Complementary Output"
+ default n
+ ---help---
+ Enables channel 2 Complementary Output.
+
+endif # AT32_TIM8_CHANNEL2
+
+config AT32_TIM8_CHANNEL3
+ bool "TIM8 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if AT32_TIM8_CHANNEL3
+
+config AT32_TIM8_CH3MODE
+ int "TIM8 Channel 3 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM8_CH3OUT
+ bool "TIM8 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+config AT32_TIM8_CH3NOUT
+ bool "TIM8 Channel 3 Complementary Output"
+ default n
+ ---help---
+ Enables channel 3 Complementary Output.
+
+endif # AT32_TIM8_CHANNEL3
+
+config AT32_TIM8_CHANNEL4
+ bool "TIM8 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if AT32_TIM8_CHANNEL4
+
+config AT32_TIM8_CH4MODE
+ int "TIM8 Channel 4 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM8_CH4OUT
+ bool "TIM8 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM8_CHANNEL4
+
+config AT32_TIM8_CHANNEL5
+ bool "TIM8 Channel 5 (internal)"
+ default n
+ depends on AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Enables channel 5 (not available externally)
+
+if AT32_TIM8_CHANNEL5
+
+config AT32_TIM8_CH5MODE
+ int "TIM8 Channel 5 Mode"
+ default 6
+ range 0 11
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM8_CH5OUT
+ bool "TIM8 Channel 5 Output"
+ default n
+ ---help---
+ Enables channel 5 output.
+
+endif # AT32_TIM8_CHANNEL5
+
+config AT32_TIM8_CHANNEL6
+ bool "TIM8 Channel 6 (internal)"
+ default n
+ depends on AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Enables channel 6 (not available externally)
+
+if AT32_TIM8_CHANNEL6
+
+config AT32_TIM8_CH6MODE
+ int "TIM8 Channel 6 Mode"
+ default 6
+ range 0 11
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM8_CH6OUT
+ bool "TIM8 Channel 6 Output"
+ default n
+ ---help---
+ Enables channel 6 output.
+
+endif # AT32_TIM8_CHANNEL6
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM8_CHANNEL
+ int "TIM8 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM8 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+if AT32_TIM8_CHANNEL = 1
+
+config AT32_TIM8_CH1OUT
+ bool "TIM8 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+config AT32_TIM8_CH1NOUT
+ bool "TIM8 Channel 1 Complementary Output"
+ default n
+ ---help---
+ Enables channel 1 Complementary Output.
+
+endif # AT32_TIM8_CHANNEL = 1
+
+if AT32_TIM8_CHANNEL = 2
+
+config AT32_TIM8_CH2OUT
+ bool "TIM8 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+config AT32_TIM8_CH2NOUT
+ bool "TIM8 Channel 2 Complementary Output"
+ default n
+ ---help---
+ Enables channel 2 Complementary Output.
+
+endif # AT32_TIM8_CHANNEL = 2
+
+if AT32_TIM8_CHANNEL = 3
+
+config AT32_TIM8_CH3OUT
+ bool "TIM8 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+config AT32_TIM8_CH3NOUT
+ bool "TIM8 Channel 3 Complementary Output"
+ default n
+ ---help---
+ Enables channel 3 Complementary Output.
+
+endif # AT32_TIM8_CHANNEL = 3
+
+if AT32_TIM8_CHANNEL = 4
+
+config AT32_TIM8_CH4OUT
+ bool "TIM8 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM8_CHANNEL = 4
+
+config AT32_TIM8_CHMODE
+ int "TIM8 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM8_PWM
+
+config AT32_TIM9_PWM
+ bool "TIM9 PWM"
+ default n
+ depends on AT32_TIM9
+ select AT32_PWM
+ ---help---
+ Reserve timer 9 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM9
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM9_PWM
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM9_CHANNEL1
+ bool "TIM9 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM9_CHANNEL1
+
+config AT32_TIM9_CH1MODE
+ int "TIM9 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM9_CH1OUT
+ bool "TIM9 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM9_CHANNEL1
+
+config AT32_TIM9_CHANNEL2
+ bool "TIM9 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if AT32_TIM9_CHANNEL2
+
+config AT32_TIM9_CH2MODE
+ int "TIM9 Channel 2 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM9_CH2OUT
+ bool "TIM9 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM9_CHANNEL2
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM9_CHANNEL
+ int "TIM9 PWM Output Channel"
+ default 1
+ range 1 2
+ ---help---
+ If TIM9 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,2}
+
+if AT32_TIM9_CHANNEL = 1
+
+config AT32_TIM9_CH1OUT
+ bool "TIM9 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM9_CHANNEL = 1
+
+if AT32_TIM9_CHANNEL = 2
+
+config AT32_TIM9_CH2OUT
+ bool "TIM9 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM9_CHANNEL = 2
+
+config AT32_TIM9_CHMODE
+ int "TIM9 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM9_PWM
+
+config AT32_TIM10_PWM
+ bool "TIM10 PWM"
+ default n
+ depends on AT32_TIM10
+ select AT32_PWM
+ ---help---
+ Reserve timer 10 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM10
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM10_PWM
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM10_CHANNEL1
+ bool "TIM10 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM10_CHANNEL1
+
+config AT32_TIM10_CH1MODE
+ int "TIM10 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM10_CH1OUT
+ bool "TIM10 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM10_CHANNEL1
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM10_CHANNEL
+ int "TIM10 PWM Output Channel"
+ default 1
+ range 1 1
+ ---help---
+ If TIM10 is enabled for PWM usage, you also need specifies the timer output
+ channel {1}
+
+if AT32_TIM10_CHANNEL = 1
+
+config AT32_TIM10_CH1OUT
+ bool "TIM10 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM10_CHANNEL = 1
+
+config AT32_TIM10_CHMODE
+ int "TIM10 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM10_PWM
+
+config AT32_TIM11_PWM
+ bool "TIM11 PWM"
+ default n
+ depends on AT32_TIM11
+ select AT32_PWM
+ ---help---
+ Reserve timer 11 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM11
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM11_PWM
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM11_CHANNEL1
+ bool "TIM11 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM11_CHANNEL1
+
+config AT32_TIM11_CH1MODE
+ int "TIM11 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM11_CH1OUT
+ bool "TIM11 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM11_CHANNEL1
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM11_CHANNEL
+ int "TIM11 PWM Output Channel"
+ default 1
+ range 1 1
+ ---help---
+ If TIM11 is enabled for PWM usage, you also need specifies the timer output
+ channel {1}
+
+if AT32_TIM11_CHANNEL = 1
+
+config AT32_TIM11_CH1OUT
+ bool "TIM11 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM11_CHANNEL = 1
+
+config AT32_TIM11_CHMODE
+ int "TIM11 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM11_PWM
+
+config AT32_TIM12_PWM
+ bool "TIM12 PWM"
+ default n
+ depends on AT32_TIM12
+ select AT32_PWM
+ ---help---
+ Reserve timer 12 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM12
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM12_PWM
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM12_CHANNEL1
+ bool "TIM12 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM12_CHANNEL1
+
+config AT32_TIM12_CH1MODE
+ int "TIM12 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM12_CH1OUT
+ bool "TIM12 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM12_CHANNEL1
+
+config AT32_TIM12_CHANNEL2
+ bool "TIM12 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if AT32_TIM12_CHANNEL2
+
+config AT32_TIM12_CH2MODE
+ int "TIM12 Channel 2 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM12_CH2OUT
+ bool "TIM12 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM12_CHANNEL2
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM12_CHANNEL
+ int "TIM12 PWM Output Channel"
+ default 1
+ range 1 2
+ ---help---
+ If TIM12 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,2}
+
+if AT32_TIM12_CHANNEL = 1
+
+config AT32_TIM12_CH1OUT
+ bool "TIM12 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM12_CHANNEL = 1
+
+if AT32_TIM12_CHANNEL = 2
+
+config AT32_TIM12_CH2OUT
+ bool "TIM12 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM12_CHANNEL = 2
+
+config AT32_TIM12_CHMODE
+ int "TIM12 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM12_PWM
+
+config AT32_TIM13_PWM
+ bool "TIM13 PWM"
+ default n
+ depends on AT32_TIM13
+ select AT32_PWM
+ ---help---
+ Reserve timer 13 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM13
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM13_PWM
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM13_CHANNEL1
+ bool "TIM13 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM13_CHANNEL1
+
+config AT32_TIM13_CH1MODE
+ int "TIM13 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM13_CH1OUT
+ bool "TIM13 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM13_CHANNEL1
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM13_CHANNEL
+ int "TIM13 PWM Output Channel"
+ default 1
+ range 1 1
+ ---help---
+ If TIM13 is enabled for PWM usage, you also need specifies the timer output
+ channel {1}
+
+if AT32_TIM13_CHANNEL = 1
+
+config AT32_TIM13_CH1OUT
+ bool "TIM13 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM13_CHANNEL = 1
+
+config AT32_TIM13_CHMODE
+ int "TIM13 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM13_PWM
+
+config AT32_TIM14_PWM
+ bool "TIM14 PWM"
+ default n
+ depends on AT32_TIM14
+ select AT32_PWM
+ ---help---
+ Reserve timer 14 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM14
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM14_PWM
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM14_CHANNEL1
+ bool "TIM14 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM14_CHANNEL1
+
+config AT32_TIM14_CH1MODE
+ int "TIM14 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM14_CH1OUT
+ bool "TIM14 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM14_CHANNEL1
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM14_CHANNEL
+ int "TIM14 PWM Output Channel"
+ default 1
+ range 1 1
+ ---help---
+ If TIM14 is enabled for PWM usage, you also need specifies the timer output
+ channel {1}
+
+if AT32_TIM14_CHANNEL = 1
+
+config AT32_TIM14_CH1OUT
+ bool "TIM14 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM14_CHANNEL = 1
+
+config AT32_TIM14_CHMODE
+ int "TIM14 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM14_PWM
+
+config AT32_TIM15_PWM
+ bool "TIM15 PWM"
+ default n
+ depends on AT32_TIM15
+ select AT32_PWM
+ ---help---
+ Reserve timer 15 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM15
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM15_PWM
+
+config AT32_TIM15_LOCK
+ int "TIM15 Lock Level Configuration"
+ default 0
+ range 0 3
+ ---help---
+ Timer 15 lock level configuration
+
+config AT32_TIM15_TDTS
+ int "TIM15 t_DTS Division"
+ default 0
+ range 0 2
+ ---help---
+ Timer 15 dead-time and sampling clock (t_DTS) division
+
+config AT32_TIM15_DEADTIME
+ int "TIM15 Initial Dead-time"
+ default 0
+ range 0 255
+ ---help---
+ Timer 15 initial dead-time
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM15_CHANNEL1
+ bool "TIM15 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM15_CHANNEL1
+
+config AT32_TIM15_CH1MODE
+ int "TIM15 Channel 1 Mode"
+ default 6
+ range 0 9 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM15_CH1OUT
+ bool "TIM15 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+config AT32_TIM15_CH1NOUT
+ bool "TIM15 Channel 1 Complementary Output"
+ default n
+ ---help---
+ Enables channel 1 Complementary Output.
+
+endif # AT32_TIM15_CHANNEL1
+
+config AT32_TIM15_CHANNEL2
+ bool "TIM15 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if AT32_TIM15_CHANNEL2
+
+config AT32_TIM15_CH2MODE
+ int "TIM15 Channel 2 Mode"
+ default 6
+ range 0 9 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM15_CH2OUT
+ bool "TIM15 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+endif # AT32_TIM15_CHANNEL2
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM15_CHANNEL
+ int "TIM15 PWM Output Channel"
+ default 1
+ range 1 2
+ ---help---
+ If TIM15 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,2}
+
+if AT32_TIM15_CHANNEL = 1
+
+config AT32_TIM15_CH1OUT
+ bool "TIM15 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+config AT32_TIM15_CH1NOUT
+ bool "TIM15 Channel 1 Complementary Output"
+ default n
+ ---help---
+ Enables channel 1 Complementary Output.
+
+endif # AT32_TIM15_CHANNEL = 1
+
+if AT32_TIM15_CHANNEL = 2
+
+config AT32_TIM15_CH2OUT
+ bool "TIM15 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+config AT32_TIM15_CH2NOUT
+ bool "TIM15 Channel 2 Complementary Output"
+ default n
+ ---help---
+ Enables channel 2 Complementary Output.
+
+endif # AT32_TIM15_CHANNEL = 2
+
+config AT32_TIM15_CHMODE
+ int "TIM15 Channel Mode"
+ default 6
+ range 0 9 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM15_PWM
+
+config AT32_TIM16_PWM
+ bool "TIM16 PWM"
+ default n
+ depends on AT32_TIM16
+ select AT32_PWM
+ ---help---
+ Reserve timer 16 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM16
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM16_PWM
+
+config AT32_TIM16_LOCK
+ int "TIM16 Lock Level Configuration"
+ default 0
+ range 0 3
+ ---help---
+ Timer 16 lock level configuration
+
+config AT32_TIM16_TDTS
+ int "TIM16 t_DTS division"
+ default 0
+ range 0 2
+ ---help---
+ Timer 16 dead-time and sampling clock (t_DTS) division
+
+config AT32_TIM16_DEADTIME
+ int "TIM16 Initial Dead-time"
+ default 0
+ range 0 255
+ ---help---
+ Timer 16 initial dead-time
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM16_CHANNEL1
+ bool "TIM16 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM16_CHANNEL1
+
+config AT32_TIM16_CH1MODE
+ int "TIM16 Channel 1 Mode"
+ default 6
+ range 0 7
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM16_CH1OUT
+ bool "TIM16 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM16_CHANNEL1
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM16_CHANNEL
+ int "TIM16 PWM Output Channel"
+ default 1
+ range 1 1
+ ---help---
+ If TIM16 is enabled for PWM usage, you also need specifies the timer output
+ channel {1}
+
+if AT32_TIM16_CHANNEL = 1
+
+config AT32_TIM16_CH1OUT
+ bool "TIM16 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM16_CHANNEL = 1
+
+config AT32_TIM16_CHMODE
+ int "TIM16 Channel Mode"
+ default 6
+ range 0 7
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM16_PWM
+
+config AT32_TIM17_PWM
+ bool "TIM17 PWM"
+ default n
+ depends on AT32_TIM17
+ select AT32_PWM
+ ---help---
+ Reserve timer 17 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM17
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM17_PWM
+
+config AT32_TIM17_LOCK
+ int "TIM17 Lock Level Configuration"
+ default 0
+ range 0 3
+ ---help---
+ Timer 17 lock level configuration
+
+config AT32_TIM17_TDTS
+ int "TIM17 t_DTS Division"
+ default 0
+ range 0 2
+ ---help---
+ Timer 17 dead-time and sampling clock (t_DTS) division
+
+config AT32_TIM17_DEADTIME
+ int "TIM17 Initial Dead-time"
+ default 0
+ range 0 255
+ ---help---
+ Timer 17 initial dead-time
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM17_CHANNEL1
+ bool "TIM17 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM17_CHANNEL1
+
+config AT32_TIM17_CH1MODE
+ int "TIM17 Channel 1 Mode"
+ default 6
+ range 0 7
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM17_CH1OUT
+ bool "TIM17 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM17_CHANNEL1
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM17_CHANNEL
+ int "TIM17 PWM Output Channel"
+ default 1
+ range 1 1
+ ---help---
+ If TIM17 is enabled for PWM usage, you also need specifies the timer output
+ channel {1}
+
+if AT32_TIM17_CHANNEL = 1
+
+config AT32_TIM17_CH1OUT
+ bool "TIM17 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+endif # AT32_TIM17_CHANNEL = 1
+
+config AT32_TIM17_CHMODE
+ int "TIM17 Channel Mode"
+ default 6
+ range 0 7
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM17_PWM
+
+config AT32_TIM20_PWM
+ bool "TIM20 PWM"
+ default n
+ depends on AT32_TIM20
+ select AT32_PWM
+ ---help---
+ Reserve timer 20 for use by PWM
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If AT32_TIM20
+ is defined then THIS following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation.
+
+if AT32_TIM20_PWM
+
+config AT32_TIM20_MODE
+ int "TIM20 Mode"
+ default 0
+ range 0 4
+ ---help---
+ Specifies the timer mode.
+
+config AT32_TIM20_LOCK
+ int "TIM20 Lock Level Configuration"
+ default 0
+ range 0 3
+ ---help---
+ Timer 1 lock level configuration
+
+config AT32_TIM20_TDTS
+ int "TIM20 t_DTS Division"
+ default 0
+ range 0 2
+ ---help---
+ Timer 1 dead-time and sampling clock (t_DTS) division
+
+config AT32_TIM20_DEADTIME
+ int "TIM20 Initial Dead-time"
+ default 0
+ range 0 255
+ ---help---
+ Timer 1 initial dead-time
+
+if AT32_PWM_MULTICHAN
+
+config AT32_TIM20_CHANNEL1
+ bool "TIM20 Channel 1"
+ default n
+ ---help---
+ Enables channel 1.
+
+if AT32_TIM20_CHANNEL1
+
+config AT32_TIM20_CH1MODE
+ int "TIM20 Channel 1 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM20_CH1OUT
+ bool "TIM20 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+config AT32_TIM20_CH1NOUT
+ bool "TIM20 Channel 1 Complementary Output"
+ default n
+ ---help---
+ Enables channel 1 Complementary Output.
+
+endif # AT32_TIM20_CHANNEL1
+
+config AT32_TIM20_CHANNEL2
+ bool "TIM20 Channel 2"
+ default n
+ ---help---
+ Enables channel 2.
+
+if AT32_TIM20_CHANNEL2
+
+config AT32_TIM20_CH2MODE
+ int "TIM20 Channel 2 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM20_CH2OUT
+ bool "TIM20 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+config AT32_TIM20_CH2NOUT
+ bool "TIM20 Channel 2 Complementary Output"
+ default n
+ ---help---
+ Enables channel 2 Complementary Output.
+
+endif # AT32_TIM20_CHANNEL2
+
+config AT32_TIM20_CHANNEL3
+ bool "TIM20 Channel 3"
+ default n
+ ---help---
+ Enables channel 3.
+
+if AT32_TIM20_CHANNEL3
+
+config AT32_TIM20_CH3MODE
+ int "TIM20 Channel 3 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM20_CH3OUT
+ bool "TIM20 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+config AT32_TIM20_CH3NOUT
+ bool "TIM20 Channel 3 Complementary Output"
+ default n
+ ---help---
+ Enables channel 3 Complementary Output.
+
+endif # AT32_TIM20_CHANNEL3
+
+config AT32_TIM20_CHANNEL4
+ bool "TIM20 Channel 4"
+ default n
+ ---help---
+ Enables channel 4.
+
+if AT32_TIM20_CHANNEL4
+
+config AT32_TIM20_CH4MODE
+ int "TIM20 Channel 4 Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM20_CH4OUT
+ bool "TIM20 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM20_CHANNEL4
+
+config AT32_TIM20_CHANNEL5
+ bool "TIM20 Channel 5 (internal)"
+ default n
+ depends on AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Enables channel 5 (not available externally)
+
+if AT32_TIM20_CHANNEL5
+
+config AT32_TIM20_CH5MODE
+ int "TIM20 Channel 5 Mode"
+ default 6
+ range 0 11
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM20_CH5OUT
+ bool "TIM20 Channel 5 Output"
+ default n
+ ---help---
+ Enables channel 5 output.
+
+endif # AT32_TIM20_CHANNEL5
+
+config AT32_TIM20_CHANNEL6
+ bool "TIM20 Channel 6 (internal)"
+ default n
+ depends on AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Enables channel 6 (not available externally)
+
+if AT32_TIM20_CHANNEL6
+
+config AT32_TIM20_CH6MODE
+ int "TIM20 Channel 6 Mode"
+ default 6
+ range 0 11
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+config AT32_TIM20_CH6OUT
+ bool "TIM20 Channel 6 Output"
+ default n
+ ---help---
+ Enables channel 6 output.
+
+endif # AT32_TIM20_CHANNEL6
+
+endif # AT32_PWM_MULTICHAN
+
+if !AT32_PWM_MULTICHAN
+
+config AT32_TIM20_CHANNEL
+ int "TIM20 PWM Output Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM20 is enabled for PWM usage, you also need specifies the timer output
+ channel {1,..,4}
+
+if AT32_TIM20_CHANNEL = 1
+
+config AT32_TIM20_CH1OUT
+ bool "TIM20 Channel 1 Output"
+ default n
+ ---help---
+ Enables channel 1 output.
+
+config AT32_TIM20_CH1NOUT
+ bool "TIM20 Channel 1 Complementary Output"
+ default n
+ ---help---
+ Enables channel 1 Complementary Output.
+
+endif # AT32_TIM20_CHANNEL = 1
+
+if AT32_TIM20_CHANNEL = 2
+
+config AT32_TIM20_CH2OUT
+ bool "TIM20 Channel 2 Output"
+ default n
+ ---help---
+ Enables channel 2 output.
+
+config AT32_TIM20_CH2NOUT
+ bool "TIM20 Channel 2 Complementary Output"
+ default n
+ ---help---
+ Enables channel 2 Complementary Output.
+
+endif # AT32_TIM20_CHANNEL = 2
+
+if AT32_TIM20_CHANNEL = 3
+
+config AT32_TIM20_CH3OUT
+ bool "TIM20 Channel 3 Output"
+ default n
+ ---help---
+ Enables channel 3 output.
+
+config AT32_TIM20_CH3NOUT
+ bool "TIM20 Channel 3 Complementary Output"
+ default n
+ ---help---
+ Enables channel 3 Complementary Output.
+
+endif # AT32_TIM20_CHANNEL = 3
+
+if AT32_TIM20_CHANNEL = 4
+
+config AT32_TIM20_CH4OUT
+ bool "TIM20 Channel 4 Output"
+ default n
+ ---help---
+ Enables channel 4 output.
+
+endif # AT32_TIM20_CHANNEL = 4
+
+config AT32_TIM20_CHMODE
+ int "TIM20 Channel Mode"
+ default 6
+ range 0 11 if AT32_HAVE_IP_TIMERS_V2
+ range 0 7 if !AT32_HAVE_IP_TIMERS_V2
+ ---help---
+ Specifies the channel mode. See enum at32_pwm_chanmode_e in at32_pwm.h.
+
+endif # !AT32_PWM_MULTICHAN
+
+endif # AT32_TIM20_PWM
+
+config AT32_PWM_MULTICHAN
+ bool "PWM Multiple Output Channels"
+ default n
+ depends on AT32_PWM
+ select ARCH_HAVE_PWM_MULTICHAN
+ ---help---
+ Specifies that the PWM driver supports multiple output
+ channels per timer.
+
+config AT32_PWM_TRGO
+ bool "TIM PWM TRGO support"
+ default n
+ depends on AT32_PWM
+ ---help---
+ Enable TRGO support for PWM driver
+
+config AT32_TIM1_ADC
+ bool "TIM1 ADC"
+ default n
+ depends on AT32_TIM1 && AT32_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If AT32_TIM1 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM1 ADC channel"
+ default AT32_TIM1_ADC1
+ depends on AT32_TIM1_ADC
+
+config AT32_TIM1_ADC1
+ bool "TIM1 ADC channel 1"
+ depends on AT32_ADC1
+ select AT32_HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM1 to trigger ADC1
+
+config AT32_TIM1_ADC2
+ bool "TIM1 ADC channel 2"
+ depends on AT32_ADC2
+ select AT32_HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM1 to trigger ADC2
+
+config AT32_TIM1_ADC3
+ bool "TIM1 ADC channel 3"
+ depends on AT32_ADC3
+ select AT32_HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM1 to trigger ADC3
+
+endchoice
+
+config AT32_TIM2_ADC
+ bool "TIM2 ADC"
+ default n
+ depends on AT32_TIM2 && AT32_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If AT32_TIM2 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM2 ADC channel"
+ default AT32_TIM2_ADC1
+ depends on AT32_TIM2_ADC
+
+config AT32_TIM2_ADC1
+ bool "TIM2 ADC channel 1"
+ depends on AT32_ADC1
+ select AT32_HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM2 to trigger ADC1
+
+config AT32_TIM2_ADC2
+ bool "TIM2 ADC channel 2"
+ depends on AT32_ADC2
+ select AT32_HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM2 to trigger ADC2
+
+config AT32_TIM2_ADC3
+ bool "TIM2 ADC channel 3"
+ depends on AT32_ADC3
+ select AT32_HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM2 to trigger ADC3
+
+endchoice
+
+config AT32_TIM3_ADC
+ bool "TIM3 ADC"
+ default n
+ depends on AT32_TIM3 && AT32_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If AT32_TIM3 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM3 ADC channel"
+ default AT32_TIM3_ADC1
+ depends on AT32_TIM3_ADC
+
+config AT32_TIM3_ADC1
+ bool "TIM3 ADC channel 1"
+ depends on AT32_ADC1
+ select AT32_HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM3 to trigger ADC1
+
+config AT32_TIM3_ADC2
+ bool "TIM3 ADC channel 2"
+ depends on AT32_ADC2
+ select AT32_HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM3 to trigger ADC2
+
+config AT32_TIM3_ADC3
+ bool "TIM3 ADC channel 3"
+ depends on AT32_ADC3
+ select AT32_HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM3 to trigger ADC3
+
+endchoice
+
+config AT32_TIM4_ADC
+ bool "TIM4 ADC"
+ default n
+ depends on AT32_TIM4 && AT32_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If AT32_TIM4 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM4 ADC channel"
+ default AT32_TIM4_ADC1
+ depends on AT32_TIM4_ADC
+
+config AT32_TIM4_ADC1
+ bool "TIM4 ADC channel 1"
+ depends on AT32_ADC1
+ select AT32_HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM4 to trigger ADC1
+
+config AT32_TIM4_ADC2
+ bool "TIM4 ADC channel 2"
+ depends on AT32_ADC2
+ select AT32_HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM4 to trigger ADC2
+
+config AT32_TIM4_ADC3
+ bool "TIM4 ADC channel 3"
+ depends on AT32_ADC3
+ select AT32_HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM4 to trigger ADC3
+
+endchoice
+
+config AT32_TIM5_ADC
+ bool "TIM5 ADC"
+ default n
+ depends on AT32_TIM5 && AT32_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If AT32_TIM5 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM5 ADC channel"
+ default AT32_TIM5_ADC1
+ depends on AT32_TIM5_ADC
+
+config AT32_TIM5_ADC1
+ bool "TIM5 ADC channel 1"
+ depends on AT32_ADC1
+ select AT32_HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM5 to trigger ADC1
+
+config AT32_TIM5_ADC2
+ bool "TIM5 ADC channel 2"
+ depends on AT32_ADC2
+ select AT32_HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM5 to trigger ADC2
+
+config AT32_TIM5_ADC3
+ bool "TIM5 ADC channel 3"
+ depends on AT32_ADC3
+ select AT32_HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM5 to trigger ADC3
+
+endchoice
+
+config AT32_TIM8_ADC
+ bool "TIM8 ADC"
+ default n
+ depends on AT32_TIM8 && AT32_ADC
+ ---help---
+ Reserve timer 1 for use by ADC
+
+ Timer devices may be used for different purposes. If AT32_TIM8 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for ADC conversion. Note that ADC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the ADC, but then you also have to configure which ADC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM8 ADC channel"
+ default AT32_TIM8_ADC1
+ depends on AT32_TIM8_ADC
+
+config AT32_TIM8_ADC1
+ bool "TIM8 ADC channel 1"
+ depends on AT32_ADC1
+ select AT32_HAVE_ADC1_TIMER
+ ---help---
+ Reserve TIM8 to trigger ADC1
+
+config AT32_TIM8_ADC2
+ bool "TIM8 ADC channel 2"
+ depends on AT32_ADC2
+ select AT32_HAVE_ADC2_TIMER
+ ---help---
+ Reserve TIM8 to trigger ADC2
+
+config AT32_TIM8_ADC3
+ bool "TIM8 ADC channel 3"
+ depends on AT32_ADC3
+ select AT32_HAVE_ADC3_TIMER
+ ---help---
+ Reserve TIM8 to trigger ADC3
+
+endchoice
+
+config AT32_HAVE_ADC1_TIMER
+ bool
+
+config AT32_HAVE_ADC2_TIMER
+ bool
+
+config AT32_HAVE_ADC3_TIMER
+ bool
+
+config AT32_HAVE_ADC4_TIMER
+ bool
+
+config AT32_HAVE_ADC5_TIMER
+ bool
+
+config AT32_ADC1_SAMPLE_FREQUENCY
+ int "ADC1 Sampling Frequency"
+ default 100
+ depends on AT32_HAVE_ADC1_TIMER
+ ---help---
+ ADC1 sampling frequency. Default: 100Hz
+
+config AT32_ADC1_TIMTRIG
+ int "ADC1 Timer Trigger"
+ default 0
+ range 0 4
+ depends on AT32_HAVE_ADC1_TIMER
+ ---help---
+ Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config AT32_ADC2_SAMPLE_FREQUENCY
+ int "ADC2 Sampling Frequency"
+ default 100
+ depends on AT32_HAVE_ADC2_TIMER
+ ---help---
+ ADC2 sampling frequency. Default: 100Hz
+
+config AT32_ADC2_TIMTRIG
+ int "ADC2 Timer Trigger"
+ default 0
+ range 0 4
+ depends on AT32_HAVE_ADC2_TIMER
+ ---help---
+ Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config AT32_ADC3_SAMPLE_FREQUENCY
+ int "ADC3 Sampling Frequency"
+ default 100
+ depends on AT32_HAVE_ADC3_TIMER
+ ---help---
+ ADC3 sampling frequency. Default: 100Hz
+
+config AT32_ADC3_TIMTRIG
+ int "ADC3 Timer Trigger"
+ default 0
+ range 0 4
+ depends on AT32_HAVE_ADC3_TIMER
+ ---help---
+ Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config AT32_TIM1_DAC
+ bool "TIM1 DAC"
+ default n
+ depends on AT32_TIM1 && AT32_DAC
+ ---help---
+ Reserve timer 1 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM1 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM1 DAC channel"
+ default AT32_TIM1_DAC1
+ depends on AT32_TIM1_DAC
+
+config AT32_TIM1_DAC1
+ bool "TIM1 DAC channel 1"
+ ---help---
+ Reserve TIM1 to trigger DAC1
+
+config AT32_TIM1_DAC2
+ bool "TIM1 DAC channel 2"
+ ---help---
+ Reserve TIM1 to trigger DAC2
+
+endchoice
+
+config AT32_TIM2_DAC
+ bool "TIM2 DAC"
+ default n
+ depends on AT32_TIM2 && AT32_DAC
+ ---help---
+ Reserve timer 2 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM2 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM2 DAC channel"
+ default AT32_TIM2_DAC1
+ depends on AT32_TIM2_DAC
+
+config AT32_TIM2_DAC1
+ bool "TIM2 DAC channel 1"
+ ---help---
+ Reserve TIM2 to trigger DAC1
+
+config AT32_TIM2_DAC2
+ bool "TIM2 DAC channel 2"
+ ---help---
+ Reserve TIM2 to trigger DAC2
+
+endchoice
+
+config AT32_TIM3_DAC
+ bool "TIM3 DAC"
+ default n
+ depends on AT32_TIM3 && AT32_DAC
+ ---help---
+ Reserve timer 3 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM3 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM3 DAC channel"
+ default AT32_TIM3_DAC1
+ depends on AT32_TIM3_DAC
+
+config AT32_TIM3_DAC1
+ bool "TIM3 DAC channel 1"
+ ---help---
+ Reserve TIM3 to trigger DAC1
+
+config AT32_TIM3_DAC2
+ bool "TIM3 DAC channel 2"
+ ---help---
+ Reserve TIM3 to trigger DAC2
+
+endchoice
+
+config AT32_TIM4_DAC
+ bool "TIM4 DAC"
+ default n
+ depends on AT32_TIM4 && AT32_DAC
+ ---help---
+ Reserve timer 4 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM4 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM4 DAC channel"
+ default AT32_TIM4_DAC1
+ depends on AT32_TIM4_DAC
+
+config AT32_TIM4_DAC1
+ bool "TIM4 DAC channel 1"
+ ---help---
+ Reserve TIM4 to trigger DAC1
+
+config AT32_TIM4_DAC2
+ bool "TIM4 DAC channel 2"
+ ---help---
+ Reserve TIM4 to trigger DAC2
+
+endchoice
+
+config AT32_TIM5_DAC
+ bool "TIM5 DAC"
+ default n
+ depends on AT32_TIM5 && AT32_DAC
+ ---help---
+ Reserve timer 5 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM5 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM5 DAC channel"
+ default AT32_TIM5_DAC1
+ depends on AT32_TIM5_DAC
+
+config AT32_TIM5_DAC1
+ bool "TIM5 DAC channel 1"
+ ---help---
+ Reserve TIM5 to trigger DAC1
+
+config AT32_TIM5_DAC2
+ bool "TIM5 DAC channel 2"
+ ---help---
+ Reserve TIM5 to trigger DAC2
+
+endchoice
+
+config AT32_TIM6_DAC
+ bool "TIM6 DAC"
+ default n
+ depends on AT32_TIM6 && AT32_DAC
+ ---help---
+ Reserve timer 6 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM6 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM6 DAC channel"
+ default AT32_TIM6_DAC1
+ depends on AT32_TIM6_DAC
+
+config AT32_TIM6_DAC1
+ bool "TIM6 DAC channel 1"
+ ---help---
+ Reserve TIM6 to trigger DAC1
+
+config AT32_TIM6_DAC2
+ bool "TIM6 DAC channel 2"
+ ---help---
+ Reserve TIM6 to trigger DAC2
+
+endchoice
+
+config AT32_TIM7_DAC
+ bool "TIM7 DAC"
+ default n
+ depends on AT32_TIM7 && AT32_DAC
+ ---help---
+ Reserve timer 7 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM7 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM7 DAC channel"
+ default AT32_TIM7_DAC1
+ depends on AT32_TIM7_DAC
+
+config AT32_TIM7_DAC1
+ bool "TIM7 DAC channel 1"
+ ---help---
+ Reserve TIM7 to trigger DAC1
+
+config AT32_TIM7_DAC2
+ bool "TIM7 DAC channel 2"
+ ---help---
+ Reserve TIM7 to trigger DAC2
+
+endchoice
+
+config AT32_TIM8_DAC
+ bool "TIM8 DAC"
+ default n
+ depends on AT32_TIM8 && AT32_DAC
+ ---help---
+ Reserve timer 8 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM8 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM8 DAC channel"
+ default AT32_TIM8_DAC1
+ depends on AT32_TIM8_DAC
+
+config AT32_TIM8_DAC1
+ bool "TIM8 DAC channel 1"
+ ---help---
+ Reserve TIM8 to trigger DAC1
+
+config AT32_TIM8_DAC2
+ bool "TIM8 DAC channel 2"
+ ---help---
+ Reserve TIM8 to trigger DAC2
+
+endchoice
+
+config AT32_TIM9_DAC
+ bool "TIM9 DAC"
+ default n
+ depends on AT32_TIM9 && AT32_DAC
+ ---help---
+ Reserve timer 9 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM9 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM9 DAC channel"
+ default AT32_TIM9_DAC1
+ depends on AT32_TIM9_DAC
+
+config AT32_TIM9_DAC1
+ bool "TIM9 DAC channel 1"
+ ---help---
+ Reserve TIM9 to trigger DAC1
+
+config AT32_TIM9_DAC2
+ bool "TIM9 DAC channel 2"
+ ---help---
+ Reserve TIM9 to trigger DAC2
+
+endchoice
+
+config AT32_TIM10_DAC
+ bool "TIM10 DAC"
+ default n
+ depends on AT32_TIM10 && AT32_DAC
+ ---help---
+ Reserve timer 10 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM10 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM10 DAC channel"
+ default AT32_TIM10_DAC1
+ depends on AT32_TIM10_DAC
+
+config AT32_TIM10_DAC1
+ bool "TIM10 DAC channel 1"
+ ---help---
+ Reserve TIM10 to trigger DAC1
+
+config AT32_TIM10_DAC2
+ bool "TIM10 DAC channel 2"
+ ---help---
+ Reserve TIM10 to trigger DAC2
+
+endchoice
+
+config AT32_TIM11_DAC
+ bool "TIM11 DAC"
+ default n
+ depends on AT32_TIM11 && AT32_DAC
+ ---help---
+ Reserve timer 11 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM11 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM11 DAC channel"
+ default AT32_TIM11_DAC1
+ depends on AT32_TIM11_DAC
+
+config AT32_TIM11_DAC1
+ bool "TIM11 DAC channel 1"
+ ---help---
+ Reserve TIM11 to trigger DAC1
+
+config AT32_TIM11_DAC2
+ bool "TIM11 DAC channel 2"
+ ---help---
+ Reserve TIM11 to trigger DAC2
+
+endchoice
+
+config AT32_TIM12_DAC
+ bool "TIM12 DAC"
+ default n
+ depends on AT32_TIM12 && AT32_DAC
+ ---help---
+ Reserve timer 12 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM12 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM12 DAC channel"
+ default AT32_TIM12_DAC1
+ depends on AT32_TIM12_DAC
+
+config AT32_TIM12_DAC1
+ bool "TIM12 DAC channel 1"
+ ---help---
+ Reserve TIM12 to trigger DAC1
+
+config AT32_TIM12_DAC2
+ bool "TIM12 DAC channel 2"
+ ---help---
+ Reserve TIM12 to trigger DAC2
+
+endchoice
+
+config AT32_TIM13_DAC
+ bool "TIM13 DAC"
+ default n
+ depends on AT32_TIM13 && AT32_DAC
+ ---help---
+ Reserve timer 13 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM13 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM13 DAC channel"
+ default AT32_TIM13_DAC1
+ depends on AT32_TIM13_DAC
+
+config AT32_TIM13_DAC1
+ bool "TIM13 DAC channel 1"
+ ---help---
+ Reserve TIM13 to trigger DAC1
+
+config AT32_TIM13_DAC2
+ bool "TIM13 DAC channel 2"
+ ---help---
+ Reserve TIM13 to trigger DAC2
+
+endchoice
+
+config AT32_TIM14_DAC
+ bool "TIM14 DAC"
+ default n
+ depends on AT32_TIM14 && AT32_DAC
+ ---help---
+ Reserve timer 14 for use by DAC
+
+ Timer devices may be used for different purposes. If AT32_TIM14 is
+ defined then the following may also be defined to indicate that the
+ timer is intended to be used for DAC conversion. Note that DAC usage
+ requires two definition: Not only do you have to assign the timer
+ for used by the DAC, but then you also have to configure which DAC
+ channel it is assigned to.
+
+choice
+ prompt "Select TIM14 DAC channel"
+ default AT32_TIM14_DAC1
+ depends on AT32_TIM14_DAC
+
+config AT32_TIM14_DAC1
+ bool "TIM14 DAC channel 1"
+ ---help---
+ Reserve TIM14 to trigger DAC1
+
+config AT32_TIM14_DAC2
+ bool "TIM14 DAC channel 2"
+ ---help---
+ Reserve TIM14 to trigger DAC2
+
+endchoice
+
+config AT32_TIM1_CAP
+ bool "TIM1 Capture"
+ default n
+ depends on AT32_TIM1
+ select AT32_CAP
+ ---help---
+ Reserve timer 1 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM1_CAP
+
+config AT32_TIM1_CHANNEL
+ int "TIM1 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM1 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM1_CLOCK
+ int "TIM1 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM1_CAP
+
+config AT32_TIM2_CAP
+ bool "TIM2 Capture"
+ default n
+ depends on AT32_TIM2
+ select AT32_CAP
+ ---help---
+ Reserve timer 2 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM2_CAP
+
+config AT32_TIM2_CHANNEL
+ int "TIM2 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM2 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM2_CLOCK
+ int "TIM2 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM2_CAP
+
+config AT32_TIM3_CAP
+ bool "TIM3 Capture"
+ default n
+ depends on AT32_TIM3
+ select AT32_CAP
+ ---help---
+ Reserve timer 3 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM3_CAP
+
+config AT32_TIM3_CHANNEL
+ int "TIM3 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM3 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM3_CLOCK
+ int "TIM3 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM3_CAP
+
+config AT32_TIM4_CAP
+ bool "TIM4 Capture"
+ default n
+ depends on AT32_TIM4
+ select AT32_CAP
+ ---help---
+ Reserve timer 4 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM4_CAP
+
+config AT32_TIM4_CHANNEL
+ int "TIM4 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM4 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM4_CLOCK
+ int "TIM4 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM4_CAP
+
+config AT32_TIM5_CAP
+ bool "TIM5 Capture"
+ default n
+ depends on AT32_TIM5
+ select AT32_CAP
+ ---help---
+ Reserve timer 5 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM5_CAP
+
+config AT32_TIM5_CHANNEL
+ int "TIM5 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM5 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM5_CLOCK
+ int "TIM5 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM5_CAP
+
+config AT32_TIM8_CAP
+ bool "TIM8 Capture"
+ default n
+ depends on AT32_TIM8
+ select AT32_CAP
+ ---help---
+ Reserve timer 8 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM8_CAP
+
+config AT32_TIM8_CHANNEL
+ int "TIM8 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM8 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM8_CLOCK
+ int "TIM8 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM8_CAP
+
+config AT32_TIM9_CAP
+ bool "TIM9 Capture"
+ default n
+ depends on AT32_TIM9
+ select AT32_CAP
+ ---help---
+ Reserve timer 9 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM9_CAP
+
+config AT32_TIM9_CHANNEL
+ int "TIM9 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM9 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM9_CLOCK
+ int "TIM9 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM9_CAP
+
+config AT32_TIM10_CAP
+ bool "TIM10 Capture"
+ default n
+ depends on AT32_TIM10
+ select AT32_CAP
+ ---help---
+ Reserve timer 10 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM10_CAP
+
+config AT32_TIM10_CHANNEL
+ int "TIM10 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM10 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM10_CLOCK
+ int "TIM10 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM10_CAP
+
+config AT32_TIM11_CAP
+ bool "TIM11 Capture"
+ default n
+ depends on AT32_TIM11
+ select AT32_CAP
+ ---help---
+ Reserve timer 11 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM11_CAP
+
+config AT32_TIM11_CHANNEL
+ int "TIM11 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM11 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM11_CLOCK
+ int "TIM11 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM11_CAP
+
+config AT32_TIM12_CAP
+ bool "TIM12 Capture"
+ default n
+ depends on AT32_TIM12
+ select AT32_CAP
+ ---help---
+ Reserve timer 12 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM12_CAP
+
+config AT32_TIM12_CHANNEL
+ int "TIM12 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM12 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM12_CLOCK
+ int "TIM12 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM12_CAP
+
+config AT32_TIM13_CAP
+ bool "TIM13 Capture"
+ default n
+ depends on AT32_TIM13
+ select AT32_CAP
+ ---help---
+ Reserve timer 13 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM13_CAP
+
+config AT32_TIM13_CHANNEL
+ int "TIM13 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM13 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM13_CLOCK
+ int "TIM13 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM13_CAP
+
+config AT32_TIM14_CAP
+ bool "TIM14 Capture"
+ default n
+ depends on AT32_TIM14
+ select AT32_CAP
+ ---help---
+ Reserve timer 14 for use by Capture
+
+ Timer devices may be used for different purposes. One special purpose is
+ to capture input.
+
+if AT32_TIM14_CAP
+
+config AT32_TIM14_CHANNEL
+ int "TIM14 Capture Input Channel"
+ default 1
+ range 1 4
+ ---help---
+ If TIM14 is enabled for capture usage, you also need specifies the timer input
+ channel {1,..,4}
+
+config AT32_TIM14_CLOCK
+ int "TIM14 work frequence for capture"
+ default 1000000
+ ---help---
+ This clock frequence limiting the count rate at the expense of resolution.
+
+endif # AT32_TIM14_CAP
+
+menu "AT32 TIMx Outputs Configuration"
+
+config AT32_TIM1_CH1POL
+ int "TIM1 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH1OUT
+ ---help---
+ TIM1 Channel 1 output polarity
+
+config AT32_TIM1_CH1IDLE
+ int "TIM1 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH1OUT
+ ---help---
+ TIM1 Channel 1 output IDLE
+
+config AT32_TIM1_CH1NPOL
+ int "TIM1 Channel 1 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH1NOUT
+ ---help---
+ TIM1 Channel 1 Complementary Output polarity
+
+config AT32_TIM1_CH1NIDLE
+ int "TIM1 Channel 1 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH1NOUT
+ ---help---
+ TIM1 Channel 1 Complementary Output IDLE
+
+config AT32_TIM1_CH2POL
+ int "TIM1 Channel 2 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH2OUT
+ ---help---
+ TIM1 Channel 2 output polarity
+
+config AT32_TIM1_CH2IDLE
+ int "TIM1 Channel 2 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH2OUT
+ ---help---
+ TIM1 Channel 2 output IDLE
+
+config AT32_TIM1_CH2NPOL
+ int "TIM1 Channel 2 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH2NOUT
+ ---help---
+ TIM1 Channel 2 Complementary Output polarity
+
+config AT32_TIM1_CH2NIDLE
+ int "TIM1 Channel 2 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH2NOUT
+ ---help---
+ TIM1 Channel 2 Complementary Output IDLE
+
+config AT32_TIM1_CH3POL
+ int "TIM1 Channel 3 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH3OUT
+ ---help---
+ TIM1 Channel 3 output polarity
+
+config AT32_TIM1_CH3IDLE
+ int "TIM1 Channel 3 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH3OUT
+ ---help---
+ TIM1 Channel 3 output IDLE
+
+config AT32_TIM1_CH3NPOL
+ int "TIM1 Channel 3 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH3NOUT
+ ---help---
+ TIM1 Channel 3 Complementary Output polarity
+
+config AT32_TIM1_CH3NIDLE
+ int "TIM1 Channel 3 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH3NOUT
+ ---help---
+ TIM1 Channel 3 Complementary Output IDLE
+
+config AT32_TIM1_CH4POL
+ int "TIM1 Channel 4 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH4OUT
+ ---help---
+ TIM1 Channel 4 output polarity
+
+config AT32_TIM1_CH4IDLE
+ int "TIM1 Channel 4 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH4OUT
+ ---help---
+ TIM1 Channel 4 output IDLE
+
+config AT32_TIM1_CH5POL
+ int "TIM1 Channel 5 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH5OUT
+ ---help---
+ TIM1 Channel 5 output polarity
+
+config AT32_TIM1_CH5IDLE
+ int "TIM1 Channel 5 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH5OUT
+ ---help---
+ TIM1 Channel 5 output IDLE
+
+config AT32_TIM1_CH6POL
+ int "TIM1 Channel 6 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH6OUT
+ ---help---
+ TIM1 Channel 6 output polarity
+
+config AT32_TIM1_CH6IDLE
+ int "TIM1 Channel 6 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM1_CH6OUT
+ ---help---
+ TIM1 Channel 6 output IDLE
+
+config AT32_TIM2_CH1POL
+ int "TIM2 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM2_CH1OUT
+ ---help---
+ TIM2 Channel 1 output polarity
+
+config AT32_TIM2_CH1IDLE
+ int "TIM2 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM2_CH1OUT
+ ---help---
+ TIM2 Channel 1 output IDLE
+
+config AT32_TIM2_CH2POL
+ int "TIM2 Channel 2 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM2_CH2OUT
+ ---help---
+ TIM2 Channel 2 output polarity
+
+config AT32_TIM2_CH2IDLE
+ int "TIM2 Channel 2 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM2_CH2OUT
+ ---help---
+ TIM2 Channel 2 output IDLE
+
+config AT32_TIM2_CH3POL
+ int "TIM2 Channel 3 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM2_CH3OUT
+ ---help---
+ TIM2 Channel 3 output polarity
+
+config AT32_TIM2_CH3IDLE
+ int "TIM2 Channel 3 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM2_CH3OUT
+ ---help---
+ TIM2 Channel 3 output IDLE
+
+config AT32_TIM2_CH4POL
+ int "TIM2 Channel 4 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM2_CH4OUT
+ ---help---
+ TIM2 Channel 4 output polarity
+
+config AT32_TIM2_CH4IDLE
+ int "TIM2 Channel 4 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM2_CH4OUT
+ ---help---
+ TIM2 Channel 4 output IDLE
+
+config AT32_TIM3_CH1POL
+ int "TIM3 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM3_CH1OUT
+ ---help---
+ TIM3 Channel 1 output polarity
+
+config AT32_TIM3_CH1IDLE
+ int "TIM3 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM3_CH1OUT
+ ---help---
+ TIM3 Channel 1 output IDLE
+
+config AT32_TIM3_CH2POL
+ int "TIM3 Channel 2 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM3_CH2OUT
+ ---help---
+ TIM3 Channel 2 output polarity
+
+config AT32_TIM3_CH2IDLE
+ int "TIM3 Channel 2 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM3_CH2OUT
+ ---help---
+ TIM3 Channel 2 output IDLE
+
+config AT32_TIM3_CH3POL
+ int "TIM3 Channel 3 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM3_CH3OUT
+ ---help---
+ TIM3 Channel 3 output polarity
+
+config AT32_TIM3_CH3IDLE
+ int "TIM3 Channel 3 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM3_CH3OUT
+ ---help---
+ TIM3 Channel 3 output IDLE
+
+config AT32_TIM3_CH4POL
+ int "TIM3 Channel 4 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM3_CH4OUT
+ ---help---
+ TIM3 Channel 4 output polarity
+
+config AT32_TIM3_CH4IDLE
+ int "TIM3 Channel 4 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM3_CH4OUT
+ ---help---
+ TIM3 Channel 4 output IDLE
+
+config AT32_TIM4_CH1POL
+ int "TIM4 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM4_CH1OUT
+ ---help---
+ TIM4 Channel 1 output polarity
+
+config AT32_TIM4_CH1IDLE
+ int "TIM4 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM4_CH1OUT
+ ---help---
+ TIM4 Channel 1 output IDLE
+
+config AT32_TIM4_CH2POL
+ int "TIM4 Channel 2 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM4_CH2OUT
+ ---help---
+ TIM4 Channel 2 output polarity
+
+config AT32_TIM4_CH2IDLE
+ int "TIM4 Channel 2 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM4_CH2OUT
+ ---help---
+ TIM4 Channel 2 output IDLE
+
+config AT32_TIM4_CH3POL
+ int "TIM4 Channel 3 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM4_CH3OUT
+ ---help---
+ TIM4 Channel 3 output polarity
+
+config AT32_TIM4_CH3IDLE
+ int "TIM4 Channel 3 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM4_CH3OUT
+ ---help---
+ TIM4 Channel 3 output IDLE
+
+config AT32_TIM4_CH4POL
+ int "TIM4 Channel 4 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM4_CH4OUT
+ ---help---
+ TIM4 Channel 4 output polarity
+
+config AT32_TIM4_CH4IDLE
+ int "TIM4 Channel 4 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM4_CH4OUT
+ ---help---
+ TIM4 Channel 4 output IDLE
+
+config AT32_TIM5_CH1POL
+ int "TIM5 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM5_CH1OUT
+ ---help---
+ TIM5 Channel 1 output polarity
+
+config AT32_TIM5_CH1IDLE
+ int "TIM5 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM5_CH1OUT
+ ---help---
+ TIM5 Channel 1 output IDLE
+
+config AT32_TIM5_CH2POL
+ int "TIM5 Channel 2 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM5_CH2OUT
+ ---help---
+ TIM5 Channel 2 output polarity
+
+config AT32_TIM5_CH2IDLE
+ int "TIM5 Channel 2 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM5_CH2OUT
+ ---help---
+ TIM5 Channel 2 output IDLE
+
+config AT32_TIM5_CH3POL
+ int "TIM5 Channel 3 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM5_CH3OUT
+ ---help---
+ TIM5 Channel 3 output polarity
+
+config AT32_TIM5_CH3IDLE
+ int "TIM5 Channel 3 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM5_CH3OUT
+ ---help---
+ TIM5 Channel 3 output IDLE
+
+config AT32_TIM5_CH4POL
+ int "TIM5 Channel 4 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM5_CH4OUT
+ ---help---
+ TIM5 Channel 4 output polarity
+
+config AT32_TIM5_CH4IDLE
+ int "TIM5 Channel 4 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM5_CH4OUT
+ ---help---
+ TIM5 Channel 4 output IDLE
+
+config AT32_TIM8_CH1POL
+ int "TIM8 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH1OUT
+ ---help---
+ TIM8 Channel 1 output polarity
+
+config AT32_TIM8_CH1IDLE
+ int "TIM8 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH1OUT
+ ---help---
+ TIM8 Channel 1 output IDLE
+
+config AT32_TIM8_CH1NPOL
+ int "TIM8 Channel 1 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH1NOUT
+ ---help---
+ TIM8 Channel 1 Complementary Output polarity
+
+config AT32_TIM8_CH1NIDLE
+ int "TIM8 Channel 1 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH1NOUT
+ ---help---
+ TIM8 Channel 1 Complementary Output IDLE
+
+config AT32_TIM8_CH2POL
+ int "TIM8 Channel 2 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH2OUT
+ ---help---
+ TIM8 Channel 2 output polarity
+
+config AT32_TIM8_CH2IDLE
+ int "TIM8 Channel 2 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH2OUT
+ ---help---
+ TIM8 Channel 2 output IDLE
+
+config AT32_TIM8_CH2NPOL
+ int "TIM8 Channel 2 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH2NOUT
+ ---help---
+ TIM8 Channel 2 Complementary Output polarity
+
+config AT32_TIM8_CH2NIDLE
+ int "TIM8 Channel 2 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH2NOUT
+ ---help---
+ TIM8 Channel 2 Complementary Output IDLE
+
+config AT32_TIM8_CH3POL
+ int "TIM8 Channel 3 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH3OUT
+ ---help---
+ TIM8 Channel 3 output polarity
+
+config AT32_TIM8_CH3IDLE
+ int "TIM8 Channel 3 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH3OUT
+ ---help---
+ TIM8 Channel 3 output IDLE
+
+config AT32_TIM8_CH3NPOL
+ int "TIM8 Channel 3 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH3NOUT
+ ---help---
+ TIM8 Channel 3 Complementary Output polarity
+
+config AT32_TIM8_CH3NIDLE
+ int "TIM8 Channel 3 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH3NOUT
+ ---help---
+ TIM8 Channel 3 Complementary Output IDLE
+
+config AT32_TIM8_CH4POL
+ int "TIM8 Channel 4 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH4OUT
+ ---help---
+ TIM8 Channel 4 output polarity
+
+config AT32_TIM8_CH4IDLE
+ int "TIM8 Channel 4 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH4OUT
+ ---help---
+ TIM8 Channel 4 output IDLE
+
+config AT32_TIM8_CH5POL
+ int "TIM8 Channel 5 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH5OUT
+ ---help---
+ TIM8 Channel 5 output polarity
+
+config AT32_TIM8_CH5IDLE
+ int "TIM8 Channel 5 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH5OUT
+ ---help---
+ TIM8 Channel 5 output IDLE
+
+config AT32_TIM8_CH6POL
+ int "TIM8 Channel 6 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH6OUT
+ ---help---
+ TIM8 Channel 6 output polarity
+
+config AT32_TIM8_CH6IDLE
+ int "TIM8 Channel 6 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM8_CH6OUT
+ ---help---
+ TIM8 Channel 6 output IDLE
+
+config AT32_TIM9_CH1POL
+ int "TIM9 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM9_CH1OUT
+ ---help---
+ TIM9 Channel 1 output polarity
+
+config AT32_TIM9_CH1IDLE
+ int "TIM9 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM9_CH1OUT
+ ---help---
+ TIM9 Channel 1 output IDLE
+
+config AT32_TIM9_CH2POL
+ int "TIM9 Channel 2 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM9_CH2OUT
+ ---help---
+ TIM9 Channel 2 output polarity
+
+config AT32_TIM9_CH2IDLE
+ int "TIM9 Channel 2 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM9_CH2OUT
+ ---help---
+ TIM9 Channel 2 output IDLE
+
+config AT32_TIM10_CH1POL
+ int "TIM10 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM10_CH1OUT
+ ---help---
+ TIM10 Channel 1 output polarity
+
+config AT32_TIM10_CH1IDLE
+ int "TIM10 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM10_CH1OUT
+ ---help---
+ TIM10 Channel 1 output IDLE
+
+config AT32_TIM11_CH1POL
+ int "TIM11 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM11_CH1OUT
+ ---help---
+ TIM11 Channel 1 output polarity
+
+config AT32_TIM11_CH1IDLE
+ int "TIM11 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM11_CH1OUT
+ ---help---
+ TIM11 Channel 1 output IDLE
+
+config AT32_TIM12_CH1POL
+ int "TIM12 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM12_CH1OUT
+ ---help---
+ TIM12 Channel 1 output polarity
+
+config AT32_TIM12_CH1IDLE
+ int "TIM12 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM12_CH1OUT
+ ---help---
+ TIM12 Channel 1 output IDLE
+
+config AT32_TIM12_CH2POL
+ int "TIM12 Channel 2 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM12_CH2OUT
+ ---help---
+ TIM12 Channel 2 output polarity
+
+config AT32_TIM12_CH2IDLE
+ int "TIM12 Channel 2 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM12_CH2OUT
+ ---help---
+ TIM12 Channel 2 output IDLE
+
+config AT32_TIM13_CH1POL
+ int "TIM13 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM13_CH1OUT
+ ---help---
+ TIM13 Channel 1 output polarity
+
+config AT32_TIM13_CH1IDLE
+ int "TIM13 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM13_CH1OUT
+ ---help---
+ TIM13 Channel 1 output IDLE
+
+config AT32_TIM14_CH1POL
+ int "TIM14 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM14_CH1OUT
+ ---help---
+ TIM14 Channel 1 output polarity
+
+config AT32_TIM14_CH1IDLE
+ int "TIM14 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM14_CH1OUT
+ ---help---
+ TIM14 Channel 1 output IDLE
+
+config AT32_TIM15_CH1POL
+ int "TIM15 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM15_CH1OUT
+ ---help---
+ TIM15 Channel 1 output polarity
+
+config AT32_TIM15_CH1IDLE
+ int "TIM15 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM15_CH1OUT
+ ---help---
+ TIM15 Channel 1 output IDLE
+
+config AT32_TIM15_CH1NPOL
+ int "TIM15 Channel 1 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM15_CH1NOUT
+ ---help---
+ TIM15 Channel 1 Complementary Output polarity
+
+config AT32_TIM15_CH1NIDLE
+ int "TIM15 Channel 1 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM15_CH1NOUT
+ ---help---
+ TIM15 Channel 1 Complementary Output IDLE
+
+config AT32_TIM15_CH2POL
+ int "TIM15 Channel 2 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM15_CH2OUT
+ ---help---
+ TIM15 Channel 2 output polarity
+
+config AT32_TIM15_CH2IDLE
+ int "TIM15 Channel 2 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM15_CH2OUT
+ ---help---
+ TIM15 Channel 2 output IDLE
+
+config AT32_TIM15_CH2NPOL
+ int "TIM15 Channel 2 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM15_CH2NOUT
+ ---help---
+ TIM15 Channel 2 Complementary Output polarity
+
+config AT32_TIM15_CH2NIDLE
+ int "TIM15 Channel 2 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM15_CH2NOUT
+ ---help---
+ TIM15 Channel 2 Complementary Output IDLE
+
+config AT32_TIM16_CH1POL
+ int "TIM16 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM16_CH1OUT
+ ---help---
+ TIM16 Channel 1 output polarity
+
+config AT32_TIM16_CH1IDLE
+ int "TIM16 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM16_CH1OUT
+ ---help---
+ TIM16 Channel 1 output IDLE
+
+config AT32_TIM17_CH1POL
+ int "TIM17 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM17_CH1OUT
+ ---help---
+ TIM17 Channel 1 output polarity
+
+config AT32_TIM17_CH1IDLE
+ int "TIM17 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM17_CH1OUT
+ ---help---
+ TIM17 Channel 1 output IDLE
+
+config AT32_TIM20_CH1POL
+ int "TIM20 Channel 1 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH1OUT
+ ---help---
+ TIM20 Channel 1 output polarity
+
+config AT32_TIM20_CH1IDLE
+ int "TIM20 Channel 1 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH1OUT
+ ---help---
+ TIM20 Channel 1 output IDLE
+
+config AT32_TIM20_CH1NPOL
+ int "TIM20 Channel 1 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH1NOUT
+ ---help---
+ TIM20 Channel 1 Complementary Output polarity
+
+config AT32_TIM20_CH1NIDLE
+ int "TIM20 Channel 1 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH1NOUT
+ ---help---
+ TIM20 Channel 1 Complementary Output IDLE
+
+config AT32_TIM20_CH2POL
+ int "TIM20 Channel 2 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH2OUT
+ ---help---
+ TIM20 Channel 2 output polarity
+
+config AT32_TIM20_CH2IDLE
+ int "TIM20 Channel 2 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH2OUT
+ ---help---
+ TIM20 Channel 2 output IDLE
+
+config AT32_TIM20_CH2NPOL
+ int "TIM20 Channel 2 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH2NOUT
+ ---help---
+ TIM20 Channel 2 Complementary Output polarity
+
+config AT32_TIM20_CH2NIDLE
+ int "TIM20 Channel 2 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH2NOUT
+ ---help---
+ TIM20 Channel 2 Complementary Output IDLE
+
+config AT32_TIM20_CH3POL
+ int "TIM20 Channel 3 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH3OUT
+ ---help---
+ TIM20 Channel 3 output polarity
+
+config AT32_TIM20_CH3IDLE
+ int "TIM20 Channel 3 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH3OUT
+ ---help---
+ TIM20 Channel 3 output IDLE
+
+config AT32_TIM20_CH3NPOL
+ int "TIM20 Channel 3 Complementary Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH3NOUT
+ ---help---
+ TIM20 Channel 3 Complementary Output polarity
+
+config AT32_TIM20_CH3NIDLE
+ int "TIM20 Channel 3 Complementary Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH3NOUT
+ ---help---
+ TIM20 Channel 3 Complementary Output IDLE
+
+config AT32_TIM20_CH4POL
+ int "TIM20 Channel 4 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH4OUT
+ ---help---
+ TIM20 Channel 4 output polarity
+
+config AT32_TIM20_CH4IDLE
+ int "TIM20 Channel 4 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH4OUT
+ ---help---
+ TIM20 Channel 4 output IDLE
+
+config AT32_TIM20_CH5POL
+ int "TIM20 Channel 5 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH5OUT
+ ---help---
+ TIM20 Channel 5 output polarity
+
+config AT32_TIM20_CH5IDLE
+ int "TIM20 Channel 5 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH5OUT
+ ---help---
+ TIM20 Channel 5 output IDLE
+
+config AT32_TIM20_CH6POL
+ int "TIM20 Channel 6 Output polarity"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH6OUT
+ ---help---
+ TIM20 Channel 6 output polarity
+
+config AT32_TIM20_CH6IDLE
+ int "TIM20 Channel 6 Output IDLE"
+ default 0
+ range 0 1
+ depends on AT32_TIM20_CH6OUT
+ ---help---
+ TIM20 Channel 6 output IDLE
+
+endmenu #AT32 TIMx Outputs Configuration
+
+endmenu # Timer Configuration
+
+menu "ADC Configuration"
+ depends on AT32_ADC
+
+config AT32_ADC1_RESOLUTION
+ int "ADC1 resolution"
+ depends on AT32_ADC1 && !AT32_HAVE_IP_ADC_V1_BASIC
+ default 0
+ range 0 3
+ ---help---
+ ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
+
+config AT32_ADC2_RESOLUTION
+ int "ADC2 resolution"
+ depends on AT32_ADC2 && !AT32_HAVE_IP_ADC_V1_BASIC
+ default 0
+ range 0 3
+ ---help---
+ ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
+
+config AT32_ADC3_RESOLUTION
+ int "ADC3 resolution"
+ depends on AT32_ADC3 && !AT32_HAVE_IP_ADC_V1_BASIC
+ default 0
+ range 0 3
+ ---help---
+ ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
+
+config AT32_ADC4_RESOLUTION
+ int "ADC4 resolution"
+ depends on AT32_ADC4 && !AT32_HAVE_IP_ADC_V1_BASIC
+ default 0
+ range 0 3
+ ---help---
+ ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
+
+config AT32_ADC5_RESOLUTION
+ int "ADC5 resolution"
+ depends on AT32_ADC5 && !AT32_HAVE_IP_ADC_V1_BASIC
+ default 0
+ range 0 3
+ ---help---
+ ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
+
+config AT32_ADC_MAX_SAMPLES
+ int "The maximum number of channels that can be sampled"
+ default 16
+ ---help---
+ The maximum number of samples which can be handled without
+ overrun depends on various factors. This is the user's
+ responsibility to correctly select this value.
+ Since the interface to update the sampling time is available
+ for all supported devices, the user can change the default
+ values in the board initialization logic and avoid ADC overrun.
+
+config AT32_ADC_NO_STARTUP_CONV
+ bool "Do not start conversion when opening ADC device"
+ default n
+ ---help---
+ Do not start conversion when opening ADC device.
+
+config AT32_ADC_NOIRQ
+ bool "Do not use default ADC interrupts"
+ default n
+ ---help---
+ Do not use default ADC interrupts handlers.
+
+config AT32_ADC_LL_OPS
+ bool "ADC low-level operations"
+ default n
+ ---help---
+ Enable low-level ADC ops.
+
+config AT32_ADC_CHANGE_SAMPLETIME
+ bool "ADC sample time configuration"
+ default n
+ depends on AT32_ADC_LL_OPS
+ ---help---
+ Enable ADC sample time configuration (SMPRx registers).
+
+config AT32_ADC1_DMA
+ bool "ADC1 DMA"
+ depends on AT32_ADC1 && AT32_HAVE_ADC1_DMA
+ default n
+ ---help---
+ If DMA is selected, then the ADC may be configured to support
+ DMA transfer, which is necessary if multiple channels are read
+ or if very high trigger frequencies are used.
+
+config AT32_ADC1_SCAN
+ bool "ADC1 scan mode"
+ depends on AT32_ADC1 && AT32_HAVE_IP_ADC_V1
+ default y if AT32_ADC1_DMA
+ default n
+
+config AT32_ADC1_DMA_CFG
+ int "ADC1 DMA configuration"
+ depends on AT32_ADC1_DMA && !AT32_HAVE_IP_ADC_V1_BASIC
+ range 0 1
+ default 0
+ ---help---
+ 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode
+
+config AT32_ADC1_ANIOC_TRIGGER
+ int "ADC1 software trigger (ANIOC_TRIGGER) configuration"
+ depends on AT32_ADC1
+ range 1 3
+ default 3
+ ---help---
+ 1 - ANIOC_TRIGGER only starts regular conversion
+ 2 - ANIOC_TRIGGER only starts injected conversion
+ 3 - ANIOC_TRIGGER starts both regular and injected conversions
+
+config AT32_ADC2_DMA
+ bool "ADC2 DMA"
+ depends on AT32_ADC2 && AT32_HAVE_ADC2_DMA
+ default n
+ ---help---
+ If DMA is selected, then the ADC may be configured to support
+ DMA transfer, which is necessary if multiple channels are read
+ or if very high trigger frequencies are used.
+
+config AT32_ADC2_SCAN
+ bool "ADC2 scan mode"
+ depends on AT32_ADC2 && AT32_HAVE_IP_ADC_V1
+ default y if AT32_ADC2_DMA
+ default n
+
+config AT32_ADC2_DMA_CFG
+ int "ADC2 DMA configuration"
+ depends on AT32_ADC2_DMA && !AT32_HAVE_IP_ADC_V1_BASIC
+ range 0 1
+ default 0
+ ---help---
+ 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode
+
+config AT32_ADC2_ANIOC_TRIGGER
+ int "ADC2 software trigger (ANIOC_TRIGGER) configuration"
+ depends on AT32_ADC2
+ range 1 3
+ default 3
+ ---help---
+ 1 - ANIOC_TRIGGER only starts regular conversion
+ 2 - ANIOC_TRIGGER only starts injected conversion
+ 3 - ANIOC_TRIGGER starts both regular and injected conversions
+
+config AT32_ADC3_DMA
+ bool "ADC3 DMA"
+ depends on AT32_ADC3 && AT32_HAVE_ADC3_DMA
+ default n
+ ---help---
+ If DMA is selected, then the ADC may be configured to support
+ DMA transfer, which is necessary if multiple channels are read
+ or if very high trigger frequencies are used.
+
+config AT32_ADC3_SCAN
+ bool "ADC3 scan mode"
+ depends on AT32_ADC3 && AT32_HAVE_IP_ADC_V1
+ default y if AT32_ADC3_DMA
+ default n
+
+config AT32_ADC3_DMA_CFG
+ int "ADC3 DMA configuration"
+ depends on AT32_ADC3_DMA && !AT32_HAVE_IP_ADC_V1_BASIC
+ range 0 1
+ default 0
+ ---help---
+ 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode
+
+config AT32_ADC3_ANIOC_TRIGGER
+ int "ADC3 software trigger (ANIOC_TRIGGER) configuration"
+ depends on AT32_ADC3
+ range 1 3
+ default 3
+ ---help---
+ 1 - ANIOC_TRIGGER only starts regular conversion
+ 2 - ANIOC_TRIGGER only starts injected conversion
+ 3 - ANIOC_TRIGGER starts both regular and injected conversions
+
+config AT32_ADC4_DMA
+ bool "ADC4 DMA"
+ depends on AT32_ADC4 && AT32_HAVE_ADC4_DMA
+ default n
+ ---help---
+ If DMA is selected, then the ADC may be configured to support
+ DMA transfer, which is necessary if multiple channels are read
+ or if very high trigger frequencies are used.
+
+config AT32_ADC4_DMA_CFG
+ int "ADC4 DMA configuration"
+ depends on AT32_ADC4_DMA && !AT32_HAVE_IP_ADC_V1_BASIC
+ range 0 1
+ default 0
+ ---help---
+ 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode
+
+config AT32_ADC4_ANIOC_TRIGGER
+ int "ADC4 software trigger (ANIOC_TRIGGER) configuration"
+ depends on AT32_ADC4
+ range 1 3
+ default 3
+ ---help---
+ 1 - ANIOC_TRIGGER only starts regular conversion
+ 2 - ANIOC_TRIGGER only starts injected conversion
+ 3 - ANIOC_TRIGGER starts both regular and injected conversions
+
+config AT32_ADC5_DMA
+ bool "ADC5 DMA"
+ depends on AT32_ADC5 && AT32_HAVE_ADC5_DMA
+ default n
+ ---help---
+ If DMA is selected, then the ADC may be configured to support
+ DMA transfer, which is necessary if multiple channels are read
+ or if very high trigger frequencies are used.
+
+config AT32_ADC5_DMA_CFG
+ int "ADC5 DMA configuration"
+ depends on AT32_ADC5_DMA && !AT32_HAVE_IP_ADC_V1_BASIC
+ range 0 1
+ default 0
+ ---help---
+ 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode
+
+config AT32_ADC1_INJECTED_CHAN
+ int "ADC1 injected channels"
+ depends on AT32_ADC1
+ range 0 4
+ default 0
+ ---help---
+ Support for ADC1 injected channels.
+
+config AT32_ADC2_INJECTED_CHAN
+ int "ADC2 injected channels"
+ depends on AT32_ADC2
+ range 0 4
+ default 0
+ ---help---
+ Support for ADC2 injected channels.
+
+config AT32_ADC3_INJECTED_CHAN
+ int "ADC3 injected channels"
+ depends on AT32_ADC3
+ range 0 4
+ default 0
+ ---help---
+ Support for ADC3 injected channels.
+
+config AT32_ADC4_INJECTED_CHAN
+ int "ADC4 injected channels"
+ depends on AT32_ADC4
+ range 0 4
+ default 0
+ ---help---
+ Support for ADC4 injected channels.
+
+config AT32_ADC5_INJECTED_CHAN
+ int "ADC5 injected channels"
+ depends on AT32_ADC5
+ range 0 4
+ default 0
+ ---help---
+ Support for ADC5 injected channels.
+
+config AT32_ADC1_EXTSEL
+ bool "ADC1 external trigger for regular group"
+ depends on AT32_ADC1 && !AT32_HAVE_ADC1_TIMER
+ default n
+ ---help---
+ Enable EXTSEL for ADC1.
+
+config AT32_ADC2_EXTSEL
+ bool "ADC2 external trigger for regular group"
+ depends on AT32_ADC2 && !AT32_HAVE_ADC2_TIMER
+ default n
+ ---help---
+ Enable EXTSEL for ADC2.
+
+config AT32_ADC3_EXTSEL
+ bool "ADC3 external trigger for regular group"
+ depends on AT32_ADC3 && !AT32_HAVE_ADC3_TIMER
+ default n
+ ---help---
+ Enable EXTSEL for ADC3.
+
+config AT32_ADC4_EXTSEL
+ bool "ADC4 external trigger for regular group"
+ depends on AT32_ADC4 && !AT32_HAVE_ADC4_TIMER
+ default n
+ ---help---
+ Enable EXTSEL for ADC4.
+
+config AT32_ADC5_EXTSEL
+ bool "ADC5 external trigger for regular group"
+ depends on AT32_ADC5 && !AT32_HAVE_ADC5_TIMER
+ default n
+ ---help---
+ Enable EXTSEL for ADC5.
+
+config AT32_ADC1_JEXTSEL
+ bool "ADC1 external trigger for injected group"
+ depends on AT32_ADC1
+ default n
+ ---help---
+ Enable JEXTSEL for ADC1.
+
+config AT32_ADC2_JEXTSEL
+ bool "ADC2 external trigger for injected group"
+ depends on AT32_ADC2
+ default n
+ ---help---
+ Enable JEXTSEL for ADC2.
+
+config AT32_ADC3_JEXTSEL
+ bool "ADC3 external trigger for injected group"
+ depends on AT32_ADC3
+ default n
+ ---help---
+ Enable JEXTSEL for ADC3.
+
+config AT32_ADC4_JEXTSEL
+ bool "ADC4 external trigger for injected group"
+ depends on AT32_ADC4
+ default n
+ ---help---
+ Enable JEXTSEL for ADC4.
+
+config AT32_ADC5_JEXTSEL
+ bool "ADC5 external trigger for injected group"
+ depends on AT32_ADC5
+ default n
+ ---help---
+ Enable JEXTSEL for ADC5.
+
+endmenu
+
+
+config AT32_USART
+ bool
+ default n
+
+config AT32_USART_RXDMA
+ bool
+ default n
+
+config AT32_SERIALDRIVER
+ bool
+ default n
+
+config AT32_1WIREDRIVER
+ bool
+ default n
+
+config AT32_HCIUART
+ bool
+ default n
+
+config AT32_HCIUART_RXDMA
+ bool
+ default n
+
+menu "U[S]ART Configuration"
+ depends on AT32_USART
+
+comment "U[S]ART Device Configuration"
+
+choice
+ prompt "USART1 Driver Configuration"
+ default AT32_USART1_SERIALDRIVER
+ depends on AT32_USART1
+
+config AT32_USART1_SERIALDRIVER
+ bool "Standard serial driver"
+ select USART1_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select AT32_SERIALDRIVER
+
+config AT32_USART1_1WIREDRIVER
+ bool "1-Wire driver"
+ select AT32_1WIREDRIVER
+
+config AT32_USART1_HCIUART
+ bool "Bluetooth HCI-UART"
+ select AT32_HCIUART
+ depends on WIRELESS_BLUETOOTH
+
+endchoice # USART1 Driver Configuration
+
+if AT32_USART1_SERIALDRIVER
+
+config USART1_RS485
+ bool "RS-485 on USART1"
+ default n
+ ---help---
+ Enable RS-485 interface on USART1. Your board config will have to
+ provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
+ used with USART1_RXDMA.
+
+config USART1_RS485_DIR_POLARITY
+ int "USART1 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on USART1_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART1_RXDMA
+ bool "USART1 Rx DMA"
+ default n
+ depends on AT32_DMA1 || AT32_DMA2
+ select AT32_USART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config USART1_TXDMA
+ bool "USART1 Tx DMA"
+ default n
+ depends on AT32_DMA1 || AT32_DMA2
+ select AT32_USART_TXDMA
+ ---help---
+ In high data rate usage, Tx DMA may reduce CPU load
+
+endif # AT32_USART1_SERIALDRIVER
+
+if AT32_USART1_HCIUART
+
+config AT32_HCIUART1_RXBUFSIZE
+ int "HCI UART1 Rx buffer size"
+ default 80
+ ---help---
+ Characters are buffered as they are received. This specifies
+ the size of the receive buffer. Ideally this should be at least
+ the size of the largest frame that can be received
+
+config AT32_HCIUART1_TXBUFSIZE
+ int "HCI UART1 Transmit buffer size"
+ default 80
+ ---help---
+ Characters are buffered before being sent. This specifies
+ the size of the transmit buffer. Ideally this should be at least
+ the size of the largest frame that can be sent
+
+config AT32_HCIUART1_BAUD
+ int "HCI UART1 initial BAUD rate"
+ default 115200
+ ---help---
+ The configured initial BAUD of the HCIR USART used during bringup.
+ In most cases this initial rate can be increased by the upper half
+ HCI UART driver using vendor-specifi HCI UART commands.
+
+config AT32_HCIUART1_RXDMA
+ bool "HCI UART1 Rx DMA"
+ default n
+ depends on AT32_DMA1 || AT32_DMA2
+ select AT32_HCIUART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+endif # AT32_USART1_HCIUART
+
+choice
+ prompt "USART2 Driver Configuration"
+ default AT32_USART2_SERIALDRIVER
+ depends on AT32_USART2
+
+config AT32_USART2_SERIALDRIVER
+ bool "Standard serial driver"
+ select USART2_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select AT32_SERIALDRIVER
+
+config AT32_USART2_1WIREDRIVER
+ bool "1-Wire driver"
+ select AT32_1WIREDRIVER
+
+config AT32_USART2_HCIUART
+ bool "Bluetooth HCI-UART"
+ select AT32_HCIUART
+ depends on WIRELESS_BLUETOOTH
+
+endchoice # USART2 Driver Configuration
+
+if AT32_USART2_SERIALDRIVER
+
+config USART2_RS485
+ bool "RS-485 on USART2"
+ default n
+ ---help---
+ Enable RS-485 interface on USART2. Your board config will have to
+ provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
+ used with USART2_RXDMA.
+
+config USART2_RS485_DIR_POLARITY
+ int "USART2 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on USART2_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART2_RXDMA
+ bool "USART2 Rx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config USART2_TXDMA
+ bool "USART2 Tx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_TXDMA
+ ---help---
+ In high data rate usage, Tx DMA may reduce CPU load
+
+endif # AT32_USART2_SERIALDRIVER
+
+if AT32_USART2_HCIUART
+
+config AT32_HCIUART2_RXBUFSIZE
+ int "HCI UART2 Rx buffer size"
+ default 80
+ ---help---
+ Characters are buffered as they are received. This specifies
+ the size of the receive buffer. Ideally this should be at least
+ the size of the largest frame that can be received
+
+config AT32_HCIUART2_TXBUFSIZE
+ int "HCI UART2 Transmit buffer size"
+ default 80
+ ---help---
+ Characters are buffered before being sent. This specifies
+ the size of the transmit buffer. Ideally this should be at least
+ the size of the largest frame that can be sent
+
+config AT32_HCIUART2_BAUD
+ int "HCI UART2 initial BAUD rate"
+ default 115200
+ ---help---
+ The configured initial BAUD of the HCIR USART used during bringup.
+ In most cases this initial rate can be increased by the upper half
+ HCI UART driver using vendor-specifi HCI UART commands.
+
+config AT32_HCIUART2_RXDMA
+ bool "HCI UART2 Rx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_HCIUART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+endif # AT32_USART2_HCIUART
+
+choice
+ prompt "USART3 Driver Configuration"
+ default AT32_USART3_SERIALDRIVER
+ depends on AT32_USART3
+
+config AT32_USART3_SERIALDRIVER
+ bool "Standard serial driver"
+ select USART3_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select AT32_SERIALDRIVER
+
+config AT32_USART3_1WIREDRIVER
+ bool "1-Wire driver"
+ select AT32_1WIREDRIVER
+
+config AT32_USART3_HCIUART
+ bool "Bluetooth HCI-UART"
+ select AT32_HCIUART
+ depends on WIRELESS_BLUETOOTH
+
+endchoice # USART3 Driver Configuration
+
+if AT32_USART3_SERIALDRIVER
+
+config USART3_RS485
+ bool "RS-485 on USART3"
+ default n
+ ---help---
+ Enable RS-485 interface on USART3. Your board config will have to
+ provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
+ used with USART3_RXDMA.
+
+config USART3_RS485_DIR_POLARITY
+ int "USART3 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on USART3_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART3_RXDMA
+ bool "USART3 Rx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config USART3_TXDMA
+ bool "USART3 Tx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_TXDMA
+ ---help---
+ In high data rate usage, Tx DMA may reduce CPU load
+
+endif # AT32_USART3_SERIALDRIVER
+
+if AT32_USART3_HCIUART
+
+config AT32_HCIUART3_RXBUFSIZE
+ int "HCI UART3 Rx buffer size"
+ default 80
+ ---help---
+ Characters are buffered as they are received. This specifies
+ the size of the receive buffer. Ideally this should be at least
+ the size of the largest frame that can be received
+
+config AT32_HCIUART3_TXBUFSIZE
+ int "HCI UART3 Transmit buffer size"
+ default 80
+ ---help---
+ Characters are buffered before being sent. This specifies
+ the size of the transmit buffer. Ideally this should be at least
+ the size of the largest frame that can be sent
+
+config AT32_HCIUART3_BAUD
+ int "HCI UART3 initial BAUD rate"
+ default 115200
+ ---help---
+ The configured initial BAUD of the HCIR USART used during bringup.
+ In most cases this initial rate can be increased by the upper half
+ HCI UART driver using vendor-specifi HCI UART commands.
+
+config AT32_HCIUART3_RXDMA
+ bool "HCI UART3 Rx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_HCIUART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+endif # AT32_USART3_HCIUART
+
+choice
+ prompt "UART4 Driver Configuration"
+ default AT32_UART4_SERIALDRIVER
+ depends on AT32_UART4
+
+config AT32_UART4_SERIALDRIVER
+ bool "Standard serial driver"
+ select UART4_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select AT32_SERIALDRIVER
+
+config AT32_UART4_1WIREDRIVER
+ bool "1-Wire driver"
+ select AT32_1WIREDRIVER
+
+endchoice # UART1 Driver Configuration
+
+if AT32_UART4_SERIALDRIVER
+
+config UART4_RS485
+ bool "RS-485 on UART4"
+ default n
+ ---help---
+ Enable RS-485 interface on UART4. Your board config will have to
+ provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be
+ used with UART4_RXDMA.
+
+config UART4_RS485_DIR_POLARITY
+ int "UART4 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on UART4_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART4_RXDMA
+ bool "UART4 Rx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART4_TXDMA
+ bool "UART4 Tx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_TXDMA
+ ---help---
+ In high data rate usage, Tx DMA may reduce CPU load
+
+endif # AT32_UART4_SERIALDRIVER
+
+choice
+ prompt "UART5 Driver Configuration"
+ default AT32_UART5_SERIALDRIVER
+ depends on AT32_UART5
+
+config AT32_UART5_SERIALDRIVER
+ bool "Standard serial driver"
+ select UART5_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select AT32_SERIALDRIVER
+
+config AT32_UART5_1WIREDRIVER
+ bool "1-Wire driver"
+ select AT32_1WIREDRIVER
+
+endchoice # UART5 Driver Configuration
+
+if AT32_UART5_SERIALDRIVER
+
+config UART5_RS485
+ bool "RS-485 on UART5"
+ default n
+ ---help---
+ Enable RS-485 interface on UART5. Your board config will have to
+ provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be
+ used with UART5_RXDMA.
+
+config UART5_RS485_DIR_POLARITY
+ int "UART5 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on UART5_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART5_RXDMA
+ bool "UART5 Rx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART5_TXDMA
+ bool "UART5 Tx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_TXDMA
+ ---help---
+ In high data rate usage, Tx DMA may reduce CPU load
+
+endif # AT32_UART5_SERIALDRIVER
+
+choice
+ prompt "USART6 Driver Configuration"
+ default AT32_USART6_SERIALDRIVER
+ depends on AT32_USART6
+
+config AT32_USART6_SERIALDRIVER
+ bool "Standard serial driver"
+ select USART6_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select AT32_SERIALDRIVER
+
+config AT32_USART6_1WIREDRIVER
+ bool "1-Wire driver"
+ select AT32_1WIREDRIVER
+
+config AT32_USART6_HCIUART
+ bool "Bluetooth HCI-UART"
+ select AT32_HCIUART
+ depends on WIRELESS_BLUETOOTH
+
+endchoice # USART6 Driver Configuration
+
+if AT32_USART6_SERIALDRIVER
+
+config USART6_RS485
+ bool "RS-485 on USART6"
+ default n
+ ---help---
+ Enable RS-485 interface on USART6. Your board config will have to
+ provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be
+ used with USART6_RXDMA.
+
+config USART6_RS485_DIR_POLARITY
+ int "USART6 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on USART6_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART6_RXDMA
+ bool "USART6 Rx DMA"
+ default n
+ depends on AT32_DMA2
+ select AT32_USART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config USART6_TXDMA
+ bool "USART6 Tx DMA"
+ default n
+ depends on AT32_DMA2
+ select AT32_USART_TXDMA
+ ---help---
+ In high data rate usage, Tx DMA may reduce CPU load
+
+endif # AT32_USART6_SERIALDRIVER
+
+if AT32_USART6_HCIUART
+
+config AT32_HCIUART6_RXBUFSIZE
+ int "HCI UART6 Rx buffer size"
+ default 80
+ ---help---
+ Characters are buffered as they are received. This specifies
+ the size of the receive buffer. Ideally this should be at least
+ the size of the largest frame that can be received
+
+config AT32_HCIUART6_TXBUFSIZE
+ int "HCI UART6 Transmit buffer size"
+ default 80
+ ---help---
+ Characters are buffered before being sent. This specifies
+ the size of the transmit buffer. Ideally this should be at least
+ the size of the largest frame that can be sent
+
+config AT32_HCIUART6_BAUD
+ int "HCI UART6 initial BAUD rate"
+ default 115200
+ ---help---
+ The configured initial BAUD of the HCIR USART used during bringup.
+ In most cases this initial rate can be increased by the upper half
+ HCI UART driver using vendor-specifi HCI UART commands.
+
+config AT32_HCIUART6_RXDMA
+ bool "HCI UART6 Rx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_HCIUART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+endif # AT32_USART6_HCIUART
+
+choice
+ prompt "UART7 Driver Configuration"
+ default AT32_UART7_SERIALDRIVER
+ depends on AT32_UART7
+
+config AT32_UART7_SERIALDRIVER
+ bool "Standard serial driver"
+ select UART7_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select AT32_SERIALDRIVER
+
+config AT32_UART7_1WIREDRIVER
+ bool "1-Wire driver"
+ select AT32_1WIREDRIVER
+
+config AT32_UART7_HCIUART
+ bool "Bluetooth HCI-UART"
+ select AT32_HCIUART
+ depends on WIRELESS_BLUETOOTH
+
+endchoice # UART7 Driver Configuration
+
+if AT32_UART7_SERIALDRIVER
+
+config UART7_RS485
+ bool "RS-485 on UART7"
+ default n
+ ---help---
+ Enable RS-485 interface on UART7. Your board config will have to
+ provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be
+ used with UART7_RXDMA.
+
+config UART7_RS485_DIR_POLARITY
+ int "UART7 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on UART7_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART7_RXDMA
+ bool "UART7 Rx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART7_TXDMA
+ bool "UART7 Tx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_TXDMA
+ ---help---
+ In high data rate usage, Tx DMA may reduce CPU load
+
+endif # AT32_UART7_SERIALDRIVER
+
+if AT32_UART7_HCIUART
+
+config AT32_HCIUART7_RXBUFSIZE
+ int "HCI UART7 Rx buffer size"
+ default 80
+ ---help---
+ Characters are buffered as they are received. This specifies
+ the size of the receive buffer. Ideally this should be at least
+ the size of the largest frame that can be received
+
+config AT32_HCIUART7_TXBUFSIZE
+ int "HCI UART7 Transmit buffer size"
+ default 80
+ ---help---
+ Characters are buffered before being sent. This specifies
+ the size of the transmit buffer. Ideally this should be at least
+ the size of the largest frame that can be sent
+
+config AT32_HCIUART7_BAUD
+ int "HCI UART7 initial BAUD rate"
+ default 115200
+ ---help---
+ The configured initial BAUD of the HCIR USART used during bringup.
+ In most cases this initial rate can be increased by the upper half
+ HCI UART driver using vendor-specifi HCI UART commands.
+
+config AT32_HCIUART7_RXDMA
+ bool "HCI UART7 Rx DMA"
+ default n
+ depends on AT32_DMA2
+ select AT32_HCIUART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+endif # AT32_UART7_HCIUART
+
+choice
+ prompt "UART8 Driver Configuration"
+ default AT32_UART8_SERIALDRIVER
+ depends on AT32_UART8
+
+config AT32_UART8_SERIALDRIVER
+ bool "Standard serial driver"
+ select UART8_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select AT32_SERIALDRIVER
+
+config AT32_UART8_1WIREDRIVER
+ bool "1-Wire driver"
+ select AT32_1WIREDRIVER
+
+config AT32_UART8_HCIUART
+ bool "Bluetooth HCI-UART"
+ select AT32_HCIUART
+ depends on WIRELESS_BLUETOOTH
+
+endchoice # UART8 Driver Configuration
+
+if AT32_UART8_SERIALDRIVER
+
+config UART8_RS485
+ bool "RS-485 on UART8"
+ default n
+ ---help---
+ Enable RS-485 interface on UART8. Your board config will have to
+ provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be
+ used with UART8_RXDMA.
+
+config UART8_RS485_DIR_POLARITY
+ int "UART8 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on UART8_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config UART8_RXDMA
+ bool "UART8 Rx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+config UART8_TXDMA
+ bool "UART8 Tx DMA"
+ default n
+ depends on AT32_DMA1
+ select AT32_USART_TXDMA
+ ---help---
+ In high data rate usage, Tx DMA may reduce CPU load
+
+endif # AT32_UART8_SERIALDRIVER
+
+if AT32_UART8_HCIUART
+
+config AT32_HCIUART8_RXBUFSIZE
+ int "HCI UART8 Rx buffer size"
+ default 80
+ ---help---
+ Characters are buffered as they are received. This specifies
+ the size of the receive buffer. Ideally this should be at least
+ the size of the largest frame that can be received
+
+config AT32_HCIUART8_TXBUFSIZE
+ int "HCI UART8 Transmit buffer size"
+ default 80
+ ---help---
+ Characters are buffered before being sent. This specifies
+ the size of the transmit buffer. Ideally this should be at least
+ the size of the largest frame that can be sent
+
+config AT32_HCIUART8_BAUD
+ int "HCI UART8 initial BAUD rate"
+ default 115200
+ ---help---
+ The configured initial BAUD of the HCIR USART used during bringup.
+ In most cases this initial rate can be increased by the upper half
+ HCI UART driver using vendor-specifi HCI UART commands.
+
+config AT32_HCIUART8_RXDMA
+ bool "HCI UART8 Rx DMA"
+ default n
+ depends on AT32_DMA2
+ select AT32_HCIUART_RXDMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+endif # AT32_UART8_HCIUART
+
+menu "Serial Driver Configuration"
+ depends on AT32_SERIALDRIVER
+
+config AT32_SERIAL_RXDMA_BUFFER_SIZE
+ int "Rx DMA buffer size"
+ default 32
+ range 32 4096
+ depends on AT32_USART_RXDMA
+ ---help---
+ The DMA buffer size when using RX DMA to emulate a FIFO.
+
+ When streaming data, the generic serial layer will be called
+ every time the FIFO receives half or this number of bytes.
+
+ Value given here will be rounded up to next multiple of 4 bytes.
+
+config AT32_SERIAL_DISABLE_REORDERING
+ bool "Disable reordering of ttySx devices."
+ default n
+ ---help---
+ NuttX per default reorders the serial ports (/dev/ttySx) so that the
+ console is always on /dev/ttyS0. If more than one UART is in use this
+ can, however, have the side-effect that all port mappings
+ (hardware USART1 -> /dev/ttyS0) change if the console is moved to another
+ UART. This is in particular relevant if a project uses the USB console
+ in some boards and a serial console in other boards, but does not
+ want the side effect of having all serial port names change when just
+ the console is moved from serial to USB.
+
+config AT32_FLOWCONTROL_BROKEN
+ bool "Use Software UART RTS flow control"
+ default n
+ ---help---
+ Enable UART RTS flow control using Software. Because Artery
+ Current AT32 have broken HW based RTS behavior (they assert
+ nRTS after every byte received) Enable this setting workaround
+ this issue by using software based management of RTS
+
+config AT32_USART_BREAKS
+ bool "Add TIOxSBRK to support sending Breaks"
+ default n
+ ---help---
+ Add TIOCxBRK routines to send a line break per the AT32 manual, the
+ break will be a pulse based on the value M. This is not a BSD compatible
+ break.
+
+config AT32_SERIALBRK_BSDCOMPAT
+ bool "Use GPIO To send Break"
+ depends on AT32_USART_BREAKS
+ default n
+ ---help---
+ Enable using GPIO on the TX pin to send a BSD compatible break:
+ TIOCSBRK will start the break and TIOCCBRK will end the break.
+ The current AT32 U[S]ARTS have no way to leave the break on
+ (TX=LOW) because software starts the break and then the hardware
+ automatically clears the break. This makes it difficult to send
+ a long break.
+
+config AT32_USART_SINGLEWIRE
+ bool "Single Wire Support"
+ default n
+ depends on AT32_USART
+ ---help---
+ Enable single wire UART support. The option enables support for the
+ TIOCSSINGLEWIRE ioctl in the AT32 serial driver.
+
+endmenu # Serial Driver Configuration
+
+menu "HCI UART Driver Configuration"
+ depends on AT32_SERIALDRIVER
+
+config AT32_HCIUART_RXDMA_BUFSIZE
+ int "Rx DMA buffer size"
+ default 32
+ range 32 4096
+ depends on AT32_HCIUART_RXDMA
+ ---help---
+ The DMA buffer size when using RX DMA to emulate a FIFO.
+
+ When streaming data, the generic serial layer will be called
+ every time the FIFO receives half or this number of bytes.
+
+ Value given here will be rounded up to next multiple of 4 bytes.
+
+config AT32_HCIUART_RXDMAPRIO
+ hex "HCI UART DMA priority"
+ default 0x00001000
+ depends on AT32_HCIUART_RXDMA
+ ---help---
+ Select HCI UART DMA priority.
+
+
+config AT32_HCIUART_SW_RXFLOW
+ bool "Use Software UART RTS flow control"
+ default n
+ ---help---
+ Enable UART RTS flow control using Software. Current AT32 have
+ broken HW based RTS behavior (they assert nRTS after every byte
+ received) Enable this setting workaround this issue by using
+ software based management of RTS
+
+ If HCI UART DMA is enabled, this is probably the better selection
+ as well. In that case, the Rx DMA buffer will avoid Rx overrun due
+ to short, bursty activity. Software RTS management will probably
+ result in overall better throughput and should still avoid Rx data
+ overrun conditions.
+
+config AT32_HCIUART_UPPER_WATERMARK
+ int "RTS flow control upper watermark (%)"
+ default 75
+ range 2 100
+ depends on AT32_HCIUART_SW_RXFLOW
+ ---help---
+ If software RTS flow control is enable, then RTS will be asserted
+ when this amount of Rx data has been buffered. The amount is
+ expressed as a percentage of the Rx buffer size.
+
+config AT32_HCIUART_LOWER_WATERMARK
+ int "RTS flow control lower watermark (%)"
+ default 25
+ range 1 99
+ depends on AT32_HCIUART_SW_RXFLOW
+ ---help---
+ If software RTS flow control is enable, then RTS will be de-asserted
+ when there is less than this amount ofdata in the Rx buffere. The
+ amount is expressed as a percentage of the Rx buffer size.
+
+endmenu # HCI UART Driver Configuration
+
+if PM
+
+config AT32_PM_SERIAL_ACTIVITY
+ int "PM serial activity"
+ default 10
+ ---help---
+ PM activity reported to power management logic on every serial
+ interrupt.
+
+endif
+
+endmenu # U[S]ART Configuration
+
+menu "SPI Configuration"
+ depends on AT32_SPI
+
+config AT32_SPI_INTERRUPTS
+ bool "Interrupt driver SPI"
+ default n
+ ---help---
+ Select to enable interrupt driven SPI support. Non-interrupt-driven,
+ poll-waiting is recommended if the interrupt rate would be to high in
+ the interrupt driven case.
+
+config AT32_SPI1_DMA
+ bool "SPI1 DMA"
+ default n
+ depends on AT32_SPI1 && !AT32_SPI_INTERRUPT
+ select AT32_SPI_DMA
+ ---help---
+ Use DMA to improve SPI1 transfer performance. Cannot be used with AT32_SPI_INTERRUPT.
+
+config AT32_SPI1_DMA_BUFFER
+ int "SPI1 DMA buffer size"
+ default 0
+ depends on AT32_SPI1_DMA
+ ---help---
+ Add a properly aligned DMA buffer for RX and TX DMA for SPI1.
+
+config AT32_SPI_DMATHRESHOLD
+ int "SPI DMA threshold"
+ default 4
+ depends on AT32_SPI_DMA
+ ---help---
+ When SPI DMA is enabled, small DMA transfers will still be performed
+ by polling logic. But we need a threshold value to determine what
+ is small.
+
+config AT32_SPI2_DMA
+ bool "SPI2 DMA"
+ default n
+ depends on AT32_SPI2 && !AT32_SPI_INTERRUPT
+ select AT32_SPI_DMA
+ ---help---
+ Use DMA to improve SPI2 transfer performance. Cannot be used with AT32_SPI_INTERRUPT.
+
+config AT32_SPI2_DMA_BUFFER
+ int "SPI2 DMA buffer size"
+ default 0
+ depends on AT32_SPI2_DMA
+ ---help---
+ Add a properly aligned DMA buffer for RX and TX DMA for SPI2.
+
+config AT32_SPI3_DMA
+ bool "SPI3 DMA"
+ default n
+ depends on AT32_SPI3 && !AT32_SPI_INTERRUPT
+ select AT32_SPI_DMA
+ ---help---
+ Use DMA to improve SPI3 transfer performance. Cannot be used with AT32_SPI_INTERRUPT.
+
+config AT32_SPI3_DMA_BUFFER
+ int "SPI3 DMA buffer size"
+ default 0
+ depends on AT32_SPI3_DMA
+ ---help---
+ Add a properly aligned DMA buffer for RX and TX DMA for SPI3.
+
+config AT32_SPI4_DMA
+ bool "SPI4 DMA"
+ default n
+ depends on AT32_SPI4 && !AT32_SPI_INTERRUPT
+ select AT32_SPI_DMA
+ ---help---
+ Use DMA to improve SPI4 transfer performance. Cannot be used with AT32_SPI_INTERRUPT.
+
+config AT32_SPI4_DMA_BUFFER
+ int "SPI4 DMA buffer size"
+ default 0
+ depends on AT32_SPI4_DMA
+ ---help---
+ Add a properly aligned DMA buffer for RX and TX DMA for SPI4.
+
+endmenu # SPI Configuration
+
+
+menu "I2C Configuration"
+ depends on AT32_I2C
+
+config AT32_I2C_DYNTIMEO
+ bool "Use dynamic timeouts"
+ default n
+ depends on AT32_I2C
+
+config AT32_I2C_DYNTIMEO_USECPERBYTE
+ int "Timeout Microseconds per Byte"
+ default 500
+ depends on AT32_I2C_DYNTIMEO
+
+config AT32_I2C_DYNTIMEO_STARTSTOP
+ int "Timeout for Start/Stop (Milliseconds)"
+ default 1000
+ depends on AT32_I2C_DYNTIMEO
+
+config AT32_I2CTIMEOSEC
+ int "Timeout seconds"
+ default 0
+ depends on AT32_I2C
+
+config AT32_I2CTIMEOMS
+ int "Timeout Milliseconds"
+ default 500
+ depends on AT32_I2C && !AT32_I2C_DYNTIMEO
+
+config AT32_I2CTIMEOTICKS
+ int "Timeout for Done and Stop (ticks)"
+ default 500
+ depends on AT32_I2C && !AT32_I2C_DYNTIMEO
+
+config AT32_I2C_DUTY16_9
+ bool "Frequency with Tlow/Thigh = 16/9"
+ default n
+ depends on AT32_I2C
+
+config AT32_I2C_DMA
+ bool "I2C DMA Support"
+ default n
+ depends on AT32_I2C && AT32_AT32F43XX && (AT32_DMA1 || AT32_DMA2) && !I2C_POLLED
+ ---help---
+ This option enables the DMA for I2C transfers.
+ Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the
+ I2C dma streams, else the default priority level is set to medium.
+
+endmenu
+
+menu "SDIO Configuration"
+ depends on (AT32_SDIO || AT32_SDIO2)
+
+config AT32_SDIO_CARD
+ bool "SDIO Card support"
+ default n
+ ---help---
+ Build in additional support needed only for SDIO cards (vs. SD
+ memory cards)
+
+config AT32_SDIO_PULLUP
+ bool "Enable internal Pull-Ups"
+ default n
+ ---help---
+ If you are using an external SDCard module that does not have the
+ pull-up resistors for the SDIO interface (like the Gadgeteer SD Card
+ Module) then enable this option to activate the internal pull-up
+ resistors.
+
+config AT32_SDIO_DMA
+ bool "Support DMA data transfers"
+ default y if AT32_DMA2
+ default n if !AT32_DMA2
+ select SDIO_DMA
+ depends on AT32_DMA2
+ ---help---
+ Support DMA data transfers. Requires AT32_SDIO and config AT32_DMA2.
+
+config AT32_SDIO_DMAPRIO
+ hex "SDIO DMA priority"
+ default 0x00001000
+ ---help---
+ Select SDIO DMA priority.
+
+ For AT32 , options are: 0x00000000 low, 0x00001000 medium,
+ 0x00002000 high, 0x00003000 very high. Default: medium.
+
+
+config AT32_SDIO_WIDTH_D1_ONLY
+ bool "Use D1 only"
+ default n
+ ---help---
+ Select 1-bit transfer mode. Default: 4-bit transfer mode.
+
+endmenu
+
+
+config AT32_HAVE_RTC_COUNTER
+ bool
+ default n
+
+config AT32_HAVE_RTC_SUBSECONDS
+ bool
+ select ARCH_HAVE_RTC_SUBSECONDS
+ default n
+
+menu "RTC Configuration"
+ depends on AT32_RTC
+
+config AT32_RTC_MAGIC_REG
+ int "BKP register"
+ default 0
+ range 0 19
+ depends on !AT32_HAVE_RTC_COUNTER
+ ---help---
+ The BKP register used to store/check the Magic value to determine if
+ RTC is already setup
+
+config AT32_RTC_MAGIC
+ hex "RTC Magic 1"
+ default 0xfacefeed
+ depends on !AT32_HAVE_RTC_COUNTER
+ ---help---
+ Value used as Magic to determine if the RTC is already setup
+
+config AT32_RTC_MAGIC_TIME_SET
+ hex "RTC Magic 2"
+ default 0xf00dface
+ depends on !AT32_HAVE_RTC_COUNTER
+ ---help---
+ Value used as Magic to determine if the RTC has been setup and has
+ time set
+
+choice
+ prompt "RTC clock source"
+ default AT32_RTC_LSECLOCK
+
+config AT32_RTC_LSECLOCK
+ bool "LSE clock"
+ ---help---
+ Drive the RTC with the LSE clock
+
+config AT32_RTC_LSICLOCK
+ bool "LSI clock"
+ ---help---
+ Drive the RTC with the LSI clock
+
+config AT32_RTC_HSECLOCK
+ bool "HSE clock"
+ ---help---
+ Drive the RTC with the HSE clock, divided down to 1MHz.
+
+endchoice # RTC clock source
+endmenu # RTC configuration
+
+menu "Ethernet MAC configuration"
+ depends on AT32_ETHMAC
+
+config AT32_PHYADDR
+ int "PHY address"
+ default 1
+ ---help---
+ The 5-bit address of the PHY on the board. Default: 1
+
+config AT32_PHYINIT
+ bool "Board-specific PHY Initialization"
+ default n
+ ---help---
+ Some boards require specialized initialization of the PHY before it can be used.
+ This may include such things as configuring GPIOs, resetting the PHY, etc. If
+ AT32_PHYINIT is defined in the configuration then the board specific logic must
+ provide at32_phyinitialize(); The AT32 Ethernet driver will call this function
+ one time before it first uses the PHY.
+
+config AT32_MII
+ bool "Use MII interface"
+ default n
+ ---help---
+ Support Ethernet MII interface.
+
+choice
+ prompt "MII clock configuration"
+ default AT32_MII_MCO1 if AT32_AT32F43XX
+ depends on AT32_MII
+
+config AT32_MII_MCO1
+ bool "Use MC01 as MII clock"
+ depends on AT32_AT32F43XX
+ ---help---
+ Use MCO1 to clock the MII interface. Default: Use MC01
+
+config AT32_MII_MCO2
+ bool "Use MC02 as MII clock"
+ depends on AT32_AT32F43XX
+ ---help---
+ Use MCO2 to clock the MII interface. Default: Use MC01
+
+config AT32_MII_EXTCLK
+ bool "External MII clock"
+ ---help---
+ Clocking is provided by external logic. Don't use MCO for MII
+ clock. Default: Use MC0[1]
+
+endchoice
+
+config AT32_AUTONEG
+ bool "Use autonegotiation"
+ default y
+ ---help---
+ Use PHY autonegotiation to determine speed and mode
+
+config AT32_ETHFD
+ bool "Full duplex"
+ default n
+ depends on !AT32_AUTONEG
+ ---help---
+ If AT32_AUTONEG is not defined, then this may be defined to select full duplex
+ mode. Default: half-duplex
+
+config AT32_ETH100MBPS
+ bool "100 Mbps"
+ default n
+ depends on !AT32_AUTONEG
+ ---help---
+ If AT32_AUTONEG is not defined, then this may be defined to select 100 MBps
+ speed. Default: 10 Mbps
+
+config AT32_PHYSR
+ int "PHY Status Register Address (decimal)"
+ depends on AT32_AUTONEG
+ ---help---
+ This must be provided if AT32_AUTONEG is defined. The PHY status register
+ address may diff from PHY to PHY. This configuration sets the address of
+ the PHY status register.
+
+config AT32_PHYSR_ALTCONFIG
+ bool "PHY Status Alternate Bit Layout"
+ default n
+ depends on AT32_AUTONEG
+ ---help---
+ Different PHYs present speed and mode information in different ways. Some
+ will present separate information for speed and mode (this is the default).
+ Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
+ full/half duplex indication. This options selects an alternative representation
+ where speed and mode information are combined. This might mean, for example,
+ separate bits for 10HD, 100HD, 10FD and 100FD.
+
+config AT32_PHYSR_SPEED
+ hex "PHY Speed Mask"
+ depends on AT32_AUTONEG && !AT32_PHYSR_ALTCONFIG
+ ---help---
+ This must be provided if AT32_AUTONEG is defined. This provides bit mask
+ for isolating the 10 or 100MBps speed indication.
+
+config AT32_PHYSR_100MBPS
+ hex "PHY 100Mbps Speed Value"
+ depends on AT32_AUTONEG && !AT32_PHYSR_ALTCONFIG
+ ---help---
+ This must be provided if AT32_AUTONEG is defined. This provides the value
+ of the speed bit(s) indicating 100MBps speed.
+
+config AT32_PHYSR_MODE
+ hex "PHY Mode Mask"
+ depends on AT32_AUTONEG && !AT32_PHYSR_ALTCONFIG
+ ---help---
+ This must be provided if AT32_AUTONEG is defined. This provide bit mask
+ for isolating the full or half duplex mode bits.
+
+config AT32_PHYSR_FULLDUPLEX
+ hex "PHY Full Duplex Mode Value"
+ depends on AT32_AUTONEG && !AT32_PHYSR_ALTCONFIG
+ ---help---
+ This must be provided if AT32_AUTONEG is defined. This provides the
+ value of the mode bits indicating full duplex mode.
+
+config AT32_PHYSR_ALTMODE
+ hex "PHY Mode Mask"
+ depends on AT32_AUTONEG && AT32_PHYSR_ALTCONFIG
+ ---help---
+ This must be provided if AT32_AUTONEG is defined. This provide bit mask
+ for isolating the speed and full/half duplex mode bits.
+
+config AT32_PHYSR_10HD
+ hex "10MBase-T Half Duplex Value"
+ depends on AT32_AUTONEG && AT32_PHYSR_ALTCONFIG
+ ---help---
+ This must be provided if AT32_AUTONEG is defined. This is the value
+ under the bit mask that represents the 10Mbps, half duplex setting.
+
+config AT32_PHYSR_100HD
+ hex "100Base-T Half Duplex Value"
+ depends on AT32_AUTONEG && AT32_PHYSR_ALTCONFIG
+ ---help---
+ This must be provided if AT32_AUTONEG is defined. This is the value
+ under the bit mask that represents the 100Mbps, half duplex setting.
+
+config AT32_PHYSR_10FD
+ hex "10Base-T Full Duplex Value"
+ depends on AT32_AUTONEG && AT32_PHYSR_ALTCONFIG
+ ---help---
+ This must be provided if AT32_AUTONEG is defined. This is the value
+ under the bit mask that represents the 10Mbps, full duplex setting.
+
+config AT32_PHYSR_100FD
+ hex "100Base-T Full Duplex Value"
+ depends on AT32_AUTONEG && AT32_PHYSR_ALTCONFIG
+ ---help---
+ This must be provided if AT32_AUTONEG is defined. This is the value
+ under the bit mask that represents the 100Mbps, full duplex setting.
+
+config AT32_ETH_PTP
+ bool "Precision Time Protocol (PTP)"
+ default n
+ ---help---
+ Precision Time Protocol (PTP). Not supported but some hooks are indicated
+ with this condition.
+
+config AT32_RMII
+ bool
+ default y if !AT32_MII
+
+choice
+ prompt "RMII clock configuration"
+ default AT32_RMII_MCO1 if AT32_AT32F43XX
+ depends on AT32_RMII
+
+config AT32_RMII_MCO1
+ bool "Use MC01 as RMII clock"
+ depends on AT32_AT32F43XX
+ ---help---
+ Use MCO1 to clock the RMII interface. Default: Use MC01
+
+config AT32_RMII_MCO2
+ bool "Use MC02 as RMII clock"
+ depends on AT32_AT32F43XX
+ ---help---
+ Use MCO2 to clock the RMII interface. Default: Use MC01
+
+config AT32_RMII_EXTCLK
+ bool "External RMII clock"
+ ---help---
+ Clocking is provided by external logic. Don't use MCO for RMII
+ clock. Default: Use MC0[1]
+
+endchoice
+
+config AT32_ETHMAC_REGDEBUG
+ bool "Register-Level Debug"
+ default n
+ depends on DEBUG_NET_INFO
+ ---help---
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES.
+
+endmenu # Ethernet MAC configuration
+
+config AT32_USBHOST
+ bool "Enable USB Host Support"
+ depends on AT32_OTGFS || AT32_OTGFS2
+ default n
+ select USBHOST
+
+menu "USB FS Host Configuration"
+ depends on AT32_OTGFS && AT32_USBHOST
+
+config AT32_OTGFS_RXFIFO_SIZE
+ int "Rx Packet Size"
+ default 128
+ ---help---
+ Size of the RX FIFO in 32-bit words. Default 128 (512 bytes)
+
+config AT32_OTGFS_NPTXFIFO_SIZE
+ int "Non-periodic Tx FIFO Size"
+ default 96
+ ---help---
+ Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
+
+config AT32_OTGFS_PTXFIFO_SIZE
+ int "Periodic Tx FIFO size"
+ default 128
+ ---help---
+ Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
+
+config AT32_OTGFS_DESCSIZE
+ int "Descriptor Size"
+ default 128
+ ---help---
+ Maximum size to allocate for descriptor memory descriptor. Default: 128
+
+config AT32_OTGFS_SOFINTR
+ bool "Enable SOF interrupts"
+ default n
+ ---help---
+ Enable SOF interrupts. Why would you ever want to do that?
+
+config AT32_OTGFS_VBUS_CONTROL
+ bool "Enable VBus Control"
+ default y
+ ---help---
+ Enable VBus control. Used when the board has VBus sensing and
+ a power switch for the OTG FS USB port. Disable this config
+ if the board lacks this USB VBus control circuitry.
+
+endmenu
+
+menu "USB FS2 Host Configuration"
+ depends on AT32_OTGFS2 && AT32_USBHOST
+
+config AT32_OTGFS2_RXFIFO_SIZE
+ int "Rx Packet Size"
+ default 128
+ ---help---
+ Size of the RX FIFO in 32-bit words. Default 128 (512 bytes)
+
+config AT32_OTGFS2_NPTXFIFO_SIZE
+ int "Non-periodic Tx FIFO Size"
+ default 96
+ ---help---
+ Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
+
+config AT32_OTGFS2_PTXFIFO_SIZE
+ int "Periodic Tx FIFO size"
+ default 128
+ ---help---
+ Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
+
+config AT32_OTGFS2_DESCSIZE
+ int "Descriptor Size"
+ default 128
+ ---help---
+ Maximum size to allocate for descriptor memory descriptor. Default: 128
+
+config AT32_OTGFS2_SOFINTR
+ bool "Enable SOF interrupts"
+ default n
+ ---help---
+ Enable SOF interrupts. Why would you ever want to do that?
+
+config AT32_OTGFS2_VBUS_CONTROL
+ bool "Enable VBus Control"
+ default y
+ ---help---
+ Enable VBus control. Used when the board has VBus sensing and
+ a power switch for the OTG FS2 USB port. Disable this config
+ if the board lacks this USB VBus control circuitry.
+
+endmenu
+
+menu "USB Host Debug Configuration"
+ depends on AT32_USBHOST
+
+config AT32_USBHOST_REGDEBUG
+ bool "Register-Level Debug"
+ default n
+ depends on AT32_USBHOST && DEBUG_USB_INFO
+ ---help---
+ Enable very low-level register access debug.
+
+config AT32_USBHOST_PKTDUMP
+ bool "Packet Dump Debug"
+ default n
+ depends on AT32_USBHOST && DEBUG_USB_INFO
+ ---help---
+ Dump all incoming and outgoing USB packets.
+
+endmenu
+
+comment "USB Device Configuration"
+
+menu "USB Full Speed Debug Configuration"
+ depends on AT32_USBFS
+
+config AT32_USBFS_REGDEBUG
+ bool "Register-Level Debug"
+ default n
+ depends on AT32_USBFS && DEBUG_USB_INFO
+ ---help---
+ Enable very low-level register access debug.
+
+endmenu
+
+menu "OTG Configuration"
+ depends on (AT32_OTGFS || AT32_OTGFS2)
+
+config OTG_ID_GPIO_DISABLE
+ bool "Disable the use of GPIO_OTG_ID pin."
+ default n
+ ---help---
+ Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use
+ cases to reuse this GPIO pin and ensure it is not set incorrectlty
+ during OS boot.
+
+endmenu
+
+
+menu "CAN driver configuration"
+ depends on AT32_CAN
+
+choice
+ prompt "CAN character driver or SocketCAN support"
+ default AT32_CAN_CHARDRIVER
+
+config AT32_CAN_CHARDRIVER
+ bool "AT32 CAN character driver support"
+ select ARCH_HAVE_CAN_ERRORS
+ select CAN
+
+config AT32_CAN_SOCKET
+ bool "AT32 CAN SocketCAN support"
+ select NET_CAN_HAVE_ERRORS
+
+endchoice # CAN character driver or SocketCAN support
+
+config AT32_CAN1_BAUD
+ int "CAN1 BAUD"
+ default 250000
+ depends on AT32_CAN1
+ ---help---
+ CAN1 BAUD rate. Required if CONFIG_AT32_CAN1 is defined.
+
+config AT32_CAN2_BAUD
+ int "CAN2 BAUD"
+ default 250000
+ depends on AT32_CAN2
+ ---help---
+ CAN2 BAUD rate. Required if CONFIG_AT32_CAN2 is defined.
+
+config AT32_CAN_TSEG1
+ int "TSEG1 quanta"
+ default 13
+ ---help---
+ The number of CAN time quanta in segment 1. Default: 13
+
+config AT32_CAN_TSEG2
+ int "TSEG2 quanta"
+ default 2
+ ---help---
+ The number of CAN time quanta in segment 2. Default: 2
+
+config AT32_CAN_REGDEBUG
+ bool "CAN Register level debug"
+ depends on DEBUG_CAN_INFO
+ default n
+ ---help---
+ Output detailed register-level CAN device debug information.
+ Requires also CONFIG_DEBUG_CAN_INFO.
+
+endmenu # "CAN driver configuration"
+
+
+menu "AT32 QEncoder Driver"
+ depends on SENSORS_QENCODER
+ depends on AT32_TIM1 || AT32_TIM2 || AT32_TIM3 || AT32_TIM4 || AT32_TIM5 || AT32_TIM8
+
+config AT32_QENCODER_DISABLE_EXTEND16BTIMERS
+ bool "Disable QEncoder timers extension from 16-bit to 32-bit"
+ default n
+
+config AT32_QENCODER_INDEX_PIN
+ bool "Enable QEncoder timers support for index pin"
+ default n
+
+config AT32_TIM1_QE
+ bool "TIM1 QE"
+ default n
+ depends on AT32_TIM1
+ ---help---
+ Reserve TIM1 for use by QEncoder.
+
+if AT32_TIM1_QE
+
+config AT32_TIM1_QEPSC
+ int "TIM1 QE pulse prescaler"
+ default 1
+ ---help---
+ This prescaler divides the number of recorded encoder pulses,
+ limiting the count rate at the expense of resolution.
+
+endif
+
+config AT32_TIM2_QE
+ bool "TIM2 QE"
+ default n
+ depends on AT32_TIM2
+ ---help---
+ Reserve TIM2 for use by QEncoder.
+
+if AT32_TIM2_QE
+
+config AT32_TIM2_QEPSC
+ int "TIM2 QE pulse prescaler"
+ default 1
+ ---help---
+ This prescaler divides the number of recorded encoder pulses,
+ limiting the count rate at the expense of resolution.
+
+endif
+
+config AT32_TIM3_QE
+ bool "TIM3 QE"
+ default n
+ depends on AT32_TIM3
+ ---help---
+ Reserve TIM3 for use by QEncoder.
+
+if AT32_TIM3_QE
+
+config AT32_TIM3_QEPSC
+ int "TIM3 QE pulse prescaler"
+ default 1
+ ---help---
+ This prescaler divides the number of recorded encoder pulses,
+ limiting the count rate at the expense of resolution.
+
+endif
+
+config AT32_TIM4_QE
+ bool "TIM4 QE"
+ default n
+ depends on AT32_TIM4
+ ---help---
+ Reserve TIM4 for use by QEncoder.
+
+if AT32_TIM4_QE
+
+config AT32_TIM4_QEPSC
+ int "TIM4 QE pulse prescaler"
+ default 1
+ ---help---
+ This prescaler divides the number of recorded encoder pulses,
+ limiting the count rate at the expense of resolution.
+
+endif
+
+config AT32_TIM5_QE
+ bool "TIM5 QE"
+ default n
+ depends on AT32_TIM5
+ ---help---
+ Reserve TIM5 for use by QEncoder.
+
+if AT32_TIM5_QE
+
+config AT32_TIM5_QEPSC
+ int "TIM5 QE pulse prescaler"
+ default 1
+ ---help---
+ This prescaler divides the number of recorded encoder pulses,
+ limiting the count rate at the expense of resolution.
+
+endif
+
+config AT32_TIM8_QE
+ bool "TIM8 QE"
+ default n
+ depends on AT32_TIM8
+ ---help---
+ Reserve TIM8 for use by QEncoder.
+
+if AT32_TIM8_QE
+
+config AT32_TIM8_QEPSC
+ int "TIM8 QE pulse prescaler"
+ default 1
+ ---help---
+ This prescaler divides the number of recorded encoder pulses,
+ limiting the count rate at the expense of resolution.
+
+endif
+
+config AT32_QENCODER_FILTER
+ bool "Enable filtering on AT32 QEncoder input"
+ default y
+
+choice
+ depends on AT32_QENCODER_FILTER
+ prompt "Input channel sampling frequency"
+ default AT32_QENCODER_SAMPLE_FDTS_4
+
+config AT32_QENCODER_SAMPLE_FDTS
+ bool "fDTS"
+
+config AT32_QENCODER_SAMPLE_CKINT
+ bool "fCK_INT"
+
+config AT32_QENCODER_SAMPLE_FDTS_2
+ bool "fDTS/2"
+
+config AT32_QENCODER_SAMPLE_FDTS_4
+ bool "fDTS/4"
+
+config AT32_QENCODER_SAMPLE_FDTS_8
+ bool "fDTS/8"
+
+config AT32_QENCODER_SAMPLE_FDTS_16
+ bool "fDTS/16"
+
+config AT32_QENCODER_SAMPLE_FDTS_32
+ bool "fDTS/32"
+
+endchoice
+
+choice
+ depends on AT32_QENCODER_FILTER
+ prompt "Input channel event count"
+ default AT32_QENCODER_SAMPLE_EVENT_6
+
+config AT32_QENCODER_SAMPLE_EVENT_1
+ depends on AT32_QENCODER_SAMPLE_FDTS
+ bool "1"
+
+config AT32_QENCODER_SAMPLE_EVENT_2
+ depends on AT32_QENCODER_SAMPLE_CKINT
+ bool "2"
+
+config AT32_QENCODER_SAMPLE_EVENT_4
+ depends on AT32_QENCODER_SAMPLE_CKINT
+ bool "4"
+
+config AT32_QENCODER_SAMPLE_EVENT_5
+ depends on AT32_QENCODER_SAMPLE_FDTS_16 || AT32_QENCODER_SAMPLE_FDTS_32
+ bool "5"
+
+config AT32_QENCODER_SAMPLE_EVENT_6
+ depends on !AT32_QENCODER_SAMPLE_FDTS && !AT32_QENCODER_SAMPLE_CKINT
+ bool "6"
+
+config AT32_QENCODER_SAMPLE_EVENT_8
+ depends on !AT32_QENCODER_SAMPLE_FDTS
+ bool "8"
+
+endchoice
+
+endmenu
+
diff --git a/arch/arm/src/at32/Make.defs b/arch/arm/src/at32/Make.defs
new file mode 100644
index 0000000000..9d24ca0a83
--- /dev/null
+++ b/arch/arm/src/at32/Make.defs
@@ -0,0 +1,181 @@
+############################################################################
+# arch/arm/src/at32/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include armv7-m/Make.defs
+
+CHIP_CSRCS = at32_allocateheap.c at32_start.c at32_rcc.c at32_lse.c
+CHIP_CSRCS += at32_lsi.c at32_gpio.c at32_exti_gpio.c at32_flash.c
+CHIP_CSRCS += at32_irq.c at32_lowputc.c
+CHIP_CSRCS += at32_waste.c at32_uid.c
+CHIP_CSRCS += at32_serial.c
+
+ifeq ($(CONFIG_AT32_TIM),y)
+CHIP_CSRCS += at32_tim.c
+endif
+
+ifeq ($(CONFIG_AT32_SDIO),y)
+CHIP_CSRCS += at32_sdio.c
+endif
+
+ifeq ($(CONFIG_AT32_SPI),y)
+CHIP_CSRCS += at32_spi.c
+endif
+
+ifeq ($(CONFIG_AT32_DMA),y)
+CHIP_CSRCS += at32_dma.c
+endif
+
+ifeq ($(CONFIG_TIMER),y)
+CHIP_CSRCS += at32_tim_lowerhalf.c
+endif
+
+ifdef CONFIG_AT32_TICKLESS_TIMER
+CHIP_CSRCS += at32_tickless.c
+else
+CHIP_CSRCS += at32_timerisr.c
+endif
+
+ifeq ($(CONFIG_AT32_ONESHOT),y)
+CHIP_CSRCS += at32_oneshot.c at32_oneshot_lowerhalf.c
+endif
+
+ifeq ($(CONFIG_AT32_FREERUN),y)
+CHIP_CSRCS += at32_freerun.c
+endif
+
+ifeq ($(CONFIG_BUILD_PROTECTED),y)
+CHIP_CSRCS += at32_userspace.c at32_mpuinit.c
+endif
+
+ifeq ($(CONFIG_AT32_I2C),y)
+CHIP_CSRCS += at32_i2c.c
+endif
+
+ifeq ($(CONFIG_USBDEV),y)
+ifeq ($(CONFIG_AT32_USB),y)
+CHIP_CSRCS += at32_usbdev.c
+endif
+ifeq ($(CONFIG_AT32_USBFS),y)
+CHIP_CSRCS += at32_usbfs.c
+endif
+ifeq ($(CONFIG_AT32_OTGFS),y)
+CHIP_CSRCS += at32_otgfsdev.c
+endif
+endif
+
+ifeq ($(CONFIG_AT32_USBHOST),y)
+ifeq ($(CONFIG_AT32_OTGFS),y)
+CHIP_CSRCS += at32_otgfshost.c
+endif
+ifeq ($(CONFIG_USBHOST_TRACE),y)
+CHIP_CSRCS += at32_usbhost.c
+else
+ifeq ($(CONFIG_DEBUG_USB),y)
+CHIP_CSRCS += at32_usbhost.c
+endif
+endif
+endif
+
+ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
+CHIP_CSRCS += at32_idle.c
+endif
+
+CHIP_CSRCS += at32_pmstop.c at32_pmstandby.c at32_pmsleep.c
+
+ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
+CHIP_CSRCS += at32_pminitialize.c
+endif
+
+ifeq ($(CONFIG_AT32_ETHMAC),y)
+CHIP_CSRCS += at32_eth.c
+endif
+
+ifeq ($(CONFIG_AT32_PWR),y)
+CHIP_CSRCS += at32_pwr.c at32_exti_pwr.c
+endif
+
+ifeq ($(CONFIG_AT32_RTC),y)
+CHIP_CSRCS += at32_rtc.c
+ifeq ($(CONFIG_RTC_ALARM),y)
+CHIP_CSRCS += at32_exti_alarm.c
+endif
+ifeq ($(CONFIG_RTC_PERIODIC),y)
+CHIP_CSRCS += at32_exti_wakeup.c
+endif
+ifeq ($(CONFIG_RTC_DRIVER),y)
+CHIP_CSRCS += at32_rtc_lowerhalf.c
+endif
+endif
+
+ifeq ($(CONFIG_AT32_ADC),y)
+CHIP_CSRCS += at32_adc.c
+endif
+
+ifeq ($(CONFIG_AT32_DAC),y)
+CHIP_CSRCS += at32_dac.c
+endif
+
+ifeq ($(CONFIG_AT32_1WIREDRIVER),y)
+CHIP_CSRCS += at32_1wire.c
+endif
+
+ifeq ($(CONFIG_AT32_HCIUART),y)
+CHIP_CSRCS += at32_hciuart.c
+endif
+
+ifeq ($(CONFIG_AT32_PWM),y)
+CHIP_CSRCS += at32_pwm.c
+endif
+
+ifeq ($(CONFIG_AT32_CAP),y)
+CHIP_CSRCS += at32_capture_lowerhalf.c
+endif
+
+
+ifeq ($(CONFIG_SENSORS_HALL3PHASE),y)
+CHIP_CSRCS += at32_hall3ph.c
+endif
+
+ifeq ($(CONFIG_AT32_CAN),y)
+ifeq ($(CONFIG_AT32_CAN_CHARDRIVER),y)
+CHIP_CSRCS += at32_can.c
+endif
+ifeq ($(CONFIG_AT32_CAN_SOCKET),y)
+CHIP_CSRCS += at32_can_sock.c
+endif
+endif
+
+ifeq ($(CONFIG_AT32_IWDG),y)
+CHIP_CSRCS += at32_iwdg.c
+endif
+
+ifeq ($(CONFIG_AT32_WWDG),y)
+CHIP_CSRCS += at32_wwdg.c
+endif
+
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
+CHIP_CSRCS += at32_dumpgpio.c
+endif
+
+ifeq ($(CONFIG_AT32_FOC),y)
+CHIP_CSRCS += at32_foc.c
+endif
+
+
diff --git a/arch/arm/src/at32/at32.h b/arch/arm/src/at32/at32.h
new file mode 100644
index 0000000000..9293581573
--- /dev/null
+++ b/arch/arm/src/at32/at32.h
@@ -0,0 +1,57 @@
+/****************************************************************************
+ * arch/arm/src/at32/at32.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_AT32_AT32_H
+#define __ARCH_ARM_SRC_AT32_AT32_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "arm_internal.h"
+
+/* Peripherals **************************************************************/
+
+#include "chip.h"
+#include "at32_gpio.h"
+#include "at32_uart.h"
+#include "at32_exti.h"
+#include "at32_flash.h"
+#include "at32_dma.h"
+#include "at32_pwr.h"
+#include "at32_rcc.h"
+#include "at32_lowputc.h"
+#include "at32_adc.h"
+#include "at32_can.h"
+#include "at32_i2c.h"
+#include "at32_rtc.h"
+#include "at32_sdio.h"
+#include "at32_spi.h"
+#include "at32_tim.h"
+#include "at32_eth.h"
+#include "at32_wdg.h"
+#include "at32_dbgmcu.h"
+
+#endif /* __ARCH_ARM_SRC_AT32_AT32_H */
diff --git a/arch/arm/src/at32/at32_adc.c b/arch/arm/src/at32/at32_adc.c
new file mode 100644
index 0000000000..59efce00a2
--- /dev/null
+++ b/arch/arm/src/at32/at32_adc.c
@@ -0,0 +1,4433 @@
+/****************************************************************************
+ * arch/arm/src/at32/at32_adc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <sys/types.h>
+#include <inttypes.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <assert.h>
+#include <debug.h>
+#include <unistd.h>
+
+#include <arch/board/board.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/analog/adc.h>
+#include <nuttx/analog/ioctl.h>
+#include <nuttx/mutex.h>
+
+#include "arm_internal.h"
+#include "chip.h"
+#include "at32_rcc.h"
+#include "at32_tim.h"
+#include "at32_dma.h"
+#include "at32_adc.h"
+
+/* The AT32 ADC lower-half driver functionality overview:
+ * - one lower-half driver for all AT32 ADC IP cores,
+ * - general lower-half logic for the NuttX upper-half ADC driver,
+ * - lower-half ADC driver can be used not only with the upper-half ADC
+ * driver, but also in the lower-half logic for special-case custom
+ * drivers (eg. power-control, custom sensors),
+ * - ADC can be used in time-critical operations (eg. control loop for
+ * converters or motor drivers) therefore it is necessary to support the
+ * high performance, zero latency ADC interrupts,
+ * - ADC triggering from different sources (EXTSEL and JEXTSEL),
+ * - regular sequence conversion (supported in upper-half ADC driver)
+ * - injected sequence conversion (not supported in upper-half ADC driver)
+ */
+
+/* AT32 ADC "lower-half" support must be enabled */
+
+#ifdef CONFIG_AT32_ADC
+
+/* This implementation is for the AT32 ADC IP version 1 and 2 */
+
+#if !defined(HAVE_IP_ADC_V1) && !defined(HAVE_IP_ADC_V2)
+# error "AT32 ADC IP version not specified"
+#endif
+
+/* Supported ADC modes:
+ * - SW triggering with/without DMA transfer
+ * - TIM triggering with/without DMA transfer
+ * - external triggering with/without DMA transfer
+ *
+ * (tested with ADC example app from NuttX apps repo).
+ */
+
+/* If ADC use HSI as clock-source and HSI is not used for PLL and system
+ * clock, then we can control it directly from ADC driver.
+ */
+
+#if defined(HAVE_ADC_CLOCK_HSI) && \
+ (AT32_CFGR_PLLSRC != 0 || AT32_SYSCLK_SW != RCC_CFGR_SW_HSI)
+# define HAVE_HSI_CONTROL
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* RCC reset ****************************************************************/
+
+#define AT32_RCC_RSTR AT32_CRM_APB2RST
+#define RCC_RSTR_ADC123RST CRM_APB2RST_ADCRST
+
+/* ADC Channels/DMA *********************************************************/
+
+#define ADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \
+ DMA_CCR_PSIZE_16BITS | \
+ DMA_CCR_MINC | \
+ DMA_CCR_CIRC)
+
+/* Sample time default configuration
+ *
+ * REVISIT: simplify this, use adc_sampletime_write() function.
+ * REVISIT: default SMPR configurable from Kconfig
+ */
+
+#if defined(CONFIG_AT32_AT32F43XX)
+
+# define ADC_SMPR_DEFAULT ADC_SMPR_92p5
+
+# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP13_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP14_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP15_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP16_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP17_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP18_SHIFT))
+# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP0_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP1_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP2_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP3_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP4_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP5_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP6_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \
+ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT))
+
+#endif
+
+/* Number of channels per ADC:
+ */
+
+#if defined(CONFIG_AT32_AT32F43XX)
+# define ADC_CHANNELS_NUMBER 19
+#else
+# error "Not supported"
+#endif
+
+/* ADC resolution. Not supported for basic AT32 ADC IPv1 */
+
+#ifndef CONFIG_AT32_HAVE_IP_ADC_V1_BASIC
+# define HAVE_ADC_RESOLUTION
+#else
+# undef HAVE_ADC_RESOLUTION
+#endif
+
+/* ADC have common registers for all cores except basic ADC IPv1 (F1, F37x) */
+
+#ifdef CONFIG_AT32_HAVE_IP_ADC_V1_BASIC
+# undef HAVE_ADC_CMN_REGS
+#else
+# define HAVE_ADC_CMN_REGS
+#endif
+#if defined(HAVE_ADC_CMN_REGS) && AT32_NADC > 1
+# define HAVE_ADC_CMN_DATA
+#else
+# undef HAVE_ADC_CMN_DATA
+#endif
+
+/* Max 4 injected channels */
+
+#define ADC_INJ_MAX_SAMPLES 4
+
+/* ADC DMA configuration bit support */
+
+#ifndef CONFIG_AT32_HAVE_IP_ADC_V1_BASIC
+# define ADC_HAVE_DMACFG 1
+#else
+# undef ADC_HAVE_DMACFG
+#endif
+
+/* ADC scan mode support - only for ADCv1 */
+
+#ifdef CONFIG_AT32_HAVE_IP_ADC_V1
+# define ADC_HAVE_SCAN 1
+# ifndef CONFIG_AT32_ADC1_SCAN
+# define CONFIG_AT32_ADC1_SCAN 0
+# endif
+# ifndef CONFIG_AT32_ADC2_SCAN
+# define CONFIG_AT32_ADC2_SCAN 0
+# endif
+# ifndef CONFIG_AT32_ADC3_SCAN
+# define CONFIG_AT32_ADC3_SCAN 0
+# endif
+#else
+# undef ADC_HAVE_SCAN
+#endif
+
+/* We have to support ADC callbacks if default ADC interrupts or
+ * DMA transfer are enabled
+ */
+
+#if !defined(CONFIG_AT32_ADC_NOIRQ) || defined(ADC_HAVE_DMA)
+# define ADC_HAVE_CB
+#else
+# undef ADC_HAVE_CB
+#endif
+
+/* ADC software trigger configuration */
+
+#define ANIOC_TRIGGER_REGULAR (1 << 0)
+#define ANIOC_TRIGGER_INJECTED (1 << 1)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* Data common to all ADC instances */
+
+#ifdef HAVE_ADC_CMN_DATA
+struct adccmn_data_s
+{
+ uint8_t refcount; /* How many ADC instances are currently in use */
+ mutex_t lock; /* Exclusive access to common ADC data */
+};
+#endif
+
+/* This structure describes the state of one ADC block
+ * REVISIT: save some space with bit fields.
+ */
+
+struct at32_dev_s
+{
+#ifdef CONFIG_AT32_ADC_LL_OPS
+ const struct at32_adc_ops_s *llops; /* Low-level ADC ops */
+ struct adc_dev_s *dev; /* Upper-half ADC reference */
+#endif
+#ifdef ADC_HAVE_CB
+ const struct adc_callback_s *cb;
+ uint8_t irq; /* Interrupt generated by this ADC block */
+#endif
+#ifdef HAVE_ADC_CMN_DATA
+ struct adccmn_data_s *cmn; /* Common ADC data */
+#endif
+ uint8_t rnchannels; /* Number of regular channels */
+ uint8_t cr_channels; /* Number of configured regular channels */
+#ifdef ADC_HAVE_INJECTED
+ uint8_t cj_channels; /* Number of configured injected channels */
+#endif
+ uint8_t intf; /* ADC interface number */
+ uint8_t initialized; /* ADC interface initialization counter */
+ uint8_t current; /* Current ADC channel being converted */
+ uint8_t anioc_trg; /* ANIOC_TRIGGER configuration */
+#ifdef HAVE_ADC_RESOLUTION
+ uint8_t resolution; /* ADC resolution (0-3) */
+#endif
+#ifdef ADC_HAVE_DMA
+ uint8_t dmachan; /* DMA channel needed by this ADC */
+# ifdef ADC_HAVE_DMACFG
+ uint8_t dmacfg; /* DMA channel configuration, only for ADC IPv2 */
+# endif
+ bool hasdma; /* True: This channel supports DMA */
+#endif
+#ifdef ADC_HAVE_SCAN
+ bool scan; /* True: Scan mode */
+#endif
+#ifdef CONFIG_AT32_ADC_CHANGE_SAMPLETIME
+ /* Sample time selection. These bits must be written only when ADON=0.
+ * REVISIT: this takes too much space. We need only 3 bits per channel.
+ */
+
+ uint8_t sample_rate[ADC_CHANNELS_NUMBER];
+ uint8_t adc_channels; /* ADC channels number */
+#endif
+#ifdef ADC_HAVE_TIMER
+ uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3,
+ * 3=CC4, 4=TRGO */
+#endif
+ xcpt_t isr; /* Interrupt handler for this ADC block */
+ uint32_t base; /* Base address of registers unique to this ADC
+ * block */
+#ifdef ADC_HAVE_EXTCFG
+ uint32_t extcfg; /* External event configuration for regular group */
+#endif
+#ifdef ADC_HAVE_JEXTCFG
+ uint32_t jextcfg; /* External event configuration for injected group */
+#endif
+#ifdef ADC_HAVE_TIMER
+ uint32_t tbase; /* Base address of timer used by this ADC block */
+ uint32_t pclck; /* The PCLK frequency that drives this timer */
+ uint32_t freq; /* The desired frequency of conversions */
+#endif
+#ifdef ADC_HAVE_DMA
+ DMA_HANDLE dma; /* Allocated DMA channel */
+
+ /* DMA transfer buffer */
+
+ uint16_t r_dmabuffer[CONFIG_AT32_ADC_MAX_SAMPLES];
+#endif
+
+ /* List of selected ADC channels to sample */
+
+ uint8_t r_chanlist[CONFIG_AT32_ADC_MAX_SAMPLES];
+
+#ifdef ADC_HAVE_INJECTED
+ /* List of selected ADC injected channels to sample */
+
+ uint8_t j_chanlist[ADC_INJ_MAX_SAMPLES];
+#endif
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* ADC Register access */
+
+#ifndef HAVE_BASIC_ADC
+static void at32_modifyreg32(unsigned int addr, uint32_t clrbits,
+ uint32_t setbits);
+#endif
+static uint32_t adc_getreg(struct at32_dev_s *priv, int offset);
+static void adc_putreg(struct at32_dev_s *priv, int offset,
+ uint32_t value);
+static void adc_modifyreg(struct at32_dev_s *priv, int offset,
+ uint32_t clrbits, uint32_t setbits);
+#ifdef HAVE_ADC_CMN_REGS
+static uint32_t adccmn_base_get(struct at32_dev_s *priv);
+static void adccmn_modifyreg(struct at32_dev_s *priv, uint32_t offset,
+ uint32_t clrbits, uint32_t setbits);
+static uint32_t adccmn_getreg(struct at32_dev_s *priv, uint32_t offset);
+#endif
+#ifdef ADC_HAVE_TIMER
+static uint16_t tim_getreg(struct at32_dev_s *priv, int offset);
+static void tim_putreg(struct at32_dev_s *priv, int offset,
+ uint16_t value);
+static void tim_modifyreg(struct at32_dev_s *priv, int offset,
+ uint16_t clrbits, uint16_t setbits);
+static void tim_dumpregs(struct at32_dev_s *priv, const char *msg);
+#endif
+
+static void adc_rccreset(struct at32_dev_s *priv, bool reset);
+
+/* ADC Interrupt Handler */
+
+#ifndef CONFIG_AT32_ADC_NOIRQ
+static int adc_interrupt(struct adc_dev_s *dev);
+# if defined(AT32_IRQ_ADC1) && defined(CONFIG_AT32_ADC1)
+static int adc1_interrupt(int irq, void *context, void *arg);
+# endif
+# if defined(AT32_IRQ_ADC12) && (defined(CONFIG_AT32_ADC1) || \
+ defined(CONFIG_AT32_ADC2))
+static int adc12_interrupt(int irq, void *context, void *arg);
+# endif
+# if (defined(AT32_IRQ_ADC3) && defined(CONFIG_AT32_ADC3))
+static int adc3_interrupt(int irq, void *context, void *arg);
+# endif
+
+# if defined(AT32_IRQ_ADC)
+static int adc123_interrupt(int irq, void *context, void *arg);
+# endif
+#endif /* CONFIG_AT32_ADC_NOIRQ */
+
+/* ADC Driver Methods */
+
+static int adc_bind(struct adc_dev_s *dev,
+ const struct adc_callback_s *callback);
+static void adc_reset(struct adc_dev_s *dev);
+static int adc_setup(struct adc_dev_s *dev);
+static void adc_shutdown(struct adc_dev_s *dev);
+static void adc_rxint(struct adc_dev_s *dev, bool enable);
+static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg);
+static void adc_enable(struct at32_dev_s *priv, bool enable);
+
+static uint32_t adc_sqrbits(struct at32_dev_s *priv, int first,
+ int last, int offset);
+static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch);
+
+static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd,
+ bool arg);
+
+#ifdef HAVE_ADC_RESOLUTION
+static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res);
+#endif
+#ifdef HAVE_ADC_VBAT
+static void adc_enable_vbat_channel(struct adc_dev_s *dev, bool enable);
+#endif
+#ifdef HAVE_ADC_POWERDOWN
+static int adc_ioc_change_sleep_between_opers(struct adc_dev_s *dev,
+ int cmd, bool arg);
+static void adc_power_down_idle(struct at32_dev_s *priv,
+ bool pdi_high);
+static void adc_power_down_delay(struct at32_dev_s *priv,
+ bool pdd_high);
+#endif
+
+#ifdef HAVE_HSI_CONTROL
+static void adc_enable_hsi(bool enable);
+static void adc_reset_hsi_disable(struct adc_dev_s *dev);
+#endif
+
+#ifdef ADC_HAVE_TIMER
+static void adc_timstart(struct at32_dev_s *priv, bool enable);
+static int adc_timinit(struct at32_dev_s *priv);
+#endif
+
+#if defined(ADC_HAVE_DMA) && !defined(CONFIG_AT32_ADC_NOIRQ)
+static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr,
+ void *arg);
+#endif
+
+static void adc_reg_startconv(struct at32_dev_s *priv, bool enable);
+#ifdef ADC_HAVE_INJECTED
+static void adc_inj_startconv(struct at32_dev_s *priv, bool enable);
+static int adc_inj_set_ch(struct adc_dev_s *dev, uint8_t ch);
+#endif
+
+#ifdef ADC_HAVE_EXTCFG
+static int adc_extcfg_set(struct at32_dev_s *priv, uint32_t extcfg);
+#endif
+#ifdef ADC_HAVE_JEXTCFG
+static int adc_jextcfg_set(struct at32_dev_s *priv, uint32_t jextcfg);
+#endif
+
+static void adc_dumpregs(struct at32_dev_s *priv);
+
+#ifdef CONFIG_AT32_ADC_LL_OPS
+static int adc_llops_setup(struct at32_adc_dev_s *dev);
+static void adc_llops_shutdown(struct at32_adc_dev_s *dev);
+static void adc_intack(struct at32_adc_dev_s *dev, uint32_t source);
+static void adc_inten(struct at32_adc_dev_s *dev, uint32_t source);
+static void adc_intdis(struct at32_adc_dev_s *dev, uint32_t source);
+static uint32_t adc_intget(struct at32_adc_dev_s *dev);
+static uint32_t adc_regget(struct at32_adc_dev_s *dev);
+static void adc_llops_reg_startconv(struct at32_adc_dev_s *dev,
+ bool enable);
+static int adc_offset_set(struct at32_adc_dev_s *dev, uint8_t ch,
+ uint8_t i, uint16_t offset);
+# ifdef ADC_HAVE_EXTCFG
+static void adc_llops_extcfg_set(struct at32_adc_dev_s *dev,
+ uint32_t extcfg);
+# endif
+# ifdef ADC_HAVE_JEXTCFG
+static void adc_llops_jextcfg_set(struct at32_adc_dev_s *dev,
+ uint32_t jextcfg);
+# endif
+# ifdef ADC_HAVE_DMA
+static int adc_regbufregister(struct at32_adc_dev_s *dev,
+ uint16_t *buffer, uint8_t len);
+# endif
+# ifdef ADC_HAVE_INJECTED
+static uint32_t adc_injget(struct at32_adc_dev_s *dev, uint8_t chan);
+static void adc_llops_inj_startconv(struct at32_adc_dev_s *dev,
+ bool enable);
+# endif
+# ifdef CONFIG_AT32_ADC_CHANGE_SAMPLETIME
+static void adc_sampletime_set(struct at32_adc_dev_s *dev,
+ struct adc_sample_time_s *time_samples);
+static void adc_sampletime_write(struct at32_adc_dev_s *dev);
+# endif
+static void adc_llops_dumpregs(struct at32_adc_dev_s *dev);
+static int adc_llops_multicfg(struct at32_adc_dev_s *dev, uint8_t mode);
+static void adc_llops_enable(struct at32_adc_dev_s *dev, bool enable);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* ADC interface operations */
+
+static const struct adc_ops_s g_adcops =
+{
+ .ao_bind = adc_bind,
+#ifdef HAVE_HSI_CONTROL
+ .ao_reset = adc_reset_hsi_disable,
+#else
+ .ao_reset = adc_reset,
+#endif
+ .ao_setup = adc_setup,
+ .ao_shutdown = adc_shutdown,
+ .ao_rxint = adc_rxint,
+ .ao_ioctl = adc_ioctl,
+};
+
+/* Publicly visible ADC lower-half operations */
+
+#ifdef CONFIG_AT32_ADC_LL_OPS
+static const struct at32_adc_ops_s g_adc_llops =
+{
+ .setup = adc_llops_setup,
+ .shutdown = adc_llops_shutdown,
+ .int_ack = adc_intack,
+ .int_get = adc_intget,
+ .int_en = adc_inten,
+ .int_dis = adc_intdis,
+ .val_get = adc_regget,
+ .reg_startconv = adc_llops_reg_startconv,
+ .offset_set = adc_offset_set,
+# ifdef ADC_HAVE_DMA
+ .regbuf_reg = adc_regbufregister,
+# endif
+# ifdef ADC_HAVE_EXTCFG
+ .extcfg_set = adc_llops_extcfg_set,
+# endif
+# ifdef ADC_HAVE_JEXTCFG
+ .jextcfg_set = adc_llops_jextcfg_set,
+# endif
+# ifdef ADC_HAVE_INJECTED
+ .inj_get = adc_injget,
+ .inj_startconv = adc_llops_inj_startconv,
+# endif
+# ifdef CONFIG_AT32_ADC_CHANGE_SAMPLETIME
+ .stime_set = adc_sampletime_set,
+ .stime_write = adc_sampletime_write,
+# endif
+ .dump_regs = adc_llops_dumpregs,
+ .multi_cfg = adc_llops_multicfg,
+ .enable = adc_llops_enable
+};
+#endif
+
+/* ADC instances are coupled in blocks for all IP versions except
+ * basic ADC IPv1 (F1, F37x).
+ */
+
+#ifdef HAVE_ADC_CMN_DATA
+# ifdef HAVE_IP_ADC_V1
+# define ADC1CMN_DATA g_adc123_cmn
+# define ADC2CMN_DATA g_adc123_cmn
+# define ADC3CMN_DATA g_adc123_cmn
+
+/* ADC123 common data */
+
+struct adccmn_data_s g_adc123_cmn =
+{
+ .refcount = 0,
+ .lock = NXMUTEX_INITIALIZER,
+};
+
+# elif defined(HAVE_IP_ADC_V2)
+# define ADC1CMN_DATA g_adc12_cmn
+# define ADC2CMN_DATA g_adc12_cmn
+# define ADC3CMN_DATA g_adc34_cmn
+# if defined(CONFIG_AT32_ADC1) || defined(CONFIG_AT32_ADC2)
+
+/* ADC12 common data */
+
+struct adccmn_data_s g_adc12_cmn =
+{
+ .refcount = 0,
+ .lock = NXMUTEX_INITIALIZER,
+};
+
+# endif
+# if defined(CONFIG_AT32_ADC3)
+
+/* ADC3 common data */
+
+struct adccmn_data_s g_adc34_cmn =
+{
+ .refcount = 0,
+ .lock = NXMUTEX_INITIALIZER,
+};
+
+# endif
+# endif /* !HAVE_IP_ADC_V1 */
+#endif /* HAVE_ADC_CMN_DATA */
+
+/* ADC1 state */
+
+#ifdef CONFIG_AT32_ADC1
+static struct at32_dev_s g_adcpriv1 =
+{
+#ifdef CONFIG_AT32_ADC_LL_OPS
+ .llops = &g_adc_llops,
+#endif
+#ifndef CONFIG_AT32_ADC_NOIRQ
+# if defined(AT32_IRQ_ADC1)
+ .irq = AT32_IRQ_ADC1,
+ .isr = adc1_interrupt,
+# elif defined(AT32_IRQ_ADC12)
+ .irq = AT32_IRQ_ADC12,
+ .isr = adc12_interrupt,
+# elif defined(AT32_IRQ_ADC)
+ .irq = AT32_IRQ_ADC,
+ .isr = adc123_interrupt,
+# else
+# error "No AT32_IRQ_ADC1 AT32_IRQ_ADC12 or AT32_IRQ_ADC defined for CONFIG_AT32_ADC1"
+# endif
+#endif /* CONFIG_AT32_ADC_NOIRQ */
+#ifdef HAVE_ADC_CMN_DATA
+ .cmn = &ADC1CMN_DATA,
+#endif
+ .intf = 1,
+ .initialized = 0,
+ .anioc_trg = CONFIG_AT32_ADC1_ANIOC_TRIGGER,
+#ifdef HAVE_ADC_RESOLUTION
+ .resolution = CONFIG_AT32_ADC1_RESOLUTION,
+#endif
+ .base = AT32_ADC1_BASE,
+#ifdef ADC1_HAVE_EXTCFG
+ .extcfg = ADC1_EXTCFG_VALUE,
+#endif
+#ifdef ADC1_HAVE_JEXTCFG
+ .jextcfg = ADC1_JEXTCFG_VALUE,
+#endif
+#ifdef ADC1_HAVE_TIMER
+ .trigger = CONFIG_AT32_ADC1_TIMTRIG,
+ .tbase = ADC1_TIMER_BASE,
+ .pclck = ADC1_TIMER_PCLK_FREQUENCY,
+ .freq = CONFIG_AT32_ADC1_SAMPLE_FREQUENCY,
+#endif
+#ifdef ADC1_HAVE_DMA
+ .dmachan = DMAMUX_ADC1,
+# ifdef ADC_HAVE_DMACFG
+ .dmacfg = CONFIG_AT32_ADC1_DMA_CFG,
+# endif
+ .hasdma = true,
+#endif
+#ifdef ADC_HAVE_SCAN
+ .scan = CONFIG_AT32_ADC1_SCAN,
+#endif
+};
+
+static struct adc_dev_s g_adcdev1 =
+{
+ .ad_ops = &g_adcops,
+ .ad_priv = &g_adcpriv1,
+};
+#endif
+
+/* ADC2 state */
+
+#ifdef CONFIG_AT32_ADC2
+static struct at32_dev_s g_adcpriv2 =
+{
+#ifdef CONFIG_AT32_ADC_LL_OPS
+ .llops = &g_adc_llops,
+#endif
+#ifndef CONFIG_AT32_ADC_NOIRQ
+# if defined(AT32_IRQ_ADC12)
+ .irq = AT32_IRQ_ADC12,
+ .isr = adc12_interrupt,
+# elif defined(AT32_IRQ_ADC)
+ .irq = AT32_IRQ_ADC,
+ .isr = adc123_interrupt,
+# else
+# error "No AT32_IRQ_ADC12 or AT32_IRQ_ADC defined for CONFIG_AT32_ADC2"
+# endif
+#endif /* CONFIG_AT32_ADC_NOIRQ */
+#ifdef HAVE_ADC_CMN_DATA
+ .cmn = &ADC2CMN_DATA,
+#endif
+ .intf = 2,
+ .initialized = 0,
+ .anioc_trg = CONFIG_AT32_ADC2_ANIOC_TRIGGER,
+#ifdef HAVE_ADC_RESOLUTION
+ .resolution = CONFIG_AT32_ADC2_RESOLUTION,
+#endif
+ .base = AT32_ADC2_BASE,
+#ifdef ADC2_HAVE_EXTCFG
+ .extcfg = ADC2_EXTCFG_VALUE,
+#endif
+#ifdef ADC2_HAVE_JEXTCFG
+ .jextcfg = ADC2_JEXTCFG_VALUE,
+#endif
+#ifdef ADC2_HAVE_TIMER
+ .trigger = CONFIG_AT32_ADC2_TIMTRIG,
+ .tbase = ADC2_TIMER_BASE,
+ .pclck = ADC2_TIMER_PCLK_FREQUENCY,
+ .freq = CONFIG_AT32_ADC2_SAMPLE_FREQUENCY,
+#endif
+#ifdef ADC2_HAVE_DMA
+ .dmachan = DMAMUX_ADC2,
+# ifdef ADC_HAVE_DMACFG
+ .dmacfg = CONFIG_AT32_ADC2_DMA_CFG,
+# endif
+ .hasdma = true,
+#endif
+#ifdef ADC_HAVE_SCAN
+ .scan = CONFIG_AT32_ADC2_SCAN,
+#endif
+};
+
+static struct adc_dev_s g_adcdev2 =
+{
+ .ad_ops = &g_adcops,
+ .ad_priv = &g_adcpriv2,
+};
+#endif
+
+/* ADC3 state */
+
+#ifdef CONFIG_AT32_ADC3
+static struct at32_dev_s g_adcpriv3 =
+{
+#ifdef CONFIG_AT32_ADC_LL_OPS
+ .llops = &g_adc_llops,
+#endif
+#ifndef CONFIG_AT32_ADC_NOIRQ
+# if defined(AT32_IRQ_ADC3)
+ .irq = AT32_IRQ_ADC3,
+ .isr = adc3_interrupt,
+# elif defined(AT32_IRQ_ADC)
+ .irq = AT32_IRQ_ADC,
+ .isr = adc123_interrupt,
+# else
+# error "No AT32_IRQ_ADC3 or AT32_IRQ_ADC defined for CONFIG_AT32_ADC3"
+# endif
+#endif /* CONFIG_AT32_ADC_NOIRQ */
+#ifdef HAVE_ADC_CMN_DATA
+ .cmn = &ADC3CMN_DATA,
+#endif
+ .intf = 3,
+ .initialized = 0,
+ .anioc_trg = CONFIG_AT32_ADC3_ANIOC_TRIGGER,
+#ifdef HAVE_ADC_RESOLUTION
+ .resolution = CONFIG_AT32_ADC3_RESOLUTION,
+#endif
+ .base = AT32_ADC3_BASE,
+#ifdef ADC3_HAVE_EXTCFG
+ .extcfg = ADC3_EXTCFG_VALUE,
+#endif
+#ifdef ADC3_HAVE_JEXTCFG
+ .jextcfg = ADC3_JEXTCFG_VALUE,
+#endif
+#ifdef ADC3_HAVE_TIMER
+ .trigger = CONFIG_AT32_ADC3_TIMTRIG,
+ .tbase = ADC3_TIMER_BASE,
+ .pclck = ADC3_TIMER_PCLK_FREQUENCY,
+ .freq = CONFIG_AT32_ADC3_SAMPLE_FREQUENCY,
+#endif
+#ifdef ADC3_HAVE_DMA
+ .dmachan = DMAMUX_ADC3,
+# ifdef ADC_HAVE_DMACFG
+ .dmacfg = CONFIG_AT32_ADC3_DMA_CFG,
+# endif
+ .hasdma = true,
+#endif
+#ifdef ADC_HAVE_SCAN
+ .scan = CONFIG_AT32_ADC3_SCAN,
+#endif
+};
+
+static struct adc_dev_s g_adcdev3 =
+{
+ .ad_ops = &g_adcops,
+ .ad_priv = &g_adcpriv3,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: at32_modifyreg32
+ *
+ * Description:
+ * Modify the value of a 32-bit register (not atomic).
+ *
+ * Input Parameters:
+ * addr - The address of the register
+ * clrbits - The bits to clear
+ * setbits - The bits to set
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifndef HAVE_BASIC_ADC
+static void at32_modifyreg32(unsigned int addr, uint32_t clrbits,
+ uint32_t setbits)
+{
+ putreg32((getreg32(addr) & ~clrbits) | setbits, addr);
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_getreg
+ *
+ * Description:
+ * Read the value of an ADC register.
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to read
+ *
+ * Returned Value:
+ * The current contents of the specified register
+ *
+ ****************************************************************************/
+
+static uint32_t adc_getreg(struct at32_dev_s *priv, int offset)
+{
+ return getreg32(priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: adc_putreg
+ *
+ * Description:
+ * Write a value to an ADC register.
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to write to
+ * value - The value to write to the register
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void adc_putreg(struct at32_dev_s *priv, int offset,
+ uint32_t value)
+{
+ putreg32(value, priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: adc_modifyreg
+ *
+ * Description:
+ * Modify the value of an ADC register (not atomic).
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to modify
+ * clrbits - The bits to clear
+ * setbits - The bits to set
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void adc_modifyreg(struct at32_dev_s *priv, int offset,
+ uint32_t clrbits, uint32_t setbits)
+{
+ adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits);
+}
+
+#ifdef HAVE_ADC_CMN_REGS
+
+/****************************************************************************
+ * Name: adccmn_base_get
+ ****************************************************************************/
+
+static uint32_t adccmn_base_get(struct at32_dev_s *priv)
+{
+ uint32_t base = 0;
+
+#if defined(HAVE_IP_ADC_V2)
+ if (priv->base == AT32_ADC1_BASE || priv->base == AT32_ADC2_BASE)
+ {
+ base = AT32_ADC12CMN_BASE;
+ }
+# if defined(CONFIG_AT32_ADC3)
+ else
+ {
+ base = AT32_ADC3CMN_BASE;
+ }
+# endif
+
+#elif defined(HAVE_IP_ADC_V1)
+ base = AT32_ADCCMN_BASE;
+ UNUSED(priv);
+#endif
+
+ return base;
+}
+
+/****************************************************************************
+ * Name: adccmn_modifyreg
+ ****************************************************************************/
+
+static void adccmn_modifyreg(struct at32_dev_s *priv, uint32_t offset,
+ uint32_t clrbits, uint32_t setbits)
+{
+ uint32_t base = 0;
+
+ /* Get base address for ADC common register */
+
+ base = adccmn_base_get(priv);
+
+ /* Modify register */
+
+ at32_modifyreg32(offset + base, clrbits, setbits);
+}
+
+/****************************************************************************
+ * Name: adccmn_getreg
+ ****************************************************************************/
+
+static uint32_t adccmn_getreg(struct at32_dev_s *priv, uint32_t offset)
+{
+ uint32_t base = 0;
+
+ /* Get base address for ADC common register */
+
+ base = adccmn_base_get(priv);
+
+ /* Return register value */
+
+ return getreg32(base + offset);
+}
+#endif /* HAVE_ADC_CMN_REGS */
+
+/****************************************************************************
+ * Name: tim_getreg
+ *
+ * Description:
+ * Read the value of an ADC timer register.
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to read
+ *
+ * Returned Value:
+ * The current contents of the specified register
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static uint16_t tim_getreg(struct at32_dev_s *priv, int offset)
+{
+ return getreg16(priv->tbase + offset);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_putreg
+ *
+ * Description:
+ * Write a value to an ADC timer register.
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to write to
+ * value - The value to write to the register
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void tim_putreg(struct at32_dev_s *priv, int offset,
+ uint16_t value)
+{
+ putreg16(value, priv->tbase + offset);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_modifyreg
+ *
+ * Description:
+ * Modify the value of an ADC timer register (not atomic).
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ * offset - The offset to the register to modify
+ * clrbits - The bits to clear
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