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Posted to commits@nuttx.apache.org by bt...@apache.org on 2021/05/20 07:54:16 UTC
[incubator-nuttx] 01/02: stm32h7 rcc: Sync h7x7xx and h7x3xx.
Changes are relevant to both
This is an automated email from the ASF dual-hosted git repository.
btashton pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 35553147ba2afdf240bfb744d1c58b7df4fc96e0
Author: Anthony Merlino <an...@vergeaero.com>
AuthorDate: Sat May 15 18:00:52 2021 -0400
stm32h7 rcc: Sync h7x7xx and h7x3xx. Changes are relevant to both
---
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 20 ++++++++++++++++++-
arch/arm/src/stm32h7/stm32h7x7xx_rcc.c | 36 ++++++++++++++++++++++++----------
2 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
index c9e0dd2..49f8d49 100644
--- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
@@ -247,11 +247,17 @@ static inline void rcc_enableahb2(void)
regval = getreg32(STM32_RCC_AHB2ENR);
#ifdef CONFIG_STM32H7_SDMMC2
- /* SDMMC clock enable */
+ /* SDMMC2 clock enable */
regval |= RCC_AHB2ENR_SDMMC2EN;
#endif
+#ifdef CONFIG_STM32H7_RNG
+ /* Random number generator clock enable */
+
+ regval |= RCC_AHB2ENR_RNGEN;
+#endif
+
putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
}
@@ -473,6 +479,18 @@ static inline void rcc_enableapb2(void)
regval |= RCC_APB2ENR_SPI5EN;
#endif
+#ifdef CONFIG_STM32H7_USART1
+ /* USART1 clock enable */
+
+ regval |= RCC_APB2ENR_USART1EN;
+#endif
+
+#ifdef CONFIG_STM32H7_USART6
+ /* USART1 clock enable */
+
+ regval |= RCC_APB2ENR_USART6EN;
+#endif
+
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
}
diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
index 13464ad..af179c5 100644
--- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
@@ -246,7 +246,17 @@ static inline void rcc_enableahb2(void)
regval = getreg32(STM32_RCC_AHB2ENR);
- /* TODO: ... */
+#ifdef CONFIG_STM32H7_SDMMC2
+ /* SDMMC2 clock enable */
+
+ regval |= RCC_AHB2ENR_SDMMC2EN;
+#endif
+
+#ifdef CONFIG_STM32H7_RNG
+ /* Random number generator clock enable */
+
+ regval |= RCC_AHB2ENR_RNGEN;
+#endif
putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
}
@@ -469,12 +479,6 @@ static inline void rcc_enableapb2(void)
regval |= RCC_APB2ENR_SPI5EN;
#endif
-#ifdef CONFIG_STM32H7_SDMMC2
- /* SDMMC2 clock enable */
-
- regval |= RCC_APB2ENR_SDMMC2EN;
-#endif
-
#ifdef CONFIG_STM32H7_USART1
/* USART1 clock enable */
@@ -826,8 +830,6 @@ void stm32_stdclockconfig(void)
regval |= STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_LDOESCUEN;
putreg32(regval, STM32_PWR_CR3);
-#if 0
-
/* Set the voltage output scale */
regval = getreg32(STM32_PWR_D3CR);
@@ -839,6 +841,12 @@ void stm32_stdclockconfig(void)
{
}
+ /* See Reference manual Section 5.4.1, System supply startup */
+
+ while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0)
+ {
+ }
+
/* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is
* over 400 MHz.
@@ -863,7 +871,6 @@ void stm32_stdclockconfig(void)
{
}
}
-#endif
/* Configure FLASH wait states */
@@ -952,6 +959,15 @@ void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_D3CCIPR);
#endif
+ /* Configure FDCAN source clock */
+
+#if defined(STM32_RCC_D2CCIP1R_FDCANSEL)
+ regval = getreg32(STM32_RCC_D2CCIP1R);
+ regval &= ~RCC_D2CCIP1R_FDCANSEL_MASK;
+ regval |= STM32_RCC_D2CCIP1R_FDCANSEL;
+ putreg32(regval, STM32_RCC_D2CCIP1R);
+#endif
+
#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK)
/* Low speed internal clock source LSI */