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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/01/09 22:55:33 UTC

[GitHub] [incubator-nuttx] Ouss4 commented on a change in pull request #5192: arch/risc-v: Merge rv32im and rv64gc into common

Ouss4 commented on a change in pull request #5192:
URL: https://github.com/apache/incubator-nuttx/pull/5192#discussion_r780842652



##########
File path: arch/risc-v/src/fe310/fe310_irq_dispatch.c
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@@ -72,7 +72,7 @@ void *fe310_dispatch_irq(uint32_t vector, uint32_t *regs)
 
   if (FE310_IRQ_ECALLM == irq)
     {
-      *mepc += 2;
+      *mepc += 4;

Review comment:
       I don't know if this was ever needed for RV32 chips since the ECALL handler does the same thing: 
   https://github.com/apache/incubator-nuttx/blob/1fd51ccbe244b554386baa78d1922af5dd89d835/arch/risc-v/src/rv32im/riscv_swint.c#L138-L141
   
   For instance, we didn't do that for ESP32-C3, but we couldn't change it for other chips since we don't have boards to test.




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