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Posted to commits@mynewt.apache.org by ad...@apache.org on 2016/06/15 22:03:56 UTC
[13/51] [partial] incubator-mynewt-site git commit: Fixed broken
Quick Start link and added OpenOCD option for Arduino Primo debugging
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/tcl.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/tcl.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/tcl.c
new file mode 100755
index 0000000..cf0daf3
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/tcl.c
@@ -0,0 +1,1115 @@
+/***************************************************************************
+ * Copyright (C) 2005 by Dominic Rath <Do...@gmx.de> *
+ * Copyright (C) 2007,2008 �yvind Harboe <oy...@zylin.com> *
+ * Copyright (C) 2008 by Spencer Oliver <sp...@spen-soft.co.uk> *
+ * Copyright (C) 2009 Zachary T Welch <zw...@superlucidity.net> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+#include "imp.h"
+#include <helper/time_support.h>
+#include <target/image.h>
+
+/**
+ * @file
+ * Implements Tcl commands used to access NOR flash facilities.
+ */
+
+COMMAND_HELPER(flash_command_get_bank_maybe_probe, unsigned name_index,
+ struct flash_bank **bank, bool do_probe)
+{
+ const char *name = CMD_ARGV[name_index];
+ int retval;
+ if (do_probe) {
+ retval = get_flash_bank_by_name(name, bank);
+ } else {
+ *bank = get_flash_bank_by_name_noprobe(name);
+ retval = ERROR_OK;
+ }
+
+ if (retval != ERROR_OK)
+ return retval;
+ if (*bank)
+ return ERROR_OK;
+
+ unsigned bank_num;
+ COMMAND_PARSE_NUMBER(uint, name, bank_num);
+
+ if (do_probe) {
+ return get_flash_bank_by_num(bank_num, bank);
+ } else {
+ *bank = get_flash_bank_by_num_noprobe(bank_num);
+ retval = (bank) ? ERROR_OK : ERROR_FAIL;
+ return retval;
+ }
+}
+
+COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
+ struct flash_bank **bank)
+{
+ return CALL_COMMAND_HANDLER(flash_command_get_bank_maybe_probe,
+ name_index, bank, true);
+}
+
+COMMAND_HANDLER(handle_flash_info_command)
+{
+ struct flash_bank *p;
+ int j = 0;
+ int retval;
+
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (p != NULL) {
+ char buf[1024];
+
+ /* attempt auto probe */
+ retval = p->driver->auto_probe(p);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* We must query the hardware to avoid printing stale information! */
+ retval = p->driver->protect_check(p);
+ if (retval != ERROR_OK)
+ return retval;
+
+ command_print(CMD_CTX,
+ "#%d : %s at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32
+ ", buswidth %i, chipwidth %i",
+ p->bank_number,
+ p->driver->name,
+ p->base,
+ p->size,
+ p->bus_width,
+ p->chip_width);
+ for (j = 0; j < p->num_sectors; j++) {
+ char *protect_state;
+
+ if (p->sectors[j].is_protected == 0)
+ protect_state = "not protected";
+ else if (p->sectors[j].is_protected == 1)
+ protect_state = "protected";
+ else
+ protect_state = "protection state unknown";
+
+ command_print(CMD_CTX,
+ "\t#%3i: 0x%8.8" PRIx32 " (0x%" PRIx32 " %" PRIi32 "kB) %s",
+ j,
+ p->sectors[j].offset,
+ p->sectors[j].size,
+ p->sectors[j].size >> 10,
+ protect_state);
+ }
+
+ if (p->driver->info != NULL) {
+ retval = p->driver->info(p, buf, sizeof(buf));
+ if (retval == ERROR_OK)
+ command_print(CMD_CTX, "%s", buf);
+ else
+ LOG_ERROR("error retrieving flash info");
+ }
+ }
+
+ return retval;
+}
+
+COMMAND_HANDLER(handle_flash_probe_command)
+{
+ struct flash_bank *p;
+ int retval;
+
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ retval = CALL_COMMAND_HANDLER(flash_command_get_bank_maybe_probe, 0, &p, false);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (p) {
+ retval = p->driver->probe(p);
+ if (retval == ERROR_OK)
+ command_print(CMD_CTX,
+ "flash '%s' found at 0x%8.8" PRIx32,
+ p->driver->name,
+ p->base);
+ } else {
+ command_print(CMD_CTX, "flash bank '#%s' is out of bounds", CMD_ARGV[0]);
+ retval = ERROR_FAIL;
+ }
+
+ return retval;
+}
+
+COMMAND_HANDLER(handle_flash_erase_check_command)
+{
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *p;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
+ if (ERROR_OK != retval)
+ return retval;
+
+ int j;
+ retval = p->driver->erase_check(p);
+ if (retval == ERROR_OK)
+ command_print(CMD_CTX, "successfully checked erase state");
+ else {
+ command_print(CMD_CTX,
+ "unknown error when checking erase state of flash bank #%s at 0x%8.8" PRIx32,
+ CMD_ARGV[0],
+ p->base);
+ }
+
+ for (j = 0; j < p->num_sectors; j++) {
+ char *erase_state;
+
+ if (p->sectors[j].is_erased == 0)
+ erase_state = "not erased";
+ else if (p->sectors[j].is_erased == 1)
+ erase_state = "erased";
+ else
+ erase_state = "erase state unknown";
+
+ command_print(CMD_CTX,
+ "\t#%3i: 0x%8.8" PRIx32 " (0x%" PRIx32 " %" PRIi32 "kB) %s",
+ j,
+ p->sectors[j].offset,
+ p->sectors[j].size,
+ p->sectors[j].size >> 10,
+ erase_state);
+ }
+
+ return retval;
+}
+
+COMMAND_HANDLER(handle_flash_erase_address_command)
+{
+ struct flash_bank *p;
+ int retval = ERROR_OK;
+ uint32_t address;
+ uint32_t length;
+ bool do_pad = false;
+ bool do_unlock = false;
+ struct target *target = get_current_target(CMD_CTX);
+
+ while (CMD_ARGC >= 3) {
+ /* Optionally pad out the address range to block/sector
+ * boundaries. We can't know if there's data in that part
+ * of the flash; only do padding if we're told to.
+ */
+ if (strcmp("pad", CMD_ARGV[0]) == 0)
+ do_pad = true;
+ else if (strcmp("unlock", CMD_ARGV[0]) == 0)
+ do_unlock = true;
+ else
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ CMD_ARGC--;
+ CMD_ARGV++;
+ }
+ if (CMD_ARGC != 2)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
+
+ if (length <= 0) {
+ command_print(CMD_CTX, "Length must be >0");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ retval = get_flash_bank_by_addr(target, address, true, &p);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* We can't know if we did a resume + halt, in which case we no longer know the erased state
+ **/
+ flash_set_dirty();
+
+ struct duration bench;
+ duration_start(&bench);
+
+ if (do_unlock)
+ retval = flash_unlock_address_range(target, address, length);
+
+ if (retval == ERROR_OK)
+ retval = flash_erase_address_range(target, do_pad, address, length);
+
+ if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ command_print(CMD_CTX, "erased address 0x%8.8" PRIx32 " (length %" PRIi32 ")"
+ " in %fs (%0.3f KiB/s)", address, length,
+ duration_elapsed(&bench), duration_kbps(&bench, length));
+ }
+
+ return retval;
+}
+
+static int flash_check_sector_parameters(struct command_context *cmd_ctx,
+ uint32_t first, uint32_t last, uint32_t num_sectors)
+{
+ if (!(first <= last)) {
+ command_print(cmd_ctx, "ERROR: "
+ "first sector must be <= last sector");
+ return ERROR_FAIL;
+ }
+
+ if (!(last <= (num_sectors - 1))) {
+ command_print(cmd_ctx, "ERROR: last sector must be <= %d",
+ (int) num_sectors - 1);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(handle_flash_erase_command)
+{
+ if (CMD_ARGC != 3)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ uint32_t first;
+ uint32_t last;
+
+ struct flash_bank *p;
+ int retval;
+
+ retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
+ if (retval != ERROR_OK)
+ return retval;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], first);
+ if (strcmp(CMD_ARGV[2], "last") == 0)
+ last = p->num_sectors - 1;
+ else
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last);
+
+ retval = flash_check_sector_parameters(CMD_CTX, first, last, p->num_sectors);
+ if (retval != ERROR_OK)
+ return retval;
+
+ struct duration bench;
+ duration_start(&bench);
+
+ retval = flash_driver_erase(p, first, last);
+
+ if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ command_print(CMD_CTX, "erased sectors %" PRIu32 " "
+ "through %" PRIu32 " on flash bank %d "
+ "in %fs", first, last, p->bank_number, duration_elapsed(&bench));
+ }
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(handle_flash_protect_command)
+{
+ if (CMD_ARGC != 4)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ uint32_t first;
+ uint32_t last;
+
+ struct flash_bank *p;
+ int retval;
+
+ retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
+ if (retval != ERROR_OK)
+ return retval;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], first);
+ if (strcmp(CMD_ARGV[2], "last") == 0)
+ last = p->num_sectors - 1;
+ else
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last);
+
+ bool set;
+ COMMAND_PARSE_ON_OFF(CMD_ARGV[3], set);
+
+ retval = flash_check_sector_parameters(CMD_CTX, first, last, p->num_sectors);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = flash_driver_protect(p, set, first, last);
+ if (retval == ERROR_OK) {
+ command_print(CMD_CTX, "%s protection for sectors %i "
+ "through %i on flash bank %d",
+ (set) ? "set" : "cleared", (int) first,
+ (int) last, p->bank_number);
+ }
+
+ return retval;
+}
+
+COMMAND_HANDLER(handle_flash_write_image_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+
+ struct image image;
+ uint32_t written;
+
+ int retval;
+
+ /* flash auto-erase is disabled by default*/
+ int auto_erase = 0;
+ bool auto_unlock = false;
+
+ while (CMD_ARGC) {
+ if (strcmp(CMD_ARGV[0], "erase") == 0) {
+ auto_erase = 1;
+ CMD_ARGV++;
+ CMD_ARGC--;
+ command_print(CMD_CTX, "auto erase enabled");
+ } else if (strcmp(CMD_ARGV[0], "unlock") == 0) {
+ auto_unlock = true;
+ CMD_ARGV++;
+ CMD_ARGC--;
+ command_print(CMD_CTX, "auto unlock enabled");
+ } else
+ break;
+ }
+
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (!target) {
+ LOG_ERROR("no target selected");
+ return ERROR_FAIL;
+ }
+
+ struct duration bench;
+ duration_start(&bench);
+
+ if (CMD_ARGC >= 2) {
+ image.base_address_set = 1;
+ COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], image.base_address);
+ } else {
+ image.base_address_set = 0;
+ image.base_address = 0x0;
+ }
+
+ image.start_address_set = 0;
+
+ retval = image_open(&image, CMD_ARGV[0], (CMD_ARGC == 3) ? CMD_ARGV[2] : NULL);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = flash_write_unlock(target, &image, &written, auto_erase, auto_unlock);
+ if (retval != ERROR_OK) {
+ image_close(&image);
+ return retval;
+ }
+
+ if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ command_print(CMD_CTX, "wrote %" PRIu32 " bytes from file %s "
+ "in %fs (%0.3f KiB/s)", written, CMD_ARGV[0],
+ duration_elapsed(&bench), duration_kbps(&bench, written));
+ }
+
+ image_close(&image);
+
+ return retval;
+}
+
+COMMAND_HANDLER(handle_flash_fill_command)
+{
+ int err = ERROR_OK;
+ uint32_t address;
+ uint32_t pattern;
+ uint32_t count;
+ uint32_t wrote = 0;
+ uint32_t cur_size = 0;
+ uint32_t chunk_count;
+ struct target *target = get_current_target(CMD_CTX);
+ unsigned i;
+ uint32_t wordsize;
+ int retval = ERROR_OK;
+
+ static size_t const chunksize = 1024;
+ uint8_t *chunk = NULL, *readback = NULL;
+
+ if (CMD_ARGC != 3) {
+ retval = ERROR_COMMAND_SYNTAX_ERROR;
+ goto done;
+ }
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], pattern);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
+
+ chunk = malloc(chunksize);
+ if (chunk == NULL)
+ return ERROR_FAIL;
+
+ readback = malloc(chunksize);
+ if (readback == NULL) {
+ free(chunk);
+ return ERROR_FAIL;
+ }
+
+ if (count == 0)
+ goto done;
+
+ switch (CMD_NAME[4]) {
+ case 'w':
+ wordsize = 4;
+ break;
+ case 'h':
+ wordsize = 2;
+ break;
+ case 'b':
+ wordsize = 1;
+ break;
+ default:
+ retval = ERROR_COMMAND_SYNTAX_ERROR;
+ goto done;
+ }
+
+ chunk_count = MIN(count, (chunksize / wordsize));
+ switch (wordsize) {
+ case 4:
+ for (i = 0; i < chunk_count; i++)
+ target_buffer_set_u32(target, chunk + i * wordsize, pattern);
+ break;
+ case 2:
+ for (i = 0; i < chunk_count; i++)
+ target_buffer_set_u16(target, chunk + i * wordsize, pattern);
+ break;
+ case 1:
+ memset(chunk, pattern, chunk_count);
+ break;
+ default:
+ LOG_ERROR("BUG: can't happen");
+ exit(-1);
+ }
+
+ struct duration bench;
+ duration_start(&bench);
+
+ for (wrote = 0; wrote < (count*wordsize); wrote += cur_size) {
+ struct flash_bank *bank;
+
+ retval = get_flash_bank_by_addr(target, address, true, &bank);
+ if (retval != ERROR_OK)
+ goto done;
+
+ cur_size = MIN((count * wordsize - wrote), chunksize);
+ err = flash_driver_write(bank, chunk, address - bank->base + wrote, cur_size);
+ if (err != ERROR_OK) {
+ retval = err;
+ goto done;
+ }
+
+ err = flash_driver_read(bank, readback, address - bank->base + wrote, cur_size);
+ if (err != ERROR_OK) {
+ retval = err;
+ goto done;
+ }
+
+ for (i = 0; i < cur_size; i++) {
+ if (readback[i] != chunk[i]) {
+ LOG_ERROR(
+ "Verification error address 0x%08" PRIx32 ", read back 0x%02x, expected 0x%02x",
+ address + wrote + i,
+ readback[i],
+ chunk[i]);
+ retval = ERROR_FAIL;
+ goto done;
+ }
+ }
+ }
+
+ if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) {
+ command_print(CMD_CTX, "wrote %" PRIu32 " bytes to 0x%8.8" PRIx32
+ " in %fs (%0.3f KiB/s)", wrote, address,
+ duration_elapsed(&bench), duration_kbps(&bench, wrote));
+ }
+
+done:
+ free(readback);
+ free(chunk);
+
+ return retval;
+}
+
+COMMAND_HANDLER(handle_flash_write_bank_command)
+{
+ uint32_t offset;
+ uint8_t *buffer;
+ struct fileio *fileio;
+
+ if (CMD_ARGC != 3)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct duration bench;
+ duration_start(&bench);
+
+ struct flash_bank *p;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
+ if (ERROR_OK != retval)
+ return retval;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], offset);
+
+ if (fileio_open(&fileio, CMD_ARGV[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
+ return ERROR_OK;
+
+ size_t filesize;
+ retval = fileio_size(fileio, &filesize);
+ if (retval != ERROR_OK) {
+ fileio_close(fileio);
+ return retval;
+ }
+
+ buffer = malloc(filesize);
+ if (buffer == NULL) {
+ fileio_close(fileio);
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+ size_t buf_cnt;
+ if (fileio_read(fileio, filesize, buffer, &buf_cnt) != ERROR_OK) {
+ free(buffer);
+ fileio_close(fileio);
+ return ERROR_OK;
+ }
+
+ retval = flash_driver_write(p, buffer, offset, buf_cnt);
+
+ free(buffer);
+ buffer = NULL;
+
+ if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
+ command_print(CMD_CTX, "wrote %zu bytes from file %s to flash bank %u"
+ " at offset 0x%8.8" PRIx32 " in %fs (%0.3f KiB/s)",
+ filesize, CMD_ARGV[1], p->bank_number, offset,
+ duration_elapsed(&bench), duration_kbps(&bench, filesize));
+ }
+
+ fileio_close(fileio);
+
+ return retval;
+}
+
+COMMAND_HANDLER(handle_flash_read_bank_command)
+{
+ uint32_t offset;
+ uint8_t *buffer;
+ struct fileio *fileio;
+ uint32_t length;
+ size_t written;
+
+ if (CMD_ARGC != 4)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct duration bench;
+ duration_start(&bench);
+
+ struct flash_bank *p;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
+ if (ERROR_OK != retval)
+ return retval;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], offset);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], length);
+
+ buffer = malloc(length);
+ if (buffer == NULL) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+
+ retval = flash_driver_read(p, buffer, offset, length);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Read error");
+ free(buffer);
+ return retval;
+ }
+
+ retval = fileio_open(&fileio, CMD_ARGV[1], FILEIO_WRITE, FILEIO_BINARY);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not open file");
+ free(buffer);
+ return retval;
+ }
+
+ retval = fileio_write(fileio, length, buffer, &written);
+ fileio_close(fileio);
+ free(buffer);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not write file");
+ return ERROR_FAIL;
+ }
+
+ if (duration_measure(&bench) == ERROR_OK)
+ command_print(CMD_CTX, "wrote %ld bytes to file %s from flash bank %u"
+ " at offset 0x%8.8" PRIx32 " in %fs (%0.3f KiB/s)",
+ (long)written, CMD_ARGV[1], p->bank_number, offset,
+ duration_elapsed(&bench), duration_kbps(&bench, written));
+
+ return retval;
+}
+
+
+COMMAND_HANDLER(handle_flash_verify_bank_command)
+{
+ uint32_t offset;
+ uint8_t *buffer_file, *buffer_flash;
+ struct fileio *fileio;
+ size_t read_cnt;
+ size_t filesize;
+ int differ;
+
+ if (CMD_ARGC != 3)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct duration bench;
+ duration_start(&bench);
+
+ struct flash_bank *p;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
+ if (ERROR_OK != retval)
+ return retval;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], offset);
+
+ retval = fileio_open(&fileio, CMD_ARGV[1], FILEIO_READ, FILEIO_BINARY);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not open file");
+ return retval;
+ }
+
+ retval = fileio_size(fileio, &filesize);
+ if (retval != ERROR_OK) {
+ fileio_close(fileio);
+ return retval;
+ }
+
+ buffer_file = malloc(filesize);
+ if (buffer_file == NULL) {
+ LOG_ERROR("Out of memory");
+ fileio_close(fileio);
+ return ERROR_FAIL;
+ }
+
+ retval = fileio_read(fileio, filesize, buffer_file, &read_cnt);
+ fileio_close(fileio);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("File read failure");
+ free(buffer_file);
+ return retval;
+ }
+
+ if (read_cnt != filesize) {
+ LOG_ERROR("Short read");
+ free(buffer_file);
+ return ERROR_FAIL;
+ }
+
+ buffer_flash = malloc(filesize);
+ if (buffer_flash == NULL) {
+ LOG_ERROR("Out of memory");
+ free(buffer_file);
+ return ERROR_FAIL;
+ }
+
+ retval = flash_driver_read(p, buffer_flash, offset, read_cnt);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Flash read error");
+ free(buffer_flash);
+ free(buffer_file);
+ return retval;
+ }
+
+ if (duration_measure(&bench) == ERROR_OK)
+ command_print(CMD_CTX, "read %ld bytes from file %s and flash bank %u"
+ " at offset 0x%8.8" PRIx32 " in %fs (%0.3f KiB/s)",
+ (long)read_cnt, CMD_ARGV[1], p->bank_number, offset,
+ duration_elapsed(&bench), duration_kbps(&bench, read_cnt));
+
+ differ = memcmp(buffer_file, buffer_flash, read_cnt);
+ command_print(CMD_CTX, "contents %s", differ ? "differ" : "match");
+ if (differ) {
+ uint32_t t;
+ int diffs = 0;
+ for (t = 0; t < read_cnt; t++) {
+ if (buffer_flash[t] == buffer_file[t])
+ continue;
+ command_print(CMD_CTX, "diff %d address 0x%08x. Was 0x%02x instead of 0x%02x",
+ diffs, t + offset, buffer_flash[t], buffer_file[t]);
+ if (diffs++ >= 127) {
+ command_print(CMD_CTX, "More than 128 errors, the rest are not printed.");
+ break;
+ }
+ keep_alive();
+ }
+ }
+ free(buffer_flash);
+ free(buffer_file);
+
+ return differ ? ERROR_FAIL : ERROR_OK;
+}
+
+void flash_set_dirty(void)
+{
+ struct flash_bank *c;
+ int i;
+
+ /* set all flash to require erasing */
+ for (c = flash_bank_list(); c; c = c->next) {
+ for (i = 0; i < c->num_sectors; i++)
+ c->sectors[i].is_erased = 0;
+ }
+}
+
+COMMAND_HANDLER(handle_flash_padded_value_command)
+{
+ if (CMD_ARGC != 2)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *p;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p);
+ if (ERROR_OK != retval)
+ return retval;
+
+ COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], p->default_padded_value);
+
+ command_print(CMD_CTX, "Default padded value set to 0x%" PRIx8 " for flash bank %u", \
+ p->default_padded_value, p->bank_number);
+
+ return retval;
+}
+
+static const struct command_registration flash_exec_command_handlers[] = {
+ {
+ .name = "probe",
+ .handler = handle_flash_probe_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Identify a flash bank.",
+ },
+ {
+ .name = "info",
+ .handler = handle_flash_info_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Print information about a flash bank.",
+ },
+ {
+ .name = "erase_check",
+ .handler = handle_flash_erase_check_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Check erase state of all blocks in a "
+ "flash bank.",
+ },
+ {
+ .name = "erase_sector",
+ .handler = handle_flash_erase_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id first_sector_num last_sector_num",
+ .help = "Erase a range of sectors in a flash bank.",
+ },
+ {
+ .name = "erase_address",
+ .handler = handle_flash_erase_address_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['pad'] ['unlock'] address length",
+ .help = "Erase flash sectors starting at address and "
+ "continuing for length bytes. If 'pad' is specified, "
+ "data outside that range may also be erased: the start "
+ "address may be decreased, and length increased, so "
+ "that all of the first and last sectors are erased. "
+ "If 'unlock' is specified, then the flash is unprotected "
+ "before erasing.",
+
+ },
+ {
+ .name = "fillw",
+ .handler = handle_flash_fill_command,
+ .mode = COMMAND_EXEC,
+ .usage = "address value n",
+ .help = "Fill n words with 32-bit value, starting at "
+ "word address. (No autoerase.)",
+ },
+ {
+ .name = "fillh",
+ .handler = handle_flash_fill_command,
+ .mode = COMMAND_EXEC,
+ .usage = "address value n",
+ .help = "Fill n halfwords with 16-bit value, starting at "
+ "word address. (No autoerase.)",
+ },
+ {
+ .name = "fillb",
+ .handler = handle_flash_fill_command,
+ .mode = COMMAND_EXEC,
+ .usage = "address value n",
+ .help = "Fill n bytes with 8-bit value, starting at "
+ "word address. (No autoerase.)",
+ },
+ {
+ .name = "write_bank",
+ .handler = handle_flash_write_bank_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id filename offset",
+ .help = "Write binary data from file to flash bank, "
+ "starting at specified byte offset from the "
+ "beginning of the bank.",
+ },
+ {
+ .name = "write_image",
+ .handler = handle_flash_write_image_command,
+ .mode = COMMAND_EXEC,
+ .usage = "[erase] [unlock] filename [offset [file_type]]",
+ .help = "Write an image to flash. Optionally first unprotect "
+ "and/or erase the region to be used. Allow optional "
+ "offset from beginning of bank (defaults to zero)",
+ },
+ {
+ .name = "read_bank",
+ .handler = handle_flash_read_bank_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id filename offset length",
+ .help = "Read binary data from flash bank to file, "
+ "starting at specified byte offset from the "
+ "beginning of the bank.",
+ },
+ {
+ .name = "verify_bank",
+ .handler = handle_flash_verify_bank_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id filename offset",
+ .help = "Read binary data from flash bank and file, "
+ "starting at specified byte offset from the "
+ "beginning of the bank. Compare the contents.",
+ },
+ {
+ .name = "protect",
+ .handler = handle_flash_protect_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id first_sector [last_sector|'last'] "
+ "('on'|'off')",
+ .help = "Turn protection on or off for a range of sectors "
+ "in a given flash bank.",
+ },
+ {
+ .name = "padded_value",
+ .handler = handle_flash_padded_value_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id value",
+ .help = "Set default flash padded value",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static int flash_init_drivers(struct command_context *cmd_ctx)
+{
+ if (!flash_bank_list())
+ return ERROR_OK;
+
+ struct command *parent = command_find_in_context(cmd_ctx, "flash");
+ return register_commands(cmd_ctx, parent, flash_exec_command_handlers);
+}
+
+COMMAND_HANDLER(handle_flash_bank_command)
+{
+ if (CMD_ARGC < 7) {
+ LOG_ERROR("usage: flash bank <name> <driver> "
+ "<base> <size> <chip_width> <bus_width> <target>");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ /* save bank name and advance arguments for compatibility */
+ const char *bank_name = *CMD_ARGV++;
+ CMD_ARGC--;
+
+ struct target *target = get_target(CMD_ARGV[5]);
+ if (target == NULL) {
+ LOG_ERROR("target '%s' not defined", CMD_ARGV[5]);
+ return ERROR_FAIL;
+ }
+
+ const char *driver_name = CMD_ARGV[0];
+ struct flash_driver *driver = flash_driver_find_by_name(driver_name);
+ if (NULL == driver) {
+ /* no matching flash driver found */
+ LOG_ERROR("flash driver '%s' not found", driver_name);
+ return ERROR_FAIL;
+ }
+
+ /* check the flash bank name is unique */
+ if (get_flash_bank_by_name_noprobe(bank_name) != NULL) {
+ /* flash bank name already exists */
+ LOG_ERROR("flash bank name '%s' already exists", bank_name);
+ return ERROR_FAIL;
+ }
+
+ /* register flash specific commands */
+ if (NULL != driver->commands) {
+ int retval = register_commands(CMD_CTX, NULL,
+ driver->commands);
+ if (ERROR_OK != retval) {
+ LOG_ERROR("couldn't register '%s' commands",
+ driver_name);
+ return ERROR_FAIL;
+ }
+ }
+
+ struct flash_bank *c = malloc(sizeof(*c));
+ c->name = strdup(bank_name);
+ c->target = target;
+ c->driver = driver;
+ c->driver_priv = NULL;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], c->base);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], c->size);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], c->chip_width);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], c->bus_width);
+ c->default_padded_value = 0xff;
+ c->num_sectors = 0;
+ c->sectors = NULL;
+ c->next = NULL;
+
+ int retval;
+ retval = CALL_COMMAND_HANDLER(driver->flash_bank_command, c);
+ if (ERROR_OK != retval) {
+ LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" PRIx32 "; usage: %s",
+ driver_name, c->base, driver->usage);
+ free(c);
+ return retval;
+ }
+
+ if (driver->usage == NULL)
+ LOG_DEBUG("'%s' driver usage field missing", driver_name);
+
+ flash_bank_add(c);
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(handle_flash_banks_command)
+{
+ if (CMD_ARGC != 0)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ unsigned n = 0;
+ for (struct flash_bank *p = flash_bank_list(); p; p = p->next, n++) {
+ LOG_USER("#%d : %s (%s) at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32 ", "
+ "buswidth %u, chipwidth %u", p->bank_number,
+ p->name, p->driver->name, p->base, p->size,
+ p->bus_width, p->chip_width);
+ }
+ return ERROR_OK;
+}
+
+static int jim_flash_list(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
+{
+ if (argc != 1) {
+ Jim_WrongNumArgs(interp, 1, argv,
+ "no arguments to 'flash list' command");
+ return JIM_ERR;
+ }
+
+ Jim_Obj *list = Jim_NewListObj(interp, NULL, 0);
+
+ for (struct flash_bank *p = flash_bank_list(); p; p = p->next) {
+ Jim_Obj *elem = Jim_NewListObj(interp, NULL, 0);
+
+ Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "name", -1));
+ Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, p->driver->name, -1));
+ Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "base", -1));
+ Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->base));
+ Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "size", -1));
+ Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->size));
+ Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "bus_width", -1));
+ Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->bus_width));
+ Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "chip_width", -1));
+ Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->chip_width));
+
+ Jim_ListAppendElement(interp, list, elem);
+ }
+
+ Jim_SetResult(interp, list);
+
+ return JIM_OK;
+}
+
+COMMAND_HANDLER(handle_flash_init_command)
+{
+ if (CMD_ARGC != 0)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ static bool flash_initialized;
+ if (flash_initialized) {
+ LOG_INFO("'flash init' has already been called");
+ return ERROR_OK;
+ }
+ flash_initialized = true;
+
+ LOG_DEBUG("Initializing flash devices...");
+ return flash_init_drivers(CMD_CTX);
+}
+
+static const struct command_registration flash_config_command_handlers[] = {
+ {
+ .name = "bank",
+ .handler = handle_flash_bank_command,
+ .mode = COMMAND_CONFIG,
+ .usage = "bank_id driver_name base_address size_bytes "
+ "chip_width_bytes bus_width_bytes target "
+ "[driver_options ...]",
+ .help = "Define a new bank with the given name, "
+ "using the specified NOR flash driver.",
+ },
+ {
+ .name = "init",
+ .mode = COMMAND_CONFIG,
+ .handler = handle_flash_init_command,
+ .help = "Initialize flash devices.",
+ },
+ {
+ .name = "banks",
+ .mode = COMMAND_ANY,
+ .handler = handle_flash_banks_command,
+ .help = "Display table with information about flash banks.",
+ },
+ {
+ .name = "list",
+ .mode = COMMAND_ANY,
+ .jim_handler = jim_flash_list,
+ .help = "Returns a list of details about the flash banks.",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration flash_command_handlers[] = {
+ {
+ .name = "flash",
+ .mode = COMMAND_ANY,
+ .help = "NOR flash command group",
+ .chain = flash_config_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+int flash_register_commands(struct command_context *cmd_ctx)
+{
+ return register_commands(cmd_ctx, NULL, flash_command_handlers);
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/tms470.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/tms470.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/tms470.c
new file mode 100755
index 0000000..86858a8
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/tms470.c
@@ -0,0 +1,1191 @@
+/***************************************************************************
+ * Copyright (C) 2007,2008 by Christopher Kilgour *
+ * techie |_at_| whiterocker |_dot_| com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+
+/* ----------------------------------------------------------------------
+ * Internal Support, Helpers
+ * ---------------------------------------------------------------------- */
+
+struct tms470_flash_bank {
+ unsigned ordinal;
+
+ /* device identification register */
+ uint32_t device_ident_reg;
+ uint32_t silicon_version;
+ uint32_t technology_family;
+ uint32_t rom_flash;
+ uint32_t part_number;
+ const char *part_name;
+
+};
+
+static const struct flash_sector TMS470R1A256_SECTORS[] = {
+ {0x00000000, 0x00002000, -1, -1},
+ {0x00002000, 0x00002000, -1, -1},
+ {0x00004000, 0x00002000, -1, -1},
+ {0x00006000, 0x00002000, -1, -1},
+ {0x00008000, 0x00008000, -1, -1},
+ {0x00010000, 0x00008000, -1, -1},
+ {0x00018000, 0x00008000, -1, -1},
+ {0x00020000, 0x00008000, -1, -1},
+ {0x00028000, 0x00008000, -1, -1},
+ {0x00030000, 0x00008000, -1, -1},
+ {0x00038000, 0x00002000, -1, -1},
+ {0x0003A000, 0x00002000, -1, -1},
+ {0x0003C000, 0x00002000, -1, -1},
+ {0x0003E000, 0x00002000, -1, -1},
+};
+
+#define TMS470R1A256_NUM_SECTORS \
+ ARRAY_SIZE(TMS470R1A256_SECTORS)
+
+static const struct flash_sector TMS470R1A288_BANK0_SECTORS[] = {
+ {0x00000000, 0x00002000, -1, -1},
+ {0x00002000, 0x00002000, -1, -1},
+ {0x00004000, 0x00002000, -1, -1},
+ {0x00006000, 0x00002000, -1, -1},
+};
+
+#define TMS470R1A288_BANK0_NUM_SECTORS \
+ ARRAY_SIZE(TMS470R1A288_BANK0_SECTORS)
+
+static const struct flash_sector TMS470R1A288_BANK1_SECTORS[] = {
+ {0x00040000, 0x00010000, -1, -1},
+ {0x00050000, 0x00010000, -1, -1},
+ {0x00060000, 0x00010000, -1, -1},
+ {0x00070000, 0x00010000, -1, -1},
+};
+
+#define TMS470R1A288_BANK1_NUM_SECTORS \
+ ARRAY_SIZE(TMS470R1A288_BANK1_SECTORS)
+
+static const struct flash_sector TMS470R1A384_BANK0_SECTORS[] = {
+ {0x00000000, 0x00002000, -1, -1},
+ {0x00002000, 0x00002000, -1, -1},
+ {0x00004000, 0x00004000, -1, -1},
+ {0x00008000, 0x00004000, -1, -1},
+ {0x0000C000, 0x00004000, -1, -1},
+ {0x00010000, 0x00004000, -1, -1},
+ {0x00014000, 0x00004000, -1, -1},
+ {0x00018000, 0x00002000, -1, -1},
+ {0x0001C000, 0x00002000, -1, -1},
+ {0x0001E000, 0x00002000, -1, -1},
+};
+
+#define TMS470R1A384_BANK0_NUM_SECTORS \
+ ARRAY_SIZE(TMS470R1A384_BANK0_SECTORS)
+
+static const struct flash_sector TMS470R1A384_BANK1_SECTORS[] = {
+ {0x00020000, 0x00008000, -1, -1},
+ {0x00028000, 0x00008000, -1, -1},
+ {0x00030000, 0x00008000, -1, -1},
+ {0x00038000, 0x00008000, -1, -1},
+};
+
+#define TMS470R1A384_BANK1_NUM_SECTORS \
+ ARRAY_SIZE(TMS470R1A384_BANK1_SECTORS)
+
+static const struct flash_sector TMS470R1A384_BANK2_SECTORS[] = {
+ {0x00040000, 0x00008000, -1, -1},
+ {0x00048000, 0x00008000, -1, -1},
+ {0x00050000, 0x00008000, -1, -1},
+ {0x00058000, 0x00008000, -1, -1},
+};
+
+#define TMS470R1A384_BANK2_NUM_SECTORS \
+ ARRAY_SIZE(TMS470R1A384_BANK2_SECTORS)
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_read_part_info(struct flash_bank *bank)
+{
+ struct tms470_flash_bank *tms470_info = bank->driver_priv;
+ struct target *target = bank->target;
+ uint32_t device_ident_reg;
+ uint32_t silicon_version;
+ uint32_t technology_family;
+ uint32_t rom_flash;
+ uint32_t part_number;
+ const char *part_name;
+
+ /* we shall not rely on the caller in this test, this function allocates memory,
+ thus and executing the code more than once may cause memory leak */
+ if (tms470_info->device_ident_reg)
+ return ERROR_OK;
+
+ /* read and parse the device identification register */
+ target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
+
+ LOG_INFO("device_ident_reg = 0x%08" PRIx32 "", device_ident_reg);
+
+ if ((device_ident_reg & 7) == 0) {
+ LOG_WARNING("Cannot identify target as a TMS470 family.");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ silicon_version = (device_ident_reg >> 12) & 0xF;
+ technology_family = (device_ident_reg >> 11) & 1;
+ rom_flash = (device_ident_reg >> 10) & 1;
+ part_number = (device_ident_reg >> 3) & 0x7f;
+
+ if (bank->sectors) {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
+ /*
+ * If the part number is known, determine if the flash bank is valid
+ * based on the base address being within the known flash bank
+ * ranges. Then fixup/complete the remaining fields of the flash
+ * bank structure.
+ */
+ switch (part_number) {
+ case 0x0a:
+ part_name = "TMS470R1A256";
+
+ if (bank->base >= 0x00040000) {
+ LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
+ part_name,
+ bank->base);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ tms470_info->ordinal = 0;
+ bank->base = 0x00000000;
+ bank->size = 256 * 1024;
+ bank->num_sectors = TMS470R1A256_NUM_SECTORS;
+ bank->sectors = malloc(sizeof(TMS470R1A256_SECTORS));
+ if (!bank->sectors)
+ return ERROR_FLASH_OPERATION_FAILED;
+ (void)memcpy(bank->sectors, TMS470R1A256_SECTORS, sizeof(TMS470R1A256_SECTORS));
+ break;
+
+ case 0x2b:
+ part_name = "TMS470R1A288";
+
+ if (bank->base < 0x00008000) {
+ tms470_info->ordinal = 0;
+ bank->base = 0x00000000;
+ bank->size = 32 * 1024;
+ bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
+ bank->sectors = malloc(sizeof(TMS470R1A288_BANK0_SECTORS));
+ if (!bank->sectors)
+ return ERROR_FLASH_OPERATION_FAILED;
+ (void)memcpy(bank->sectors, TMS470R1A288_BANK0_SECTORS,
+ sizeof(TMS470R1A288_BANK0_SECTORS));
+ } else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000)) {
+ tms470_info->ordinal = 1;
+ bank->base = 0x00040000;
+ bank->size = 256 * 1024;
+ bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
+ bank->sectors = malloc(sizeof(TMS470R1A288_BANK1_SECTORS));
+ if (!bank->sectors)
+ return ERROR_FLASH_OPERATION_FAILED;
+ (void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS,
+ sizeof(TMS470R1A288_BANK1_SECTORS));
+ } else {
+ LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
+ part_name, bank->base);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ break;
+
+ case 0x2d:
+ part_name = "TMS470R1A384";
+
+ if (bank->base < 0x00020000) {
+ tms470_info->ordinal = 0;
+ bank->base = 0x00000000;
+ bank->size = 128 * 1024;
+ bank->num_sectors = TMS470R1A384_BANK0_NUM_SECTORS;
+ bank->sectors = malloc(sizeof(TMS470R1A384_BANK0_SECTORS));
+ if (!bank->sectors)
+ return ERROR_FLASH_OPERATION_FAILED;
+ (void)memcpy(bank->sectors, TMS470R1A384_BANK0_SECTORS,
+ sizeof(TMS470R1A384_BANK0_SECTORS));
+ } else if ((bank->base >= 0x00020000) && (bank->base < 0x00040000)) {
+ tms470_info->ordinal = 1;
+ bank->base = 0x00020000;
+ bank->size = 128 * 1024;
+ bank->num_sectors = TMS470R1A384_BANK1_NUM_SECTORS;
+ bank->sectors = malloc(sizeof(TMS470R1A384_BANK1_SECTORS));
+ if (!bank->sectors)
+ return ERROR_FLASH_OPERATION_FAILED;
+ (void)memcpy(bank->sectors, TMS470R1A384_BANK1_SECTORS,
+ sizeof(TMS470R1A384_BANK1_SECTORS));
+ } else if ((bank->base >= 0x00040000) && (bank->base < 0x00060000)) {
+ tms470_info->ordinal = 2;
+ bank->base = 0x00040000;
+ bank->size = 128 * 1024;
+ bank->num_sectors = TMS470R1A384_BANK2_NUM_SECTORS;
+ bank->sectors = malloc(sizeof(TMS470R1A384_BANK2_SECTORS));
+ if (!bank->sectors)
+ return ERROR_FLASH_OPERATION_FAILED;
+ (void)memcpy(bank->sectors, TMS470R1A384_BANK2_SECTORS,
+ sizeof(TMS470R1A384_BANK2_SECTORS));
+ } else {
+ LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
+ part_name, bank->base);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ break;
+
+ default:
+ LOG_WARNING("Could not identify part 0x%02x as a member of the TMS470 family.",
+ (unsigned)part_number);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* turn off memory selects */
+ target_write_u32(target, 0xFFFFFFE4, 0x00000000);
+ target_write_u32(target, 0xFFFFFFE0, 0x00000000);
+
+ bank->chip_width = 32;
+ bank->bus_width = 32;
+
+ LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
+ part_name,
+ (int)(silicon_version),
+ (technology_family ? "1.8v" : "3.3v"),
+ (rom_flash ? "rom" : "flash"));
+
+ tms470_info->device_ident_reg = device_ident_reg;
+ tms470_info->silicon_version = silicon_version;
+ tms470_info->technology_family = technology_family;
+ tms470_info->rom_flash = rom_flash;
+ tms470_info->part_number = part_number;
+ tms470_info->part_name = part_name;
+
+ /*
+ * Disable reset on address access violation.
+ */
+ target_write_u32(target, 0xFFFFFFE0, 0x00004007);
+
+ return ERROR_OK;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static uint32_t keysSet;
+static uint32_t flashKeys[4];
+
+COMMAND_HANDLER(tms470_handle_flash_keyset_command)
+{
+ if (CMD_ARGC > 4)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ else if (CMD_ARGC == 4) {
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ int start = (0 == strncmp(CMD_ARGV[i], "0x", 2)) ? 2 : 0;
+
+ if (1 != sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flashKeys[i])) {
+ command_print(CMD_CTX, "could not process flash key %s",
+ CMD_ARGV[i]);
+ LOG_ERROR("could not process flash key %s", CMD_ARGV[i]);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ }
+
+ keysSet = 1;
+ } else if (CMD_ARGC != 0) {
+ command_print(CMD_CTX, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ if (keysSet) {
+ command_print(CMD_CTX,
+ "using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
+ flashKeys[0],
+ flashKeys[1],
+ flashKeys[2],
+ flashKeys[3]);
+ } else
+ command_print(CMD_CTX, "flash keys not set");
+
+ return ERROR_OK;
+}
+
+static const uint32_t FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF,};
+
+static const uint32_t FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,};
+
+static const uint32_t FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
+ 0xf0fff0ff, 0xf0fff0ff};
+
+static const uint32_t FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
+ 0x0000ffff, 0x0000ffff};
+
+/* ---------------------------------------------------------------------- */
+
+static int oscMHz = 12;
+
+COMMAND_HANDLER(tms470_handle_osc_megahertz_command)
+{
+ if (CMD_ARGC > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ else if (CMD_ARGC == 1)
+ sscanf(CMD_ARGV[0], "%d", &oscMHz);
+
+ if (oscMHz <= 0) {
+ LOG_ERROR("osc_megahertz must be positive and non-zero!");
+ command_print(CMD_CTX, "osc_megahertz must be positive and non-zero!");
+ oscMHz = 12;
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ command_print(CMD_CTX, "osc_megahertz=%d", oscMHz);
+
+ return ERROR_OK;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int plldis;
+
+COMMAND_HANDLER(tms470_handle_plldis_command)
+{
+ if (CMD_ARGC > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ else if (CMD_ARGC == 1) {
+ sscanf(CMD_ARGV[0], "%d", &plldis);
+ plldis = plldis ? 1 : 0;
+ }
+
+ command_print(CMD_CTX, "plldis=%d", plldis);
+
+ return ERROR_OK;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_check_flash_unlocked(struct target *target)
+{
+ uint32_t fmbbusy;
+
+ target_read_u32(target, 0xFFE89C08, &fmbbusy);
+ LOG_INFO("tms470 fmbbusy = 0x%08" PRIx32 " -> %s",
+ fmbbusy,
+ fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
+ return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_try_flash_keys(struct target *target, const uint32_t *key_set)
+{
+ uint32_t glbctrl, fmmstat;
+ int retval = ERROR_FLASH_OPERATION_FAILED;
+
+ /* set GLBCTRL.4 */
+ target_read_u32(target, 0xFFFFFFDC, &glbctrl);
+ target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
+
+ /* only perform the key match when 3VSTAT is clear */
+ target_read_u32(target, 0xFFE8BC0C, &fmmstat);
+ if (!(fmmstat & 0x08)) {
+ unsigned i;
+ uint32_t fmbptr, fmbac2, orig_fmregopt;
+
+ target_write_u32(target, 0xFFE8BC04, fmmstat & ~0x07);
+
+ /* wait for pump ready */
+ do {
+ target_read_u32(target, 0xFFE8A814, &fmbptr);
+ alive_sleep(1);
+ } while (!(fmbptr & 0x0200));
+
+ /* force max wait states */
+ target_read_u32(target, 0xFFE88004, &fmbac2);
+ target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
+
+ /* save current access mode, force normal read mode */
+ target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
+ target_write_u32(target, 0xFFE89C00, 0x00);
+
+ for (i = 0; i < 4; i++) {
+ uint32_t tmp;
+
+ /* There is no point displaying the value of tmp, it is
+ * filtered by the chip. The purpose of this read is to
+ * prime the unlocking logic rather than read out the value.
+ */
+ target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
+
+ LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32 "", key_set[i]);
+ target_write_u32(target, 0xFFE89C0C, key_set[i]);
+ }
+
+ if (ERROR_OK == tms470_check_flash_unlocked(target)) {
+ /*
+ * There seems to be a side-effect of reading the FMPKEY
+ * register in that it re-enables the protection. So we
+ * re-enable it.
+ */
+ for (i = 0; i < 4; i++) {
+ uint32_t tmp;
+
+ target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
+ target_write_u32(target, 0xFFE89C0C, key_set[i]);
+ }
+ retval = ERROR_OK;
+ }
+
+ /* restore settings */
+ target_write_u32(target, 0xFFE89C00, orig_fmregopt);
+ target_write_u32(target, 0xFFE88004, fmbac2);
+ }
+
+ /* clear config bit */
+ target_write_u32(target, 0xFFFFFFDC, glbctrl);
+
+ return retval;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_unlock_flash(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ const uint32_t *p_key_sets[5];
+ unsigned i, key_set_count;
+
+ if (keysSet) {
+ key_set_count = 5;
+ p_key_sets[0] = flashKeys;
+ p_key_sets[1] = FLASH_KEYS_ALL_ONES;
+ p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
+ p_key_sets[3] = FLASH_KEYS_MIX1;
+ p_key_sets[4] = FLASH_KEYS_MIX2;
+ } else {
+ key_set_count = 4;
+ p_key_sets[0] = FLASH_KEYS_ALL_ONES;
+ p_key_sets[1] = FLASH_KEYS_ALL_ZEROS;
+ p_key_sets[2] = FLASH_KEYS_MIX1;
+ p_key_sets[3] = FLASH_KEYS_MIX2;
+ }
+
+ for (i = 0; i < key_set_count; i++) {
+ if (tms470_try_flash_keys(target, p_key_sets[i]) == ERROR_OK) {
+ LOG_INFO("tms470 flash is unlocked");
+ return ERROR_OK;
+ }
+ }
+
+ LOG_WARNING("tms470 could not unlock flash memory protection level 2");
+ return ERROR_FLASH_OPERATION_FAILED;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_flash_initialize_internal_state_machine(struct flash_bank *bank)
+{
+ uint32_t fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
+ struct target *target = bank->target;
+ struct tms470_flash_bank *tms470_info = bank->driver_priv;
+ int result = ERROR_OK;
+
+ /*
+ * Select the desired bank to be programmed by writing BANK[2:0] of
+ * FMMAC2.
+ */
+ target_read_u32(target, 0xFFE8BC04, &fmmac2);
+ fmmac2 &= ~0x0007;
+ fmmac2 |= (tms470_info->ordinal & 7);
+ target_write_u32(target, 0xFFE8BC04, fmmac2);
+ LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
+
+ /*
+ * Disable level 1 sector protection by setting bit 15 of FMMAC1.
+ */
+ target_read_u32(target, 0xFFE8BC00, &fmmac1);
+ fmmac1 |= 0x8000;
+ target_write_u32(target, 0xFFE8BC00, fmmac1);
+ LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
+
+ /*
+ * FMTCREG = 0x2fc0;
+ */
+ target_write_u32(target, 0xFFE8BC10, 0x2fc0);
+ LOG_DEBUG("set fmtcreg = 0x2fc0");
+
+ /*
+ * MAXPP = 50
+ */
+ target_write_u32(target, 0xFFE8A07C, 50);
+ LOG_DEBUG("set fmmaxpp = 50");
+
+ /*
+ * MAXCP = 0xf000 + 2000
+ */
+ target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
+ LOG_DEBUG("set fmmaxcp = 0x%04x", 0xf000 + 2000);
+
+ /*
+ * configure VHV
+ */
+ target_read_u32(target, 0xFFE8A080, &fmmaxep);
+ if (fmmaxep == 0xf000) {
+ fmmaxep = 0xf000 + 4095;
+ target_write_u32(target, 0xFFE8A80C, 0x9964);
+ LOG_DEBUG("set fmptr3 = 0x9964");
+ } else {
+ fmmaxep = 0xa000 + 4095;
+ target_write_u32(target, 0xFFE8A80C, 0x9b64);
+ LOG_DEBUG("set fmptr3 = 0x9b64");
+ }
+ target_write_u32(target, 0xFFE8A080, fmmaxep);
+ LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
+
+ /*
+ * FMPTR4 = 0xa000
+ */
+ target_write_u32(target, 0xFFE8A810, 0xa000);
+ LOG_DEBUG("set fmptr4 = 0xa000");
+
+ /*
+ * FMPESETUP, delay parameter selected based on clock frequency.
+ *
+ * According to the TI App Note SPNU257 and flashing code, delay is
+ * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
+ * clock is usually derived from the ZPLL module, and selected by
+ * the plldis global.
+ */
+ target_read_u32(target, 0xFFFFFFDC, &glbctrl);
+ sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7));
+ delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
+ target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
+ LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
+
+ /*
+ * FMPVEVACCESS, based on delay.
+ */
+ k = delay | (delay << 8);
+ target_write_u32(target, 0xFFE8A05C, k);
+ LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
+
+ /*
+ * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
+ */
+ k <<= 1;
+ target_write_u32(target, 0xFFE8A034, k);
+ LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
+ target_write_u32(target, 0xFFE8A040, k);
+ LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
+ target_write_u32(target, 0xFFE8A024, k);
+ LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
+
+ /*
+ * FMCVACCESS, based on delay.
+ */
+ k = delay * 16;
+ target_write_u32(target, 0xFFE8A060, k);
+ LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
+
+ /*
+ * FMCSETUP, based on delay.
+ */
+ k = 0x3000 | delay * 20;
+ target_write_u32(target, 0xFFE8A020, k);
+ LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
+
+ /*
+ * FMEHOLD, based on delay.
+ */
+ k = (delay * 20) << 2;
+ target_write_u32(target, 0xFFE8A038, k);
+ LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
+
+ /*
+ * PWIDTH, CWIDTH, EWIDTH, based on delay.
+ */
+ target_write_u32(target, 0xFFE8A050, delay * 8);
+ LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
+ target_write_u32(target, 0xFFE8A058, delay * 1000);
+ LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
+ target_write_u32(target, 0xFFE8A054, delay * 5400);
+ LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
+
+ return result;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_flash_status(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ int result = ERROR_OK;
+ uint32_t fmmstat;
+
+ target_read_u32(target, 0xFFE8BC0C, &fmmstat);
+ LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
+
+ if (fmmstat & 0x0080) {
+ LOG_WARNING("tms470 flash command: erase still active after busy clear.");
+ result = ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ if (fmmstat & 0x0040) {
+ LOG_WARNING("tms470 flash command: program still active after busy clear.");
+ result = ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ if (fmmstat & 0x0020) {
+ LOG_WARNING("tms470 flash command: invalid data command.");
+ result = ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ if (fmmstat & 0x0010) {
+ LOG_WARNING("tms470 flash command: program, erase or validate sector failed.");
+ result = ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ if (fmmstat & 0x0008) {
+ LOG_WARNING("tms470 flash command: voltage instability detected.");
+ result = ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ if (fmmstat & 0x0006) {
+ LOG_WARNING("tms470 flash command: command suspend detected.");
+ result = ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ if (fmmstat & 0x0001) {
+ LOG_WARNING("tms470 flash command: sector was locked.");
+ result = ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ return result;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_erase_sector(struct flash_bank *bank, int sector)
+{
+ uint32_t glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
+ struct target *target = bank->target;
+ uint32_t flashAddr = bank->base + bank->sectors[sector].offset;
+ int result = ERROR_OK;
+
+ /*
+ * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
+ * module) to enable writing to the flash registers }.
+ */
+ target_read_u32(target, 0xFFFFFFDC, &glbctrl);
+ target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
+ LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl | 0x10);
+
+ /* Force normal read mode. */
+ target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
+ target_write_u32(target, 0xFFE89C00, 0);
+ LOG_DEBUG("set fmregopt = 0x%08x", 0);
+
+ (void)tms470_flash_initialize_internal_state_machine(bank);
+
+ /*
+ * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
+ * protection for the particular sector to be erased/written.
+ */
+ if (sector < 16) {
+ target_read_u32(target, 0xFFE88008, &fmbsea);
+ target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
+ LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea | (1 << sector));
+ } else {
+ target_read_u32(target, 0xFFE8800C, &fmbseb);
+ target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
+ LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
+ }
+ bank->sectors[sector].is_protected = 0;
+
+ /*
+ * clear status regiser, sent erase command, kickoff erase
+ */
+ target_write_u16(target, flashAddr, 0x0040);
+ LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flashAddr);
+ target_write_u16(target, flashAddr, 0x0020);
+ LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0020", flashAddr);
+ target_write_u16(target, flashAddr, 0xffff);
+ LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0xffff", flashAddr);
+
+ /*
+ * Monitor FMMSTAT, busy until clear, then check and other flags for
+ * ultimate result of the operation.
+ */
+ do {
+ target_read_u32(target, 0xFFE8BC0C, &fmmstat);
+ if (fmmstat & 0x0100)
+ alive_sleep(1);
+ } while (fmmstat & 0x0100);
+
+ result = tms470_flash_status(bank);
+
+ if (sector < 16) {
+ target_write_u32(target, 0xFFE88008, fmbsea);
+ LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
+ bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
+ } else {
+ target_write_u32(target, 0xFFE8800C, fmbseb);
+ LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
+ bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
+ }
+ target_write_u32(target, 0xFFE89C00, orig_fmregopt);
+ LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
+ target_write_u32(target, 0xFFFFFFDC, glbctrl);
+ LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
+
+ if (result == ERROR_OK)
+ bank->sectors[sector].is_erased = 1;
+
+ return result;
+}
+
+/*----------------------------------------------------------------------
+ * Implementation of Flash Driver Interfaces
+ *---------------------------------------------------------------------- */
+
+static const struct command_registration tms470_any_command_handlers[] = {
+ {
+ .name = "flash_keyset",
+ .usage = "<key0> <key1> <key2> <key3>",
+ .handler = tms470_handle_flash_keyset_command,
+ .mode = COMMAND_ANY,
+ .help = "tms470 flash_keyset <key0> <key1> <key2> <key3>",
+ },
+ {
+ .name = "osc_megahertz",
+ .usage = "<MHz>",
+ .handler = tms470_handle_osc_megahertz_command,
+ .mode = COMMAND_ANY,
+ .help = "tms470 osc_megahertz <MHz>",
+ },
+ {
+ .name = "plldis",
+ .usage = "<0 | 1>",
+ .handler = tms470_handle_plldis_command,
+ .mode = COMMAND_ANY,
+ .help = "tms470 plldis <0/1>",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration tms470_command_handlers[] = {
+ {
+ .name = "tms470",
+ .mode = COMMAND_ANY,
+ .help = "TI tms470 flash command group",
+ .usage = "",
+ .chain = tms470_any_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_erase(struct flash_bank *bank, int first, int last)
+{
+ struct tms470_flash_bank *tms470_info = bank->driver_priv;
+ int sector, result = ERROR_OK;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ tms470_read_part_info(bank);
+
+ if ((first < 0) || (first >= bank->num_sectors) || (last < 0) ||
+ (last >= bank->num_sectors) || (first > last)) {
+ LOG_ERROR("Sector range %d to %d invalid.", first, last);
+ return ERROR_FLASH_SECTOR_INVALID;
+ }
+
+ result = tms470_unlock_flash(bank);
+ if (result != ERROR_OK)
+ return result;
+
+ for (sector = first; sector <= last; sector++) {
+ LOG_INFO("Erasing tms470 bank %d sector %d...", tms470_info->ordinal, sector);
+
+ result = tms470_erase_sector(bank, sector);
+
+ if (result != ERROR_OK) {
+ LOG_ERROR("tms470 could not erase flash sector.");
+ break;
+ } else
+ LOG_INFO("sector erased successfully.");
+ }
+
+ return result;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ struct tms470_flash_bank *tms470_info = bank->driver_priv;
+ struct target *target = bank->target;
+ uint32_t fmmac2, fmbsea, fmbseb;
+ int sector;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ tms470_read_part_info(bank);
+
+ if ((first < 0) || (first >= bank->num_sectors) || (last < 0) ||
+ (last >= bank->num_sectors) || (first > last)) {
+ LOG_ERROR("Sector range %d to %d invalid.", first, last);
+ return ERROR_FLASH_SECTOR_INVALID;
+ }
+
+ /* enable the appropriate bank */
+ target_read_u32(target, 0xFFE8BC04, &fmmac2);
+ target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
+
+ /* get the original sector proection flags for this bank */
+ target_read_u32(target, 0xFFE88008, &fmbsea);
+ target_read_u32(target, 0xFFE8800C, &fmbseb);
+
+ for (sector = 0; sector < bank->num_sectors; sector++) {
+ if (sector < 16) {
+ fmbsea = set ? fmbsea & ~(1 << sector) : fmbsea | (1 << sector);
+ bank->sectors[sector].is_protected = set ? 1 : 0;
+ } else {
+ fmbseb = set ? fmbseb &
+ ~(1 << (sector - 16)) : fmbseb | (1 << (sector - 16));
+ bank->sectors[sector].is_protected = set ? 1 : 0;
+ }
+ }
+
+ /* update the protection bits */
+ target_write_u32(target, 0xFFE88008, fmbsea);
+ target_write_u32(target, 0xFFE8800C, fmbseb);
+
+ return ERROR_OK;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ uint32_t glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
+ int result = ERROR_OK;
+ uint32_t i;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ tms470_read_part_info(bank);
+
+ LOG_INFO("Writing %" PRId32 " bytes starting at 0x%08" PRIx32 "", count, bank->base +
+ offset);
+
+ /* set GLBCTRL.4 */
+ target_read_u32(target, 0xFFFFFFDC, &glbctrl);
+ target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
+
+ (void)tms470_flash_initialize_internal_state_machine(bank);
+
+ /* force max wait states */
+ target_read_u32(target, 0xFFE88004, &fmbac2);
+ target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
+
+ /* save current access mode, force normal read mode */
+ target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
+ target_write_u32(target, 0xFFE89C00, 0x00);
+
+ /*
+ * Disable Level 1 protection for all sectors to be erased/written.
+ */
+ target_read_u32(target, 0xFFE88008, &fmbsea);
+ target_write_u32(target, 0xFFE88008, 0xffff);
+ target_read_u32(target, 0xFFE8800C, &fmbseb);
+ target_write_u32(target, 0xFFE8800C, 0xffff);
+
+ /* read MAXPP */
+ target_read_u32(target, 0xFFE8A07C, &fmmaxpp);
+
+ for (i = 0; i < count; i += 2) {
+ uint32_t addr = bank->base + offset + i;
+ uint16_t word = (((uint16_t) buffer[i]) << 8) | (uint16_t) buffer[i + 1];
+
+ if (word != 0xffff) {
+ LOG_INFO("writing 0x%04x at 0x%08" PRIx32 "", word, addr);
+
+ /* clear status register */
+ target_write_u16(target, addr, 0x0040);
+ /* program flash command */
+ target_write_u16(target, addr, 0x0010);
+ /* burn the 16-bit word (big-endian) */
+ target_write_u16(target, addr, word);
+
+ /*
+ * Monitor FMMSTAT, busy until clear, then check and other flags
+ * for ultimate result of the operation.
+ */
+ do {
+ target_read_u32(target, 0xFFE8BC0C, &fmmstat);
+ if (fmmstat & 0x0100)
+ alive_sleep(1);
+ } while (fmmstat & 0x0100);
+
+ if (fmmstat & 0x3ff) {
+ LOG_ERROR("fmstat = 0x%04" PRIx32 "", fmmstat);
+ LOG_ERROR(
+ "Could not program word 0x%04x at address 0x%08" PRIx32 ".",
+ word,
+ addr);
+ result = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+ } else
+ LOG_INFO("skipping 0xffff at 0x%08" PRIx32 "", addr);
+ }
+
+ /* restore */
+ target_write_u32(target, 0xFFE88008, fmbsea);
+ target_write_u32(target, 0xFFE8800C, fmbseb);
+ target_write_u32(target, 0xFFE88004, fmbac2);
+ target_write_u32(target, 0xFFE89C00, orig_fmregopt);
+ target_write_u32(target, 0xFFFFFFDC, glbctrl);
+
+ return result;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_probe(struct flash_bank *bank)
+{
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_WARNING("Cannot communicate... target not halted.");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ return tms470_read_part_info(bank);
+}
+
+static int tms470_auto_probe(struct flash_bank *bank)
+{
+ struct tms470_flash_bank *tms470_info = bank->driver_priv;
+
+ if (tms470_info->device_ident_reg)
+ return ERROR_OK;
+ return tms470_probe(bank);
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_erase_check(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct tms470_flash_bank *tms470_info = bank->driver_priv;
+ int sector, result = ERROR_OK;
+ uint32_t fmmac2, fmbac2, glbctrl, orig_fmregopt;
+ static uint8_t buffer[64 * 1024];
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (!tms470_info->device_ident_reg)
+ tms470_read_part_info(bank);
+
+ /* set GLBCTRL.4 */
+ target_read_u32(target, 0xFFFFFFDC, &glbctrl);
+ target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
+
+ /* save current access mode, force normal read mode */
+ target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
+ target_write_u32(target, 0xFFE89C00, 0x00);
+
+ /* enable the appropriate bank */
+ target_read_u32(target, 0xFFE8BC04, &fmmac2);
+ target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
+
+ /* TCR = 0 */
+ target_write_u32(target, 0xFFE8BC10, 0x2fc0);
+
+ /* clear TEZ in fmbrdy */
+ target_write_u32(target, 0xFFE88010, 0x0b);
+
+ /* save current wait states, force max */
+ target_read_u32(target, 0xFFE88004, &fmbac2);
+ target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
+
+ /*
+ * The TI primitives inspect the flash memory by reading one 32-bit
+ * word at a time. Here we read an entire sector and inspect it in
+ * an attempt to reduce the JTAG overhead.
+ */
+ for (sector = 0; sector < bank->num_sectors; sector++) {
+ if (bank->sectors[sector].is_erased != 1) {
+ uint32_t i, addr = bank->base + bank->sectors[sector].offset;
+
+ LOG_INFO("checking flash bank %d sector %d", tms470_info->ordinal, sector);
+
+ target_read_buffer(target, addr, bank->sectors[sector].size, buffer);
+
+ bank->sectors[sector].is_erased = 1;
+ for (i = 0; i < bank->sectors[sector].size; i++) {
+ if (buffer[i] != 0xff) {
+ LOG_WARNING("tms470 bank %d, sector %d, not erased.",
+ tms470_info->ordinal,
+ sector);
+ LOG_WARNING(
+ "at location 0x%08" PRIx32 ": flash data is 0x%02x.",
+ addr + i,
+ buffer[i]);
+
+ bank->sectors[sector].is_erased = 0;
+ break;
+ }
+ }
+ }
+ if (bank->sectors[sector].is_erased != 1) {
+ result = ERROR_FLASH_SECTOR_NOT_ERASED;
+ break;
+ } else
+ LOG_INFO("sector erased");
+ }
+
+ /* reset TEZ, wait states, read mode, GLBCTRL.4 */
+ target_write_u32(target, 0xFFE88010, 0x0f);
+ target_write_u32(target, 0xFFE88004, fmbac2);
+ target_write_u32(target, 0xFFE89C00, orig_fmregopt);
+ target_write_u32(target, 0xFFFFFFDC, glbctrl);
+
+ return result;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int tms470_protect_check(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct tms470_flash_bank *tms470_info = bank->driver_priv;
+ int sector, result = ERROR_OK;
+ uint32_t fmmac2, fmbsea, fmbseb;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (!tms470_info->device_ident_reg)
+ tms470_read_part_info(bank);
+
+ /* enable the appropriate bank */
+ target_read_u32(target, 0xFFE8BC04, &fmmac2);
+ target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
+
+ target_read_u32(target, 0xFFE88008, &fmbsea);
+ target_read_u32(target, 0xFFE8800C, &fmbseb);
+
+ for (sector = 0; sector < bank->num_sectors; sector++) {
+ int protected;
+
+ if (sector < 16) {
+ protected = fmbsea & (1 << sector) ? 0 : 1;
+ bank->sectors[sector].is_protected = protected;
+ } else {
+ protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
+ bank->sectors[sector].is_protected = protected;
+ }
+
+ LOG_DEBUG("bank %d sector %d is %s",
+ tms470_info->ordinal,
+ sector,
+ protected ? "protected" : "not protected");
+ }
+
+ return result;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int get_tms470_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ int used = 0;
+ struct tms470_flash_bank *tms470_info = bank->driver_priv;
+
+ if (!tms470_info->device_ident_reg)
+ tms470_read_part_info(bank);
+
+ if (!tms470_info->device_ident_reg) {
+ (void)snprintf(buf, buf_size, "Cannot identify target as a TMS470\n");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ used =
+ snprintf(buf, buf_size, "\ntms470 information: Chip is %s\n",
+ tms470_info->part_name);
+ buf += used;
+ buf_size -= used;
+
+ snprintf(buf, buf_size, "Flash protection level 2 is %s\n",
+ tms470_check_flash_unlocked(bank->target) == ERROR_OK ? "disabled" : "enabled");
+
+ return ERROR_OK;
+}
+
+/* ---------------------------------------------------------------------- */
+
+/*
+ * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
+ * [options...]
+ */
+
+FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command)
+{
+ bank->driver_priv = malloc(sizeof(struct tms470_flash_bank));
+
+ if (!bank->driver_priv)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ (void)memset(bank->driver_priv, 0, sizeof(struct tms470_flash_bank));
+
+ return ERROR_OK;
+}
+
+struct flash_driver tms470_flash = {
+ .name = "tms470",
+ .commands = tms470_command_handlers,
+ .flash_bank_command = tms470_flash_bank_command,
+ .erase = tms470_erase,
+ .protect = tms470_protect,
+ .write = tms470_write,
+ .read = default_flash_read,
+ .probe = tms470_probe,
+ .auto_probe = tms470_auto_probe,
+ .erase_check = tms470_erase_check,
+ .protect_check = tms470_protect_check,
+ .info = get_tms470_info,
+};
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/virtual.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/virtual.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/virtual.c
new file mode 100755
index 0000000..599a9c0
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/virtual.c
@@ -0,0 +1,235 @@
+/***************************************************************************
+ * Copyright (C) 2010 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+
+static struct flash_bank *virtual_get_master_bank(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank;
+
+ master_bank = get_flash_bank_by_name_noprobe(bank->driver_priv);
+ if (master_bank == NULL)
+ LOG_ERROR("master flash bank '%s' does not exist", (char *)bank->driver_priv);
+
+ return master_bank;
+}
+
+static void virtual_update_bank_info(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+
+ if (master_bank == NULL)
+ return;
+
+ /* update the info we do not have */
+ bank->size = master_bank->size;
+ bank->chip_width = master_bank->chip_width;
+ bank->bus_width = master_bank->bus_width;
+ bank->default_padded_value = master_bank->default_padded_value;
+ bank->num_sectors = master_bank->num_sectors;
+ bank->sectors = master_bank->sectors;
+}
+
+FLASH_BANK_COMMAND_HANDLER(virtual_flash_bank_command)
+{
+ if (CMD_ARGC < 7)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ /* get the master flash bank */
+ const char *bank_name = CMD_ARGV[6];
+ struct flash_bank *master_bank = get_flash_bank_by_name_noprobe(bank_name);
+
+ if (master_bank == NULL) {
+ LOG_ERROR("master flash bank '%s' does not exist", bank_name);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* save master bank name - use this to get settings later */
+ bank->driver_priv = strdup(bank_name);
+
+ return ERROR_OK;
+}
+
+static int virtual_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* call master handler */
+ retval = master_bank->driver->protect(master_bank, set, first, last);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int virtual_protect_check(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* call master handler */
+ retval = master_bank->driver->protect_check(master_bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int virtual_erase(struct flash_bank *bank, int first, int last)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* call master handler */
+ retval = master_bank->driver->erase(master_bank, first, last);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int virtual_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* call master handler */
+ retval = master_bank->driver->write(master_bank, buffer, offset, count);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int virtual_probe(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* call master handler */
+ retval = master_bank->driver->probe(master_bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* update the info we do not have */
+ virtual_update_bank_info(bank);
+
+ return ERROR_OK;
+}
+
+static int virtual_auto_probe(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* call master handler */
+ retval = master_bank->driver->auto_probe(master_bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* update the info we do not have */
+ virtual_update_bank_info(bank);
+
+ return ERROR_OK;
+}
+
+static int virtual_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+
+ if (master_bank == NULL)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ snprintf(buf, buf_size, "%s driver for flash bank %s at 0x%8.8" PRIx32 "",
+ bank->driver->name, master_bank->name, master_bank->base);
+
+ return ERROR_OK;
+}
+
+static int virtual_blank_check(struct flash_bank *bank)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* call master handler */
+ retval = master_bank->driver->erase_check(master_bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int virtual_flash_read(struct flash_bank *bank,
+ uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+ struct flash_bank *master_bank = virtual_get_master_bank(bank);
+ int retval;
+
+ if (master_bank == NULL)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* call master handler */
+ retval = master_bank->driver->read(master_bank, buffer, offset, count);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+struct flash_driver virtual_flash = {
+ .name = "virtual",
+ .flash_bank_command = virtual_flash_bank_command,
+ .erase = virtual_erase,
+ .protect = virtual_protect,
+ .write = virtual_write,
+ .read = virtual_flash_read,
+ .probe = virtual_probe,
+ .auto_probe = virtual_auto_probe,
+ .erase_check = virtual_blank_check,
+ .protect_check = virtual_protect_check,
+ .info = virtual_info,
+};