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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/06/15 23:05:01 UTC
[GitHub] [incubator-nuttx] acassis opened a new pull request, #6448: xtensa/esp32s3: Add esp32s3-eye board support
acassis opened a new pull request, #6448:
URL: https://github.com/apache/incubator-nuttx/pull/6448
## Summary
Add esp32s3-eye board support
## Impact
Only ESP32-S3
## Testing
ESP32-S3-EYE
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[GitHub] [incubator-nuttx] Ouss4 commented on a diff in pull request #6448: xtensa/esp32s3: Add esp32s3-eye board support
Posted by GitBox <gi...@apache.org>.
Ouss4 commented on code in PR #6448:
URL: https://github.com/apache/incubator-nuttx/pull/6448#discussion_r899109171
##########
boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3.ld:
##########
@@ -0,0 +1,269 @@
+/****************************************************************************
+ * boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3_flash.ld
+ ****************************************************************************/
+
+/* Default entry point: */
+
+ENTRY(__start);
+
+_diram_i_start = 0x40378000;
+
+SECTIONS
+{
+ /* Send .iram0 code to iram */
+
+ .iram0.vectors :
+ {
+ _iram_start = ABSOLUTE(.);
+
+ /* Vectors go to IRAM. */
+
+ _init_start = ABSOLUTE(.);
+
+ /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
+
+ . = 0x0;
+ KEEP (*(.window_vectors.text));
+ . = 0x180;
+ KEEP (*(.xtensa_level2_vector.text));
+ . = 0x1c0;
+ KEEP (*(.xtensa_level3_vector.text));
+ . = 0x200;
+ KEEP (*(.xtensa_level4_vector.text));
+ . = 0x240;
+ KEEP (*(.xtensa_level5_vector.text));
+ . = 0x280;
+ KEEP (*(.debug_exception_vector.text));
+ . = 0x2c0;
+ KEEP (*(.nmi_vector.text));
+ . = 0x300;
+ KEEP (*(.kernel_exception_vector.text));
+ . = 0x340;
+ KEEP (*(.user_exception_vector.text));
+ . = 0x3c0;
+ KEEP (*(.double_exception_vector.text));
+ . = 0x400;
+ *(.*_vector.literal)
+
+ . = ALIGN(16);
+
+ *(.entry.text)
+ *(.init.literal)
+ *(.init)
+ } > iram0_0_seg
+
+ .iram0.text :
+ {
+ /* Code marked as running out of IRAM */
+
+ *(.iram1 .iram1.*)
+
+ /* align + add 16B for CPU dummy speculative instr. fetch */
+
+ . = ALIGN(4) + 16;
+
+ _iram_text = ABSOLUTE(.);
+ } > iram0_0_seg
+
+ .dram0.dummy (NOLOAD) :
+ {
+ /* This section is required to skip .iram0.text area because iram0_0_seg
+ * and dram0_0_seg reflect the same address space on different buses.
+ */
+
+ . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
+ } > dram0_0_seg
+
+ /* Shared RAM */
+
+ .dram0.bss (NOLOAD) :
+ {
+ /* .bss initialized on power-up */
+
+ . = ALIGN(8);
+ _sbss = ABSOLUTE(.);
+
+ *(.bss .bss.*)
+ *(COMMON)
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ *(.dynbss)
+ *(.share.mem)
+ *(.gnu.linkonce.b.*)
+
+ . = ALIGN(8);
+ _ebss = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .noinit (NOLOAD) :
+ {
+ /* This section contains data that is not initialized during load,
+ * or during the application's initialization sequence.
+ */
+
+ . = ALIGN(4);
+
+ *(.noinit .noinit.*)
+
+ . = ALIGN(4);
+ } > dram0_0_seg
+
+ .dram0.data :
+ {
+ /* .data initialized on power-up in ROMed configurations. */
+
+ _sdata = ABSOLUTE(.);
+ KEEP (*(.data))
+ KEEP (*(.data.*))
+ KEEP (*(.gnu.linkonce.d.*))
+ KEEP (*(.data1))
+ KEEP (*(.sdata))
+ KEEP (*(.sdata.*))
+ KEEP (*(.gnu.linkonce.s.*))
+ KEEP (*(.sdata2))
+ KEEP (*(.sdata2.*))
+ KEEP (*(.gnu.linkonce.s2.*))
+ KEEP (*(.jcr))
+ *(.dram1 .dram1.*)
+
+ _edata = ABSOLUTE(.);
+ . = ALIGN(4);
+
+ /* Heap starts at the end of .data */
+
+ _sheap = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .flash.text :
+ {
+ _stext = .;
+ *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+ *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.fini.literal)
+ *(.fini)
+ *(.gnu.version)
+
+ /* CPU will try to prefetch up to 16 bytes of instructions.
+ * This means that any configuration (e.g. MMU, PMS) must allow
+ * safe access to up to 16 bytes after the last real instruction, add
+ * dummy bytes to ensure this
+ */
+
+ . += 16;
+
+ _etext = .;
+ } > default_code_seg
+
+ .flash_rodata_dummy (NOLOAD) :
+ {
+ /* This dummy section represents the .flash.text section but in default_rodata_seg.
+ * Thus, it must have its alignment and (at least) its size.
+ */
+
+ /* Start at the same alignment constraint than .flash.text */
+
+ . = ALIGN(ALIGNOF(.flash.text));
+
+ /* Create an empty gap as big as .flash.text section */
+
+ . = SIZEOF(.flash.text);
+
+ /* Prepare the alignment of the section above. Few bytes (0x20) must be
+ * added for the mapping header.
+ */
+
+ . = ALIGN(0x10000) + 0x20;
+ _rodata_reserved_start = .;
+ } > default_rodata_seg
+
+ .flash.rodata : ALIGN(0x10)
+ {
+ _srodata = ABSOLUTE(.);
+
+ *(.rodata)
+ *(.rodata.*)
+ *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.gnu.linkonce.r.*)
+ *(.rodata1)
+ __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+ *(.xt_except_table)
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.gnu.linkonce.e.*)
+ *(.gnu.version_r)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+
+ /* C++ constructor and destructor tables, properly ordered: */
+
+ _sinit = ABSOLUTE(.);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ _einit = ABSOLUTE(.);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+
+ /* C++ exception handlers table: */
+
+ __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+ *(.xt_except_desc)
+ *(.gnu.linkonce.h.*)
+ __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+ *(.xt_except_desc_end)
+ *(.dynamic)
+ *(.gnu.version_d)
+ _erodata = ABSOLUTE(.);
+
+ /* Literals are also RO data. */
+
+ _lit4_start = ABSOLUTE(.);
+ *(*.lit4)
+ *(.lit4.*)
+ *(.gnu.linkonce.lit4.*)
+ _lit4_end = ABSOLUTE(.);
+ _rodata_reserved_end = ABSOLUTE(.);
+ . = ALIGN(4);
+ } > default_rodata_seg
+
+ /* Marks the end of IRAM code segment */
+
+ .iram0.text_end (NOLOAD) :
+ {
+ /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and
+ * 256B alignment for PMS split lines.
+ */
+
+ . += 16;
+ . = ALIGN(256);
+ } > iram0_0_seg
+
+ .iram0.data :
+ {
+ . = ALIGN(4);
+
+ *(.iram.data)
+ *(.iram.data.*)
+ } > iram0_0_seg
+
+ .iram0.bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+
+ *(.iram.bss)
+ *(.iram.bss.*)
+
+ . = ALIGN(4);
+ _iram_end = ABSOLUTE(.);
+ } > iram0_0_seg
Review Comment:
We did this refactoring only for ESP32 around the time MCUBoot was introduced. The LD scripts are just grouped in the common directory and used if there are no board specific ones.
Sections are not generated, the only part that's generated is the memory part where defconfig options select things like running out of IRAM only or using Flash, size of flash, etc.
The ROM linker script is autogenerated, but that's a different story. We just copy it from somewhere.
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6448: xtensa/esp32s3: Add esp32s3-eye board support
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6448:
URL: https://github.com/apache/incubator-nuttx/pull/6448#discussion_r899046105
##########
boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3.ld:
##########
@@ -0,0 +1,269 @@
+/****************************************************************************
+ * boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3_flash.ld
+ ****************************************************************************/
+
+/* Default entry point: */
+
+ENTRY(__start);
+
+_diram_i_start = 0x40378000;
+
+SECTIONS
+{
+ /* Send .iram0 code to iram */
+
+ .iram0.vectors :
+ {
+ _iram_start = ABSOLUTE(.);
+
+ /* Vectors go to IRAM. */
+
+ _init_start = ABSOLUTE(.);
+
+ /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
+
+ . = 0x0;
+ KEEP (*(.window_vectors.text));
+ . = 0x180;
+ KEEP (*(.xtensa_level2_vector.text));
+ . = 0x1c0;
+ KEEP (*(.xtensa_level3_vector.text));
+ . = 0x200;
+ KEEP (*(.xtensa_level4_vector.text));
+ . = 0x240;
+ KEEP (*(.xtensa_level5_vector.text));
+ . = 0x280;
+ KEEP (*(.debug_exception_vector.text));
+ . = 0x2c0;
+ KEEP (*(.nmi_vector.text));
+ . = 0x300;
+ KEEP (*(.kernel_exception_vector.text));
+ . = 0x340;
+ KEEP (*(.user_exception_vector.text));
+ . = 0x3c0;
+ KEEP (*(.double_exception_vector.text));
+ . = 0x400;
+ *(.*_vector.literal)
+
+ . = ALIGN(16);
+
+ *(.entry.text)
+ *(.init.literal)
+ *(.init)
+ } > iram0_0_seg
+
+ .iram0.text :
+ {
+ /* Code marked as running out of IRAM */
+
+ *(.iram1 .iram1.*)
+
+ /* align + add 16B for CPU dummy speculative instr. fetch */
+
+ . = ALIGN(4) + 16;
+
+ _iram_text = ABSOLUTE(.);
+ } > iram0_0_seg
+
+ .dram0.dummy (NOLOAD) :
+ {
+ /* This section is required to skip .iram0.text area because iram0_0_seg
+ * and dram0_0_seg reflect the same address space on different buses.
+ */
+
+ . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
+ } > dram0_0_seg
+
+ /* Shared RAM */
+
+ .dram0.bss (NOLOAD) :
+ {
+ /* .bss initialized on power-up */
+
+ . = ALIGN(8);
+ _sbss = ABSOLUTE(.);
+
+ *(.bss .bss.*)
+ *(COMMON)
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ *(.dynbss)
+ *(.share.mem)
+ *(.gnu.linkonce.b.*)
+
+ . = ALIGN(8);
+ _ebss = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .noinit (NOLOAD) :
+ {
+ /* This section contains data that is not initialized during load,
+ * or during the application's initialization sequence.
+ */
+
+ . = ALIGN(4);
+
+ *(.noinit .noinit.*)
+
+ . = ALIGN(4);
+ } > dram0_0_seg
+
+ .dram0.data :
+ {
+ /* .data initialized on power-up in ROMed configurations. */
+
+ _sdata = ABSOLUTE(.);
+ KEEP (*(.data))
+ KEEP (*(.data.*))
+ KEEP (*(.gnu.linkonce.d.*))
+ KEEP (*(.data1))
+ KEEP (*(.sdata))
+ KEEP (*(.sdata.*))
+ KEEP (*(.gnu.linkonce.s.*))
+ KEEP (*(.sdata2))
+ KEEP (*(.sdata2.*))
+ KEEP (*(.gnu.linkonce.s2.*))
+ KEEP (*(.jcr))
+ *(.dram1 .dram1.*)
+
+ _edata = ABSOLUTE(.);
+ . = ALIGN(4);
+
+ /* Heap starts at the end of .data */
+
+ _sheap = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .flash.text :
+ {
+ _stext = .;
+ *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+ *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.fini.literal)
+ *(.fini)
+ *(.gnu.version)
+
+ /* CPU will try to prefetch up to 16 bytes of instructions.
+ * This means that any configuration (e.g. MMU, PMS) must allow
+ * safe access to up to 16 bytes after the last real instruction, add
+ * dummy bytes to ensure this
+ */
+
+ . += 16;
+
+ _etext = .;
+ } > default_code_seg
+
+ .flash_rodata_dummy (NOLOAD) :
+ {
+ /* This dummy section represents the .flash.text section but in default_rodata_seg.
+ * Thus, it must have its alignment and (at least) its size.
+ */
+
+ /* Start at the same alignment constraint than .flash.text */
+
+ . = ALIGN(ALIGNOF(.flash.text));
+
+ /* Create an empty gap as big as .flash.text section */
+
+ . = SIZEOF(.flash.text);
+
+ /* Prepare the alignment of the section above. Few bytes (0x20) must be
+ * added for the mapping header.
+ */
+
+ . = ALIGN(0x10000) + 0x20;
+ _rodata_reserved_start = .;
+ } > default_rodata_seg
+
+ .flash.rodata : ALIGN(0x10)
+ {
+ _srodata = ABSOLUTE(.);
+
+ *(.rodata)
+ *(.rodata.*)
+ *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.gnu.linkonce.r.*)
+ *(.rodata1)
+ __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+ *(.xt_except_table)
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.gnu.linkonce.e.*)
+ *(.gnu.version_r)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+
+ /* C++ constructor and destructor tables, properly ordered: */
+
+ _sinit = ABSOLUTE(.);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ _einit = ABSOLUTE(.);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+
+ /* C++ exception handlers table: */
+
+ __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+ *(.xt_except_desc)
+ *(.gnu.linkonce.h.*)
+ __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+ *(.xt_except_desc_end)
+ *(.dynamic)
+ *(.gnu.version_d)
+ _erodata = ABSOLUTE(.);
+
+ /* Literals are also RO data. */
+
+ _lit4_start = ABSOLUTE(.);
+ *(*.lit4)
+ *(.lit4.*)
+ *(.gnu.linkonce.lit4.*)
+ _lit4_end = ABSOLUTE(.);
+ _rodata_reserved_end = ABSOLUTE(.);
+ . = ALIGN(4);
+ } > default_rodata_seg
+
+ /* Marks the end of IRAM code segment */
+
+ .iram0.text_end (NOLOAD) :
+ {
+ /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and
+ * 256B alignment for PMS split lines.
+ */
+
+ . += 16;
+ . = ALIGN(256);
+ } > iram0_0_seg
+
+ .iram0.data :
+ {
+ . = ALIGN(4);
+
+ *(.iram.data)
+ *(.iram.data.*)
+ } > iram0_0_seg
+
+ .iram0.bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+
+ *(.iram.bss)
+ *(.iram.bss.*)
+
+ . = ALIGN(4);
+ _iram_end = ABSOLUTE(.);
+ } > iram0_0_seg
Review Comment:
isn't LD script autogenerated from common?
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[GitHub] [incubator-nuttx] acassis commented on a diff in pull request #6448: xtensa/esp32s3: Add esp32s3-eye board support
Posted by GitBox <gi...@apache.org>.
acassis commented on code in PR #6448:
URL: https://github.com/apache/incubator-nuttx/pull/6448#discussion_r899048693
##########
boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3.ld:
##########
@@ -0,0 +1,269 @@
+/****************************************************************************
+ * boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3_flash.ld
+ ****************************************************************************/
+
+/* Default entry point: */
+
+ENTRY(__start);
+
+_diram_i_start = 0x40378000;
+
+SECTIONS
+{
+ /* Send .iram0 code to iram */
+
+ .iram0.vectors :
+ {
+ _iram_start = ABSOLUTE(.);
+
+ /* Vectors go to IRAM. */
+
+ _init_start = ABSOLUTE(.);
+
+ /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
+
+ . = 0x0;
+ KEEP (*(.window_vectors.text));
+ . = 0x180;
+ KEEP (*(.xtensa_level2_vector.text));
+ . = 0x1c0;
+ KEEP (*(.xtensa_level3_vector.text));
+ . = 0x200;
+ KEEP (*(.xtensa_level4_vector.text));
+ . = 0x240;
+ KEEP (*(.xtensa_level5_vector.text));
+ . = 0x280;
+ KEEP (*(.debug_exception_vector.text));
+ . = 0x2c0;
+ KEEP (*(.nmi_vector.text));
+ . = 0x300;
+ KEEP (*(.kernel_exception_vector.text));
+ . = 0x340;
+ KEEP (*(.user_exception_vector.text));
+ . = 0x3c0;
+ KEEP (*(.double_exception_vector.text));
+ . = 0x400;
+ *(.*_vector.literal)
+
+ . = ALIGN(16);
+
+ *(.entry.text)
+ *(.init.literal)
+ *(.init)
+ } > iram0_0_seg
+
+ .iram0.text :
+ {
+ /* Code marked as running out of IRAM */
+
+ *(.iram1 .iram1.*)
+
+ /* align + add 16B for CPU dummy speculative instr. fetch */
+
+ . = ALIGN(4) + 16;
+
+ _iram_text = ABSOLUTE(.);
+ } > iram0_0_seg
+
+ .dram0.dummy (NOLOAD) :
+ {
+ /* This section is required to skip .iram0.text area because iram0_0_seg
+ * and dram0_0_seg reflect the same address space on different buses.
+ */
+
+ . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
+ } > dram0_0_seg
+
+ /* Shared RAM */
+
+ .dram0.bss (NOLOAD) :
+ {
+ /* .bss initialized on power-up */
+
+ . = ALIGN(8);
+ _sbss = ABSOLUTE(.);
+
+ *(.bss .bss.*)
+ *(COMMON)
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ *(.dynbss)
+ *(.share.mem)
+ *(.gnu.linkonce.b.*)
+
+ . = ALIGN(8);
+ _ebss = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .noinit (NOLOAD) :
+ {
+ /* This section contains data that is not initialized during load,
+ * or during the application's initialization sequence.
+ */
+
+ . = ALIGN(4);
+
+ *(.noinit .noinit.*)
+
+ . = ALIGN(4);
+ } > dram0_0_seg
+
+ .dram0.data :
+ {
+ /* .data initialized on power-up in ROMed configurations. */
+
+ _sdata = ABSOLUTE(.);
+ KEEP (*(.data))
+ KEEP (*(.data.*))
+ KEEP (*(.gnu.linkonce.d.*))
+ KEEP (*(.data1))
+ KEEP (*(.sdata))
+ KEEP (*(.sdata.*))
+ KEEP (*(.gnu.linkonce.s.*))
+ KEEP (*(.sdata2))
+ KEEP (*(.sdata2.*))
+ KEEP (*(.gnu.linkonce.s2.*))
+ KEEP (*(.jcr))
+ *(.dram1 .dram1.*)
+
+ _edata = ABSOLUTE(.);
+ . = ALIGN(4);
+
+ /* Heap starts at the end of .data */
+
+ _sheap = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .flash.text :
+ {
+ _stext = .;
+ *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+ *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.fini.literal)
+ *(.fini)
+ *(.gnu.version)
+
+ /* CPU will try to prefetch up to 16 bytes of instructions.
+ * This means that any configuration (e.g. MMU, PMS) must allow
+ * safe access to up to 16 bytes after the last real instruction, add
+ * dummy bytes to ensure this
+ */
+
+ . += 16;
+
+ _etext = .;
+ } > default_code_seg
+
+ .flash_rodata_dummy (NOLOAD) :
+ {
+ /* This dummy section represents the .flash.text section but in default_rodata_seg.
+ * Thus, it must have its alignment and (at least) its size.
+ */
+
+ /* Start at the same alignment constraint than .flash.text */
+
+ . = ALIGN(ALIGNOF(.flash.text));
+
+ /* Create an empty gap as big as .flash.text section */
+
+ . = SIZEOF(.flash.text);
+
+ /* Prepare the alignment of the section above. Few bytes (0x20) must be
+ * added for the mapping header.
+ */
+
+ . = ALIGN(0x10000) + 0x20;
+ _rodata_reserved_start = .;
+ } > default_rodata_seg
+
+ .flash.rodata : ALIGN(0x10)
+ {
+ _srodata = ABSOLUTE(.);
+
+ *(.rodata)
+ *(.rodata.*)
+ *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.gnu.linkonce.r.*)
+ *(.rodata1)
+ __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+ *(.xt_except_table)
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.gnu.linkonce.e.*)
+ *(.gnu.version_r)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+
+ /* C++ constructor and destructor tables, properly ordered: */
+
+ _sinit = ABSOLUTE(.);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ _einit = ABSOLUTE(.);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+
+ /* C++ exception handlers table: */
+
+ __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+ *(.xt_except_desc)
+ *(.gnu.linkonce.h.*)
+ __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+ *(.xt_except_desc_end)
+ *(.dynamic)
+ *(.gnu.version_d)
+ _erodata = ABSOLUTE(.);
+
+ /* Literals are also RO data. */
+
+ _lit4_start = ABSOLUTE(.);
+ *(*.lit4)
+ *(.lit4.*)
+ *(.gnu.linkonce.lit4.*)
+ _lit4_end = ABSOLUTE(.);
+ _rodata_reserved_end = ABSOLUTE(.);
+ . = ALIGN(4);
+ } > default_rodata_seg
+
+ /* Marks the end of IRAM code segment */
+
+ .iram0.text_end (NOLOAD) :
+ {
+ /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and
+ * 256B alignment for PMS split lines.
+ */
+
+ . += 16;
+ . = ALIGN(256);
+ } > iram0_0_seg
+
+ .iram0.data :
+ {
+ . = ALIGN(4);
+
+ *(.iram.data)
+ *(.iram.data.*)
+ } > iram0_0_seg
+
+ .iram0.bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+
+ *(.iram.bss)
+ *(.iram.bss.*)
+
+ . = ALIGN(4);
+ _iram_end = ABSOLUTE(.);
+ } > iram0_0_seg
Review Comment:
I think it is not done for ESP32-S3, see boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3.ld
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[GitHub] [incubator-nuttx] pkarashchenko merged pull request #6448: xtensa/esp32s3: Add esp32s3-eye board support
Posted by GitBox <gi...@apache.org>.
pkarashchenko merged PR #6448:
URL: https://github.com/apache/incubator-nuttx/pull/6448
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6448: xtensa/esp32s3: Add esp32s3-eye board support
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6448:
URL: https://github.com/apache/incubator-nuttx/pull/6448#discussion_r899139293
##########
boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3.ld:
##########
@@ -0,0 +1,269 @@
+/****************************************************************************
+ * boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3_flash.ld
+ ****************************************************************************/
+
+/* Default entry point: */
+
+ENTRY(__start);
+
+_diram_i_start = 0x40378000;
+
+SECTIONS
+{
+ /* Send .iram0 code to iram */
+
+ .iram0.vectors :
+ {
+ _iram_start = ABSOLUTE(.);
+
+ /* Vectors go to IRAM. */
+
+ _init_start = ABSOLUTE(.);
+
+ /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
+
+ . = 0x0;
+ KEEP (*(.window_vectors.text));
+ . = 0x180;
+ KEEP (*(.xtensa_level2_vector.text));
+ . = 0x1c0;
+ KEEP (*(.xtensa_level3_vector.text));
+ . = 0x200;
+ KEEP (*(.xtensa_level4_vector.text));
+ . = 0x240;
+ KEEP (*(.xtensa_level5_vector.text));
+ . = 0x280;
+ KEEP (*(.debug_exception_vector.text));
+ . = 0x2c0;
+ KEEP (*(.nmi_vector.text));
+ . = 0x300;
+ KEEP (*(.kernel_exception_vector.text));
+ . = 0x340;
+ KEEP (*(.user_exception_vector.text));
+ . = 0x3c0;
+ KEEP (*(.double_exception_vector.text));
+ . = 0x400;
+ *(.*_vector.literal)
+
+ . = ALIGN(16);
+
+ *(.entry.text)
+ *(.init.literal)
+ *(.init)
+ } > iram0_0_seg
+
+ .iram0.text :
+ {
+ /* Code marked as running out of IRAM */
+
+ *(.iram1 .iram1.*)
+
+ /* align + add 16B for CPU dummy speculative instr. fetch */
+
+ . = ALIGN(4) + 16;
+
+ _iram_text = ABSOLUTE(.);
+ } > iram0_0_seg
+
+ .dram0.dummy (NOLOAD) :
+ {
+ /* This section is required to skip .iram0.text area because iram0_0_seg
+ * and dram0_0_seg reflect the same address space on different buses.
+ */
+
+ . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
+ } > dram0_0_seg
+
+ /* Shared RAM */
+
+ .dram0.bss (NOLOAD) :
+ {
+ /* .bss initialized on power-up */
+
+ . = ALIGN(8);
+ _sbss = ABSOLUTE(.);
+
+ *(.bss .bss.*)
+ *(COMMON)
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ *(.dynbss)
+ *(.share.mem)
+ *(.gnu.linkonce.b.*)
+
+ . = ALIGN(8);
+ _ebss = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .noinit (NOLOAD) :
+ {
+ /* This section contains data that is not initialized during load,
+ * or during the application's initialization sequence.
+ */
+
+ . = ALIGN(4);
+
+ *(.noinit .noinit.*)
+
+ . = ALIGN(4);
+ } > dram0_0_seg
+
+ .dram0.data :
+ {
+ /* .data initialized on power-up in ROMed configurations. */
+
+ _sdata = ABSOLUTE(.);
+ KEEP (*(.data))
+ KEEP (*(.data.*))
+ KEEP (*(.gnu.linkonce.d.*))
+ KEEP (*(.data1))
+ KEEP (*(.sdata))
+ KEEP (*(.sdata.*))
+ KEEP (*(.gnu.linkonce.s.*))
+ KEEP (*(.sdata2))
+ KEEP (*(.sdata2.*))
+ KEEP (*(.gnu.linkonce.s2.*))
+ KEEP (*(.jcr))
+ *(.dram1 .dram1.*)
+
+ _edata = ABSOLUTE(.);
+ . = ALIGN(4);
+
+ /* Heap starts at the end of .data */
+
+ _sheap = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .flash.text :
+ {
+ _stext = .;
+ *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+ *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.fini.literal)
+ *(.fini)
+ *(.gnu.version)
+
+ /* CPU will try to prefetch up to 16 bytes of instructions.
+ * This means that any configuration (e.g. MMU, PMS) must allow
+ * safe access to up to 16 bytes after the last real instruction, add
+ * dummy bytes to ensure this
+ */
+
+ . += 16;
+
+ _etext = .;
+ } > default_code_seg
+
+ .flash_rodata_dummy (NOLOAD) :
+ {
+ /* This dummy section represents the .flash.text section but in default_rodata_seg.
+ * Thus, it must have its alignment and (at least) its size.
+ */
+
+ /* Start at the same alignment constraint than .flash.text */
+
+ . = ALIGN(ALIGNOF(.flash.text));
+
+ /* Create an empty gap as big as .flash.text section */
+
+ . = SIZEOF(.flash.text);
+
+ /* Prepare the alignment of the section above. Few bytes (0x20) must be
+ * added for the mapping header.
+ */
+
+ . = ALIGN(0x10000) + 0x20;
+ _rodata_reserved_start = .;
+ } > default_rodata_seg
+
+ .flash.rodata : ALIGN(0x10)
+ {
+ _srodata = ABSOLUTE(.);
+
+ *(.rodata)
+ *(.rodata.*)
+ *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.gnu.linkonce.r.*)
+ *(.rodata1)
+ __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+ *(.xt_except_table)
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.gnu.linkonce.e.*)
+ *(.gnu.version_r)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+
+ /* C++ constructor and destructor tables, properly ordered: */
+
+ _sinit = ABSOLUTE(.);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ _einit = ABSOLUTE(.);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+
+ /* C++ exception handlers table: */
+
+ __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+ *(.xt_except_desc)
+ *(.gnu.linkonce.h.*)
+ __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+ *(.xt_except_desc_end)
+ *(.dynamic)
+ *(.gnu.version_d)
+ _erodata = ABSOLUTE(.);
+
+ /* Literals are also RO data. */
+
+ _lit4_start = ABSOLUTE(.);
+ *(*.lit4)
+ *(.lit4.*)
+ *(.gnu.linkonce.lit4.*)
+ _lit4_end = ABSOLUTE(.);
+ _rodata_reserved_end = ABSOLUTE(.);
+ . = ALIGN(4);
+ } > default_rodata_seg
+
+ /* Marks the end of IRAM code segment */
+
+ .iram0.text_end (NOLOAD) :
+ {
+ /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and
+ * 256B alignment for PMS split lines.
+ */
+
+ . += 16;
+ . = ALIGN(256);
+ } > iram0_0_seg
+
+ .iram0.data :
+ {
+ . = ALIGN(4);
+
+ *(.iram.data)
+ *(.iram.data.*)
+ } > iram0_0_seg
+
+ .iram0.bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+
+ *(.iram.bss)
+ *(.iram.bss.*)
+
+ . = ALIGN(4);
+ _iram_end = ABSOLUTE(.);
+ } > iram0_0_seg
Review Comment:
Ok.
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