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Posted to commits@nuttx.apache.org by xi...@apache.org on 2023/02/15 11:07:03 UTC
[nuttx] branch master updated (2092e9a9ca -> 4f30c298bf)
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xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
from 2092e9a9ca Adding myself to AUTHORS
new a59e65db3f stm32h7: fix comment
new 4f30c298bf stm32h7: reduce the extended filter size to 64
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Summary of changes:
arch/arm/src/stm32h7/hardware/stm32_fdcan.h | 2 +-
arch/arm/src/stm32h7/stm32_fdcan_sock.c | 17 +++++++++++++++--
2 files changed, 16 insertions(+), 3 deletions(-)
[nuttx] 01/02: stm32h7: fix comment
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit a59e65db3f93bc1af4c94480fd9d5d4dbd5cc414
Author: Julian Oes <ju...@oes.ch>
AuthorDate: Wed Feb 15 17:05:52 2023 +1300
stm32h7: fix comment
This was likely just a copy-paste error.
Signed-off-by: Julian Oes <ju...@oes.ch>
---
arch/arm/src/stm32h7/hardware/stm32_fdcan.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/src/stm32h7/hardware/stm32_fdcan.h b/arch/arm/src/stm32h7/hardware/stm32_fdcan.h
index 144e6c6f51..e2f932beb2 100644
--- a/arch/arm/src/stm32h7/hardware/stm32_fdcan.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_fdcan.h
@@ -698,7 +698,7 @@
/* *************** Bit definition for FDCAN_XIDFC register ****************/
#define FDCAN_XIDFC_FLESA_SHIFT (2U)
#define FDCAN_XIDFC_FLESA_MASK (0x3FFFU << FDCAN_XIDFC_FLESA_SHIFT) /* 0x0000FFFC */
-#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_MASK /* Filter List Standard Start Address */
+#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_MASK /* Filter List Extended Start Address */
#define FDCAN_XIDFC_LSE_SHIFT (16U)
#define FDCAN_XIDFC_LSE_MASK (0xFFU << FDCAN_XIDFC_LSE_SHIFT) /* 0x00FF0000 */
#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_MASK /* List Size Extended */
[nuttx] 02/02: stm32h7: reduce the extended filter size to 64
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 4f30c298bf67407be2dfabb130e0c27c6c651a58
Author: Julian Oes <ju...@oes.ch>
AuthorDate: Wed Feb 15 17:14:21 2023 +1300
stm32h7: reduce the extended filter size to 64
When I checked how this register was set I discovered that 128 was not
accepted by the H7 but 64 was ok. Looking at the STM32Cube's HAL it
seems to be only 64 words long, however, the reference manual claims
otherwise.
I have opened a discussion on the ST community forum
https://community.st.com/s/question/0D73W000001nzqFSAQ
but unfortunately not received an answer yet.
In the meantime, I think, we should update this to what I found to be
working though.
Signed-off-by: Julian Oes <ju...@oes.ch>
---
arch/arm/src/stm32h7/stm32_fdcan_sock.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.c b/arch/arm/src/stm32h7/stm32_fdcan_sock.c
index 3892c0839c..f13e5ad5d0 100644
--- a/arch/arm/src/stm32h7/stm32_fdcan_sock.c
+++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.c
@@ -2236,9 +2236,22 @@ int fdcan_initialize(struct fdcan_driver_s *priv)
putreg32(regval, priv->base + STM32_FDCAN_SIDFC_OFFSET);
ram_offset += n_stdid;
- /* Extended ID Filters: Allow space for 128 filters (128 words) */
+ /* Extended ID Filters: Allow space for 64 filters (64 words)
+ * The register definition of FDCAN_XIDFC:LSE - List size extended, in the
+ * reference manual (RM0433 Rev 8) is defined as 8 bits and claims that a
+ * value of 0-128 (Number of extended ID filter elements) are possible, but
+ * in the text in section 56.4.22 and in STM32CubeH7's HAL it's only 64.
+ *
+ * HAL source:
+ * https://github.com/STMicroelectronics/STM32CubeH7/blob/
+ * 43c9e552ba1c038577c48723d96ca8c825b11987/Drivers/STM32H7xx_HAL_Driver/
+ * Inc/stm32h7xx_hal_fdcan.h#L112-L113
+ *
+ * Discussion:
+ * https://community.st.com/s/question/0D73W000001nzqFSAQ
+ */
- const uint8_t n_extid = 128;
+ const uint8_t n_extid = 64;
priv->message_ram.filt_extid_addr = gl_ram_base + ram_offset * WORD_LENGTH;
regval = (n_extid << FDCAN_XIDFC_LSE_SHIFT) & FDCAN_XIDFC_LSE_MASK;