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Posted to dev@tvm.apache.org by Luis Vega <no...@github.com> on 2019/04/11 23:28:55 UTC
[dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
RFC in #3009
You can view, comment on, or merge this pull request online at:
https://github.com/dmlc/tvm/pull/3010
-- Commit Summary --
* merge files
* move verilator to the right place
* change name to tsim
-- File Changes --
M cmake/modules/VTA.cmake (5)
A vta/apps/tsim/CMakeLists.txt (22)
A vta/apps/tsim/Makefile (26)
A vta/apps/tsim/cmake/modules/driver.cmake (8)
A vta/apps/tsim/cmake/modules/tsim.cmake (135)
A vta/apps/tsim/hardware/chisel/Makefile (2)
A vta/apps/tsim/hardware/chisel/build.sbt (50)
A vta/apps/tsim/hardware/chisel/project/build.properties (1)
A vta/apps/tsim/hardware/chisel/project/plugins.sbt (1)
A vta/apps/tsim/hardware/chisel/src/main/scala/accel/Accel.scala (33)
A vta/apps/tsim/hardware/chisel/src/main/scala/accel/Compute.scala (95)
A vta/apps/tsim/hardware/chisel/src/main/scala/accel/RegFile.scala (86)
A vta/apps/tsim/hardware/chisel/src/test/scala/dut/TestAccel.scala (51)
A vta/apps/tsim/hardware/verilog/Accel.v (103)
A vta/apps/tsim/hardware/verilog/Compute.v (139)
A vta/apps/tsim/hardware/verilog/RegFile.v (129)
A vta/apps/tsim/hardware/verilog/TestAccel.v (98)
A vta/apps/tsim/python/tsim/__init__.py (0)
A vta/apps/tsim/python/tsim/config.json (7)
A vta/apps/tsim/python/tsim/config.py (44)
A vta/apps/tsim/python/tsim/load.py (39)
A vta/apps/tsim/src/test_driver.cc (73)
A vta/apps/tsim/tests/python/test_tsim.py (21)
A vta/hardware/chisel/Makefile (2)
A vta/hardware/chisel/build.sbt (49)
A vta/hardware/chisel/project/build.properties (1)
A vta/hardware/chisel/project/plugins.sbt (1)
A vta/hardware/chisel/src/main/resources/verilog/VTAHostDPI.v (101)
A vta/hardware/chisel/src/main/resources/verilog/VTAMemDPI.v (87)
A vta/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala (53)
A vta/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala (54)
A vta/include/vta/verilator/dpi_module.h (25)
A vta/include/vta/verilator/tsim.h (88)
A vta/src/verilator/dpi_module.cc (353)
A vta/src/verilator/tsim.cc (113)
-- Patch Links --
https://github.com/dmlc/tvm/pull/3010.patch
https://github.com/dmlc/tvm/pull/3010.diff
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by Tianqi Chen <no...@github.com>.
High-level structural comments, given that dpi part(verilog shell and c file) of the codebase is compiled with the verilator. We should consider a distinct folder structure. Here is one possible recommendation
```
/vta
/vta/dpi
- VTATSimMemHost.v
- vta_tsim_dpi.h
- vta_tsim_dpi.cc
- README.md
/vta/include/vta
- dpi_module.h (the common dpi module defs that can be re-used)
/vta/src
- dpi_module.cc (consider links to vta instead of tvm runtime, import vta will import the dpi)
```
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by SharpTVRepairDubai <no...@github.com>.
Great discussion, learned a lot. Thanks,
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by Liangfu Chen <no...@github.com>.
Thanks @vegaluisjose and all the reviewers ! This is a great start for us to develop, evaluate and integrate chisel3 based implement of VTA.
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by Thierry Moreau <no...@github.com>.
I've approved the changes @vegaluisjose @tqchen. There seems to be an issue with the pr-merge CI; perhaps the branch should be re-based?
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by Thierry Moreau <no...@github.com>.
In order not to confuse adopters of TSIM, who would like to use TSIM to simulate any hardware instead of VTA itself, can we have a guide that is not part of the `install.md` file aimed at VTA developers?
Once VTA can be simulated by TSIM we can merge it back.
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by Thierry Moreau <no...@github.com>.
Merged #3010 into master.
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by Tianqi Chen <no...@github.com>.
@tmoreau89 the ci is now green
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by Jared Roesch <no...@github.com>.
Do we need to commit the Verilog code? isn't generated
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by Tianqi Chen <no...@github.com>.
@tmoreau89 can you review again and https://docs.tvm.ai/contribute/code_review.html#approve-and-request-changes-explicitly?
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by Luis Vega <no...@github.com>.
Ok I have addressed most of the issues, except for `unsigned long long` complains cpplint is giving on arguments for DPI functions. The reason why I used this type is because this is the same type used by Verilator when it compiles 64-bit hardware types to C.
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Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
Posted by Tianqi Chen <no...@github.com>.
@jroesch @tmoreau89 please help to review this PR
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