[GitHub] [activemq-artemis-native] franz1981 edited a comment on issue #5: ARTEMIS-2533 Support multiple architecture for ASYNCIO kernel by-pass

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franz1981 edited a comment on issue #5: ARTEMIS-2533 Support multiple architecture for ASYNCIO kernel by-pass
URL: https://github.com/apache/activemq-artemis-native/pull/5#issuecomment-547575936
 
 
   The issue is the reordering performed by the processor: on x86 such operation won't get reordered and we can just use memory barriers for the compilers, but power pc (like arm) does aggressive reordering and I'm not sure is ok, it can fail without being unnoticed. Indeed the Linux kernel implement the barriers for power pc in a different way then x86.
   
   The code of the ring buffer Is concurrent but with the kernel: so we need to respect the order by which the kernel is populating the ring buffer.

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