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Posted to commits@nuttx.apache.org by ac...@apache.org on 2020/02/29 15:22:36 UTC
[incubator-nuttx] 13/13: Clean up comments and formatting
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch pr402
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 17985a296d99be7f6e7fdbe9dd40e10f8c36c579
Author: Joshua Lange <jl...@2g-eng.com>
AuthorDate: Fri Feb 28 13:08:19 2020 -0600
Clean up comments and formatting
---
arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h | 14 ++--
arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h | 2 +-
arch/arm/src/stm32h7/stm32_adc.c | 43 +++++++-----
arch/arm/src/stm32h7/stm32_ethernet.c | 62 +++++++++---------
arch/arm/src/stm32h7/stm32_ethernet.h | 4 +-
arch/arm/src/stm32h7/stm32_flash.c | 80 +++++++++++++----------
arch/arm/src/stm32h7/stm32_flash.h | 4 +-
arch/arm/src/stm32h7/stm32_iwdg.c | 61 +++++++++--------
arch/arm/src/stm32h7/stm32_pm.h | 12 ++--
arch/arm/src/stm32h7/stm32_pminitialize.c | 2 +-
arch/arm/src/stm32h7/stm32_pmsleep.c | 6 +-
arch/arm/src/stm32h7/stm32_pmstandby.c | 5 +-
arch/arm/src/stm32h7/stm32_pmstop.c | 10 +--
arch/arm/src/stm32h7/stm32_pwr.c | 17 +++--
arch/arm/src/stm32h7/stm32_pwr.h | 17 +++--
arch/arm/src/stm32h7/stm32_wdg.h | 10 +--
arch/arm/src/stm32h7/stm32_wwdg.c | 63 ++++++++++--------
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 17 +++--
18 files changed, 237 insertions(+), 192 deletions(-)
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
index 976c67a..aa29308 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
@@ -1,4 +1,4 @@
-/******************************************************************************
+/****************************************************************************
* arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -31,16 +31,16 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- *****************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H
#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H
-/******************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- *****************************************************************************/
+ ****************************************************************************/
-/* Register Offsets *****************************************************************/
+/* Register Offsets *********************************************************/
#define STM32_FLASH_ACR_OFFSET 0x0000 /* Access control register */
#define STM32_FLASH_KEYR1_OFFSET 0x0004 /* Key register for bank 1 */
@@ -84,7 +84,7 @@
#define STM32_FLASH_BANK1_OFFSET 0x0000 /* Bank 1 registers offset */
#define STM32_FLASH_BANK2_OFFSET 0x0100 /* Bank 2 registers offset */
-/* Register Addresses ***************************************************************/
+/* Register Addresses *******************************************************/
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
#define STM32_FLASH_KEYR1 (STM32_FLASHIF_BASE + STM32_FLASH_KEYR1_OFFSET)
@@ -125,7 +125,7 @@
#define STM32_FLASH_CRCEADD2R (STM32_FLASHIF_BASE + STM32_FLASH_CRCEADD2R_OFFSET)
#define STM32_FLASH_ECC_FA2R (STM32_FLASHIF_BASE + STM32_FLASH_ECC_FA2R_OFFSET)
-/* Register Bitfield Definitions ****************************************************/
+/* Register Bitfield Definitions ********************************************/
/* Flash Access Control Register (ACR) Bank 1 or 2 */
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
index 7cae78c..13509ef 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
@@ -75,7 +75,6 @@
/* Bits 1-3: Reserved */
#define PWR_CR1_PVDE (1 << 4) /* Bit 4: Programmable voltage detector enable */
-
#define PWR_CR1_PLS_SHIFT (5) /* Bits 5-7: Programmable voltage detector level */
#define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT)
# define PWR_CR1_PLS_1V95 (0 << PWR_CR1_PLS_SHIFT) /* 000: */
@@ -105,6 +104,7 @@
/* Bits 19-31: Reserved */
/* Power control/status register 1 (CSR1) */
+
/* Bits 0-3: Reserved */
#define PWR_CSR1_PVDO (1 << 4) /* Bit 4: Programmable voltage detect output*/
/* Bits 5-12: Reserved */
diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c
index 9f135bf..db2290b 100644
--- a/arch/arm/src/stm32h7/stm32_adc.c
+++ b/arch/arm/src/stm32h7/stm32_adc.c
@@ -86,7 +86,8 @@
((type *)((intptr_t)(ptr) - offsetof(type, member)))
#endif
-/* ADC Channels/DMA ********************************************************/
+/* ADC Channels/DMA *********************************************************/
+
/* The maximum number of channels that can be sampled. While DMA support is
* very nice for reliable multi-channel sampling, the STM32H7 can function
* without, although there is a risk of overrun.
@@ -174,7 +175,7 @@ struct stm32_dev_s
uint32_t base; /* Base address of registers unique to this ADC
* block */
uint32_t mbase; /* Base address of master ADC (allows for access to
- shared common registers) */
+ * shared common registers) */
bool initialized; /* Keeps track of the initialization status of the ADC */
#ifdef ADC_HAVE_TIMER
uint32_t tbase; /* Base address of timer used by this ADC block */
@@ -228,10 +229,11 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv,
static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset);
static void adc_enable(FAR struct stm32_dev_s *priv);
-static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last,
- int offset);
+static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first,
+ int last, int offset);
static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch);
-static bool adc_internal(FAR struct stm32_dev_s * priv, uint32_t *adc_ccr);
+static bool adc_internal(FAR struct stm32_dev_s * priv,
+ uint32_t *adc_ccr);
#ifdef ADC_HAVE_TIMER
static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable);
@@ -485,6 +487,7 @@ static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset,
{
adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits);
}
+
/****************************************************************************
* Name: adc_getregm
*
@@ -848,7 +851,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
/* Set the reload and prescaler values */
- tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler-1);
+ tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1);
tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload);
/* Clear the advanced timers repetition counter in TIM1 */
@@ -949,6 +952,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
case 4: /* TimerX TRGO event */
{
/* TODO: TRGO support not yet implemented */
+
/* Set the event TRGO */
ccenable = 0;
@@ -1053,9 +1057,11 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
*
* Description:
* Called by power management framework when it wants to enter low power
- * states. Check if ADC is in progress and if so prevent from entering STOP.
+ * states. Check if ADC is in progress and if so prevent from entering
+ * STOP.
*
****************************************************************************/
+
#ifdef CONFIG_PM
static int adc_pm_prepare(struct pm_callback_s *cb, int domain,
enum pm_state_e state)
@@ -1167,7 +1173,7 @@ static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
bit = RCC_AHB1RSTR_ADC12RST;
}
- /* First must disable interrupts because the AHB2RSTR register is used by
+ /* First must disable interrupts because the AHB2RSTR register is used by
* several different drivers.
*/
@@ -1249,8 +1255,8 @@ static void adc_enable(FAR struct stm32_dev_s *priv)
* Name: adc_bind
*
* Description:
- * Bind the upper-half driver callbacks to the lower-half implementation. This
- * must be called early in order to receive ADC event notifications.
+ * Bind the upper-half driver callbacks to the lower-half implementation.
+ * This must be called early in order to receive ADC event notifications.
*
****************************************************************************/
@@ -1332,15 +1338,16 @@ static int adc_setup(FAR struct adc_dev_s *dev)
* other has already been reset. (We only need to worry about this if both
* ADC1 and ADC2 are enabled.)
*/
+
#if defined(CONFIG_STM32H7_ADC1) && defined(CONFIG_STM32H7_ADC2)
if ((dev == &g_adcdev1 &&
!((FAR struct stm32_dev_s *)g_adcdev2.ad_priv)->initialized) ||
(dev == &g_adcdev2 &&
!((FAR struct stm32_dev_s *)g_adcdev1.ad_priv)->initialized))
#endif
- {
- adc_reset(dev);
- }
+ {
+ adc_reset(dev);
+ }
/* Initialize the same sample time for each ADC.
* During sample cycles channel selection bits must remain unchanged.
@@ -1447,7 +1454,6 @@ static int adc_setup(FAR struct adc_dev_s *dev)
adc_modifyreg(priv, STM32_ADC_PCSEL_OFFSET, clrbits, setbits);
-
/* Set ADEN to wake up the ADC from Power Down. */
adc_enable(priv);
@@ -1554,6 +1560,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
regval &= ~ADC_INT_MASK;
}
+
adc_putreg(priv, STM32_ADC_IER_OFFSET, regval);
}
@@ -1608,9 +1615,9 @@ static bool adc_internal(FAR struct stm32_dev_s * priv, uint32_t *adc_ccr)
break;
}
}
-
}
}
+
return internal;
}
@@ -1786,7 +1793,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
/* Set the watchdog threshold register */
- regval= ((arg << ADC_LTR1_LT_SHIFT) & ADC_LTR1_LT_MASK);
+ regval = ((arg << ADC_LTR1_LT_SHIFT) & ADC_LTR1_LT_MASK);
adc_putreg(priv, STM32_ADC_LTR1_OFFSET, regval);
/* Ensure analog watchdog is enabled */
@@ -1941,6 +1948,7 @@ static int adc12_interrupt(int irq, FAR void *context, FAR void *arg)
* Returned Value:
*
****************************************************************************/
+
#ifdef CONFIG_STM32H7_ADC3
static int adc3_interrupt(int irq, FAR void *context, FAR void *arg)
{
@@ -1994,7 +2002,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
for (i = 0; i < priv->nchannels; i++)
{
- priv->cb->au_receive(dev, priv->chanlist[priv->current], priv->dmabuffer[priv->current]);
+ priv->cb->au_receive(dev, priv->chanlist[priv->current],
+ priv->dmabuffer[priv->current]);
priv->current++;
if (priv->current >= priv->nchannels)
{
diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c
index a3d1974..c8035dd 100644
--- a/arch/arm/src/stm32h7/stm32_ethernet.c
+++ b/arch/arm/src/stm32h7/stm32_ethernet.c
@@ -786,6 +786,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv);
/****************************************************************************
* Private Functions
****************************************************************************/
+
/****************************************************************************
* Name: stm32_getreg
*
@@ -834,14 +835,14 @@ static uint32_t stm32_getreg(uint32_t addr)
else
{
- /* Did we print "..." for the previous value? */
+ /* Did we print "..." for the previous value? */
- if (count > 3)
- {
- /* Yes.. then show how many times the value repeated */
+ if (count > 3)
+ {
+ /* Yes.. then show how many times the value repeated */
- ninfo("[repeats %d more times]\n", count - 3);
- }
+ ninfo("[repeats %d more times]\n", count - 3);
+ }
/* Save the new address, value, and count */
@@ -1038,6 +1039,7 @@ static inline bool stm32_isfreebuffer(struct stm32_ethmac_s *priv)
* pointer to the next tx descriptor for the current interface
*
****************************************************************************/
+
static struct eth_desc_s *stm32_get_next_txdesc(struct stm32_ethmac_s *priv,
struct eth_desc_s * curr)
{
@@ -1081,8 +1083,8 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
struct eth_desc_s *txdesc;
struct eth_desc_s *txfirst;
- /* The internal (optimal) network buffer size may be configured to be larger
- * than the Ethernet buffer size.
+ /* The internal (optimal) network buffer size may be configured to be
+ * larger than the Ethernet buffer size.
*/
#if OPTIMAL_ETH_BUFSIZE > ALIGNED_BUFSIZE
@@ -1116,24 +1118,24 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
#if OPTIMAL_ETH_BUFSIZE > ALIGNED_BUFSIZE
if (priv->dev.d_len > ALIGNED_BUFSIZE)
- {
- /* Yes... how many buffers will be need to send the packet? */
+ {
+ /* Yes... how many buffers will be need to send the packet? */
- bufcount = (priv->dev.d_len + (ALIGNED_BUFSIZE - 1)) / ALIGNED_BUFSIZE;
- lastsize = priv->dev.d_len - (bufcount - 1) * ALIGNED_BUFSIZE;
+ bufcount = (priv->dev.d_len + (ALIGNED_BUFSIZE - 1)) / ALIGNED_BUFSIZE;
+ lastsize = priv->dev.d_len - (bufcount - 1) * ALIGNED_BUFSIZE;
- ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
+ ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
- /* Set the first segment bit in the first TX descriptor */
+ /* Set the first segment bit in the first TX descriptor */
- txdesc->des3 = ETH_TDES3_RD_FD;
+ txdesc->des3 = ETH_TDES3_RD_FD;
- /* Set up all but the last TX descriptor */
+ /* Set up all but the last TX descriptor */
- buffer = priv->dev.d_buf;
+ buffer = priv->dev.d_buf;
- for (i = 0; i < bufcount; i++)
- {
+ for (i = 0; i < bufcount; i++)
+ {
/* This could be a normal event but the design does not handle it */
DEBUGASSERT((txdesc->des3 & ETH_TDES3_RD_OWN) == 0);
@@ -1541,6 +1543,7 @@ static void stm32_disableint(struct stm32_ethmac_s *priv, uint32_t ierbit)
* pointer to the next rx descriptor for the current interface
*
****************************************************************************/
+
static struct eth_desc_s *stm32_get_next_rxdesc(struct stm32_ethmac_s *priv,
struct eth_desc_s * curr)
{
@@ -2887,7 +2890,6 @@ static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac)
static void stm32_txdescinit(struct stm32_ethmac_s *priv,
union stm32_desc_u *txtable)
-
{
struct eth_desc_s *txdesc;
int i;
@@ -4286,18 +4288,18 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv)
ninfo("Initialize the PHY\n");
ret = stm32_phyinit(priv);
if (ret < 0)
- {
- return ret;
- }
+ {
+ return ret;
+ }
/* Initialize the MAC and DMA */
ninfo("Initialize the MAC and DMA\n");
ret = stm32_macconfig(priv);
if (ret < 0)
- {
- return ret;
- }
+ {
+ return ret;
+ }
/* Enable normal MAC operation */
@@ -4372,11 +4374,11 @@ static inline int stm32_ethinitialize(int intf)
/* Attach the IRQ to the driver */
if (irq_attach(STM32_IRQ_ETH, stm32_interrupt, NULL))
- {
- /* We could not attach the ISR to the interrupt */
+ {
+ /* We could not attach the ISR to the interrupt */
- return -EAGAIN;
- }
+ return -EAGAIN;
+ }
/* Put the interface in the down state. */
diff --git a/arch/arm/src/stm32h7/stm32_ethernet.h b/arch/arm/src/stm32h7/stm32_ethernet.h
index 92da890..fc17197 100644
--- a/arch/arm/src/stm32h7/stm32_ethernet.h
+++ b/arch/arm/src/stm32h7/stm32_ethernet.h
@@ -48,7 +48,7 @@
#ifndef __ASSEMBLY__
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
#undef EXTERN
@@ -103,7 +103,7 @@ int stm32_ethinitialize(int intf);
*
* Assumptions:
*
- ***************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_STM32H7_PHYINIT
int stm32_phy_boardinitialize(int intf);
diff --git a/arch/arm/src/stm32h7/stm32_flash.c b/arch/arm/src/stm32h7/stm32_flash.c
index 0881eac..c7dc127 100644
--- a/arch/arm/src/stm32h7/stm32_flash.c
+++ b/arch/arm/src/stm32h7/stm32_flash.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/stm32h7/stm32h7_flash.c
+ * arch/arm/src/stm32h7/stm32_flash.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gn...@nuttx.org>
@@ -76,8 +76,8 @@
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT is set the
- * CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on the
- * chip part number. This value can be overridden with
+ * CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on
+ * the chip part number. This value can be overridden with
* CONFIG_STM32H7_FLASH_OVERRIDE_x
*
* Parts STM32H74xxE have 512Kb of FLASH
@@ -147,7 +147,7 @@
#define PROGMEM_NBLOCKS STM32_FLASH_NPAGES
-/*****************************************************************************
+/****************************************************************************
* Private Types
****************************************************************************/
@@ -184,13 +184,13 @@ static struct stm32h7_flash_priv_s stm32h7_flash_bank2_priv =
* Private Functions
****************************************************************************/
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_flash_getreg32
*
* Description:
* Get a 32-bit register value by offset
*
- *****************************************************************************/
+ ****************************************************************************/
static inline uint32_t stm32h7_flash_getreg32(FAR struct stm32h7_flash_priv_s
*priv, uint32_t offset)
@@ -198,7 +198,7 @@ static inline uint32_t stm32h7_flash_getreg32(FAR struct stm32h7_flash_priv_s
return getreg32(priv->ifbase + offset);
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_flash_putreg32
*
* Description:
@@ -213,13 +213,13 @@ static inline void stm32h7_flash_putreg32(FAR struct stm32h7_flash_priv_s
putreg32(value, priv->ifbase + offset);
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_flash_modifyreg32
*
* Description:
* Modify a 32-bit register value by offset
*
- *****************************************************************************/
+ ****************************************************************************/
static inline void stm32h7_flash_modifyreg32(FAR struct stm32h7_flash_priv_s
*priv, uint32_t offset,
@@ -229,26 +229,26 @@ static inline void stm32h7_flash_modifyreg32(FAR struct stm32h7_flash_priv_s
modifyreg32(priv->ifbase + offset, clearbits, setbits);
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_flash_sem_lock
*
* Description:
* Take the Bank exclusive access semaphore
*
- *****************************************************************************/
+ ****************************************************************************/
static void stm32h7_flash_sem_lock(FAR struct stm32h7_flash_priv_s *priv)
{
nxsem_wait_uninterruptible(&priv->sem);
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_flash_sem_unlock
*
* Description:
* Release the Bank exclusive access semaphore
*
- *****************************************************************************/
+ ****************************************************************************/
static inline void stm32h7_flash_sem_unlock(FAR struct stm32h7_flash_priv_s
*priv)
@@ -256,13 +256,13 @@ static inline void stm32h7_flash_sem_unlock(FAR struct stm32h7_flash_priv_s
nxsem_post(&priv->sem);
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_unlock_flash
*
* Description:
* Unlock the Bank
*
- *****************************************************************************/
+ ****************************************************************************/
static void stm32h7_unlock_flash(FAR struct stm32h7_flash_priv_s *priv)
{
@@ -279,38 +279,39 @@ static void stm32h7_unlock_flash(FAR struct stm32h7_flash_priv_s *priv)
}
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_lock_flash
*
* Description:
* Lock the Bank
*
- *****************************************************************************/
+ ****************************************************************************/
static void stm32h7_lock_flash(FAR struct stm32h7_flash_priv_s *priv)
{
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, 0, FLASH_CR_LOCK);
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_flash_size
*
* Description:
* Returns the size in bytes of FLASH
*
- *****************************************************************************/
+ ****************************************************************************/
static inline uint32_t stm32h7_flash_size(FAR struct stm32h7_flash_priv_s *priv)
{
return FLASH_SECTOR_SIZE * PROGMEM_NBLOCKS;
}
-/*****************************************************************************
+
+/****************************************************************************
* Name: stm32h7_flash_bank
*
* Description:
* Returns the priv pointer to the correct bank
*
- *****************************************************************************/
+ ****************************************************************************/
static inline
FAR struct stm32h7_flash_priv_s * stm32h7_flash_bank(size_t address)
@@ -320,6 +321,7 @@ FAR struct stm32h7_flash_priv_s * stm32h7_flash_bank(size_t address)
{
return NULL;
}
+
#if STM32_FLASH_NPAGES > 1
if (address >= stm32h7_flash_bank2_priv.base)
{
@@ -330,13 +332,13 @@ FAR struct stm32h7_flash_priv_s * stm32h7_flash_bank(size_t address)
return priv;
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_unlock_flashopt
*
* Description:
* Unlock the flash option bytes
*
- *****************************************************************************/
+ ****************************************************************************/
static void stm32h7_unlock_flashopt(FAR struct stm32h7_flash_priv_s *priv)
{
@@ -353,26 +355,26 @@ static void stm32h7_unlock_flashopt(FAR struct stm32h7_flash_priv_s *priv)
}
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_lock_flashopt
*
* Description:
* Lock the flash option bytes
*
- *****************************************************************************/
+ ****************************************************************************/
static void stm32h7_lock_flashopt(FAR struct stm32h7_flash_priv_s *priv)
{
stm32h7_flash_modifyreg32(priv, STM32_FLASH_OPTCR_OFFSET, 0, FLASH_OPTCR_OPTLOCK);
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_save_flashopt
*
* Description:
* Save the flash option bytes to non-volatile storage.
*
- *****************************************************************************/
+ ****************************************************************************/
static void stm32h7_save_flashopt(FAR struct stm32h7_flash_priv_s *priv)
{
@@ -386,13 +388,18 @@ static void stm32h7_save_flashopt(FAR struct stm32h7_flash_priv_s *priv)
}
/* Can only write flash options if the option control reg is unlocked */
- if (!(stm32h7_flash_getreg32(priv, STM32_FLASH_OPTCR_OFFSET) & FLASH_OPTCR_OPTLOCK))
+
+ if (!(stm32h7_flash_getreg32(priv, STM32_FLASH_OPTCR_OFFSET) &
+ FLASH_OPTCR_OPTLOCK))
{
- stm32h7_flash_modifyreg32(priv, STM32_FLASH_OPTCR_OFFSET, 0, FLASH_OPTCR_OPTSTRT);
+ stm32h7_flash_modifyreg32(priv, STM32_FLASH_OPTCR_OFFSET, 0,
+ FLASH_OPTCR_OPTSTRT);
}
/* Wait for the update to complete */
- while (stm32h7_flash_getreg32(priv, STM32_FLASH_OPTSR_CUR_OFFSET) & FLASH_OPTSR_BUSYV)
+
+ while (stm32h7_flash_getreg32(priv, STM32_FLASH_OPTSR_CUR_OFFSET) &
+ FLASH_OPTSR_BUSYV)
{
}
}
@@ -401,13 +408,13 @@ static void stm32h7_save_flashopt(FAR struct stm32h7_flash_priv_s *priv)
* Public Functions
****************************************************************************/
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_flash_unlock
*
* Description:
* Unlocks a bank
*
- *****************************************************************************/
+ ****************************************************************************/
int stm32h7_flash_unlock(size_t addr)
{
@@ -425,13 +432,13 @@ int stm32h7_flash_unlock(size_t addr)
return rv;
}
-/*****************************************************************************
+/****************************************************************************
* Name: stm32h7_flash_lock
*
* Description:
* Locks a bank
*
- *****************************************************************************/
+ ****************************************************************************/
int stm32h7_flash_lock(size_t addr)
{
@@ -506,6 +513,7 @@ uint32_t stm32h7_flash_getopt(void)
{
return stm32h7_flash_getreg32(priv, STM32_FLASH_OPTSR_CUR_OFFSET);
}
+
return 0;
}
@@ -526,7 +534,7 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set)
stm32h7_unlock_flashopt(priv);
stm32h7_flash_modifyreg32(priv, STM32_FLASH_OPTSR_PRG_OFFSET, clear, set);
stm32h7_save_flashopt(priv);
- }
+ }
}
/****************************************************************************
@@ -566,6 +574,7 @@ ssize_t up_progmem_getpage(size_t addr)
{
return -EFAULT;
}
+
return priv->stblock + ((addr - priv->base) / FLASH_SECTOR_SIZE);
}
@@ -811,6 +820,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
}
}
}
+
stm32h7_flash_modifyreg32(priv, STM32_FLASH_CR1_OFFSET, FLASH_CR_PG, 0);
stm32h7_flash_sem_unlock(priv);
return written;
diff --git a/arch/arm/src/stm32h7/stm32_flash.h b/arch/arm/src/stm32h7/stm32_flash.h
index ca2696a..abc4301 100644
--- a/arch/arm/src/stm32h7/stm32_flash.h
+++ b/arch/arm/src/stm32h7/stm32_flash.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/stm32h7/stm32_fflash.h
+ * arch/arm/src/stm32h7/stm32_flash.h
*
* Copyright (C) 2020 Gregory Nutt. All rights reserved.
* Author: Joshua Lange <jl...@2g-eng.com>
@@ -46,7 +46,7 @@
#include "hardware/stm32_flash.h"
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
diff --git a/arch/arm/src/stm32h7/stm32_iwdg.c b/arch/arm/src/stm32h7/stm32_iwdg.c
index 184592a..12d95d4 100644
--- a/arch/arm/src/stm32h7/stm32_iwdg.c
+++ b/arch/arm/src/stm32h7/stm32_iwdg.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32_iwdg.c
*
- * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016, 2020 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -58,7 +58,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Clocking *****************************************************************/
+
/* The minimum frequency of the IWDG clock is:
*
* Fmin = Flsi / 256
@@ -111,6 +113,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
+
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* well-known watchdog_lowerhalf_s structure.
@@ -130,6 +133,7 @@ struct stm32_lowerhalf_s
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
+
/* Register operations ******************************************************/
#ifdef CONFIG_STM32H7_IWDG_REGDEBUG
@@ -155,6 +159,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
/****************************************************************************
* Private Data
****************************************************************************/
+
/* "Lower half" driver methods */
static const struct watchdog_ops_s g_wdgops =
@@ -195,8 +200,8 @@ static uint16_t stm32_getreg(uint32_t addr)
uint16_t val = getreg16(addr);
- /* Is this the same value that we read from the same register last time? Are
- * we polling the register? If so, suppress some of the output.
+ /* Is this the same value that we read from the same register last time?
+ * Are we polling the register? If so, suppress some of the output.
*/
if (addr == prevaddr && val == preval)
@@ -222,7 +227,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- wdinfo("[repeats %d more times]\n", count-3);
+ wdinfo("[repeats %d more times]\n", count - 3);
}
/* Save the new address, value, and count */
@@ -268,8 +273,8 @@ static void stm32_putreg(uint16_t val, uint32_t addr)
* that can only be done one time.
*
* Input Parameters:
- * priv - A pointer the internal representation of the "lower-half"
- * driver state structure.
+ * priv - a pointer to the internal representation of the
+ * "lower-half" driver state structure.
*
****************************************************************************/
@@ -311,8 +316,8 @@ static inline void stm32_setprescaler(FAR struct stm32_lowerhalf_s *priv)
* Start the watchdog timer, resetting the time to the current timeout,
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - a pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@@ -331,10 +336,11 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
if (!priv->started)
{
- /* REVISIT: It appears that you can only setup the prescaler and reload
- * registers once. After that, the SR register's PVU and RVU bits never go
- * to zero. So we defer setting up these registers until the watchdog
- * is started, then refuse any further attempts to change timeout.
+ /* REVISIT: It appears that you can only setup the prescaler and
+ * reload registers once. After that, the SR register's PVU and RVU
+ * bits never go to zero. So we defer setting up these registers until
+ * the watchdog is started, then refuse any further attempts to change
+ * timeout.
*/
/* Set up prescaler and reload value for the selected timeout before
@@ -346,8 +352,8 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
#endif
/* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE:
- * If the "Hardware watchdog" feature is enabled through the device option
- * bits, the watchdog is automatically enabled at power-on.
+ * If the "Hardware watchdog" feature is enabled through the device
+ * option bits, the watchdog is automatically enabled at power-on.
*/
flags = enter_critical_section();
@@ -367,8 +373,8 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
* Stop the watchdog timer
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - a pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@@ -392,8 +398,8 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
* the watchdog timer or "petting the dog".
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - a pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@@ -424,8 +430,8 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* Get the current watchdog timer status
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - a pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
* status - The location to return the watchdog status information.
*
* Returned Value:
@@ -483,8 +489,8 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* Set a new timeout value (and reset the watchdog timer)
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - A pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
* Returned Value:
@@ -604,8 +610,8 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
*/
#ifndef CONFIG_STM32H7_IWDG_ONETIMESETUP
- /* If CONFIG_STM32H7_IWDG_DEFERREDSETUP is selected, then perform the register
- * configuration only if the timer has been started.
+ /* If CONFIG_STM32H7_IWDG_DEFERREDSETUP is selected, then perform the
+ * register configuration only if the timer has been started.
*/
#ifdef CONFIG_STM32H7_IWDG_DEFERREDSETUP
@@ -629,8 +635,8 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* Name: stm32_iwdginitialize
*
* Description:
- * Initialize the IWDG watchdog timer. The watchdog timer is initialized and
- * registers as 'devpath'. The initial state of the watchdog timer is
+ * Initialize the IWDG watchdog timer. The watchdog timer is initialized
+ * and registers as 'devpath'. The initial state of the watchdog timer is
* disabled.
*
* Input Parameters:
@@ -674,7 +680,8 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
* device option bits, the watchdog is automatically enabled at power-on.
*/
- stm32_settimeout((FAR struct watchdog_lowerhalf_s *)priv, CONFIG_STM32H7_IWDG_DEFTIMOUT);
+ stm32_settimeout((FAR struct watchdog_lowerhalf_s *)priv,
+ CONFIG_STM32H7_IWDG_DEFTIMOUT);
/* Register the watchdog driver as /dev/watchdog0 */
diff --git a/arch/arm/src/stm32h7/stm32_pm.h b/arch/arm/src/stm32h7/stm32_pm.h
index 5339ffe..bcbc899 100644
--- a/arch/arm/src/stm32h7/stm32_pm.h
+++ b/arch/arm/src/stm32h7/stm32_pm.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/stm32h7/stm32_pm.h
*
* Copyright (C) 2018 Haltian Ltd. All rights reserved.
@@ -31,7 +31,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_PM_H
#define __ARCH_ARM_SRC_STM32H7_STM32_PM_H
@@ -68,8 +68,8 @@ extern "C"
*
* Input Parameters:
* lpds - true: To further reduce power consumption in Stop mode, put the
- * internal voltage regulator in low-power under-drive mode using the
- * LPDS and LPUDS bits of the Power control register (PWR_CR1).
+ * internal voltage regulator in low-power under-drive mode using
+ * the LPDS and LPUDS bits of the Power control register (PWR_CR1).
*
* Returned Value:
* None
@@ -104,8 +104,8 @@ void stm32_pmstandby(void);
* sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is
* executed, the MCU enters Sleep mode as soon as it
* exits the lowest priority ISR.
- * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep mode
- * as soon as WFI or WFE instruction is executed.
+ * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep
+ * mode as soon as WFI or WFE instruction is executed.
* Returned Value:
* None
*
diff --git a/arch/arm/src/stm32h7/stm32_pminitialize.c b/arch/arm/src/stm32h7/stm32_pminitialize.c
index ffcd5d0..14914b4 100644
--- a/arch/arm/src/stm32h7/stm32_pminitialize.c
+++ b/arch/arm/src/stm32h7/stm32_pminitialize.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32_pminitialize.c
*
- * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2017, 2020 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/arm/src/stm32h7/stm32_pmsleep.c b/arch/arm/src/stm32h7/stm32_pmsleep.c
index b7c92e4..d77da01 100644
--- a/arch/arm/src/stm32h7/stm32_pmsleep.c
+++ b/arch/arm/src/stm32h7/stm32_pmsleep.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32_pmsleep.c
*
- * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2017, 2020 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gn...@nuttx.org>
* Diego Sanchez <ds...@nx-engineering.com>
*
@@ -61,8 +61,8 @@
* sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is
* executed, the MCU enters Sleep mode as soon as it
* exits the lowest priority ISR.
- * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep mode
- * as soon as WFI or WFE instruction is executed.
+ * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep
+ * mode as soon as WFI or WFE instruction is executed.
* Returned Value:
* None
*
diff --git a/arch/arm/src/stm32h7/stm32_pmstandby.c b/arch/arm/src/stm32h7/stm32_pmstandby.c
index 2486e1c..bddcfc1 100644
--- a/arch/arm/src/stm32h7/stm32_pmstandby.c
+++ b/arch/arm/src/stm32h7/stm32_pmstandby.c
@@ -80,8 +80,9 @@ void stm32_pmstandby(void)
modifyreg32(STM32_RCC_CSR, 0, RCC_RSR_RMVF);
- /* Set the domain Power Down Deep Sleep (PDDS) bits in the power control register.
- * so that D1, D2, and D3 will go into the DStop state. */
+ /* Set the domain Power Down Deep Sleep (PDDS) bits in the power control
+ * register so that D1, D2, and D3 will go into the DStop state.
+ */
modifyreg32(STM32_PWR_CPUCR, 0, STM32_PWR_CPUCR_PDDS_D1 |
STM32_PWR_CPUCR_PDDS_D2 |
diff --git a/arch/arm/src/stm32h7/stm32_pmstop.c b/arch/arm/src/stm32h7/stm32_pmstop.c
index 6159e8c..5c6f005 100644
--- a/arch/arm/src/stm32h7/stm32_pmstop.c
+++ b/arch/arm/src/stm32h7/stm32_pmstop.c
@@ -58,8 +58,8 @@
*
* Input Parameters:
* lpds - true: To further reduce power consumption in Stop mode, put the
- * internal voltage regulator in low-power under-drive mode using the
- * LPDS and LPUDS bits of the Power control register (PWR_CR1).
+ * internal voltage regulator in low-power under-drive mode using
+ * the LPDS and LPUDS bits of the Power control register (PWR_CR1).
*
* Returned Value:
* None
@@ -70,7 +70,8 @@ void stm32_pmstop(bool lpds)
{
uint32_t regval;
- /* Clear the Low Power Deep Sleep (LPDS) bit in the CPU power control register.
+ /* Clear the Low Power Deep Sleep (LPDS) bit in the CPU power control
+ * register.
*/
regval = getreg32(STM32_PWR_CR1);
@@ -94,7 +95,8 @@ void stm32_pmstop(bool lpds)
/* Clear the domain standby bits so D1, D2 and D3 remain in DStop mode */
regval = getreg32(STM32_PWR_CPUCR);
- regval &= ~(STM32_PWR_CPUCR_PDDS_D1 | STM32_PWR_CPUCR_PDDS_D2 | STM32_PWR_CPUCR_PDDS_D3);
+ regval &= ~(STM32_PWR_CPUCR_PDDS_D1 | STM32_PWR_CPUCR_PDDS_D2 |
+ STM32_PWR_CPUCR_PDDS_D3);
putreg32(regval, STM32_PWR_CPUCR);
/* Set SLEEPDEEP bit of Cortex System Control Register */
diff --git a/arch/arm/src/stm32h7/stm32_pwr.c b/arch/arm/src/stm32h7/stm32_pwr.c
index 0ae5051..e087b4f 100644
--- a/arch/arm/src/stm32h7/stm32_pwr.c
+++ b/arch/arm/src/stm32h7/stm32_pwr.c
@@ -270,12 +270,13 @@ void stm32_pwr_disablepvd(void)
* Description:
* Enables the Backup regulator, the Backup regulator (used to maintain backup
* SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup
- * regulator is switched off. The backup SRAM can still be used but its content will
- * be lost in the Standby and VBAT modes. Once set, the application must wait that
- * the Backup Regulator Ready flag (BRR) is set to indicate that the data written
- * into the RAM will be maintained in the Standby and VBAT modes.
+ * regulator is switched off. The backup SRAM can still be used but its content
+ * will be lost in the Standby and VBAT modes. Once set, the application must wait
+ * that the Backup Regulator Ready flag (BRR) is set to indicate that the data
+ * written into the RAM will be maintained in the Standby and VBAT modes.
*
- * This function needs to be called after stm32_pwr_enablebkp(true) has been called.
+ * This function needs to be called after stm32_pwr_enablebkp(true) has been
+ * called.
*
* Input Parameters:
* region - state to set it to
@@ -367,7 +368,9 @@ void stm32_pwr_configurewkup(uint32_t pin, bool en, bool rising, uint32_t pull)
{
regval |= STM32_PWR_WKUPP(pin);
}
+
/* Set to the no pull-up state by default*/
+
regval &= ~ (STM32_PWR_WKUPPUPD_MASK << STM32_PWR_WKUPPUPD_SHIFT(pin));
if (pull == GPIO_PULLUP)
@@ -394,12 +397,14 @@ void stm32_pwr_configurewkup(uint32_t pin, bool en, bool rising, uint32_t pull)
*
* Input Parameters:
* enable - Enables the charge resistor if true, disables it if false
- * resistor - Sets charge resistor to 1.5 KOhm if true, sets it to 5 KOhm if false.
+ * resistor - Sets charge resistor to 1.5 KOhm if true,
+ * sets it to 5 KOhm if false.
*
* Returned Value:
* None
*
************************************************************************************/
+
void stm32_pwr_setvbatcharge(bool enable, bool resistor)
{
irqstate_t flags;
diff --git a/arch/arm/src/stm32h7/stm32_pwr.h b/arch/arm/src/stm32h7/stm32_pwr.h
index 5b753e6..eb4d614 100644
--- a/arch/arm/src/stm32h7/stm32_pwr.h
+++ b/arch/arm/src/stm32h7/stm32_pwr.h
@@ -63,7 +63,7 @@ extern "C"
#endif
/************************************************************************************
- * Public Functions
+ * Public Function Prototypes
************************************************************************************/
/************************************************************************************
@@ -110,10 +110,13 @@ void stm32_pwr_enablebkp(bool writable);
* Description:
* Enables the Backup regulator, the Backup regulator (used to maintain backup
* SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup
- * regulator is switched off. The backup SRAM can still be used but its content will
- * be lost in the Standby and VBAT modes. Once set, the application must wait that
- * the Backup Regulator Ready flag (BRR) is set to indicate that the data written
- * into the RAM will be maintained in the Standby and VBAT modes.
+ * regulator is switched off. The backup SRAM can still be used but its content
+ * will be lost in the Standby and VBAT modes. Once set, the application must wait
+ * that the Backup Regulator Ready flag (BRR) is set to indicate that the data
+ * written into the RAM will be maintained in the Standby and VBAT modes.
+ *
+ * This function needs to be called after stm32_pwr_enablebkp(true) has been
+ * called.
*
* Input Parameters:
* region - state to set it to
@@ -158,12 +161,14 @@ void stm32_pwr_configurewkup(uint32_t pin, bool en, bool rising, uint32_t pull);
*
* Input Parameters:
* enable - Enables the charge resistor if true, disables it if false
- * resistor - Sets charge resistor to 1.5 KOhm if true, sets it to 5 KOhm if false.
+ * resistor - Sets charge resistor to 1.5 KOhm if true,
+ * sets it to 5 KOhm if false.
*
* Returned Value:
* None
*
************************************************************************************/
+
void stm32_pwr_setvbatcharge(bool enable, bool resistor);
#undef EXTERN
diff --git a/arch/arm/src/stm32h7/stm32_wdg.h b/arch/arm/src/stm32h7/stm32_wdg.h
index 06a0011..290d39f 100644
--- a/arch/arm/src/stm32h7/stm32_wdg.h
+++ b/arch/arm/src/stm32h7/stm32_wdg.h
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32_wdg.h
*
- * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2015, 2020 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -63,7 +63,7 @@ extern "C"
#endif
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
/****************************************************************************
@@ -71,7 +71,7 @@ extern "C"
*
* Description:
* Initialize the IWDG watchdog time. The watchdog timer is initialized
- * and registers as 'devpath. The initial state of the watchdog time is
+ * and registers as 'devpath'. The initial state of the watchdog time is
* disabled.
*
* Input Parameters:
@@ -92,8 +92,8 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq);
* Name: stm32_wwdginitialize
*
* Description:
- * Initialize the WWDG watchdog time. The watchdog timer is initializeed and
- * registers as 'devpath. The initial state of the watchdog time is
+ * Initialize the WWDG watchdog time. The watchdog timer is initialized
+ * and registers as 'devpath'. The initial state of the watchdog time is
* disabled.
*
* Input Parameters:
diff --git a/arch/arm/src/stm32h7/stm32_wwdg.c b/arch/arm/src/stm32h7/stm32_wwdg.c
index c0d1083..23a9101 100644
--- a/arch/arm/src/stm32h7/stm32_wwdg.c
+++ b/arch/arm/src/stm32h7/stm32_wwdg.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32_wwdg.c
*
- * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016, 2020 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -56,7 +56,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Clocking *****************************************************************/
+
/* The minimum frequency of the WWDG clock is:
*
* Fmin = PCLK1 / 4096 / 8
@@ -87,6 +89,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
+
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* well-known watchdog_lowerhalf_s structure.
@@ -106,6 +109,7 @@ struct stm32_lowerhalf_s
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
+
/* Register operations ******************************************************/
#ifdef CONFIG_STM32H7_WWDG_REGDEBUG
@@ -139,6 +143,7 @@ static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
/****************************************************************************
* Private Data
****************************************************************************/
+
/* "Lower half" driver methods */
static const struct watchdog_ops_s g_wdgops =
@@ -179,8 +184,8 @@ static uint16_t stm32_getreg(uint32_t addr)
uint16_t val = getreg16(addr);
- /* Is this the same value that we read from the same registe last time? Are
- * we polling the register? If so, suppress some of the output.
+ /* Is this the same value that we read from the same register last time?
+ * Are we polling the register? If so, suppress some of the output.
*/
if (addr == prevaddr && val == preval)
@@ -206,7 +211,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- wdinfo("[repeats %d more times]\n", count-3);
+ wdinfo("[repeats %d more times]\n", count - 3);
}
/* Save the new address, value, and count */
@@ -325,8 +330,8 @@ static int stm32_interrupt(int irq, FAR void *context, FAR void *arg)
* Start the watchdog timer, resetting the time to the current timeout,
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - A pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@@ -357,8 +362,8 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
* Stop the watchdog timer
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - A pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@@ -385,14 +390,14 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
* the watchdog timer or "petting the dog".
*
* The application program must write in the WWDG_CR register at regular
- * intervals during normal operation to prevent an MCU reset. This operation
- * must occur only when the counter value is lower than the window register
- * value. The value to be stored in the WWDG_CR register must be between
- * 0xff and 0xC0:
+ * intervals during normal operation to prevent an MCU reset. This
+ * operation must occur only when the counter value is lower than the
+ * window register value. The value to be stored in the WWDG_CR register
+ * must be between 0xff and 0xC0:
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - A pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@@ -421,8 +426,8 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* Get the current watchdog timer status
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - A pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
* status - The location to return the watchdog status information.
*
* Returned Value:
@@ -477,7 +482,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* Set a new timeout value (and reset the watchdog timer)
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the
+ * lower - A pointer to the publicly visible representation of the
* "lower-half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
@@ -516,8 +521,8 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* wdgtb is one of {1, 2, 4, or 8}
*/
- /* Select the smallest prescaler that will result in a reload field value that is
- * less than the maximum.
+ /* Select the smallest prescaler that will result in a reload field value
+ * that is less than the maximum.
*/
for (wdgtb = 0; ; wdgtb++)
@@ -530,7 +535,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
/* Get the WWDG counter frequency in Hz. */
- fwwdg = (STM32_PCLK1_FREQUENCY/4096) >> wdgtb;
+ fwwdg = (STM32_PCLK1_FREQUENCY / 4096) >> wdgtb;
/* The formula to calculate the timeout value is given by:
*
@@ -594,8 +599,8 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT;
stm32_putreg(regval, STM32_WWDG_CFR);
- /* Reset the 7-bit window value to the maximum value.. essentially disabling
- * the lower limit of the watchdog reset time.
+ /* Reset the 7-bit window value to the maximum value...essentially
+ * disabling the lower limit of the watchdog reset time.
*/
stm32_setwindow(priv, 0x7f);
@@ -611,8 +616,8 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* behavior.
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - A pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
* newhandler - The new watchdog expiration function pointer. If this
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
@@ -642,7 +647,7 @@ static xcpt_t stm32_capture(FAR struct watchdog_lowerhalf_s *lower,
/* Save the new handler */
- priv->handler = handler;
+ priv->handler = handler;
/* Are we attaching or detaching the handler? */
@@ -678,8 +683,8 @@ static xcpt_t stm32_capture(FAR struct watchdog_lowerhalf_s *lower,
* are forwarded to the lower half driver through this method.
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - A pointer to the publicly visible representation of the
+ * "lower-half" driver state structure.
* cmd - The ioctl command value
* arg - The optional argument that accompanies the 'cmd'. The
* interpretation of this argument depends on the particular
@@ -733,8 +738,8 @@ static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
* Name: stm32_wwdginitialize
*
* Description:
- * Initialize the WWDG watchdog timer. The watchdog timer is initialized and
- * registers as 'devpath'. The initial state of the watchdog timer is
+ * Initialize the WWDG watchdog timer. The watchdog timer is initialized
+ * and registers as 'devpath'. The initial state of the watchdog timer is
* disabled.
*
* Input Parameters:
diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
index 536b225..b1881e4 100644
--- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
@@ -95,7 +95,6 @@
# endif
#endif
-
/* PLL are only enabled if the P,Q or R outputs are enabled. */
#undef USE_PLL1
@@ -143,8 +142,8 @@ static inline void rcc_reset(void)
putreg32(regval, STM32_RCC_CR);
#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR)
- /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to data
- * read corruption. See ES0392 Rev 6.
+ /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to
+ * data read corruption. See ES0392 Rev 6.
*/
putreg32(AXI_TARG_READ_ISS_OVERRIDE, STM32_AXI_TARG7_FN_MOD);
@@ -767,6 +766,7 @@ static void stm32_stdclockconfig(void)
{
}
#endif
+
#if defined(USE_PLL3)
/* Wait until the PLL3 is ready */
@@ -776,15 +776,15 @@ static void stm32_stdclockconfig(void)
#endif
/* Ww must write the lower byte of the PWR_CR3 register is written once
- * after POR and it shall be written before changing VOS level or ck_sys
- * clock frequency. No limitation applies to the upper bytes.
+ * after POR and it shall be written before changing VOS level or
+ * ck_sys clock frequency. No limitation applies to the upper bytes.
*
* Programming data corresponding to an invalid combination of
* LDOEN and BYPASS bits will be ignored: data will not be written,
* the written-once mechanism will lock the register and any further
* write access will be ignored. The default supply configuration will
- * be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1)
- * will go on indicating invalid voltage levels.
+ * be kept and the ACTVOSRDY bit in PWR control status register 1
+ * (PWR_CSR1) will go on indicating invalid voltage levels.
*
* N.B. The system shall be power cycled before writing a new value.
*/
@@ -805,6 +805,7 @@ static void stm32_stdclockconfig(void)
}
/* See Reference manual Section 5.4.1, System supply startup */
+
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0)
{
}
@@ -817,7 +818,6 @@ static void stm32_stdclockconfig(void)
if ((STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) &&
STM32_SYSCLK_FREQUENCY > 400000000)
{
-
/* Enable System configuration controller clock to Enable ODEN */
regval = getreg32(STM32_RCC_APB4ENR);
@@ -840,7 +840,6 @@ static void stm32_stdclockconfig(void)
regval = FLASH_ACR_WRHIGHFREQ(BOARD_FLASH_PROGDELAY) |
FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
-
putreg32(regval, STM32_FLASH_ACR);
/* Select the PLL1P as system clock source */