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Posted to commits@mynewt.apache.org by je...@apache.org on 2020/10/23 11:20:16 UTC
[mynewt-core] branch master updated: hw/mcu/stm/stm32_common: SPI_4
and SPI_5 definitions.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
The following commit(s) were added to refs/heads/master by this push:
new 093eaec hw/mcu/stm/stm32_common: SPI_4 and SPI_5 definitions.
093eaec is described below
commit 093eaec50c33e22568f8208e914432ffe26f2291
Author: Rafa Couto <ca...@treboada.net>
AuthorDate: Mon Oct 5 02:46:45 2020 +0200
hw/mcu/stm/stm32_common: SPI_4 and SPI_5 definitions.
Missing SPI definitions on STM32 common drivers. HAL is ready to
use SPI_4 and SPI_5 but they are not expanded from application.
---
hw/mcu/stm/stm32_common/syscfg.yml | 64 ++++++++++++++++++++++++++++++++++++--
1 file changed, 61 insertions(+), 3 deletions(-)
diff --git a/hw/mcu/stm/stm32_common/syscfg.yml b/hw/mcu/stm/stm32_common/syscfg.yml
index f7fd2cb..abb641e 100644
--- a/hw/mcu/stm/stm32_common/syscfg.yml
+++ b/hw/mcu/stm/stm32_common/syscfg.yml
@@ -283,17 +283,17 @@ syscfg.defs:
value: ''
SPI_3_MASTER:
- description: 'SPI 2 master'
+ description: 'SPI 3 master'
value: 0
restrictions:
- "!SPI_3_SLAVE"
SPI_3_SLAVE:
- description: 'SPI 2 slave'
+ description: 'SPI 3 slave'
value: 0
restrictions:
- "!SPI_3_MASTER"
SPI_3:
- description: 'SPI 2 enabled'
+ description: 'SPI 3 enabled'
value: 'MYNEWT_VAL_SPI_3_MASTER || MYNEWT_VAL_SPI_3_SLAVE'
SPI_3_CUSTOM_CFG:
description: 'Allow SPI_3 configuration override'
@@ -311,6 +311,64 @@ syscfg.defs:
description: 'SS pin for SPI_3'
value: ''
+ SPI_4_MASTER:
+ description: 'SPI 4 master'
+ value: 0
+ restrictions:
+ - "!SPI_4_SLAVE"
+ SPI_4_SLAVE:
+ description: 'SPI 4 slave'
+ value: 0
+ restrictions:
+ - "!SPI_4_MASTER"
+ SPI_4:
+ description: 'SPI 4 enabled'
+ value: 'MYNEWT_VAL_SPI_4_MASTER || MYNEWT_VAL_SPI_4_SLAVE'
+ SPI_4_CUSTOM_CFG:
+ description: 'Allow SPI_4 configuration override'
+ value: 0
+ SPI_4_PIN_SCK:
+ description: 'SCK pin for SPI_4'
+ value: ''
+ SPI_4_PIN_MOSI:
+ description: 'MOSI pin for SPI_4'
+ value: ''
+ SPI_4_PIN_MISO:
+ description: 'MISO pin for SPI_4'
+ value: ''
+ SPI_4_PIN_SS:
+ description: 'SS pin for SPI_4'
+ value: ''
+
+ SPI_5_MASTER:
+ description: 'SPI 5 master'
+ value: 0
+ restrictions:
+ - "!SPI_5_SLAVE"
+ SPI_5_SLAVE:
+ description: 'SPI 5 slave'
+ value: 0
+ restrictions:
+ - "!SPI_5_MASTER"
+ SPI_5:
+ description: 'SPI 5 enabled'
+ value: 'MYNEWT_VAL_SPI_5_MASTER || MYNEWT_VAL_SPI_5_SLAVE'
+ SPI_5_CUSTOM_CFG:
+ description: 'Allow SPI_5 configuration override'
+ value: 0
+ SPI_5_PIN_SCK:
+ description: 'SCK pin for SPI_5'
+ value: ''
+ SPI_5_PIN_MOSI:
+ description: 'MOSI pin for SPI_5'
+ value: ''
+ SPI_5_PIN_MISO:
+ description: 'MISO pin for SPI_5'
+ value: ''
+ SPI_5_PIN_SS:
+ description: 'SS pin for SPI_5'
+ value: ''
+
I2C_0:
description: 'I2C (TWI) interface 0'
value: 0