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Posted to commits@mynewt.apache.org by je...@apache.org on 2021/02/18 11:57:04 UTC

[mynewt-core] 01/02: hw/mcu/dialog: Synchronize DCDC handling between cores

This is an automated email from the ASF dual-hosted git repository.

jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git

commit 5dce508a1f60f233a3c97b838543814b76da96a2
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Tue Feb 16 16:08:31 2021 +0100

    hw/mcu/dialog: Synchronize DCDC handling between cores
    
    When DCDC is turned off by M33 set shared memory accordingly
    so DCDC is not turned on by CMAC.
---
 hw/mcu/dialog/da1469x/src/da1469x_prail.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/hw/mcu/dialog/da1469x/src/da1469x_prail.c b/hw/mcu/dialog/da1469x/src/da1469x_prail.c
index 319bb7a..0ea9d1b 100644
--- a/hw/mcu/dialog/da1469x/src/da1469x_prail.c
+++ b/hw/mcu/dialog/da1469x/src/da1469x_prail.c
@@ -24,6 +24,9 @@
 #include "mcu/da1469x_hal.h"
 #include "mcu/da1469x_prail.h"
 #include "mcu/da1469x_retreg.h"
+#if MYNEWT_VAL_CHOICE(BLE_HCI_TRANSPORT, dialog_cmac)
+#include "cmac_driver/cmac_shared.h"
+#endif
 #include "os/util.h"
 
 #define POWER_CTRL_REG_SET(_field, _val)                                        \
@@ -176,6 +179,10 @@ da1469x_prail_dcdc_restore(void)
     if (CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Msk) {
         da1469x_retreg_restore(g_mcu_dcdc_config, ARRAY_SIZE(g_mcu_dcdc_config));
         DCDC->DCDC_CTRL1_REG |= DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk;
+#if MYNEWT_VAL_CHOICE(BLE_HCI_TRANSPORT, dialog_cmac)
+        /* Enable turning DCDC on from CMAC core. */
+        g_cmac_shared_data->dcdc.enabled = 1;
+#endif
     }
 }
 #endif
@@ -183,6 +190,10 @@ da1469x_prail_dcdc_restore(void)
 void
 da1469x_prail_dcdc_disable(void)
 {
+#if MYNEWT_VAL_CHOICE(BLE_HCI_TRANSPORT, dialog_cmac)
+    /* Prevent CMAC from turning DCDC on. */
+    g_cmac_shared_data->dcdc.enabled = 0;
+#endif
     DCDC->DCDC_CTRL1_REG &= ~DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk;
 }