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Posted to commits@nuttx.apache.org by xi...@apache.org on 2026/10/15 11:42:01 UTC
(nuttx) 02/02: Documentation/rm57: Update the RM57 and LAUNCHXL2-RM57L pages
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commit 3ffd832cf23b8679b979fb2f620e60d3cfd0766c
Author: Mahmut Sami ÖZMEN <ma...@gmail.com>
AuthorDate: Thu Oct 15 01:01:19 2026 +0300
Documentation/rm57: Update the RM57 and LAUNCHXL2-RM57L pages
The RM57 pages were written during the first bring-up and no longer
matched the code. They listed MibSPI, I2C, ESM and PBIST/STC as missing,
said buttons were not supported, gave the alternate MII balls instead of
the ones the board uses, and did not mention half of the board
configurations.
Chip page:
- Add Core, ESM, self test, GIO interrupts, MibSPI and I2C to the
peripheral table, and say for each row how it was tested (on
hardware, loopback only, or build only).
- Leave only peripherals that are really not implemented in the todo.
- Add short Safety diagnostics, MibSPI and I2C sections.
- EMAC: the board is MII only; add the measured iperf throughput
(19.4Mbit/s TX, 9.2Mbit/s RX) and the DHCP retry note.
- Fix the AD1EVT note: the board takes MII_RX_ER from U5, not N19.
Board page:
- Document the buttons and the LED polarity.
- Pin table: use the dedicated MII balls from the schematic, and add the
PHY clock and control lines, MibSPI1/3 and I2C1/2.
- Add the buttons, can, candma, cansock, ethnsh, spi, spitest and i2c
configurations, plus the SCI3 loopback in scidma.
- Explain the 38400 baud console in ethnsh, and add the errata GCM#60
debugger hint.
Checked with docutils: no errors apart from the Sphinx-only directives.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Mahmut Sami ÖZMEN <ma...@gmail.com>
---
.../arm/rm57/boards/rm57l843-launchxl2/index.rst | 190 +++++++++++++++++----
Documentation/platforms/arm/rm57/index.rst | 142 ++++++++++++---
2 files changed, 270 insertions(+), 62 deletions(-)
diff --git a/Documentation/platforms/arm/rm57/boards/rm57l843-launchxl2/index.rst b/Documentation/platforms/arm/rm57/boards/rm57l843-launchxl2/index.rst
index 9e41b929867..61d907c2ef4 100644
--- a/Documentation/platforms/arm/rm57/boards/rm57l843-launchxl2/index.rst
+++ b/Documentation/platforms/arm/rm57/boards/rm57l843-launchxl2/index.rst
@@ -12,16 +12,14 @@ than any particular application.
.. warning::
- This board port is new and experimental. The serial console (SCI1),
- the two user LEDs, the DMA controller, DCAN, and EMAC/MDIO (Ethernet)
- are currently supported; button support and most other on-chip
- peripherals are not yet implemented. Some of the values documented
- below (PLL/clock configuration, LED polarity, JTAG IDCODE, and for
- Ethernet the exact PHY ball assignments and RMII clock source) were
- taken from TI's HALCoGen-generated reference project or from the
- RM57L843 datasheet rather than confirmed against this specific
- board's schematic — see the comments in
- ``boards/arm/rm57/rm57l843-launchxl2/include/board.h`` for details.
+ This board port is new. The console, LEDs, buttons, serial DMA,
+ Ethernet, ADC, temperature sensors and start-up diagnostics are tested
+ on this board. DCAN, MibSPI and I2C are only tested in their internal
+ loopback modes, because the LaunchPad has no CAN transceiver and no
+ SPI or I2C device. Pin assignments were checked against the board
+ schematic (SPRR397). The PLL values come from TI's HALCoGen project,
+ and the CAN bit timing and the I2C transfer times measured on the
+ board confirm them.
Features
========
@@ -31,7 +29,10 @@ Features
PLL/GCLK) in the current clock configuration
* 4 MB of on-chip program flash, 512 KB of on-chip SRAM
* Onboard XDS110 debug probe (JTAG)
-* 2 user LEDs
+* 2 user LEDs and 2 user buttons
+* 10/100 Ethernet (DP83630 PHY, MII)
+* MibSPI1 and MibSPI3 on the BoosterPack headers; I2C1 and I2C2 on the
+ BoosterPack and proto headers (no pull-up resistors on the board)
* SCI1 wired up as the serial console; SCI2-SCI4 are supported by the
driver but not enabled by this board's default configuration (and
SCI2-SCI4 pin-mux is not programmed by this board port - see the
@@ -46,10 +47,9 @@ Features
.. note::
- Peripherals that are part of the RM57L843 chip itself (N2HET, MibSPI,
- I2C, the ESM diagnostic module, PBIST/STC self-test, etc.) but are
- not yet wired up by this board port are tracked on the
- :doc:`RM57 chip documentation page </platforms/arm/rm57/index>`.
+ The :doc:`RM57 chip documentation page </platforms/arm/rm57/index>`
+ lists the chip peripherals that are not implemented yet (N2HET, ePWM,
+ eCAP, eQEP and others).
Buttons and LEDs
================
@@ -58,12 +58,19 @@ LEDs
----
The LAUNCHXL2-RM57L has two user LEDs, labeled **B6** and **B7** on the
-board silkscreen, driven by GIOB[6] and GIOB[7] respectively.
+board silkscreen, driven by GIOB[6] and GIOB[7] respectively. They are
+active high. With ``CONFIG_ARCH_LEDS`` NuttX uses them to show the OS
+state; otherwise they are available through ``CONFIG_USERLED``.
Buttons
-------
-Button support is not yet implemented by this board port.
+The two user buttons, **B4** and **B5**, are on GIOB[4] and GIOB[5]. They
+are active low and use the internal pull-up. They are supported through
+``board_buttons()``, and with ``CONFIG_ARCH_IRQBUTTONS`` and
+``CONFIG_RM57_GIO_IRQ`` through ``board_button_irq()`` with an interrupt
+on both edges. The ``buttons`` configuration has a small demo: holding
+B4 lights LED B6, and holding B5 lights LED B7.
Pin Mapping
===========
@@ -95,18 +102,42 @@ Only the pins used by the currently supported peripherals are listed.
* - F1
- GIOB[7]
- User LED B7
- * - V5 / G3
- - MDIO_CLK / MDIO_D
- - MDIO bus shared by the EMAC's PHY (DP83630, address 1)
- * - D19 / E18 / R2 / J19 / J18
- - MII_TX_CLK / MII_TXD[3:0]
- - EMAC transmit, MII mode
- * - H19 / F3 / B4
- - MII_TXEN / MII_COL / MII_CRS
- - EMAC transmit control, MII mode
- * - K19 / H18 / G19 / A14 / P1 / B11 / N19
- - MII_RXCLK / MII_RXD[3:0] / MII_RX_DV / MII_RX_ER
- - EMAC receive, MII mode
+ * - (n/a)
+ - GIOB[4] / GIOB[5]
+ - User buttons B4 / B5, active low
+ * - T9 / F4
+ - MDCLK / MDIO
+ - MDIO bus to the DP83630 PHY (address 1)
+ * - U7 / U8 / R1 / T2 / G4 / E4
+ - MII_TX_CLK / MII_TXD[0:3] / MII_TXEN
+ - EMAC transmit
+ * - T4 / U4 / T3 / U3 / V3 / U6 / U5
+ - MII_RXCLK / MII_RXD[0:3] / MII_RX_DV / MII_RX_ER
+ - EMAC receive
+ * - W4 / V4
+ - MII_COL / MII_CRS
+ - EMAC collision and carrier sense
+ * - A12
+ - ECLK1
+ - 25MHz reference clock for the PHY (the PHY has no crystal)
+ * - E1 / A6
+ - GIOA[3] / GIOA[4]
+ - PHY power-down and reset, driven at bring-up
+ * - J5.7 / J6.6 / J6.7
+ - MIBSPI1CLK / SIMO / SOMI
+ - MibSPI1, BoosterPack site 2. Chip selects nCS[0:2] on J6.3, J6.8,
+ J6.9
+ * - J1.7 / J2.6 / J2.7
+ - MIBSPI3CLK / SIMO / SOMI
+ - MibSPI3, BoosterPack site 1. Chip selects nCS[0:3] on J5.5, J2.3,
+ J2.8, J2.9 (nCS[2:3] only when I2C1 is disabled)
+ * - B2 / C3
+ - I2C1 SDA / SCL
+ - J2.8 / J2.9, taken from MibSPI3 nCS[2:3] when ``CONFIG_RM57_I2C1``
+ is enabled
+ * - G17 / G16
+ - I2C2 SDA / SCL
+ - Proto header J10.9 / J10.8
* - T19
- AD1IN[6]
- On-board 1k trim potentiometer U10 (wiper, with 4700pF to GND);
@@ -126,12 +157,11 @@ Only the pins used by the currently supported peripherals are listed.
.. note::
- The EMAC/MDIO ball assignments above are this port's default choice
- among two alternate-ball options the RM57L843 offers for nearly every
- MII signal (see the ``BOARD_PINMUX_EMAC`` comment in ``board.h``) and
- are **not** independently confirmed against the LAUNCHXL2-RM57L
- schematic. RMII mode uses a smaller subset of these balls (see
- ``board.h``) plus K19 as the RMII 50MHz reference clock input.
+ Most MII signals can also be routed to an alternate ball. This board
+ connects the PHY to the dedicated balls listed above, which are the
+ reset defaults; the alternates go to the BoosterPack headers (see
+ the ``BOARD_PINMUX_EMAC`` comment in ``board.h``). The PHY is strapped
+ for MII, so RMII cannot be used on this board.
.. note::
@@ -150,6 +180,11 @@ SCI1 is used as the serial console. The default configuration is:
* 9600 baud, 8 data bits, no parity, 2 stop bits
+The console goes over the XDS110's USB serial port. ``ethnsh`` uses
+38400 baud, because a slow console makes network warnings costly. Rates
+above 38400 are not recommended: the baud divider has no fractional
+part, so 115200 is off by 1.7%.
+
The baud rate and stop bits are configurable via ``CONFIG_SCI1_BAUD`` and
``CONFIG_SCI1_2STOP``.
@@ -180,13 +215,30 @@ usable here). OpenOCD can be used with a Cortex-R5 (``cortex_r4`` driver)
target configuration that routes through the ICEpick-C, followed by GDB
to load and debug the image.
+On Rev B silicon, errata GCM#60 (SPNZ233B) can leave VCLK at the wrong
+rate after an external reset, and the debugger causes one each time it
+connects. If something works after a power cycle but not under the
+debugger (Ethernet is the most likely), suspect this first.
+
Configurations
==============
nsh
---
-Basic NuttShell configuration (console enabled on SCI1, at 9600 baud).
+Basic NuttShell configuration (console enabled on SCI1, at 9600 baud),
+with ``ostest``::
+
+ nsh> ostest
+
+buttons
+-------
+
+``nsh`` with ``CONFIG_ARCH_BUTTONS``, ``CONFIG_ARCH_IRQBUTTONS`` and
+``CONFIG_RM57_GIO_IRQ``, and with ``CONFIG_ARCH_LEDS`` disabled so that
+the board code controls the LEDs. While B4 is held, LED B6 is lit, and while B5 is
+held, LED B7 is lit. The LEDs are switched from the GIO interrupt
+handler, so this checks the whole GIO interrupt path.
scitest
-------
@@ -226,6 +278,30 @@ console input from stalling behind that threshold, RTI compare 1 calls
console and the test ports therefore behave the same as in ``scitest``,
only with the transfers themselves done by DMA.
+SCI3 is also put in internal loopback (``CONFIG_RM57_SCI3_LOOPBACK``),
+so ``/dev/ttyS1`` receives what it sends without any wiring. This is how
+the DMA receive path was tested on the board.
+
+can, candma, cansock
+--------------------
+
+NuttShell with DCAN1 in loopback test mode (``CONFIG_RM57_DCAN_LOOPBACK``),
+so the controller receives its own frames while still driving the TX
+ball (A10) for a logic analyzer. No transceiver or bus is needed.
+
+* ``can``: character driver ``/dev/can0`` with the ``can`` example::
+
+ nsh> can -n 8
+
+* ``candma``: the same, with the IF3 DMA receive path
+ (``CONFIG_RM57_DCAN1_RX_IF3DMA``, experimental).
+* ``cansock``: SocketCAN interface ``can0`` with ``candump`` and
+ ``cansend``::
+
+ nsh> ifup can0
+ nsh> candump can0 &
+ nsh> cansend can0 123#DEADBEEF
+
eth
---
@@ -242,7 +318,22 @@ page), NSH's automatic network initialization
If the network doesn't come up automatically, check ``ifconfig eth0``
for the assigned address and bring the link up manually with
-``ifup eth0`` / ``ifdown eth0``.
+``ifup eth0`` / ``ifdown eth0``. Some routers ignore the first DHCP
+requests after the link comes up, so ``CONFIG_NETUTILS_DHCPC_RETRIES``
+is set to 10.
+
+ethnsh
+------
+
+``eth`` plus a telnet server for NSH, ``iperf`` and a small web server,
+with the console at 38400 baud. From a PC on the same network::
+
+ $ telnet <board-ip>
+ $ iperf -c <board-ip> # board receives: nsh> iperf -s
+ $ iperf -s # board transmits: nsh> iperf -c <pc-ip>
+
+The best results measured on the board are 19.4Mbit/s transmit and
+9.2Mbit/s receive.
adc
---
@@ -363,6 +454,31 @@ other direction.
``sensortest`` - it opens ``O_NONBLOCK`` - works. Use it, or open the node
non-blocking yourself.
+spi, spitest
+------------
+
+NuttShell with MibSPI1 (compatibility mode with DMA) and MibSPI3
+(multi-buffer mode), registered as ``/dev/spi1`` and ``/dev/spi3``, and
+the ``spi`` tool. ``spitest`` also enables ``CONFIG_RM57_MIBSPI_LOOPBACK``,
+which runs a loopback test on both buses at boot and prints one ``ok`` or
+error line per pattern. To try a real exchange, connect SIMO to SOMI
+(J6.6 to J6.7 for MibSPI1) and run::
+
+ nsh> spi exch -b 1 -x 4 deadbeef
+
+i2c
+---
+
+NuttShell with I2C1 and I2C2, registered as ``/dev/i2c1`` and
+``/dev/i2c2``, and the ``i2c`` tool. ``CONFIG_RM57_I2C_LOOPBACK`` runs the
+digital loopback test on both buses at 100kHz and 400kHz at boot. Each
+bus ends with ``I2Cn: loopback self-test passed (0 failed)``. Enabling
+I2C1 takes
+MibSPI3 nCS[2:3] away. Real devices need external pull-up resistors::
+
+ nsh> i2c bus
+ nsh> i2c dev -b 2 0x03 0x77
+
selftest
--------
diff --git a/Documentation/platforms/arm/rm57/index.rst b/Documentation/platforms/arm/rm57/index.rst
index 70c577aa236..c5e24a6a76f 100644
--- a/Documentation/platforms/arm/rm57/index.rst
+++ b/Documentation/platforms/arm/rm57/index.rst
@@ -11,14 +11,12 @@ NuttX currently supports the **RM57L843** part.
.. warning::
- Support for this chip family is new and experimental. Only the
- SCI/LIN (serial), DMA, GIO (LED), DCAN, and EMAC/MDIO (Ethernet)
- peripherals have been brought up so far; the PLL/clock configuration
- values, JTAG IDCODE, LED polarity, and (for Ethernet) the exact PHY
- pin assignments and RMII clock source have not all been independently
- confirmed against hardware/schematics. See the
- :doc:`board documentation <boards/rm57l843-launchxl2/index>` for
- details.
+ Support for this chip family is new and has been tested on a single
+ LAUNCHXL2-RM57L (RM57L843 Rev B). The table below says how far each
+ peripheral was tested. Where it says *loopback only*, the
+ peripheral's internal loopback mode was used: the driver logic is
+ tested, but nothing at the pins (signal timing, a real device, a real
+ bus) has been checked.
Peripheral Support
==================
@@ -28,11 +26,22 @@ The following list indicates RM57 peripherals currently supported in NuttX:
============== =====
Peripheral Notes
============== =====
+Core Lockstep-safe start-up, PLL (300MHz GCLK, 150MHz HCLK,
+ 75MHz VCLK), SRAM ECC, MPU, VIM interrupt controller and
+ RTI system tick. Tested on hardware with ``ostest``.
+ESM Error Signalling Module. With
+ ``CONFIG_ARMV7R_DECODEFIQ`` a FIQ handler reports and
+ clears group 1/2 errors (``CONFIG_RM57_ESM_PANIC`` panics
+ instead). Tested on hardware. See `Safety diagnostics`_.
+Self test Optional start-up diagnostics (``CONFIG_RM57_SELFTEST``):
+ PBIST, STC/LBIST, CCM-R5F, eFuse, L2RAMW. Tested on
+ hardware, including fault injection.
SCI SCI1-SCI4. SCI1/LIN1 and SCI2/LIN2 are dual-role SCI/LIN
modules; the serial driver always runs them in SCI
compatibility mode (GCR1 LIN_MODE=0). Interrupt-driven by
default; optional RX/TX DMA (see `Serial DMA`_ below).
- Used for the console.
+ Used for the console. Tested on hardware: console with and
+ without DMA, SCI3 in internal loopback with DMA.
LIN Configuration and polled-transfer scaffold only
(``CONFIG_RM57_LIN``, requires ``CONFIG_EXPERIMENTAL``) -
not a complete LIN protocol stack. See
@@ -45,8 +54,16 @@ DCAN All four DCAN (Bosch D_CAN, CAN 2.0A/B) controllers
(``CONFIG_RM57_DCANn``). Per instance either a character
device (``/dev/can<n>``) or a SocketCAN network interface
(``can<n>``); both frontends can coexist in one image on
- different instances. See `DCAN`_ below.
-GIO General purpose I/O, used for LEDs
+ different instances. See `DCAN`_ below. Loopback only (the
+ board has no CAN transceiver).
+GIO General purpose I/O with pin interrupts
+ (``CONFIG_RM57_GIO_IRQ``). Used for the LEDs and buttons.
+ Tested on hardware.
+MibSPI SPI master on all five MibSPI modules
+ (``CONFIG_RM57_MIBSPIn``). See `MibSPI`_ below. Loopback
+ only.
+I2C I2C1 and I2C2 master (``CONFIG_RM57_I2Cn``). See `I2C`_
+ below. Loopback only.
ADC Both MibADC modules (``CONFIG_RM57_ADC1`` /
``CONFIG_RM57_ADC2``), 10- or 12-bit. Each of a module's
three conversion groups is registered as its own
@@ -55,17 +72,81 @@ ADC Both MibADC modules (``CONFIG_RM57_ADC1`` /
enhanced channel selection mode are all supported, along with
the three on-die temperature sensors
(``CONFIG_RM57_ADC_TEMPSENSOR``). See `ADC (MibADC)`_ below.
+ Conversions and temperature sensors tested on hardware;
+ DMA, self test and magnitude compare are build-tested only.
EMAC 10/100 Ethernet MAC + EMAC Control module + MDIO
(``CONFIG_RM57_EMAC``). Single netdev interface (``eth0``),
MII or RMII (``RM57_EMAC_MII`` / ``RM57_EMAC_RMII``). See
- `EMAC/MDIO (Ethernet)`_ below.
+ `EMAC/MDIO (Ethernet)`_ below. MII tested on hardware.
============== =====
.. todo::
- Many peripherals available on the RM57L843 (N2HET, MibSPI, I2C,
- the ESM diagnostic module, PBIST/STC self-test, etc.) are not yet
- implemented. Contributions are welcome.
+ Not implemented yet: N2HET, ePWM, eCAP, eQEP, EMIF, the CRC module,
+ the RTI digital watchdog and flash programming. Contributions are
+ welcome.
+
+Safety diagnostics
+==================
+
+``CONFIG_RM57_SELFTEST`` runs the start-up diagnostics before the OS
+starts: an ESM group 3 check, the PBIST ROM tests (with the errata
+PBIST#4 workaround), the STC self-check and CPU logic BIST, the four
+CCM-R5F diagnostics in all three modes, the eFuse controller tests
+(power-on reset only), and the L2RAMW ECC and address decode tests. The
+result of each test is printed on the console. A failing test drives
+nERROR, and with ``CONFIG_RM57_SELFTEST_HALT_ON_FAIL`` stops the boot.
+
+The CCM-R5F is off while a debugger is attached, so the ROM tests, the
+STC and the CCM diagnostics report ``skipped`` in a debug session. The
+``CONFIG_RM57_SELFTEST_INJECT_*`` options inject one fault per build to
+check that the detection path works. All five injected faults were
+detected on the board. The ``selftest`` board configuration shows the
+console output.
+
+At run time, VIM channel 0 (the ESM high-level interrupt) is hard-wired
+to FIQ. With ``CONFIG_ARMV7R_DECODEFIQ`` the ESM handler decodes,
+reports and clears each pending channel. Without that option the FIQ
+vector does nothing, and a latched nonmaskable group 2 error is never
+acknowledged.
+
+MibSPI
+======
+
+All five MibSPI modules work as SPI masters through the standard
+``spi_dev_s`` interface. Each module can be set up in one of three ways:
+
+- compatibility mode with polled transfers (default);
+- compatibility mode with DMA (``CONFIG_RM57_MIBSPIn_DMA``);
+- multi-buffer mode using transfer group 0
+ (``CONFIG_RM57_MIBSPIn_MULTIBUF``).
+
+Chip selects are driven as GIO. On this board only MibSPI1 and MibSPI3
+are routed to headers, and they are registered as ``/dev/spi1`` and
+``/dev/spi3``.
+
+``CONFIG_RM57_MIBSPI_LOOPBACK`` adds a start-up test. It uses
+``SPIGCR1.LOOPBACK`` and sends patterns of 1 to 1000 words, 8 and 16 bits
+wide, at 1MHz and 37.5MHz, then reads them back. Every mode passes this
+test on both modules. Internal loopback cannot show the clock polarity
+and phase at the pins, so the CPOL/CPHA mapping and the real SPICLK rate
+are not measured yet.
+
+I2C
+===
+
+I2C1 and I2C2 work as interrupt-driven masters through ``i2c_master_s``
+(standard and fast mode, repeated START, ``I2C_M_NOSTART``,
+``CONFIG_I2C_RESET``). Slave mode and DMA are not supported. The
+LAUNCHXL2-RM57L has no I2C pull-up resistors, so a real bus needs
+external ones (2.2k to 4.7k).
+
+``CONFIG_RM57_I2C_LOOPBACK`` adds a start-up test that uses digital
+loopback (``MDR.DLB``) on each bus at 100kHz and 400kHz. On the board,
+all tests pass, and a timed 2048-byte write takes 101% of the nominal
+time. Digital loopback only works for master transmit, so master
+receive, real ACK/NACK handling and the SCL timing at the pin are not
+measured yet.
DCAN
====
@@ -109,7 +190,10 @@ at CMOS levels, so a real bus needs an external transceiver, while the
loopback test mode still drives the TX ball for logic-analyzer capture.
The board configurations ``can`` (character driver,
loopback self-test), ``cansock`` (SocketCAN with candump/cansend) and
-``candma`` (IF3 DMA receive path) are provided.
+``candma`` (IF3 DMA receive path) are provided. In loopback on the board,
+``can -n 8`` receives all 8 frames, and the bit timing the driver
+computes is the same as HALCoGen's. A real bus (ACK from another node,
+arbitration, bus-off recovery) has not been tested.
Serial DMA
==========
@@ -214,8 +298,9 @@ or two GIOB pins. The Event group has no such choice: it is always started
by its trigger source, so only the source and its edge are configurable.
When the ADxEVT pin is not used as a trigger it can serve as a general
-purpose I/O through the ``ANIOC_RM57_EVTPIN`` ioctl. Note that AD1EVT shares
-ball N19 with the Ethernet MII_RX_ER signal, so it is unavailable when
+purpose I/O through the ``ANIOC_RM57_EVTPIN`` ioctl. AD1EVT is on ball N19,
+which can also carry MII_RX_ER. The LAUNCHXL2-RM57L takes MII_RX_ER from its
+dedicated ball U5 instead, so AD1EVT is still available when
``CONFIG_RM57_EMAC`` is enabled.
Result transfer
@@ -369,14 +454,13 @@ channel that halted between the driver reading its tail and appending a
new descriptor.
``CONFIG_RM57_EMAC_MII`` / ``CONFIG_RM57_EMAC_RMII`` select the PHY
-interface mode; the LAUNCHXL2-RM57L's DP83630 PHY is wired for MII, while
-the IOMM reset default is RMII, so MII must be explicitly selected to
-match that board. The EMAC's internal logic clock (``VCLKA4_DIVR_EMAC``)
+interface mode. The IOMM reset default is RMII, but the LAUNCHXL2-RM57L's
+DP83630 PHY is strapped for MII with no way to change it, so that board
+must select MII. The EMAC's internal logic clock (``VCLKA4_DIVR_EMAC``)
must be exactly 25MHz for MII or 50MHz for RMII (SPNS215 Section 6.6.3);
-see the ``BOARD_VCLKA4_*`` comment in the board's ``board.h`` for how
-each mode's clock is derived and the caveat on the RMII (PLL2-sourced)
-path, which this port has not independently verified against real
-hardware.
+see the ``BOARD_VCLKA4_*`` comment in the board's ``board.h``. Only MII
+has been tested on hardware. The RMII path (clocked from PLL2) builds,
+but no board available to this port wires RMII.
The MDIO module addresses up to 32 PHYs (``CONFIG_RM57_EMAC_PHYADDR``,
default 1) over a single-transaction register interface
@@ -414,6 +498,14 @@ board bring-up; without ``CONFIG_NETDEV_LATEINIT`` the interface
self-registers via ``arm_netinitialize()`` with a fixed placeholder
address (``02:00:00:00:00:01``) instead.
+Tested on the LAUNCHXL2-RM57L at 100Mbit/s full duplex: DHCP, ping (RTT
+2-7ms through a home router), DNS, NSH over telnet and HTTP all work.
+With ``iperf`` the best measured TCP throughput is 19.4Mbit/s for
+transmit (board as client) and 9.2Mbit/s for receive (board as server).
+After a 10MB transfer, every EMAC error counter reads zero. On some boots
+the DHCP server does not answer the first DISCOVERs, so the ``eth``
+configuration raises ``CONFIG_NETUTILS_DHCPC_RETRIES`` to 10.
+
Supported Boards
=================