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Posted to commits@tvm.apache.org by GitBox <gi...@apache.org> on 2021/11/05 16:42:04 UTC
[GitHub] [tvm] adstraw commented on a change in pull request #9390: Add back-to-back conv2d Hexagon test for stripe scheduling
adstraw commented on a change in pull request #9390:
URL: https://github.com/apache/tvm/pull/9390#discussion_r743819086
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File path: tests/python/contrib/test_hexagon/test_conv2d_conv2d.py
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@@ -0,0 +1,340 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+import sys
+
+import tvm
+from tvm import te
+from tvm import topi
+from tvm.topi import testing
+
+from .infrastructure import (
+ ceildiv,
+ build_and_run,
+ get_block_shape,
+ get_conv2d_nhwc_shape,
+ get_filter_block_shape,
+ get_packed_filter_layout,
+ get_packed_activation_layout,
+ verify_conv2d,
+)
+
+import numpy as np
+import pytest
+
+
+def conv2dconv2d(
+ shape_input,
+ pad1,
+ stride1,
+ dilation1,
+ shape_filter1,
+ pad2,
+ stride2,
+ dilation2,
+ shape_filter2,
+ k_split_factor,
+ h_split_factor,
+ dtype,
+ storage_scope="global",
+):
+ """
+ Conv2d -> Conv2d wherein the input activation is defined by its
+ logical NHWC layout. The filter is provided in its physical
+ packed layout (oihw8i32o4i). The input is padded and then packed
+ into its physical packed layout (nhwc8h8w32c). The resulting
+ computation is in the same physical packed layout (nhwc8h8w32c).
+ """
+
+ # nhwc layout
+ X = te.placeholder(shape_input, dtype=dtype)
+
+ # oihw8i32o4i layout
+ filt_packed1 = te.placeholder(shape_filter1, dtype=dtype)
+ filt_packed2 = te.placeholder(shape_filter2, dtype=dtype)
+
+ # calculate kernel size and output channels
+ # given oihw8i32o4i filter layout
+ kernel_size1 = tuple(shape_filter1[2:4])
+ out_channels1 = shape_filter1[0] * shape_filter1[5]
+
+ # get the the logical output shape of conv2d #1
+ logical_output_shape1 = get_conv2d_nhwc_shape(
+ shape_input,
+ kernel_size1,
+ stride1,
+ pad1,
+ dilation1,
+ out_channels1,
+ )
+
+ block_shape = get_block_shape()
+ block_H, block_W, block_C = block_shape
+
+ # Calculate padded input
+ N, H, W, C = shape_input
+ pad_h = (block_H - ((H + pad1[1]) % block_H)) % block_H
+ pad_w = (block_W - ((W + pad1[3]) % block_W)) % block_W
+ X_pad = topi.nn.pad(
+ X, [0, pad1[0], pad1[2], 0], [0, pad_h, pad_w, 0], pad_value=0, name="padded_input"
+ )
+
+ # Calculate packed input
+ packed_shape = get_packed_activation_layout(X_pad.shape, block_shape)
+ X_packed = te.compute(
+ packed_shape,
+ lambda n, ho, wo, co, hi, wi, ci: X_pad[
+ n, ho * block_H + hi, wo * block_W + wi, co * block_C + ci
+ ],
+ name="packed_input",
+ )
+
+ filter_Cio, filter_Ki, filter_Cii = get_filter_block_shape()
+ filter_Ci = filter_Cio * filter_Cii
+
+ rh = te.reduce_axis((0, kernel_size1[0]), name="rh")
+ rw = te.reduce_axis((0, kernel_size1[1]), name="rw")
+ rc = te.reduce_axis((0, C), name="rc")
+
+ def compute(n, ho, wo, ko, hi, wi, ki):
+ h = ho * block_H + hi
+ h_contig = h * stride1[0] + rh
+ h_block_id = h_contig // block_H
+ h_block_offset = h_contig % block_H
+
+ w = wo * block_W + wi
+ w_contig = w * stride1[1] + rw
+ w_block_id = w_contig // block_W
+ w_block_offset = w_contig % block_W
+
+ c_block_id = rc // block_C
+ c_block_offset = rc % block_C
+
+ rco = rc // filter_Ci
+ rcio = (rc % filter_Ci) // filter_Cii
+ rcii = rc % filter_Cii
+
+ return te.sum(
+ X_packed[
+ n,
+ h_block_id,
+ w_block_id,
+ c_block_id,
+ h_block_offset,
+ w_block_offset,
+ c_block_offset,
+ ]
+ * filt_packed1[ko, rco, rh, rw, rcio, ki, rcii],
+ axis=[rh, rw, rc],
+ )
+
+ output_shape1 = get_packed_activation_layout(logical_output_shape1, block_shape)
+ temp_Y = te.compute(output_shape1, compute, name="temp_output")
+
+ # calculate kernel size and output channels
+ # given oihw8i32o4i filter layout
+ kernel_size2 = tuple(shape_filter2[2:4])
+ out_channels2 = shape_filter2[0] * shape_filter2[5]
+
+ # get the the logical output shape of conv2d #2
+ logical_input_shape2 = logical_output_shape1
+ logical_output_shape2 = get_conv2d_nhwc_shape(
+ logical_input_shape2,
+ kernel_size2,
+ stride2,
+ pad2,
+ dilation2,
+ out_channels2,
+ )
+
+ rh = te.reduce_axis((0, kernel_size2[0]), name="rh")
+ rw = te.reduce_axis((0, kernel_size2[1]), name="rw")
+ rc = te.reduce_axis((0, logical_input_shape2[3]), name="rc")
+
+ def compute2(n, ho, wo, ko, hi, wi, ki):
+ h = ho * block_H + hi
+ h_contig = h * stride2[0] + rh
+ h_block_id = h_contig // block_H
+ h_block_offset = h_contig % block_H
+
+ w = wo * block_W + wi
+ w_contig = w * stride2[1] + rw
+ w_block_id = w_contig // block_W
+ w_block_offset = w_contig % block_W
+
+ c_block_id = rc // block_C
+ c_block_offset = rc % block_C
+
+ rco = rc // filter_Ci
+ rcio = (rc % filter_Ci) // filter_Cii
+ rcii = rc % filter_Cii
Review comment:
Yes. I would like to do this in a refactor which is already work in progress.
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