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Posted to commits@mynewt.apache.org by je...@apache.org on 2021/12/17 06:59:07 UTC
[mynewt-core] branch master updated (a40d915 -> 99dbb55)
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git.
from a40d915 pic32: Fix CPU0 register definitions
new f7d2de8 stm32: Add 4th I2C peripheral
new 99dbb55 nucleo-f767zi: Add additional I2C peripherals
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
hw/bsp/nucleo-f767zi/src/hal_bsp.c | 41 +++++++++++++++++++++++++++++-
hw/bsp/nucleo-f767zi/syscfg.yml | 6 +++++
hw/mcu/stm/stm32_common/src/hal_i2c.c | 20 +++++++++++++--
hw/mcu/stm/stm32_common/src/stm32_periph.c | 7 +++++
hw/mcu/stm/stm32_common/syscfg.yml | 9 +++++++
5 files changed, 80 insertions(+), 3 deletions(-)
[mynewt-core] 01/02: stm32: Add 4th I2C peripheral
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit f7d2de84b51a0d344cdd34bbb94590fbcbbd912f
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Thu Dec 16 12:01:01 2021 +0100
stm32: Add 4th I2C peripheral
Four I2C peripherals are sometime present.
Limited pin assignments in STM MCUs calls for
separate configuration even when only one
I2C is used.
---
hw/mcu/stm/stm32_common/src/hal_i2c.c | 20 ++++++++++++++++++--
hw/mcu/stm/stm32_common/src/stm32_periph.c | 7 +++++++
hw/mcu/stm/stm32_common/syscfg.yml | 9 +++++++++
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/hw/mcu/stm/stm32_common/src/hal_i2c.c b/hw/mcu/stm/stm32_common/src/hal_i2c.c
index e59da38..cacf29c 100644
--- a/hw/mcu/stm/stm32_common/src/hal_i2c.c
+++ b/hw/mcu/stm/stm32_common/src/hal_i2c.c
@@ -28,7 +28,15 @@
#include <mcu/stm32_hal.h>
+#if MYNEWT_VAL(I2C_3)
+#define HAL_I2C_MAX_DEVS 4
+#elif MYNEWT_VAL(I2C_2)
#define HAL_I2C_MAX_DEVS 3
+#elif MYNEWT_VAL(I2C_1)
+#define HAL_I2C_MAX_DEVS 2
+#else
+#define HAL_I2C_MAX_DEVS 1
+#endif
#define I2C_ADDRESS 0xae
@@ -52,6 +60,9 @@ static struct stm32_hal_i2c i2c1;
#if MYNEWT_VAL(I2C_2)
static struct stm32_hal_i2c i2c2;
#endif
+#if MYNEWT_VAL(I2C_3)
+static struct stm32_hal_i2c i2c3;
+#endif
static struct stm32_hal_i2c *hal_i2c_devs[HAL_I2C_MAX_DEVS] = {
#if MYNEWT_VAL(I2C_0)
@@ -61,12 +72,17 @@ static struct stm32_hal_i2c *hal_i2c_devs[HAL_I2C_MAX_DEVS] = {
#endif
#if MYNEWT_VAL(I2C_1)
&i2c1,
-#else
+#elif HAL_I2C_MAX_DEVS > 2
NULL,
#endif
#if MYNEWT_VAL(I2C_2)
&i2c2,
-#else
+#elif HAL_I2C_MAX_DEVS > 3
+ NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+ &i2c3,
+#elif HAL_I2C_MAX_DEVS > 4
NULL,
#endif
};
diff --git a/hw/mcu/stm/stm32_common/src/stm32_periph.c b/hw/mcu/stm/stm32_common/src/stm32_periph.c
index 172c16c..2ed29cd 100644
--- a/hw/mcu/stm/stm32_common/src/stm32_periph.c
+++ b/hw/mcu/stm/stm32_common/src/stm32_periph.c
@@ -154,6 +154,9 @@ extern const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg;
#if MYNEWT_VAL(I2C_2)
extern const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg;
#endif
+#if MYNEWT_VAL(I2C_3)
+extern const struct stm32_hal_i2c_cfg os_bsp_i2c3_cfg;
+#endif
#if MYNEWT_VAL(BUS_DRIVER_PRESENT)
@@ -498,6 +501,10 @@ stm32_periph_create_i2c(void)
rc = hal_i2c_init(2, (void *)&os_bsp_i2c2_cfg);
assert(rc == 0);
#endif
+#if MYNEWT_VAL(I2C_3)
+ rc = hal_i2c_init(3, (void *)&os_bsp_i2c3_cfg);
+ assert(rc == 0);
+#endif
}
#if MYNEWT_VAL(BUS_DRIVER_PRESENT)
diff --git a/hw/mcu/stm/stm32_common/syscfg.yml b/hw/mcu/stm/stm32_common/syscfg.yml
index 3ecb73e..a157faf 100644
--- a/hw/mcu/stm/stm32_common/syscfg.yml
+++ b/hw/mcu/stm/stm32_common/syscfg.yml
@@ -396,6 +396,15 @@ syscfg.defs:
I2C_2_PIN_SDA:
description: 'SDA pin for I2C_2'
value: -1
+ I2C_3:
+ description: 'I2C (TWI) interface 3'
+ value: 0
+ I2C_3_PIN_SCL:
+ description: 'SCL pin for I2C_3'
+ value: -1
+ I2C_3_PIN_SDA:
+ description: 'SDA pin for I2C_3'
+ value: -1
TRNG:
description: 'True Random Number Generator (RNG)'
[mynewt-core] 02/02: nucleo-f767zi: Add additional I2C peripherals
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 99dbb55d1fbdf693e93801b5609cc4a97b9de2ee
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Thu Dec 16 12:07:20 2021 +0100
nucleo-f767zi: Add additional I2C peripherals
Only I2C_0 was supported.
Now four of them can be used.
---
hw/bsp/nucleo-f767zi/src/hal_bsp.c | 41 +++++++++++++++++++++++++++++++++++++-
hw/bsp/nucleo-f767zi/syscfg.yml | 6 ++++++
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/hw/bsp/nucleo-f767zi/src/hal_bsp.c b/hw/bsp/nucleo-f767zi/src/hal_bsp.c
index ce5b41b..a039e20 100644
--- a/hw/bsp/nucleo-f767zi/src/hal_bsp.c
+++ b/hw/bsp/nucleo-f767zi/src/hal_bsp.c
@@ -106,7 +106,46 @@ const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = {
.hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL),
.hic_pin_af = GPIO_AF4_I2C1,
.hic_10bit = 0,
- .hic_timingr = 0x30420F13, /* 100KHz at 16MHz of SysCoreClock */
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = {
+ .hic_i2c = I2C2,
+ .hic_rcc_reg = &RCC->APB1ENR,
+ .hic_rcc_dev = RCC_APB1ENR_I2C2EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C2,
+ .hic_10bit = 0,
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = {
+ .hic_i2c = I2C3,
+ .hic_rcc_reg = &RCC->APB1ENR,
+ .hic_rcc_dev = RCC_APB1ENR_I2C3EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C3,
+ .hic_10bit = 0,
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+const struct stm32_hal_i2c_cfg os_bsp_i2c3_cfg = {
+ .hic_i2c = I2C4,
+ .hic_rcc_reg = &RCC->APB1ENR,
+ .hic_rcc_dev = RCC_APB1ENR_I2C4EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_3_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_3_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C4,
+ .hic_10bit = 0,
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
};
#endif
diff --git a/hw/bsp/nucleo-f767zi/syscfg.yml b/hw/bsp/nucleo-f767zi/syscfg.yml
index b4ffd38..eccbbb8 100644
--- a/hw/bsp/nucleo-f767zi/syscfg.yml
+++ b/hw/bsp/nucleo-f767zi/syscfg.yml
@@ -55,6 +55,12 @@ syscfg.vals:
SPI_0_PIN_MOSI: 'MCU_GPIO_PORTA(7)'
I2C_0_PIN_SCL: 'MCU_GPIO_PORTB(8)'
I2C_0_PIN_SDA: 'MCU_GPIO_PORTB(9)'
+ I2C_1_PIN_SCL: 'MCU_GPIO_PORTF(1)'
+ I2C_1_PIN_SDA: 'MCU_GPIO_PORTF(0)'
+ I2C_2_PIN_SCL: 'MCU_GPIO_PORTA(8)'
+ I2C_2_PIN_SDA: 'MCU_GPIO_PORTC(9)'
+ I2C_3_PIN_SCL: 'MCU_GPIO_PORTD(12)'
+ I2C_3_PIN_SDA: 'MCU_GPIO_PORTD(13)'
TIMER_0_TIM: 'TIM9'
TIMER_1_TIM: 'TIM10'
TIMER_2_TIM: 'TIM11'