You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by xi...@apache.org on 2023/05/15 09:32:39 UTC
[nuttx] 02/02: stm32h7/otg: allow USBDEV and USBHOST to work simultaneously
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 5c3fa2d788e0c83c6aa5ef585294c437c714b166
Author: raiden00pl <ra...@railab.me>
AuthorDate: Tue May 9 11:55:39 2023 +0200
stm32h7/otg: allow USBDEV and USBHOST to work simultaneously
---
arch/arm/src/stm32h7/Kconfig | 29 ++++++++++++++++++-
arch/arm/src/stm32h7/stm32_otg.h | 24 +++-------------
arch/arm/src/stm32h7/stm32_otgdev.c | 54 ++++++++++++++++++++++++++++++------
arch/arm/src/stm32h7/stm32_otghost.c | 31 +++++++++++++++++++--
4 files changed, 106 insertions(+), 32 deletions(-)
diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig
index dc82855c89..eebabc17aa 100644
--- a/arch/arm/src/stm32h7/Kconfig
+++ b/arch/arm/src/stm32h7/Kconfig
@@ -1040,7 +1040,7 @@ config STM32H7_I2CTIMEOTICKS
endmenu # "I2C Configuration"
menu "OTG Configuration"
- depends on STM32H7_OTGFS
+ depends on STM32H7_OTGFS || STM32H7_OTGHS
config OTG_ID_GPIO_DISABLE
bool "Disable the use of GPIO_OTG_ID pin."
@@ -1050,6 +1050,33 @@ config OTG_ID_GPIO_DISABLE
cases to reuse this GPIO pin and ensure it is not set incorrectlty
during OS boot.
+choice
+ prompt "STM32H7 OTGFS role"
+ depends on STM32H7_OTGFS
+ default STM32H7_OTGFS_USBDEV if USBDEV
+ default STM32H7_OTGFS_USBHOST if !USBDEV && USBHOST
+
+config STM32H7_OTGFS_USBDEV
+ bool "OTGFS as USBDEV"
+ depends on USBDEV
+
+config STM32H7_OTGFS_HOST
+ bool "OTGFS as HOST"
+ depends on USBHOST
+
+endchoice # "STM32H7 OTGFS role"
+
+choice
+ prompt "STM32H7 OTGHS role (only USBDEV supported for now)"
+ depends on STM32H7_OTGHS
+ default STM32H7_OTGHS_USBDEV if USBDEV
+
+config STM32H7_OTGHS_USBDEV
+ bool "OTGHS as USBDEV"
+ depends on USBDEV
+
+endchoice # "STM32H7 OTGHS role"
+
endmenu
menu "SPI Configuration"
diff --git a/arch/arm/src/stm32h7/stm32_otg.h b/arch/arm/src/stm32h7/stm32_otg.h
index c1d546cb9f..7218234e8e 100644
--- a/arch/arm/src/stm32h7/stm32_otg.h
+++ b/arch/arm/src/stm32h7/stm32_otg.h
@@ -59,27 +59,11 @@
/* Configuration ************************************************************/
-#if defined(CONFIG_STM32H7_OTGFS)
-# define STM32_IRQ_OTG STM32_IRQ_OTGFS
-# define STM32_OTG_BASE STM32_OTGFS_BASE /* OTG FS */
-# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
-# define GPIO_OTG_DM GPIO_OTGFS_DM
-# define GPIO_OTG_DP GPIO_OTGFS_DP
-# define GPIO_OTG_ID GPIO_OTGFS_ID
-# define GPIO_OTG_SOF GPIO_OTGFS_SOF
-# define STM32_OTG_FIFO_SIZE 4096
-#endif
+/* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one
+ * bit for direction
+ */
-#if defined(CONFIG_STM32H7_OTGHS)
-# define STM32_IRQ_OTG STM32_IRQ_OTGHS
-# define STM32_OTG_BASE STM32_OTGHS_BASE /* OTG HS/FS */
-# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
-# define GPIO_OTG_DM GPIO_OTGHS_DM
-# define GPIO_OTG_DP GPIO_OTGHS_DP
-# define GPIO_OTG_ID GPIO_OTGHS_ID
-# define GPIO_OTG_SOF GPIO_OTGHS_SOF
-# define STM32_OTG_FIFO_SIZE 4096
-#endif
+#define STM32_NENDPOINTS (7)
/****************************************************************************
* Public Function Prototypes
diff --git a/arch/arm/src/stm32h7/stm32_otgdev.c b/arch/arm/src/stm32h7/stm32_otgdev.c
index 68abf01fed..80ef60ea1f 100644
--- a/arch/arm/src/stm32h7/stm32_otgdev.c
+++ b/arch/arm/src/stm32h7/stm32_otgdev.c
@@ -58,6 +58,32 @@
* Pre-processor Definitions
****************************************************************************/
+/* OTG device selection *****************************************************/
+
+#if defined(CONFIG_STM32H7_OTGFS_USBDEV)
+# define STM32_IRQ_OTG STM32_IRQ_OTGFS
+# define STM32_OTG_BASE STM32_OTGFS_BASE
+# define GPIO_OTG_DM GPIO_OTGFS_DM
+# define GPIO_OTG_DP GPIO_OTGFS_DP
+# define GPIO_OTG_ID GPIO_OTGFS_ID
+# define GPIO_OTG_SOF GPIO_OTGFS_SOF
+# define STM32_OTG_FIFO_SIZE 4096
+#elif defined(CONFIG_STM32H7_OTGHS_USBDEV)
+# define STM32_IRQ_OTG STM32_IRQ_OTGHS
+# define STM32_OTG_BASE STM32_OTGHS_BASE
+# define GPIO_OTG_DM GPIO_OTGHS_DM
+# define GPIO_OTG_DP GPIO_OTGHS_DP
+# define GPIO_OTG_ID GPIO_OTGHS_ID
+# define GPIO_OTG_SOF GPIO_OTGHS_SOF
+# define STM32_OTG_FIFO_SIZE 4096
+#else
+# error Not selected USBDEV peripheral
+#endif
+
+#if defined(CONFIG_STM32H7_OTGFS_USBDEV) && defined(CONFIG_STM32H7_OTGHS_USBDEV)
+# error Only one USBDEV role supported
+#endif
+
/* Configuration ************************************************************/
#ifndef CONFIG_USBDEV_EP0_MAXSIZE
@@ -2110,7 +2136,8 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv)
stm32_setaddress(priv, 0);
priv->devstate = DEVSTATE_DEFAULT;
-#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI
+#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \
+ defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI)
priv->usbdev.speed = USB_SPEED_HIGH;
#else
priv->usbdev.speed = USB_SPEED_FULL;
@@ -5259,7 +5286,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG);
-#if defined(CONFIG_STM32H7_OTGHS_NO_ULPI) || defined(CONFIG_STM32H7_OTGFS)
+#if (defined(CONFIG_STM32H7_OTGHS_USBDEV) && \
+ defined(CONFIG_STM32H7_OTGHS_NO_ULPI)) || \
+ defined(CONFIG_STM32H7_OTGFS_USBDEV)
/* Full speed serial transceiver select */
regval = stm32_getreg(STM32_OTG_GUSBCFG);
@@ -5267,7 +5296,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
stm32_putreg(regval, STM32_OTG_GUSBCFG);
#endif
-#if defined(CONFIG_STM32H7_OTGHS_FS) && \
+#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \
+ defined(CONFIG_STM32H7_OTGHS_FS) && \
defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI)
/* ULPI Full speed mode */
@@ -5310,7 +5340,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
regval = stm32_getreg(STM32_OTG_GCCFG);
-#if defined(CONFIG_STM32H7_OTGHS_NO_ULPI) || defined(CONFIG_STM32H7_OTGFS)
+#if (defined(CONFIG_STM32H7_OTGHS_USBDEV) && \
+ defined(CONFIG_STM32H7_OTGHS_NO_ULPI)) || \
+ defined(CONFIG_STM32H7_OTGFS_USBDEV)
/* Enable USB FS transceiver */
regval |= OTG_GCCFG_PWRDWN;
@@ -5325,7 +5357,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
stm32_putreg(regval, STM32_OTG_GCCFG);
up_mdelay(20);
-#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI
+#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \
+ defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI)
/* Enable delay to default timing, necessary for some ULPI PHYs such
* as such as USB334x
*/
@@ -5368,9 +5401,10 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
regval = stm32_getreg(STM32_OTG_DCFG);
regval &= ~OTG_DCFG_DSPD_MASK;
-#if defined(CONFIG_STM32H7_OTGHS_FS)
+#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \
+ defined(CONFIG_STM32H7_OTGHS_FS)
regval |= OTG_DCFG_DSPD_FSHS;
-#elif defined(CONFIG_STM32H7_OTGHS)
+#elif defined(CONFIG_STM32H7_OTGHS_USBDEV)
regval |= OTG_DCFG_DSPD_HS;
#else
regval |= OTG_DCFG_DSPD_FS;
@@ -5513,7 +5547,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
regval &= OTG_GINT_RESERVED;
stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS);
-#if defined(CONFIG_STM32H7_OTGHS) && defined(CONFIG_STM32H7_OTGHS_NO_ULPI)
+#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \
+ defined(CONFIG_STM32H7_OTGHS_NO_ULPI)
/* Disable the ULPI Clock enable in RCC AHB1 Register. This must
* be done because if both the ULPI and the FS PHY clock enable bits
* are set at the same time, the ARM never awakens from WFI due to
@@ -5622,7 +5657,8 @@ void arm_usbinitialize(void)
* current detection.
*/
-#ifndef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI
+#if !(defined(CONFIG_STM32H7_OTGHS_USBDEV) && \
+ defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI))
/* Configure OTG alternate function pins */
stm32_configgpio(GPIO_OTG_DM);
diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c
index 1b9caf1873..888c1c11b5 100644
--- a/arch/arm/src/stm32h7/stm32_otghost.c
+++ b/arch/arm/src/stm32h7/stm32_otghost.c
@@ -64,6 +64,33 @@
* Pre-processor Definitions
****************************************************************************/
+/* OTG host selection *******************************************************/
+
+#if defined(CONFIG_STM32H7_OTGFS_HOST)
+# define STM32_IRQ_OTG STM32_IRQ_OTGFS
+# define STM32_OTG_BASE STM32_OTGFS_BASE
+# define GPIO_OTG_DM GPIO_OTGFS_DM
+# define GPIO_OTG_DP GPIO_OTGFS_DP
+# define GPIO_OTG_ID GPIO_OTGFS_ID
+# define GPIO_OTG_SOF GPIO_OTGFS_SOF
+# define STM32_OTG_FIFO_SIZE 4096
+#elif defined(CONFIG_STM32H7_OTGHS_HOST)
+# error OTGHS HOST role not supported yet
+# define STM32_IRQ_OTG STM32_IRQ_OTGHS
+# define STM32_OTG_BASE STM32_OTGHS_BASE
+# define GPIO_OTG_DM GPIO_OTGHS_DM
+# define GPIO_OTG_DP GPIO_OTGHS_DP
+# define GPIO_OTG_ID GPIO_OTGHS_ID
+# define GPIO_OTG_SOF GPIO_OTGHS_SOF
+# define STM32_OTG_FIFO_SIZE 4096
+#else
+# error Not selected USBDEV peripheral
+#endif
+
+#if defined(CONFIG_STM32H7_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_HOST)
+# error Only one HOST role supported
+#endif
+
/* Configuration ************************************************************/
/* STM32 USB OTG FS Host Driver Support
@@ -5439,7 +5466,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller)
/* Attach USB host controller interrupt handler */
- if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr, NULL) != 0)
+ if (irq_attach(STM32_IRQ_OTG, stm32_gint_isr, NULL) != 0)
{
usbhost_trace1(OTG_TRACE1_IRQATTACH, 0);
return NULL;
@@ -5451,7 +5478,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller)
/* Enable interrupts at the interrupt controller */
- up_enable_irq(STM32_IRQ_OTGFS);
+ up_enable_irq(STM32_IRQ_OTG);
return &g_usbconn;
}