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Posted to issues@mxnet.apache.org by "Kellen Sunderland (JIRA)" <ji...@apache.org> on 2018/10/18 22:21:00 UTC
[jira] [Updated] (MXNET-1084) Enable FP16 Mode for Integrated
TensorRT Inference
[ https://issues.apache.org/jira/browse/MXNET-1084?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel ]
Kellen Sunderland updated MXNET-1084:
-------------------------------------
Description:
As as owner of a Turing, Volta, Pascal, or Jetson TX1 device, I would like to run inference using TensorRT with FP16 DType tensors to make use of dedicated hardware optimizations present.
Reference: [https://devblogs.nvidia.com/tensor-core-ai-performance-milestones/]
[https://devblogs.nvidia.com/programming-tensor-cores-cuda-9/]
was:
As as an owner of a Turing, Volta, Pascal, or Jetson TX1 device, I would like to run inference using TensorRT with FP16 DType tensors to make use of dedicated hardware optimizations present.
Reference: https://devblogs.nvidia.com/tensor-core-ai-performance-milestones/
https://devblogs.nvidia.com/programming-tensor-cores-cuda-9/
> Enable FP16 Mode for Integrated TensorRT Inference
> --------------------------------------------------
>
> Key: MXNET-1084
> URL: https://issues.apache.org/jira/browse/MXNET-1084
> Project: Apache MXNet
> Issue Type: Improvement
> Reporter: Kellen Sunderland
> Priority: Major
>
> As as owner of a Turing, Volta, Pascal, or Jetson TX1 device, I would like to run inference using TensorRT with FP16 DType tensors to make use of dedicated hardware optimizations present.
> Reference: [https://devblogs.nvidia.com/tensor-core-ai-performance-milestones/]
> [https://devblogs.nvidia.com/programming-tensor-cores-cuda-9/]
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