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Posted to commits@mynewt.apache.org by je...@apache.org on 2026/10/29 17:00:26 UTC
(mynewt-core) branch master updated (adc3dd342 -> 61862d693)
This is an automated email from the ASF dual-hosted git repository.
kasjer pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
from adc3dd342 hw/hal: Paste flash id directly in HAL_FLASH_DEV
new ea42088ec hw/bus/drivers/spi_stm32: Add PD7 as SPI1 MOSI for H7 and F7
new 61862d693 hw/bsp: Add WeAct H743VI board
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
.clang-format-ignore | 1 +
.rat-excludes | 1 +
hw/bsp/{stm32f7discovery => weact_h743vi}/bsp.yml | 53 +++++---
hw/bsp/{nucleo-h563zi => weact_h743vi}/debug.sh | 0
.../include/bsp/bsp.h | 22 ++--
.../include/bsp/stm32h7xx_hal_conf.h | 3 +-
.../weact_h743vi}/link/include/memory_regions.ld.h | 3 +
hw/bsp/{nucleo-h723zg => weact_h743vi}/pkg.yml | 15 ++-
.../{nucleo-h723zg => weact_h743vi}/src/hal_bsp.c | 142 +++++++++------------
hw/bsp/weact_h743vi/syscfg.yml | 103 +++++++++++++++
hw/bus/drivers/spi_stm32/src/spi_stm32.c | 3 +
11 files changed, 228 insertions(+), 118 deletions(-)
copy hw/bsp/{stm32f7discovery => weact_h743vi}/bsp.yml (63%)
copy hw/bsp/{nucleo-h563zi => weact_h743vi}/debug.sh (100%)
copy hw/bsp/{weact_h503cb => weact_h743vi}/include/bsp/bsp.h (73%)
copy hw/bsp/{nucleo-h723zg => weact_h743vi}/include/bsp/stm32h7xx_hal_conf.h (99%)
copy hw/{mcu/stm/stm32h7xx => bsp/weact_h743vi}/link/include/memory_regions.ld.h (86%)
copy hw/bsp/{nucleo-h723zg => weact_h743vi}/pkg.yml (81%)
copy hw/bsp/{nucleo-h723zg => weact_h743vi}/src/hal_bsp.c (67%)
create mode 100644 hw/bsp/weact_h743vi/syscfg.yml
(mynewt-core) 01/02: hw/bus/drivers/spi_stm32: Add PD7 as SPI1 MOSI for H7 and F7
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
kasjer pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit ea42088ec0cc8c167f2d8337673c5015f8acfa88
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Sun Oct 25 00:46:26 2026 +0200
hw/bus/drivers/spi_stm32: Add PD7 as SPI1 MOSI for H7 and F7
PD7 can be used as SPI1_MOSI (AF5) on STM32H7 and STM32F7. It is
used by weact_h743vi for SPI flash.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Jerzy Kasenberg <je...@apache.org>
---
hw/bus/drivers/spi_stm32/src/spi_stm32.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/bus/drivers/spi_stm32/src/spi_stm32.c b/hw/bus/drivers/spi_stm32/src/spi_stm32.c
index 9e3270502..0d6db0a40 100644
--- a/hw/bus/drivers/spi_stm32/src/spi_stm32.c
+++ b/hw/bus/drivers/spi_stm32/src/spi_stm32.c
@@ -205,6 +205,9 @@ static const struct spi_pin_def spi_pin[] = {
SPI_PIN_DEF(0, MCU_GPIO_PORTA(7), SPI_MOSI, SPI_AF_5),
SPI_PIN_DEF(0, MCU_GPIO_PORTB(5), SPI_MOSI, SPI_AF_5),
+#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32F7)
+ SPI_PIN_DEF(0, MCU_GPIO_PORTD(7), SPI_MOSI, SPI_AF_5),
+#endif
SPI_PIN_DEF(0, MCU_GPIO_PORTA(6), SPI_MISO, SPI_AF_5),
SPI_PIN_DEF(0, MCU_GPIO_PORTB(4), SPI_MISO, SPI_AF_5),
(mynewt-core) 02/02: hw/bsp: Add WeAct H743VI board
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
kasjer pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 61862d69317e4b695810faede5ebd8a35ef85566
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Sun Oct 25 01:37:11 2026 +0200
hw/bsp: Add WeAct H743VI board
BSP for WeAct MiniSTM32H7xx board with STM32H743VIT6.
Board has two 8MB Winbond W25Q64JV flashes: QSPI flash (flash id 1,
enabled with stm32_qspi package) and SPI flash on SPI1 (flash id 2).
Both flashes use common hal_bsp_flash_dev().
Internal flash holds only bootloader and image 0 (1920kB). SPI flash
holds image 1, scratch, config and reboot log areas. SPI DMA is
disabled because spi_stm32 DMA transfers return stale data on H7.
Bus drivers (spi_hal, i2c_hal) are used only by applications,
bootloader accesses SPI flash through hal_spi.
UART_n and I2C_n numbers match USARTn and I2Cn peripherals, there is
no UART_0 and I2C_0. Console is on UART_3 (USART3, PD8/PD9).
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Jerzy Kasenberg <je...@apache.org>
---
.clang-format-ignore | 1 +
.rat-excludes | 1 +
hw/bsp/weact_h743vi/bsp.yml | 79 ++++
hw/bsp/weact_h743vi/debug.sh | 34 ++
hw/bsp/weact_h743vi/include/bsp/bsp.h | 62 +++
.../weact_h743vi/include/bsp/stm32h7xx_hal_conf.h | 425 +++++++++++++++++++++
.../weact_h743vi/link/include/memory_regions.ld.h | 24 ++
hw/bsp/weact_h743vi/pkg.yml | 45 +++
hw/bsp/weact_h743vi/src/hal_bsp.c | 227 +++++++++++
hw/bsp/weact_h743vi/syscfg.yml | 103 +++++
10 files changed, 1001 insertions(+)
diff --git a/.clang-format-ignore b/.clang-format-ignore
index 95e7f4928..64de401de 100644
--- a/.clang-format-ignore
+++ b/.clang-format-ignore
@@ -47,6 +47,7 @@ hw/bsp/stm32f7discovery/include/bsp/stm32f7xx_hal_conf.h
hw/bsp/stm32l152discovery/include/bsp/stm32l1xx_hal_conf.h
hw/bsp/nucleo-u575zi-q/include/bsp/stm32u5xx_hal_conf.h
hw/bsp/weact_g431cb/include/bsp/stm32g4xx_hal_conf.h
+hw/bsp/weact_h743vi/include/bsp/stm32h7xx_hal_conf.h
hw/mcu/stm/stm32f1xx/src/system_stm32f1xx.c
hw/mcu/stm/stm32f3xx/src/system_stm32f3xx.c
hw/mcu/stm/stm32f7xx/src/system_stm32f7xx.c
diff --git a/.rat-excludes b/.rat-excludes
index eaa9d4635..831cbe65b 100644
--- a/.rat-excludes
+++ b/.rat-excludes
@@ -231,6 +231,7 @@ hw/bsp/stm32f7discovery/include/bsp/stm32f7xx_hal_conf.h
hw/bsp/stm32l152discovery/include/bsp/stm32l1xx_hal_conf.h
hw/bsp/weact_g431cb/include/bsp/stm32g4xx_hal_conf.h
hw/bsp/weact_h503cb/include/bsp/stm32h5xx_hal_conf.h
+hw/bsp/weact_h743vi/include/bsp/stm32h7xx_hal_conf.h
# baselibc - BSD License.
# tinyprintf - BSD License.
diff --git a/hw/bsp/weact_h743vi/bsp.yml b/hw/bsp/weact_h743vi/bsp.yml
new file mode 100644
index 000000000..e93dfab47
--- /dev/null
+++ b/hw/bsp/weact_h743vi/bsp.yml
@@ -0,0 +1,79 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.name: "WeAct H743VI"
+bsp.url: https://github.com/WeActStudio/MiniSTM32H7xx
+bsp.maker: "WeAct"
+bsp.arch: cortex_m7
+bsp.compiler: compiler/arm-none-eabi-m7
+bsp.linkerscript: autogenerated
+bsp.downloadscript: "hw/scripts/download.sh"
+bsp.debugscript: "hw/bsp/weact_h743vi/debug.sh"
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ # Internal flash holds only bootloader and image 0.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x08000000
+ size: 128kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x08020000
+ size: 1920kB
+ # Image 1 and scratch in external SPI flash (SPI1)
+ FLASH_AREA_IMAGE_1:
+ device: 2
+ offset: 0x00000000
+ size: 1920kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 2
+ offset: 0x001E0000
+ size: 128kB
+
+ # User areas.
+ # External SPI flash (SPI1)
+ FLASH_AREA_CONFIG:
+ user_id: 1
+ device: 2
+ offset: 0x00200000
+ size: 32kB
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 2
+ device: 2
+ offset: 0x00208000
+ size: 32kB
+ FLASH_AREA_SPI:
+ user_id: 3
+ device: 2
+ offset: 0x00210000
+ size: 128kB
+
+ # External QSPI flash
+ FLASH_AREA_LITTLEFS:
+ user_id: 4
+ device: 1
+ offset: 0x90000000
+ size: 128kB
+ FLASH_AREA_FCB:
+ user_id: 5
+ device: 1
+ offset: 0x90020000
+ size: 64kB
diff --git a/hw/bsp/weact_h743vi/debug.sh b/hw/bsp/weact_h743vi/debug.sh
new file mode 100644
index 000000000..28886adf6
--- /dev/null
+++ b/hw/bsp/weact_h743vi/debug.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+. $CORE_PATH/hw/scripts/stm32_programmer.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+
+stm32_debug
diff --git a/hw/bsp/weact_h743vi/include/bsp/bsp.h b/hw/bsp/weact_h743vi/include/bsp/bsp.h
new file mode 100644
index 000000000..29ed9338f
--- /dev/null
+++ b/hw/bsp/weact_h743vi/include/bsp/bsp.h
@@ -0,0 +1,62 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+#include <mcu/mcu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start[];
+extern uint8_t _dtcmram_start;
+extern uint8_t _itcmram_start;
+
+#define RAM_SIZE (512 * 1024)
+#define DTCMRAM_SIZE (128 * 1024)
+#define ITCMRAM_SIZE (64 * 1024)
+
+/* LED pins */
+#define LED_1 MCU_GPIO_PORTE(3)
+
+#define LED_GREEN LED_1
+
+#define LED_BLINK_PIN LED_1
+
+/* BUTTON pins */
+#define BTN_USER_1 MCU_GPIO_PORTC(13)
+
+/* Button pin */
+#define BUTTON_1 BTN_USER_1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
diff --git a/hw/bsp/weact_h743vi/include/bsp/stm32h7xx_hal_conf.h b/hw/bsp/weact_h743vi/include/bsp/stm32h7xx_hal_conf.h
new file mode 100644
index 000000000..0a274c94c
--- /dev/null
+++ b/hw/bsp/weact_h743vi/include/bsp/stm32h7xx_hal_conf.h
@@ -0,0 +1,425 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_conf_template.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32h7xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_CONF_H
+#define __STM32H7xx_HAL_CONF_H
+
+#include <syscfg/syscfg.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DFSDM_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FDCAN_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_HRTIM_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_JPEG_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_MDIOS_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RAMECC_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPDIFRX_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SWPMI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if defined (MYNEWT_VAL_STM32_CLOCK_HSE_VALUE)
+#define HSE_VALUE MYNEWT_VAL(STM32_CLOCK_HSE_VALUE)
+#elif !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal oscillator (CSI) default value.
+ * This value is the default CSI value after Reset.
+ */
+#if !defined (CSI_VALUE)
+#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */
+#define USE_SPI_CRC 1U /*!< use CRC in SPI */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0 ((uint8_t)0x02)
+#define ETH_MAC_ADDR1 ((uint8_t)0x00)
+#define ETH_MAC_ADDR2 ((uint8_t)0x00)
+#define ETH_MAC_ADDR3 ((uint8_t)0x00)
+#define ETH_MAC_ADDR4 ((uint8_t)0x00)
+#define ETH_MAC_ADDR5 ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+#include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+#include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+#include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+#include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+#include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+#include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+#include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+#include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+#include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+
+#ifdef HAL_MMC_MODULE_ENABLED
+#include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+#include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+#include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+#include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+#include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+#include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+#include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t * file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
diff --git a/hw/bsp/weact_h743vi/link/include/memory_regions.ld.h b/hw/bsp/weact_h743vi/link/include/memory_regions.ld.h
new file mode 100644
index 000000000..1bb51cfb9
--- /dev/null
+++ b/hw/bsp/weact_h743vi/link/include/memory_regions.ld.h
@@ -0,0 +1,24 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* clang-format off */
+ ITCM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
+ DTCM (rw!x) : ORIGIN = 0x20000000, LENGTH = 128K
+ SRAM123 (rw!x) : ORIGIN = 0x30000000, LENGTH = 384K
+ SRAM4 (rw!x) : ORIGIN = 0x38000000, LENGTH = 64K
diff --git a/hw/bsp/weact_h743vi/pkg.yml b/hw/bsp/weact_h743vi/pkg.yml
new file mode 100644
index 000000000..9f88df6e0
--- /dev/null
+++ b/hw/bsp/weact_h743vi/pkg.yml
@@ -0,0 +1,45 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/weact_h743vi
+pkg.type: bsp
+pkg.description: BSP definition for the WeAct STM32H743VIT6 board.
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - stm32
+ - stm32h7
+
+pkg.cflags:
+ - -DSTM32H743xx
+ - -DUSE_FULL_LL_DRIVER
+
+pkg.cflags.HARDFLOAT:
+ - -mfloat-abi=hard -mfpu=fpv5-d16
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/mcu/stm/stm32h7xx"
+ - "@apache-mynewt-core/libc"
+ - "@apache-mynewt-core/hw/drivers/flash/spiflash"
+ - "@apache-mynewt-core/hw/scripts"
+ - "@apache-mynewt-core/boot/startup"
+
+pkg.deps.'!BOOT_LOADER':
+ - "@apache-mynewt-core/hw/bus/drivers/spi_hal"
+ - "@apache-mynewt-core/hw/bus/drivers/i2c_hal"
diff --git a/hw/bsp/weact_h743vi/src/hal_bsp.c b/hw/bsp/weact_h743vi/src/hal_bsp.c
new file mode 100644
index 000000000..18963fe64
--- /dev/null
+++ b/hw/bsp/weact_h743vi/src/hal_bsp.c
@@ -0,0 +1,227 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "bsp/bsp.h"
+#include "os/mynewt.h"
+
+#include <hal/hal_bsp.h>
+#include <hal/hal_flash_int.h>
+#include <hal/hal_system.h>
+
+#include <stm32h743xx.h>
+#include <stm32_common/stm32_hal.h>
+
+#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2)
+#include <pwm_stm32/pwm_stm32.h>
+#endif
+
+#if MYNEWT_VAL(PWM_0)
+struct stm32_pwm_conf os_bsp_pwm0_cfg = {
+ .tim = TIM3,
+ .irq = TIM3_IRQn,
+};
+#endif
+#if MYNEWT_VAL(PWM_1)
+struct stm32_pwm_conf os_bsp_pwm1_cfg = {
+ .tim = TIM4,
+ .irq = TIM4_IRQn,
+};
+#endif
+#if MYNEWT_VAL(PWM_2)
+struct stm32_pwm_conf os_bsp_pwm2_cfg = {
+ .tim = TIM12,
+ .irq = TIM8_BRK_TIM12_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_1)
+const struct stm32_uart_cfg os_bsp_uart1_cfg = {
+ .suc_uart = USART1,
+ .suc_rcc_reg = &RCC->APB2ENR,
+ .suc_rcc_dev = RCC_APB2ENR_USART1EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_1_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_1_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_1_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_1_PIN_CTS),
+ .suc_pin_af = GPIO_AF7_USART1,
+ .suc_irqn = USART1_IRQn
+};
+#endif
+
+#if MYNEWT_VAL(UART_2)
+const struct stm32_uart_cfg os_bsp_uart2_cfg = {
+ .suc_uart = USART2,
+ .suc_rcc_reg = &RCC->APB1LENR,
+ .suc_rcc_dev = RCC_APB1LENR_USART2EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_2_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_2_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_2_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_2_PIN_CTS),
+ .suc_pin_af = GPIO_AF7_USART2,
+ .suc_irqn = USART2_IRQn
+};
+#endif
+
+#if MYNEWT_VAL(UART_3)
+const struct stm32_uart_cfg os_bsp_uart3_cfg = {
+ .suc_uart = USART3,
+ .suc_rcc_reg = &RCC->APB1LENR,
+ .suc_rcc_dev = RCC_APB1LENR_USART3EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_3_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_3_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_3_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_3_PIN_CTS),
+ .suc_pin_af = GPIO_AF7_USART3,
+ .suc_irqn = USART3_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = {
+ .hic_i2c = I2C1,
+ .hic_rcc_reg = &RCC->APB1LENR,
+ .hic_rcc_dev = RCC_APB1LENR_I2C1EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C1,
+ .hic_10bit = 0,
+ .hic_speed = 100000, /* 100kHz */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = {
+ .hic_i2c = I2C2,
+ .hic_rcc_reg = &RCC->APB1LENR,
+ .hic_rcc_dev = RCC_APB1LENR_I2C2EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C2,
+ .hic_10bit = 0,
+ .hic_speed = 100000, /* 100kHz */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+const struct stm32_hal_i2c_cfg os_bsp_i2c3_cfg = {
+ .hic_i2c = I2C3,
+ .hic_rcc_reg = &RCC->APB1LENR,
+ .hic_rcc_dev = RCC_APB1LENR_I2C3EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_3_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_3_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C3,
+ .hic_10bit = 0,
+ .hic_speed = 100000, /* 100kHz */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_4)
+const struct stm32_hal_i2c_cfg os_bsp_i2c4_cfg = {
+ .hic_i2c = I2C4,
+ .hic_rcc_reg = &RCC->APB4ENR,
+ .hic_rcc_dev = RCC_APB4ENR_I2C4EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_4_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_4_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C4,
+ .hic_10bit = 0,
+ .hic_speed = 100000, /* 100kHz */
+};
+#endif
+
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+ [0] = {
+ .hbmd_start = &_ram_start,
+ .hbmd_size = RAM_SIZE,
+ },
+ [1] = {
+ .hbmd_start = &_dtcmram_start,
+ .hbmd_size = DTCMRAM_SIZE,
+ },
+ [2] = {
+ .hbmd_start = &_itcmram_start,
+ .hbmd_size = ITCMRAM_SIZE,
+ },
+};
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+void
+hal_bsp_init(void)
+{
+ stm32_periph_create();
+}
+
+void
+hal_bsp_deinit(void)
+{
+ RCC->AHB1ENR = 0;
+ RCC->AHB2ENR = 0;
+ RCC->AHB3ENR = 0;
+ RCC->AHB4ENR = 0;
+
+ RCC->APB1LENR = 0;
+ RCC->APB1HENR = 0;
+ RCC->APB2ENR = 0;
+ RCC->APB3ENR = 0;
+ RCC->APB4ENR = 0x00010000;
+
+ RCC->AHB1RSTR = 0x06038203;
+ RCC->AHB2RSTR = 0x60030271;
+ RCC->AHB3RSTR = 0x00E95011;
+ RCC->AHB4RSTR = 0x132806FF;
+
+ RCC->APB1LRSTR = 0xEAFFC3FF;
+ RCC->APB1HRSTR = 0x03000136;
+ RCC->APB2RSTR = 0x40A730F3;
+ RCC->APB3RSTR = 0x00000008;
+ RCC->APB4RSTR = 0x0420DEAA;
+
+ RCC->AHB1RSTR = 0;
+ RCC->AHB2RSTR = 0;
+ RCC->AHB3RSTR = 0;
+ RCC->AHB4RSTR = 0;
+
+ RCC->APB1LRSTR = 0;
+ RCC->APB1HRSTR = 0;
+ RCC->APB2RSTR = 0;
+ RCC->APB3RSTR = 0;
+ RCC->APB4RSTR = 0;
+}
+
+/**
+ * Returns the configured priority for the given interrupt. If no priority
+ * configured, return the priority passed in
+ *
+ * @param irq_num
+ * @param pri
+ *
+ * @return uint32_t
+ */
+uint32_t
+hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
+{
+ /* Add any interrupt priorities configured by the bsp here */
+ return pri;
+}
diff --git a/hw/bsp/weact_h743vi/syscfg.yml b/hw/bsp/weact_h743vi/syscfg.yml
new file mode 100644
index 000000000..0e448c0c3
--- /dev/null
+++ b/hw/bsp/weact_h743vi/syscfg.yml
@@ -0,0 +1,103 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.vals:
+ SPIFLASH_FLASH_ID: 2
+ STM32_FLASH_SIZE_KB: 2048
+ STM32_FLASH_NUM_AREAS: 16
+ # Image 1 (1920kB) with 4kB sectors in SPI flash
+ BOOTUTIL_MAX_IMG_SECTORS: 512
+ CONFIG_FCB_FLASH_AREA: FLASH_AREA_CONFIG
+ REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
+ COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
+ MCU_RAM_START: 0x24000000
+ MCU_RAM_SIZE: 512K
+ STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE0'
+ STM32_CLOCK_HSI: 1
+ STM32_CLOCK_HSE: 1
+ STM32_CLOCK_HSE_BYPASS: 0
+ STM32_CLOCK_PLL_PLLM: 5
+ STM32_CLOCK_PLL_PLLN: 192
+ STM32_CLOCK_PLL_PLLP: 2
+ STM32_CLOCK_PLL_PLLQ: 20
+ STM32_CLOCK_PLL_PLLR: 2
+ STM32_CLOCK_AHB_DIVIDER: 'RCC_HCLK_DIV2'
+ STM32_CLOCK_APB1_DIVIDER: 'RCC_APB1_DIV2'
+ STM32_CLOCK_APB2_DIVIDER: 'RCC_APB2_DIV2'
+ STM32_CLOCK_APB3_DIVIDER: 'RCC_APB3_DIV2'
+ STM32_CLOCK_APB4_DIVIDER: 'RCC_APB4_DIV2'
+ STM32_CLOCK_PLLRGE: 'RCC_PLL1VCIRANGE_3'
+ STM32_FLASH_LATENCY: 'FLASH_LATENCY_4'
+ STM32_ENABLE_ICACHE: 1
+ WATCHDOG_INTERVAL: 28000
+ UART_1_PIN_TX: 'MCU_GPIO_PORTA(9)'
+ UART_1_PIN_RX: 'MCU_GPIO_PORTA(10)'
+ # USART3 (PD8/PD9) is UART_3, there is no UART_0
+ UART_0: 0
+ UART_3: 1
+ UART_3_PIN_TX: 'MCU_GPIO_PORTD(8)'
+ UART_3_PIN_RX: 'MCU_GPIO_PORTD(9)'
+ CONSOLE_UART_DEV: '"uart3"'
+ SPI_0_PIN_SS: -1
+ SPI_0_PIN_SCK: 'MCU_GPIO_PORTB(3)'
+ SPI_0_PIN_MISO: 'MCU_GPIO_PORTB(4)'
+ SPI_0_PIN_MOSI: 'MCU_GPIO_PORTD(7)'
+ I2C_1_PIN_SCL: 'MCU_GPIO_PORTB(8)'
+ I2C_1_PIN_SDA: 'MCU_GPIO_PORTB(9)'
+ I2C_2_PIN_SCL: 'MCU_GPIO_PORTB(10)'
+ I2C_2_PIN_SDA: 'MCU_GPIO_PORTB(11)'
+ I2C_3_PIN_SCL: 'MCU_GPIO_PORTA(8)'
+ I2C_3_PIN_SDA: 'MCU_GPIO_PORTC(9)'
+ # PD12/PD13 are also QSPI flash IO1/IO3
+ I2C_4_PIN_SCL: 'MCU_GPIO_PORTD(12)'
+ I2C_4_PIN_SDA: 'MCU_GPIO_PORTD(13)'
+ TIMER_0_TIM: 'TIM12'
+ TIMER_1_TIM: 'TIM13'
+ TIMER_2_TIM: 'TIM14'
+
+ # SPI flash on SPI1 (SPI_0): Winbond W25Q64JV, 8MB, holds image 1
+ SPIFLASH: 1
+ SPI_0_MASTER: 1
+ SPIFLASH_SPI_NUM: 0
+ SPIFLASH_SPI_CS_PIN: 'MCU_GPIO_PORTD(6)'
+ SPIFLASH_SPI_MODE: 0
+ SPIFLASH_BAUDRATE: 8000
+ SPIFLASH_SECTOR_SIZE: 4096
+ SPIFLASH_PAGE_SIZE: 256
+ SPIFLASH_SECTOR_COUNT: 2048
+ SPIFLASH_W25Q64JV: 1
+ # spi_stm32 DMA transfers return stale data on H7 (D-cache)
+ SPI_STM32_MIN_RX_LENGTH_FOR_DMA: -1
+ SPI_STM32_MIN_TX_LENGTH_FOR_DMA: -1
+
+ # Flasher parameters
+ MYNEWT_DOWNLOADER: stm32_programmer_cli
+ MYNEWT_DOWNLOADER_MFG_IMAGE_FLASH_OFFSET: 0x08000000
+ JLINK_TARGET: STM32H743VI
+
+# QSPI flash: Winbond W25Q64JV, 8MB
+syscfg.vals.STM32_QSPI_FLASH:
+ STM32_QSPI_FLASH_PIN_CS: MCU_AFIO_PORTB(6, GPIO_AF10_QUADSPI)
+ STM32_QSPI_FLASH_PIN_SCK: MCU_AFIO_PORTB(2, GPIO_AF9_QUADSPI)
+ STM32_QSPI_FLASH_PIN_DIO0: MCU_AFIO_PORTD(11, GPIO_AF9_QUADSPI)
+ STM32_QSPI_FLASH_PIN_DIO1: MCU_AFIO_PORTD(12, GPIO_AF9_QUADSPI)
+ STM32_QSPI_FLASH_PIN_DIO2: MCU_AFIO_PORTE(2, GPIO_AF9_QUADSPI)
+ STM32_QSPI_FLASH_PIN_DIO3: MCU_AFIO_PORTD(13, GPIO_AF9_QUADSPI)
+ STM32_QSPI_FLASH_SECTOR_COUNT: 2048
+