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Posted to commits@nuttx.apache.org by xi...@apache.org on 2023/07/31 14:49:03 UTC
[nuttx] 03/08: riscv/riscv_fpu: Clear the full FPU status/control register on boot
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 0ea9debfceacb9e1989cdfc2572695a67a2a8116
Author: Ville Juven <vi...@unikie.com>
AuthorDate: Thu Jul 27 11:05:19 2023 +0300
riscv/riscv_fpu: Clear the full FPU status/control register on boot
Instead of clearing the fields individually, just wipe the whole register.
This can be done because flags and rm are just parts of the fcsr.
31 8 5 0
+--------------+--------+-----------+
| | | |
| RESERVED | FRM | FSTATUS |
| | | |
+--------------+--------+-----------+
FCSR
---
arch/risc-v/src/common/riscv_fpu.S | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/risc-v/src/common/riscv_fpu.S b/arch/risc-v/src/common/riscv_fpu.S
index 9d5feb9390..cc88e769dd 100644
--- a/arch/risc-v/src/common/riscv_fpu.S
+++ b/arch/risc-v/src/common/riscv_fpu.S
@@ -69,8 +69,7 @@ riscv_fpuconfig:
li a0, MSTATUS_FS_INIT
csrs CSR_STATUS, a0
- fsflags zero
- fsrm zero
+ fscsr zero
fence.i
ret