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Posted to commits@nuttx.apache.org by gn...@apache.org on 2020/04/26 17:35:19 UTC
[incubator-nuttx] branch master updated (0106033 -> b2c7f1e)
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 0106033 More compliance to the naming standard.
new 4cb8be9 arch/arm/src/stm32/stm32_adc.c: move adc_offset_set to llops section
new a85ffd0 arch/arm/src/stm32/stm32_adc.c: enable callback logic if DMA enabled
new 0e09d16 arch/arm/src/stm32/stm32_adc.c: fix injected channels configuration for ADC IPv1
new 1b4e0fd arch/arm/src/stm32/stm32_adc.h: move generalized ADC definitions to the header file
new f837bfe arch/arm/src/stm32/stm32_adc.h: add prefix STM32 to low-level ops macros
new 6b7b18e boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c: fix nxstyle issues
new 7cdd9b1 boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c: fix nxstyle issues
new a916000 boards/arm/stm32/stm32f334-disco/src/stm32_smps.c fix nxstyle issues
new b2c7f1e boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c: fix nxstyle issues
The 9 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/stm32/stm32_adc.c | 200 ++++++++++-----------
arch/arm/src/stm32/stm32_adc.h | 65 +++++--
boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c | 18 +-
boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c | 20 ++-
boards/arm/stm32/stm32f334-disco/src/stm32_smps.c | 155 +++++++++-------
.../arm/stm32/stm32f429i-disco/src/stm32_highpri.c | 18 +-
6 files changed, 269 insertions(+), 207 deletions(-)
[incubator-nuttx] 04/09: arch/arm/src/stm32/stm32_adc.h: move
generalized ADC definitions to the header file
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 1b4e0fddb886c711b10d765ea4dd1f90230d79fd
Author: raiden00pl <ra...@railab.me>
AuthorDate: Tue Apr 21 21:46:14 2020 +0200
arch/arm/src/stm32/stm32_adc.h: move generalized ADC definitions to the header file
---
arch/arm/src/stm32/stm32_adc.c | 39 ---------------------------------------
arch/arm/src/stm32/stm32_adc.h | 39 +++++++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c
index 02fa5e8..d3172d6 100644
--- a/arch/arm/src/stm32/stm32_adc.c
+++ b/arch/arm/src/stm32/stm32_adc.c
@@ -159,45 +159,6 @@
# define RCC_RSTR_ADC34RST RCC_AHBRSTR_ADC34RST
#endif
-/* ADC interrupts ***********************************************************/
-
-#if defined(HAVE_IP_ADC_V1)
-# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CR2_OFFSET
-# define ADC_DMAREG_DMA ADC_CR2_DMA
-# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CR2_OFFSET
-# define ADC_EXTREG_EXTSEL_MASK ADC_CR2_EXTSEL_MASK
-# define STM32_ADC_JEXTREG_OFFSET STM32_ADC_CR2_OFFSET
-# define ADC_JEXTREG_JEXTSEL_MASK ADC_CR2_JEXTSEL_MASK
-# define STM32_ADC_ISR_OFFSET STM32_ADC_SR_OFFSET
-# define STM32_ADC_IER_OFFSET STM32_ADC_CR1_OFFSET
-# ifdef HAVE_BASIC_ADC
-# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTTRIG
-# define ADC_EXTREG_EXTEN_NONE 0
-# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTTRIG
-# define ADC_JEXTREG_JEXTEN_MASK ADC_CR2_JEXTTRIG
-# define ADC_JEXTREG_JEXTEN_NONE 0
-# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_CR2_JEXTTRIG
-# else
-# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTEN_MASK
-# define ADC_EXTREG_EXTEN_NONE ADC_CR2_EXTEN_NONE
-# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTEN_RISING
-# define ADC_JEXTREG_JEXTEN_MASK ADC_CR2_JEXTEN_MASK
-# define ADC_JEXTREG_JEXTEN_NONE ADC_CR2_JEXTEN_NONE
-# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_CR2_JEXTEN_RISING
-# endif
-#elif defined(HAVE_IP_ADC_V2)
-# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR1_OFFSET
-# define ADC_DMAREG_DMA ADC_CFGR1_DMAEN
-# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR1_OFFSET
-# define ADC_EXTREG_EXTSEL_MASK ADC_CFGR1_EXTSEL_MASK
-# define ADC_EXTREG_EXTEN_MASK ADC_CFGR1_EXTEN_MASK
-# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR1_EXTEN_RISING
-# define STM32_ADC_JEXTREG_OFFSET STM32_ADC_JSQR_OFFSET
-# define ADC_JEXTREG_JEXTSEL_MASK ADC_JSQR_JEXTSEL_MASK
-# define ADC_JEXTREG_JEXTEN_MASK ADC_JSQR_JEXTEN_MASK
-# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_JSQR_JEXTEN_RISING
-#endif
-
/* ADC Channels/DMA *********************************************************/
/* The maximum number of channels that can be sampled. If DMA support is
diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/stm32/stm32_adc.h
index a807823..cae8f83 100644
--- a/arch/arm/src/stm32/stm32_adc.h
+++ b/arch/arm/src/stm32/stm32_adc.h
@@ -54,6 +54,45 @@
* Pre-processor Definitions
************************************************************************************/
+/* Generalized definitions for ADC *************************************************/
+
+#if defined(HAVE_IP_ADC_V1)
+# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CR2_OFFSET
+# define ADC_DMAREG_DMA ADC_CR2_DMA
+# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CR2_OFFSET
+# define ADC_EXTREG_EXTSEL_MASK ADC_CR2_EXTSEL_MASK
+# define STM32_ADC_JEXTREG_OFFSET STM32_ADC_CR2_OFFSET
+# define ADC_JEXTREG_JEXTSEL_MASK ADC_CR2_JEXTSEL_MASK
+# define STM32_ADC_ISR_OFFSET STM32_ADC_SR_OFFSET
+# define STM32_ADC_IER_OFFSET STM32_ADC_CR1_OFFSET
+# ifdef HAVE_BASIC_ADC
+# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTTRIG
+# define ADC_EXTREG_EXTEN_NONE 0
+# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTTRIG
+# define ADC_JEXTREG_JEXTEN_MASK ADC_CR2_JEXTTRIG
+# define ADC_JEXTREG_JEXTEN_NONE 0
+# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_CR2_JEXTTRIG
+# else
+# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTEN_MASK
+# define ADC_EXTREG_EXTEN_NONE ADC_CR2_EXTEN_NONE
+# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTEN_RISING
+# define ADC_JEXTREG_JEXTEN_MASK ADC_CR2_JEXTEN_MASK
+# define ADC_JEXTREG_JEXTEN_NONE ADC_CR2_JEXTEN_NONE
+# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_CR2_JEXTEN_RISING
+# endif
+#elif defined(HAVE_IP_ADC_V2)
+# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR1_OFFSET
+# define ADC_DMAREG_DMA ADC_CFGR1_DMAEN
+# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR1_OFFSET
+# define ADC_EXTREG_EXTSEL_MASK ADC_CFGR1_EXTSEL_MASK
+# define ADC_EXTREG_EXTEN_MASK ADC_CFGR1_EXTEN_MASK
+# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR1_EXTEN_RISING
+# define STM32_ADC_JEXTREG_OFFSET STM32_ADC_JSQR_OFFSET
+# define ADC_JEXTREG_JEXTSEL_MASK ADC_JSQR_JEXTSEL_MASK
+# define ADC_JEXTREG_JEXTEN_MASK ADC_JSQR_JEXTEN_MASK
+# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_JSQR_JEXTEN_RISING
+#endif
+
/* Configuration ********************************************************************/
/* Timer devices may be used for different purposes. One special purpose is to
[incubator-nuttx] 08/09:
boards/arm/stm32/stm32f334-disco/src/stm32_smps.c fix nxstyle issues
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit a91600050b435926362bca8adb65c3bec8a60610
Author: raiden00pl <ra...@railab.me>
AuthorDate: Sat Apr 25 21:04:45 2020 +0200
boards/arm/stm32/stm32f334-disco/src/stm32_smps.c fix nxstyle issues
---
boards/arm/stm32/stm32f334-disco/src/stm32_smps.c | 135 +++++++++++++---------
1 file changed, 82 insertions(+), 53 deletions(-)
diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c b/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c
index 017473b..5240e17 100644
--- a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c
+++ b/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c
@@ -201,7 +201,7 @@ enum converter_mode_e
CONVERTER_MODE_INIT, /* Initial mode */
CONVERTER_MODE_BUCK, /* Buck mode operations (V_in > V_out) */
CONVERTER_MODE_BOOST, /* Boost mode operations (V_in < V_out) */
- CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out)*/
+ CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out) */
};
/* SMPS lower drivers structure */
@@ -396,7 +396,7 @@ static int smps_setup(FAR struct smps_dev_s *dev)
/* Update ADC sample time */
- for (i = 0; i < ADC1_NCHANNELS; i+= 1)
+ for (i = 0; i < ADC1_NCHANNELS; i += 1)
{
channels[i].sample_time = ADC_SMPR_61p5;
channels[i].channel = g_adc1chan[i];
@@ -450,7 +450,7 @@ static int smps_start(FAR struct smps_dev_s *dev)
/* Get TIMA period value for given frequency */
fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMA);
- per = fclk/TIMA_PWM_FREQ;
+ per = fclk / TIMA_PWM_FREQ;
if (per > HRTIM_PER_MAX)
{
pwrerr("ERROR: Can not achieve tima pwm freq=%u if fclk=%llu\n",
@@ -466,7 +466,7 @@ static int smps_start(FAR struct smps_dev_s *dev)
/* Get TIMB period value for given frequency */
fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMB);
- per = fclk/TIMB_PWM_FREQ;
+ per = fclk / TIMB_PWM_FREQ;
if (per > HRTIM_PER_MAX)
{
pwrerr("ERROR: Can not achieve timb pwm freq=%u if fclk=%llu\n",
@@ -485,14 +485,18 @@ static int smps_start(FAR struct smps_dev_s *dev)
/* Configure TIMER A and TIMER B deadtime mode
*
- * NOTE: In deadtime mode we have to configure output 1 only (SETx1, RSTx1),
- * output 2 configuration is not significant.
+ * NOTE: In deadtime mode we have to configure output 1 only
+ * (SETx1, RSTx1), output 2 configuration is not significant.
*/
- HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_RISING, DT_RISING);
- HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_FALLING, DT_FALLING);
- HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_RISING, DT_RISING);
- HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_FALLING, DT_FALLING);
+ HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_RISING,
+ DT_RISING);
+ HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_FALLING,
+ DT_FALLING);
+ HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_RISING,
+ DT_RISING);
+ HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_FALLING,
+ DT_FALLING);
/* Set T4 and T12 to a low state.
* Deadtime mode force T11 and T5 to a high state.
@@ -635,28 +639,28 @@ static int smps_limits_set(FAR struct smps_dev_s *dev,
if (limits->v_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT)
{
- limits->v_out = (float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT/1000.0;
+ limits->v_out = (float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT / 1000.0;
pwrwarn("WARNING: "
- "SMPS output voltage limiit > SMPS absolute output voltage limit."
- " Set output voltage limit to %.2f.\n",
+ "SMPS output voltage limiit > SMPS absolute output voltage "
+ "limit. Set output voltage limit to %.2f.\n",
limits->v_out);
}
if (limits->v_in * 1000 > CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT)
{
- limits->v_in = (float)CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT/1000.0;
+ limits->v_in = (float)CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT / 1000.0;
pwrwarn("WARNING: "
- "SMPS input voltage limiit > SMPS absolute input voltage limit."
- " Set input voltage limit to %.2f.\n",
+ "SMPS input voltage limiit > SMPS absolute input voltage "
+ "limit. Set input voltage limit to %.2f.\n",
limits->v_in);
}
if (limits->i_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT)
{
- limits->i_out = (float)CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT/1000.0;
+ limits->i_out = (float)CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT / 1000.0;
pwrwarn("WARNING: "
- "SMPS output current limiit > SMPS absolute output current limit."
- " Set output current limit to %.2f.\n",
+ "SMPS output current limiit > SMPS absolute output current "
+ "limit. Set output current limit to %.2f.\n",
limits->i_out);
}
@@ -738,7 +742,8 @@ static float smps_controller(FAR struct smps_priv_s *priv, float err)
* Name: smps_duty_set
****************************************************************************/
-static void smps_duty_set(struct smps_priv_s *priv, struct smps_lower_dev_s *lower,
+static void smps_duty_set(struct smps_priv_s *priv,
+ struct smps_lower_dev_s *lower,
float out)
{
FAR struct hrtim_dev_s *hrtim = lower->hrtim;
@@ -761,7 +766,7 @@ static void smps_duty_set(struct smps_priv_s *priv, struct smps_lower_dev_s *low
if (out >= priv->v_in) out = priv->v_in;
if (out < 0.0) out = 0.0;
- duty = out/priv->v_in;
+ duty = out / priv->v_in;
#warning TODO: current limit in buck mode
@@ -769,7 +774,7 @@ static void smps_duty_set(struct smps_priv_s *priv, struct smps_lower_dev_s *low
cmp = (uint16_t)(per * duty);
- if (cmp > per-30) cmp = per - 30;
+ if (cmp > per - 30) cmp = per - 30;
/* Set T4 duty cycle. T11 is complementary to T4 */
@@ -785,7 +790,7 @@ static void smps_duty_set(struct smps_priv_s *priv, struct smps_lower_dev_s *low
if (out < priv->v_in) out = priv->v_in;
if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX;
- duty = 1.0 - priv->v_in/out;
+ duty = 1.0 - priv->v_in / out;
#warning TODO: current limit in boost mode
@@ -809,7 +814,7 @@ static void smps_duty_set(struct smps_priv_s *priv, struct smps_lower_dev_s *low
if (out < priv->v_in) out = priv->v_in;
if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX;
- duty = 1.0 - priv->v_in/out;
+ duty = 1.0 - priv->v_in / out;
#warning TODO: current limit in buck boost mode
@@ -841,7 +846,8 @@ static void smps_duty_set(struct smps_priv_s *priv, struct smps_lower_dev_s *low
*
****************************************************************************/
-static void smps_conv_mode_set(struct smps_priv_s *priv, struct smps_lower_dev_s *lower,
+static void smps_conv_mode_set(struct smps_priv_s *priv,
+ struct smps_lower_dev_s *lower,
uint8_t mode)
{
FAR struct hrtim_dev_s *hrtim = lower->hrtim;
@@ -854,7 +860,6 @@ static void smps_conv_mode_set(struct smps_priv_s *priv, struct smps_lower_dev_s
{
case CONVERTER_MODE_INIT:
{
-
break;
}
@@ -862,15 +867,19 @@ static void smps_conv_mode_set(struct smps_priv_s *priv, struct smps_lower_dev_s
{
/* Set T12 low (T5 high) on the next PER */
- HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_SET_NONE);
- HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_RST_PER);
-
+ HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1,
+ HRTIM_OUT_SET_NONE);
+ HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1,
+ HRTIM_OUT_RST_PER);
/* Set T4 to a high state on PER and reset on CMP1.
- T11 is complementary to T4. */
+ * T11 is complementary to T4.
+ */
- HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_SET_PER);
- HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_RST_CMP1);
+ HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1,
+ HRTIM_OUT_SET_PER);
+ HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1,
+ HRTIM_OUT_RST_CMP1);
break;
}
@@ -879,14 +888,19 @@ static void smps_conv_mode_set(struct smps_priv_s *priv, struct smps_lower_dev_s
{
/* Set T4 high (T11 low) on the next PER */
- HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_SET_PER);
- HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_RST_NONE);
+ HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1,
+ HRTIM_OUT_SET_PER);
+ HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1,
+ HRTIM_OUT_RST_NONE);
/* Set T12 to a high state on PER and reset on CMP1.
- T5 is complementary to T12. */
+ * T5 is complementary to T12.
+ */
- HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_SET_PER);
- HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_RST_CMP1);
+ HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1,
+ HRTIM_OUT_SET_PER);
+ HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1,
+ HRTIM_OUT_RST_CMP1);
break;
}
@@ -894,22 +908,28 @@ static void smps_conv_mode_set(struct smps_priv_s *priv, struct smps_lower_dev_s
case CONVERTER_MODE_BUCKBOOST:
{
/* Set T4 to a high state on PER and reset on CMP1.
- T11 is complementary to T4. */
+ * T11 is complementary to T4.
+ */
- HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_SET_PER);
- HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_RST_CMP1);
+ HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1,
+ HRTIM_OUT_SET_PER);
+ HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1,
+ HRTIM_OUT_RST_CMP1);
/* Set T12 to a high state on PER and reset on CMP1.
- T5 is complementary to T12. */
+ * T5 is complementary to T12.
+ */
- HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_SET_PER);
- HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_RST_CMP1);
+ HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1,
+ HRTIM_OUT_SET_PER);
+ HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1,
+ HRTIM_OUT_RST_CMP1);
/* Set fixed duty cycle (80%) on buck converter (T4 and T11) */
HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP1,
- 0.8 * ((uint16_t)HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA)));
-
+ 0.8 * ((uint16_t)HRTIM_PER_GET(hrtim,
+ HRTIM_TIMER_TIMA)));
break;
}
@@ -962,25 +982,33 @@ static void adc12_handler(void)
priv->v_out = (priv->v_out_raw * ref / bit) * V_OUT_RATIO;
priv->v_in = (priv->v_in_raw * ref / bit) * V_IN_RATIO;
- /* According to measured voltages we set converter in appropriate mode */
+ /* According to measured voltages we set converter
+ * in appropriate mode
+ */
- if (smps->param.v_out > (priv->v_in+SMPS_BUCKBOOST_RANGE))
+ if (smps->param.v_out > (priv->v_in + SMPS_BUCKBOOST_RANGE))
{
- /* Desired output voltage greater than input voltage - set boost converter */
+ /* Desired output voltage greater than input voltage - set
+ * boost converter
+ */
mode = CONVERTER_MODE_BOOST;
}
- else if (smps->param.v_out < (priv->v_in-SMPS_BUCKBOOST_RANGE))
+ else if (smps->param.v_out < (priv->v_in - SMPS_BUCKBOOST_RANGE))
{
- /* Desired output voltage lower than input voltage - set buck converter */
+ /* Desired output voltage lower than input voltage - set
+ * buck converter
+ */
mode = CONVERTER_MODE_BUCK;
}
else
{
- /* Desired output voltage close to input voltage - set buck-boost converter */
+ /* Desired output voltage close to input voltage - set
+ * buck-boost converter
+ */
mode = CONVERTER_MODE_BUCKBOOST;
}
@@ -1101,8 +1129,9 @@ int stm32_smps_setup(void)
adc->ad_ops->ao_setup(adc);
- /* We do not need register character drivers for SMPS lower peripherals.
- * All control should be done via SMPS character driver.
+ /* We do not need register character drivers for SMPS lower
+ * peripherals. All control should be done via SMPS character
+ * driver.
*/
ret = smps_register(CONFIG_EXAMPLES_SMPS_DEVPATH, smps, (void *)lower);
[incubator-nuttx] 05/09: arch/arm/src/stm32/stm32_adc.h: add prefix
STM32 to low-level ops macros
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit f837bfecdbd5af5a44e267f725138c32527ca69f
Author: raiden00pl <ra...@railab.me>
AuthorDate: Sat Apr 25 20:51:44 2020 +0200
arch/arm/src/stm32/stm32_adc.h: add prefix STM32 to low-level ops macros
---
arch/arm/src/stm32/stm32_adc.h | 26 +++++++++++-----------
boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c | 14 ++++++------
boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c | 14 ++++++------
boards/arm/stm32/stm32f334-disco/src/stm32_smps.c | 20 ++++++++---------
.../arm/stm32/stm32f429i-disco/src/stm32_highpri.c | 14 ++++++------
5 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/stm32/stm32_adc.h
index cae8f83..04338f3 100644
--- a/arch/arm/src/stm32/stm32_adc.h
+++ b/arch/arm/src/stm32/stm32_adc.h
@@ -1948,31 +1948,31 @@
/* Low-level ops helpers ************************************************************/
-#define ADC_INT_ACK(adc, source) \
+#define STM32_ADC_INT_ACK(adc, source) \
(adc)->llops->int_ack(adc, source)
-#define ADC_INT_GET(adc) \
+#define STM32_ADC_INT_GET(adc) \
(adc)->llops->int_get(adc)
-#define ADC_INT_ENABLE(adc, source) \
+#define STM32_ADC_INT_ENABLE(adc, source) \
(adc)->llops->int_en(adc, source)
-#define ADC_INT_DISABLE(adc, source) \
+#define STM32_ADC_INT_DISABLE(adc, source) \
(adc)->llops->int_dis(adc, source)
-#define ADC_REGDATA_GET(adc) \
+#define STM32_ADC_REGDATA_GET(adc) \
(adc)->llops->val_get(adc)
-#define ADC_REGBUF_REGISTER(adc, buffer, len) \
+#define STM32_ADC_REGBUF_REGISTER(adc, buffer, len) \
(adc)->llops->regbuf_reg(adc, buffer, len)
-#define ADC_REG_STARTCONV(adc, state) \
+#define STM32_ADC_REG_STARTCONV(adc, state) \
(adc)->llops->reg_startconv(adc, state)
-#define ADC_OFFSET_SET(adc, ch, i, o) \
+#define STM32_ADC_OFFSET_SET(adc, ch, i, o) \
(adc)->llops->offset_set(adc, ch, i, o)
-#define ADC_INJ_STARTCONV(adc, state) \
+#define STM32_ADC_INJ_STARTCONV(adc, state) \
(adc)->llops->inj_startconv(adc, state)
-#define ADC_INJDATA_GET(adc, chan) \
+#define STM32_ADC_INJDATA_GET(adc, chan) \
(adc)->llops->inj_get(adc, chan)
-#define ADC_SAMPLETIME_SET(adc, time_samples) \
+#define STM32_ADC_SAMPLETIME_SET(adc, time_samples) \
(adc)->llops->stime_set(adc, time_samples)
-#define ADC_SAMPLETIME_WRITE(adc) \
+#define STM32_ADC_SAMPLETIME_WRITE(adc) \
(adc)->llops->stime_write(adc)
-#define ADC_DUMP_REGS(adc) \
+#define STM32_ADC_DUMP_REGS(adc) \
(adc)->llops->dump_regs(adc)
/************************************************************************************
diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c
index c7c22ef..2f9eba6 100644
--- a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c
+++ b/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c
@@ -220,7 +220,7 @@ void adc12_handler(void)
/* Get pending ADC interrupts */
- pending = ADC_INT_GET(adc);
+ pending = STM32_ADC_INT_GET(adc);
if (g_highpri.lock == true)
{
@@ -238,7 +238,7 @@ void adc12_handler(void)
/* Get regular data */
- g_highpri.r_val[g_highpri.current] = ADC_REGDATA_GET(adc);
+ g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc);
/* Do some floating point operations */
@@ -269,7 +269,7 @@ void adc12_handler(void)
for (i = 0; i < INJ_NCHANNELS; i += 1)
{
- g_highpri.j_val[i] = ADC_INJDATA_GET(adc, i);
+ g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i);
}
/* Do some floating point operations */
@@ -284,7 +284,7 @@ void adc12_handler(void)
irq_out:
/* Clear ADC pending interrupts */
- ADC_INT_ACK(adc, pending);
+ STM32_ADC_INT_ACK(adc, pending);
}
#endif
@@ -478,17 +478,17 @@ int highpri_main(int argc, char *argv[])
#ifndef CONFIG_STM32_ADC1_DMA
/* Enable ADC regular conversion interrupts if no DMA */
- ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
+ STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
#else
/* Register ADC buffer for DMA transfer */
- ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
+ STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
#endif
#ifdef HIGHPRI_HAVE_INJECTED
/* Enable ADC injected sequence end interrupts */
- ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS);
+ STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS);
#endif
#ifdef HIGHPRI_HAVE_TIM1
diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c
index 50b105c..221965c 100644
--- a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c
+++ b/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c
@@ -235,7 +235,7 @@ void adc12_handler(void)
/* Get pending ADC interrupts */
- pending = ADC_INT_GET(adc);
+ pending = STM32_ADC_INT_GET(adc);
if (g_highpri.lock == true)
{
@@ -253,7 +253,7 @@ void adc12_handler(void)
/* Get regular data */
- g_highpri.r_val[g_highpri.current] = ADC_REGDATA_GET(adc);
+ g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc);
/* Do some floating point operations */
@@ -284,7 +284,7 @@ void adc12_handler(void)
for (i = 0; i < INJ_NCHANNELS; i += 1)
{
- g_highpri.j_val[i] = ADC_INJDATA_GET(adc, i);
+ g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i);
}
/* Do some floating point operations */
@@ -299,7 +299,7 @@ void adc12_handler(void)
irq_out:
/* Clear ADC pending interrupts */
- ADC_INT_ACK(adc, pending);
+ STM32_ADC_INT_ACK(adc, pending);
}
#endif
@@ -514,17 +514,17 @@ int highpri_main(int argc, char *argv[])
#ifndef CONFIG_STM32_ADC1_DMA
/* Enable ADC regular conversion interrupts if no DMA */
- ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
+ STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
#else
/* Register ADC buffer for DMA transfer */
- ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
+ STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
#endif
#ifdef HIGHPRI_HAVE_INJECTED
/* Enable ADC injected sequence end interrupts */
- ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS);
+ STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS);
#endif
#ifdef HIGHPRI_HAVE_HRTIM
diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c b/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c
index e13716f..017473b 100644
--- a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c
+++ b/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c
@@ -407,8 +407,8 @@ static int smps_setup(FAR struct smps_dev_s *dev)
stime.channels_nbr = ADC1_NCHANNELS;
stime.channel = channels;
- ADC_SAMPLETIME_SET(adc, &stime);
- ADC_SAMPLETIME_WRITE(adc);
+ STM32_ADC_SAMPLETIME_SET(adc, &stime);
+ STM32_ADC_SAMPLETIME_WRITE(adc);
/* TODO: create current limit table */
@@ -512,7 +512,7 @@ static int smps_start(FAR struct smps_dev_s *dev)
/* Enable ADC JEOS interrupts */
- ADC_INT_ENABLE(adc, ADC_INT_JEOS);
+ STM32_ADC_INT_ENABLE(adc, ADC_INT_JEOS);
/* Enable ADC12 interrupts */
@@ -520,7 +520,7 @@ static int smps_start(FAR struct smps_dev_s *dev)
/* Start injected conversion */
- ADC_INJ_STARTCONV(adc, true);
+ STM32_ADC_INJ_STARTCONV(adc, true);
errout:
return ret;
@@ -540,11 +540,11 @@ static int smps_stop(FAR struct smps_dev_s *dev)
/* Stop injected conversion */
- ADC_INJ_STARTCONV(adc, false);
+ STM32_ADC_INJ_STARTCONV(adc, false);
/* Disable ADC JEOS interrupts */
- ADC_INT_DISABLE(adc, ADC_INT_JEOS);
+ STM32_ADC_INT_DISABLE(adc, ADC_INT_JEOS);
/* Disable ADC12 interrupts */
@@ -948,14 +948,14 @@ static void adc12_handler(void)
float out;
uint8_t mode;
- pending = ADC_INT_GET(adc);
+ pending = STM32_ADC_INT_GET(adc);
if (pending & ADC_INT_JEOC && priv->running == true)
{
/* Get raw ADC values */
- priv->v_out_raw = ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL);
- priv->v_in_raw = ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL);
+ priv->v_out_raw = STM32_ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL);
+ priv->v_in_raw = STM32_ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL);
/* Convert raw values to real values */
@@ -1010,7 +1010,7 @@ static void adc12_handler(void)
/* Clear pending */
- ADC_INT_ACK(adc, pending);
+ STM32_ADC_INT_ACK(adc, pending);
}
/****************************************************************************
diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c
index 1f7f325..2c789cb 100644
--- a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c
+++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c
@@ -205,7 +205,7 @@ void adc_handler(void)
/* Get pending ADC1 interrupts */
- pending = ADC_INT_GET(adc);
+ pending = STM32_ADC_INT_GET(adc);
if (g_highpri.lock == true)
{
@@ -223,7 +223,7 @@ void adc_handler(void)
/* Get regular data */
- g_highpri.r_val[g_highpri.current] = ADC_REGDATA_GET(adc);
+ g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc);
/* Do some floating point operations */
@@ -254,7 +254,7 @@ void adc_handler(void)
for (i = 0; i < INJ_NCHANNELS; i += 1)
{
- g_highpri.j_val[i] = ADC_INJDATA_GET(adc, i);
+ g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i);
}
/* Do some floating point operations */
@@ -269,7 +269,7 @@ void adc_handler(void)
irq_out:
/* Clear ADC pending interrupts */
- ADC_INT_ACK(adc, pending);
+ STM32_ADC_INT_ACK(adc, pending);
}
#endif
@@ -463,7 +463,7 @@ int highpri_main(int argc, char *argv[])
#ifndef CONFIG_STM32_ADC1_DMA
/* Enable ADC regular conversion interrupts if no DMA */
- ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
+ STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC);
#else
/* Note: ADC and DMA must be reset after overrun occurs.
* For this example we assume that overrun will not occur.
@@ -473,13 +473,13 @@ int highpri_main(int argc, char *argv[])
/* Register ADC buffer for DMA transfer */
- ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
+ STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS);
#endif
#ifdef HIGHPRI_HAVE_INJECTED
/* Enable ADC injected channels end of conversion interrupts */
- ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOC);
+ STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOC);
#endif
#ifdef HIGHPRI_HAVE_TIM1
[incubator-nuttx] 02/09: arch/arm/src/stm32/stm32_adc.c: enable
callback logic if DMA enabled
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit a85ffd0fbde1e803908f958569076a44b1e88fc9
Author: raiden00pl <ra...@railab.me>
AuthorDate: Tue Apr 21 21:35:54 2020 +0200
arch/arm/src/stm32/stm32_adc.c: enable callback logic if DMA enabled
---
arch/arm/src/stm32/stm32_adc.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c
index 5ac3b58..f4ecc4e 100644
--- a/arch/arm/src/stm32/stm32_adc.c
+++ b/arch/arm/src/stm32/stm32_adc.c
@@ -460,6 +460,16 @@
# undef ADC_HAVE_DMACFG
#endif
+/* We have to support ADC callbacks if default ADC interrupts or
+ * DMA transfer are enabled
+ */
+
+#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_DMA)
+# define ADC_HAVE_CB
+#else
+# undef ADC_HAVE_CB
+#endif
+
/****************************************************************************
* Private Types
****************************************************************************/
@@ -483,7 +493,7 @@ struct stm32_dev_s
#ifdef CONFIG_STM32_ADC_LL_OPS
FAR const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */
#endif
-#ifndef CONFIG_STM32_ADC_NOIRQ
+#ifdef ADC_HAVE_CB
FAR const struct adc_callback_s *cb;
uint8_t irq; /* Interrupt generated by this ADC block */
#endif
@@ -2331,11 +2341,14 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr,
static int adc_bind(FAR struct adc_dev_s *dev,
FAR const struct adc_callback_s *callback)
{
-#ifndef CONFIG_STM32_ADC_NOIRQ
+#ifdef ADC_HAVE_CB
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
DEBUGASSERT(priv != NULL);
priv->cb = callback;
+#else
+ UNUSED(dev);
+ UNUSED(callback);
#endif
return OK;
@@ -2725,6 +2738,8 @@ static void adc_dma_start(FAR struct adc_dev_s *dev)
priv->dma = stm32_dmachannel(priv->dmachan);
#ifndef CONFIG_STM32_ADC_NOIRQ
+ /* Start DMA only if standard ADC interrupts used */
+
stm32_dmasetup(priv->dma,
priv->base + STM32_ADC_DR_OFFSET,
(uint32_t)priv->r_dmabuffer,
@@ -4708,7 +4723,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
priv->adc_channels = ADC_CHANNELS_NUMBER;
#endif
-#ifndef CONFIG_STM32_ADC_NOIRQ
+#ifdef ADC_HAVE_CB
priv->cb = NULL;
#endif
[incubator-nuttx] 06/09:
boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c: fix nxstyle issues
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 6b7b18e8351b2f26cccc3d284211c8ea14051dea
Author: raiden00pl <ra...@railab.me>
AuthorDate: Sat Apr 25 21:04:07 2020 +0200
boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c: fix nxstyle issues
---
boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c
index 2f9eba6..84c62bf 100644
--- a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c
+++ b/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c
@@ -245,7 +245,7 @@ void adc12_handler(void)
g_highpri.r_volt[g_highpri.current] =
(float)g_highpri.r_val[g_highpri.current] * ref / bit;
- if (g_highpri.current >= REG_NCHANNELS-1)
+ if (g_highpri.current >= REG_NCHANNELS - 1)
{
g_highpri.current = 0;
}
@@ -282,6 +282,7 @@ void adc12_handler(void)
#endif
irq_out:
+
/* Clear ADC pending interrupts */
STM32_ADC_INT_ACK(adc, pending);
@@ -323,6 +324,7 @@ void dma1ch1_handler(void)
}
irq_out:
+
/* Clear DMA pending interrupts */
stm32_dma_intack(STM32_DMA1_CHAN1, pending);
[incubator-nuttx] 03/09: arch/arm/src/stm32/stm32_adc.c: fix
injected channels configuration for ADC IPv1
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 0e09d162e24ade4d6f604c8c092e8092e31c3d95
Author: raiden00pl <ra...@railab.me>
AuthorDate: Tue Apr 21 21:37:47 2020 +0200
arch/arm/src/stm32/stm32_adc.c: fix injected channels configuration for ADC IPv1
---
arch/arm/src/stm32/stm32_adc.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c
index f4ecc4e..02fa5e8 100644
--- a/arch/arm/src/stm32/stm32_adc.c
+++ b/arch/arm/src/stm32/stm32_adc.c
@@ -3798,8 +3798,22 @@ static int adc_inj_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
for (i = 0 ; i < priv->cj_channels; i += 1)
{
+#if defined(HAVE_IP_ADC_V1)
+ /* Injected channels sequence for for ADC IPv1:
+ *
+ * 1 2 3 4
+ * IL=1: JSQR4,
+ * IL=2: JSQR3, JSQR4
+ * IL=3: JSQR2, JSQR3, JSQR4
+ * IL=4: JSQR1, JSQR2, JSQR3, JSQR4
+ */
+
+ setbits |= (priv->j_chanlist[priv->cj_channels - 1 - i] <<
+ (ADC_JSQR_JSQ4_SHIFT - ADC_JSQR_JSQ_SHIFT * i));
+#else
setbits |= priv->j_chanlist[i] << (ADC_JSQR_JSQ1_SHIFT +
- ADC_JSQR_JSQ_SHIFT * i);
+ ADC_JSQR_JSQ_SHIFT * i);
+#endif
}
/* Write register */
[incubator-nuttx] 07/09:
boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c: fix nxstyle issues
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 7cdd9b12213e0aa658652c18959ca61061822857
Author: raiden00pl <ra...@railab.me>
AuthorDate: Sat Apr 25 21:04:18 2020 +0200
boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c: fix nxstyle issues
---
boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c
index 221965c..1d6bbfa 100644
--- a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c
+++ b/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c
@@ -260,7 +260,7 @@ void adc12_handler(void)
g_highpri.r_volt[g_highpri.current] =
(float)g_highpri.r_val[g_highpri.current] * ref / bit;
- if (g_highpri.current >= REG_NCHANNELS-1)
+ if (g_highpri.current >= REG_NCHANNELS - 1)
{
g_highpri.current = 0;
}
@@ -297,6 +297,7 @@ void adc12_handler(void)
#endif
irq_out:
+
/* Clear ADC pending interrupts */
STM32_ADC_INT_ACK(adc, pending);
@@ -338,6 +339,7 @@ void dma1ch1_handler(void)
}
irq_out:
+
/* Clear DMA pending interrupts */
stm32_dma_intack(STM32_DMA1_CHAN1, pending);
@@ -411,7 +413,7 @@ int highpri_main(int argc, char *argv[])
/* Set Timer A Period */
- HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, 0xFFD0);
+ HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, 0xffd0);
#endif /* HIGHPRI_HAVE_HRTIM */
#ifdef HIGHPRI_HAVE_TIM1
[incubator-nuttx] 01/09: arch/arm/src/stm32/stm32_adc.c: move
adc_offset_set to llops section
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 4cb8be9608805c5358b66c9b863fc7129db09a53
Author: raiden00pl <ra...@railab.me>
AuthorDate: Tue Apr 21 21:31:27 2020 +0200
arch/arm/src/stm32/stm32_adc.c: move adc_offset_set to llops section
---
arch/arm/src/stm32/stm32_adc.c | 124 ++++++++++++++++++++---------------------
1 file changed, 61 insertions(+), 63 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c
index a3aa130..5ac3b58 100644
--- a/arch/arm/src/stm32/stm32_adc.c
+++ b/arch/arm/src/stm32/stm32_adc.c
@@ -3694,69 +3694,6 @@ static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first,
}
/****************************************************************************
- * Name: adc_offset_set
- ****************************************************************************/
-
-#ifdef CONFIG_STM32_ADC_LL_OPS
-#ifdef HAVE_IP_ADC_V2
-static int adc_offset_set(FAR struct stm32_adc_dev_s *dev, uint8_t ch,
- uint8_t i, uint16_t offset)
-{
- FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
- uint32_t regval = 0;
- uint32_t reg = 0;
- int ret = OK;
-
- if (i >= 4)
- {
- /* There are only four offset registers. */
-
- ret = -E2BIG;
- goto errout;
- }
-
- reg = STM32_ADC_OFR1_OFFSET + i * 4;
-
- regval = ADC_OFR_OFFSETY_EN;
- adc_putreg(priv, reg, regval);
-
- regval |= ADC_OFR_OFFSETY_CH(ch) | ADC_OFR_OFFSETY(offset);
- adc_putreg(priv, reg, regval);
-
-errout:
- return ret;
-}
-#else /* HAVE_IP_ADC_V1 */
-static int adc_offset_set(FAR struct stm32_adc_dev_s *dev, uint8_t ch,
- uint8_t i, uint16_t offset)
-{
- FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
- uint32_t reg = 0;
- int ret = OK;
-
- /* WARNING: Offset only for injected channels! */
-
- UNUSED(ch);
-
- if (i >= 4)
- {
- /* There are only four offset registers. */
-
- ret = -E2BIG;
- goto errout;
- }
-
- reg = STM32_ADC_JOFR1_OFFSET + i * 4;
-
- adc_putreg(priv, reg, offset);
-
-errout:
- return ret;
-}
-#endif
-#endif /* CONFIG_STM32_ADC_LL_OPS */
-
-/****************************************************************************
* Name: adc_set_ch
*
* Description:
@@ -4325,6 +4262,67 @@ static void adc_llops_reg_startconv(FAR struct stm32_adc_dev_s *dev,
}
/****************************************************************************
+ * Name: adc_offset_set
+ ****************************************************************************/
+
+#ifdef HAVE_IP_ADC_V2
+static int adc_offset_set(FAR struct stm32_adc_dev_s *dev, uint8_t ch,
+ uint8_t i, uint16_t offset)
+{
+ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+ uint32_t regval = 0;
+ uint32_t reg = 0;
+ int ret = OK;
+
+ if (i >= 4)
+ {
+ /* There are only four offset registers. */
+
+ ret = -E2BIG;
+ goto errout;
+ }
+
+ reg = STM32_ADC_OFR1_OFFSET + i * 4;
+
+ regval = ADC_OFR_OFFSETY_EN;
+ adc_putreg(priv, reg, regval);
+
+ regval |= ADC_OFR_OFFSETY_CH(ch) | ADC_OFR_OFFSETY(offset);
+ adc_putreg(priv, reg, regval);
+
+errout:
+ return ret;
+}
+#else /* HAVE_IP_ADC_V1 */
+static int adc_offset_set(FAR struct stm32_adc_dev_s *dev, uint8_t ch,
+ uint8_t i, uint16_t offset)
+{
+ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+ uint32_t reg = 0;
+ int ret = OK;
+
+ /* WARNING: Offset only for injected channels! */
+
+ UNUSED(ch);
+
+ if (i >= 4)
+ {
+ /* There are only four offset registers. */
+
+ ret = -E2BIG;
+ goto errout;
+ }
+
+ reg = STM32_ADC_JOFR1_OFFSET + i * 4;
+
+ adc_putreg(priv, reg, offset);
+
+errout:
+ return ret;
+}
+#endif
+
+/****************************************************************************
* Name: adc_regbufregister
****************************************************************************/
[incubator-nuttx] 09/09:
boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c: fix nxstyle issues
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit b2c7f1ecfa05ae1999bbcebdad99cfd8fe854cfc
Author: raiden00pl <ra...@railab.me>
AuthorDate: Sat Apr 25 21:05:46 2020 +0200
boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c: fix nxstyle issues
---
boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c
index 2c789cb..a32b482 100644
--- a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c
+++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c
@@ -230,7 +230,7 @@ void adc_handler(void)
g_highpri.r_volt[g_highpri.current] =
(float)g_highpri.r_val[g_highpri.current] * ref / bit;
- if (g_highpri.current >= REG_NCHANNELS-1)
+ if (g_highpri.current >= REG_NCHANNELS - 1)
{
g_highpri.current = 0;
}
@@ -267,6 +267,7 @@ void adc_handler(void)
#endif
irq_out:
+
/* Clear ADC pending interrupts */
STM32_ADC_INT_ACK(adc, pending);
@@ -308,6 +309,7 @@ void dma2s0_handler(void)
}
irq_out:
+
/* Clear DMA pending interrupts */
stm32_dma_intack(DMA2, DMA_STREAM0, pending);