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Posted to commits@mynewt.apache.org by vi...@apache.org on 2021/04/19 15:50:58 UTC
[mynewt-core] branch master updated: nrf53/hal: icache config
enable is in netcore.
This is an automated email from the ASF dual-hosted git repository.
vipulrahane pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
The following commit(s) were added to refs/heads/master by this push:
new cec8bf2 nrf53/hal: icache config enable is in netcore.
new 186f947 Merge pull request #2571 from vikrant-proxy/mcu/nrf5340-icache
cec8bf2 is described below
commit cec8bf25e47290f2206b0442578fcfd7a609e4c5
Author: Vikrant More <vi...@proxy.com>
AuthorDate: Sun Apr 18 18:10:05 2021 -0700
nrf53/hal: icache config enable is in netcore.
---
hw/mcu/nordic/nrf5340/src/hal_system.c | 4 ----
hw/mcu/nordic/nrf5340/syscfg.yml | 12 +++---------
hw/mcu/nordic/nrf5340_net/src/hal_system.c | 3 +++
hw/mcu/nordic/nrf5340_net/syscfg.yml | 6 ++++++
4 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/hw/mcu/nordic/nrf5340/src/hal_system.c b/hw/mcu/nordic/nrf5340/src/hal_system.c
index d314f51..4b9058b 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_system.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_system.c
@@ -36,10 +36,6 @@
void
hal_system_init(void)
{
-#if MYNEWT_VAL(MCU_ICACHE_ENABLED)
- NRF_NVMC_S->ICACHECNF = 1;
-#endif
-
#if MYNEWT_VAL(MCU_CACHE_ENABLED)
NRF_CACHE_S->ENABLE = 1;
#endif
diff --git a/hw/mcu/nordic/nrf5340/syscfg.yml b/hw/mcu/nordic/nrf5340/syscfg.yml
index 288d2cf..18be972 100644
--- a/hw/mcu/nordic/nrf5340/syscfg.yml
+++ b/hw/mcu/nordic/nrf5340/syscfg.yml
@@ -67,19 +67,13 @@ syscfg.defs:
Default value 4, clock runs at 48MHz.
range: 1,2,4
value: 4
-
+
MCU_CACHE_ENABLED:
description: >
Enable instruction and data cache
Default value is 0, so disabled.
value: 0
- MCU_ICACHE_ENABLED:
- description: >
- Enable instruction code cache
- Default value is 0, so disabled.
- value: 0
-
# MCU peripherals definitions
ADC_0:
description: 'Enable nRF5340 ADC 0'
@@ -181,7 +175,7 @@ syscfg.defs:
UART_3_PIN_CTS:
description: 'CTS pin for UART3'
value: -1
-
+
TIMER_0:
description: 'Enable nRF5340 Timer 0'
value: 1
@@ -316,7 +310,7 @@ syscfg.defs:
SPI_0_SLAVE_PIN_SS:
description: 'SS pin for SPI_0_SLAVE'
value: ''
-
+
SPI_1_MASTER:
description: 'Enable nRF5340 SPI Master 1'
value: 0
diff --git a/hw/mcu/nordic/nrf5340_net/src/hal_system.c b/hw/mcu/nordic/nrf5340_net/src/hal_system.c
index 571f7c0..df61efa 100644
--- a/hw/mcu/nordic/nrf5340_net/src/hal_system.c
+++ b/hw/mcu/nordic/nrf5340_net/src/hal_system.c
@@ -36,6 +36,9 @@
void
hal_system_init(void)
{
+#if MYNEWT_VAL(MCU_ICACHE_ENABLED)
+ NRF_NVMC_NS->ICACHECNF = 1;
+#endif
}
void
diff --git a/hw/mcu/nordic/nrf5340_net/syscfg.yml b/hw/mcu/nordic/nrf5340_net/syscfg.yml
index 57caca1..2e039a1 100644
--- a/hw/mcu/nordic/nrf5340_net/syscfg.yml
+++ b/hw/mcu/nordic/nrf5340_net/syscfg.yml
@@ -54,6 +54,12 @@ syscfg.defs:
the breakpoint wherever it gets called, For example, reset and crash
value: 0
+ MCU_ICACHE_ENABLED:
+ description: >
+ Enable instruction code cache
+ Default value is 0, so disabled.
+ value: 0
+
# MCU peripherals definitions
TRNG:
description: 'Enable nRF5340 TRNG'