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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/06/16 12:30:13 UTC
[GitHub] [incubator-nuttx] acassis commented on a diff in pull request #6422: New chip family stm32wb (WIP)
acassis commented on code in PR #6422:
URL: https://github.com/apache/incubator-nuttx/pull/6422#discussion_r899028473
##########
arch/arm/include/stm32wb/chip.h:
##########
@@ -0,0 +1,80 @@
+/************************************************************************************
+ * arch/arm/include/stm32wb/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_STM32WB_CHIP_H
+#define __ARCH_ARM_INCLUDE_STM32WB_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#if defined (CONFIG_ARCH_CHIP_STM32WB55R) /* VFQFPN68 package, 1024Kb FLASH, 256KiB SRAM */
+# define STM32WB_NFSMC 0 /* No FSMC */
+# define STM32WB_NATIM 1 /* One advanced timers TIM1 */
+# define STM32WB_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */
+# define STM32WB_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */
+# define STM32WB_NBTIM 0 /* No basic timers */
+# define STM32WB_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
+# define STM32WB_NGTIMNDMA 0 /* No general timers without DMA */
+# define STM32WB_NDMA 2 /* DMA1-2 with 7 channels each */
+# define STM32WB_NSPI 3 /* SPI1-2, QSPI */
+# define STM32WB_NI2S 1 /* SAI1 (dual channel high quality audio) */
+# define STM32WB_NUSART 2 /* USART1, LPUART1 */
+# define STM32WB_NI2C 2 /* I2C1, I2C3 */
+# define STM32WB_NCAN 0 /* No CAN */
+# define STM32WB_NSDIO 0 /* One SDIO interface */
Review Comment:
```suggestion
# define STM32WB_NSDIO 0 /* No SDIO interface */
```
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