[GitHub] [tvm] erwango commented on a diff in pull request #12756: [microTVM][Zephyr] Fix PLL freq. in overlay for nucleo_l4r5zi board

[GitBox <gi...@apache.org>]

erwango commented on code in PR #12756:
URL: https://github.com/apache/tvm/pull/12756#discussion_r969342711


##########
apps/microtvm/zephyr/template_project/app-overlay/nucleo_l4r5zi.overlay:
##########
@@ -21,3 +21,29 @@
 &rcc {
 	clock-frequency = <DT_FREQ_M(120)>;
 };
+
+/* Set PLL, where:
+
+   VCO freq = PLL clock input freq (HSI: 16 MHz) * N / M,
+   Core freq = VCO freq / R,
+   PLL48M1CLK freq = VCO freq / Q, and
+   PLLSAI3CLK freq = VCO freq / P,
+
+   Hence, since div-q = 2 => Q = 6 and div-p = 7 => P = 7:
+
+   VCO freq = 16 * 30 / 2 = 240 MHz
+
+   Core freq = 240 MHz / 2 = 120 MHz
+   PLL48M1CLK freq = 240 MHz / PLLQ = 40 MHz
+   PLLSAI3CLK freq = 240 MHz / PLLP = 34.28571 MHz
+*/
+
+&pll {
+	div-m = <2>;
+	mul-n = <30>;
+	div-p = <7>;
+	div-q = <2>;

Review Comment:
   Note: To save power, you can just remove these if these PLL outputs are not required.



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