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Posted to commits@nuttx.apache.org by xi...@apache.org on 2020/10/31 17:40:52 UTC

[incubator-nuttx] 03/04: arch: imxrt, s32k1xx, stm32f7 spi: fix CONFIG_SPI_BITORDER build errors

This is an automated email from the ASF dual-hosted git repository.

xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git

commit 77bbb077491c5e3faea52a28a225d53f8a643a1b
Author: Juha Niskanen <ju...@haltian.com>
AuthorDate: Sat Oct 31 17:46:33 2020 +0200

    arch: imxrt, s32k1xx, stm32f7 spi: fix CONFIG_SPI_BITORDER build errors
    
    Signed-off-by: Juha Niskanen <ju...@haltian.com>
---
 arch/arm/src/imxrt/imxrt_lpspi.c     |  3 +--
 arch/arm/src/s32k1xx/s32k1xx_lpspi.c |  3 +--
 arch/arm/src/stm32f7/stm32_spi.c     | 21 +++++++++++----------
 3 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c
index 8444882..c657420 100644
--- a/arch/arm/src/imxrt/imxrt_lpspi.c
+++ b/arch/arm/src/imxrt/imxrt_lpspi.c
@@ -1187,7 +1187,6 @@ static int imxrt_lpspi_hwfeatures(FAR struct spi_dev_s *dev,
   FAR struct imxrt_lpspidev_s *priv = (FAR struct imxrt_lpspidev_s *)dev;
   uint32_t setbits;
   uint32_t clrbits;
-  int savbits = nbits;
 
   spiinfo("features=%08x\n", features);
 
@@ -1204,7 +1203,7 @@ static int imxrt_lpspi_hwfeatures(FAR struct spi_dev_s *dev,
       clrbits = LPSPI_TCR_LSBF;
     }
 
-  imxrt_lpspi_modigyreg32(priv, IMXRT_LPSPI_TCR_OFFSET, clrbits, setbits);
+  imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET, clrbits, setbits);
 
   /* Other H/W features are not supported */
 
diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c
index e601613..5ce449d 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c
@@ -1147,7 +1147,6 @@ static int s32k1xx_lpspi_hwfeatures(FAR struct spi_dev_s *dev,
   FAR struct s32k1xx_lpspidev_s *priv = (FAR struct s32k1xx_lpspidev_s *)dev;
   uint32_t setbits;
   uint32_t clrbits;
-  int savbits = nbits;
 
   spiinfo("features=%08x\n", features);
 
@@ -1164,7 +1163,7 @@ static int s32k1xx_lpspi_hwfeatures(FAR struct spi_dev_s *dev,
       clrbits = LPSPI_TCR_LSBF;
     }
 
-  s32k1xx_lpspi_modigyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET, clrbits, setbits);
+  s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET, clrbits, setbits);
 
   /* Other H/W features are not supported */
 
diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c
index 1904b91..e394a44 100644
--- a/arch/arm/src/stm32f7/stm32_spi.c
+++ b/arch/arm/src/stm32f7/stm32_spi.c
@@ -1545,11 +1545,8 @@ static int spi_hwfeatures(FAR struct spi_dev_s *dev,
 #endif
 
 #ifdef CONFIG_SPI_BITORDER
-  uint16_t setbitscr1;
-  uint16_t clrbitscr1;
-  uint16_t setbitscr2;
-  uint16_t clrbitscr2;
-  int savbits = nbits;
+  uint16_t setbits;
+  uint16_t clrbits;
 
   spiinfo("features=%08x\n", features);
 
@@ -1791,13 +1788,15 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
 
   DEBUGASSERT(priv != NULL);
 
-  /* Convert the number of word to a number of bytes */
+  /* Convert the number of word to a number of bytes. */
 
   size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords;
 
 #ifdef CONFIG_STM32F7_SPI_DMATHRESHOLD
 
-  /* If this is a small SPI transfer, then let spi_exchange_nodma() do the work. */
+  /* If this is a small SPI transfer, then let spi_exchange_nodma()
+   * do the work.
+   */
 
   if (nbytes <= CONFIG_STM32F7_SPI_DMATHRESHOLD)
     {
@@ -1847,10 +1846,10 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
 
       /* If this bus uses a in driver buffers we will incur 2 copies,
        * The copy cost is << less the non DMA transfer time and having
-       * the buffer in the driver ensures DMA can be used. This is bacause
+       * the buffer in the driver ensures DMA can be used. This is because
        * the API does not support passing the buffer extent so the only
        * extent is buffer + the transfer size. These can sizes be less than
-       * the cache line size, and not aligned and tyicaly greater then 4
+       * the cache line size, and not aligned and typically greater then 4
        * bytes, which is about the break even point for the DMA IO overhead.
        */
 
@@ -2081,7 +2080,9 @@ static int spi_pm_prepare(FAR struct pm_callback_s *cb, int domain,
 
       if (sval <= 0)
         {
-          /* Exclusive lock is held, do not allow entry to deeper PM states. */
+          /* Exclusive lock is held, do not allow entry to deeper
+           * PM states.
+           */
 
           return -EBUSY;
         }