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Posted to commits@nuttx.apache.org by pk...@apache.org on 2022/07/04 10:26:03 UTC
[incubator-nuttx] 01/02: arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 9ab34178827a2d1bea14395a259fa8e5bf88b813
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Sat Jul 2 11:26:26 2022 +0800
arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place
1.Move __XSTR from include/arch.h to include/irq.h
2.Move FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
arch/risc-v/include/arch.h | 26 -------------------------
arch/risc-v/include/irq.h | 10 ++++++++--
arch/risc-v/include/syscall.h | 2 --
arch/risc-v/src/common/riscv_exception_common.S | 2 --
arch/risc-v/src/common/riscv_internal.h | 22 ++++++++++++++++++++-
arch/risc-v/src/mpfs/chip.h | 1 +
6 files changed, 30 insertions(+), 33 deletions(-)
diff --git a/arch/risc-v/include/arch.h b/arch/risc-v/include/arch.h
index 8435cd8f5d..27165c2b25 100644
--- a/arch/risc-v/include/arch.h
+++ b/arch/risc-v/include/arch.h
@@ -40,32 +40,6 @@
* Pre-processor Definitions
****************************************************************************/
-#ifdef __ASSEMBLY__
-# define __STR(s) s
-#else
-# define __STR(s) #s
-#endif
-#define __XSTR(s) __STR(s)
-
-#if defined(CONFIG_ARCH_QPFPU)
-# define FLOAD __STR(flq)
-# define FSTORE __STR(fsq)
-#elif defined(CONFIG_ARCH_DPFPU)
-# define FLOAD __STR(fld)
-# define FSTORE __STR(fsd)
-#else
-# define FLOAD __STR(flw)
-# define FSTORE __STR(fsw)
-#endif
-
-#ifdef CONFIG_ARCH_RV32
-# define REGLOAD __STR(lw)
-# define REGSTORE __STR(sw)
-#else
-# define REGLOAD __STR(ld)
-# define REGSTORE __STR(sd)
-#endif
-
/* Provide the maximum amount of page table levels per MMU type */
#ifdef CONFIG_ARCH_MMU_TYPE_SV39
diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h
index 7303344482..ca6f911988 100644
--- a/arch/risc-v/include/irq.h
+++ b/arch/risc-v/include/irq.h
@@ -33,9 +33,8 @@
#include <nuttx/config.h>
-#include <arch/types.h>
+#include <sys/types.h>
-#include <arch/arch.h>
#include <arch/csr.h>
#include <arch/chip/irq.h>
#include <arch/mode.h>
@@ -44,6 +43,13 @@
* Pre-processor Definitions
****************************************************************************/
+#ifdef __ASSEMBLY__
+# define __STR(s) s
+#else
+# define __STR(s) #s
+#endif
+#define __XSTR(s) __STR(s)
+
/* Map RISC-V exception code to NuttX IRQ */
/* IRQ 0-15 : (exception:interrupt=0) */
diff --git a/arch/risc-v/include/syscall.h b/arch/risc-v/include/syscall.h
index ccb751fb07..daa6b66f65 100644
--- a/arch/risc-v/include/syscall.h
+++ b/arch/risc-v/include/syscall.h
@@ -31,8 +31,6 @@
#include <nuttx/config.h>
-#include <arch/arch.h>
-
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S
index 0bf0f74f09..218f1b1fa3 100644
--- a/arch/risc-v/src/common/riscv_exception_common.S
+++ b/arch/risc-v/src/common/riscv_exception_common.S
@@ -34,8 +34,6 @@
#include "riscv_macros.S"
-#include "riscv_internal.h"
-
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h
index dc2575f678..472967db10 100644
--- a/arch/risc-v/src/common/riscv_internal.h
+++ b/arch/risc-v/src/common/riscv_internal.h
@@ -29,18 +29,38 @@
#ifndef __ASSEMBLY__
# include <nuttx/compiler.h>
-# include <nuttx/arch.h>
# include <sys/types.h>
# include <stdint.h>
# include <syscall.h>
#endif
+#include <nuttx/irq.h>
+
#include "riscv_common_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+#if defined(CONFIG_ARCH_QPFPU)
+# define FLOAD __STR(flq)
+# define FSTORE __STR(fsq)
+#elif defined(CONFIG_ARCH_DPFPU)
+# define FLOAD __STR(fld)
+# define FSTORE __STR(fsd)
+#else
+# define FLOAD __STR(flw)
+# define FSTORE __STR(fsw)
+#endif
+
+#ifdef CONFIG_ARCH_RV32
+# define REGLOAD __STR(lw)
+# define REGSTORE __STR(sw)
+#else
+# define REGLOAD __STR(ld)
+# define REGSTORE __STR(sd)
+#endif
+
/* This is the value used to mark the stack for subsequent stack monitoring
* logic.
*/
diff --git a/arch/risc-v/src/mpfs/chip.h b/arch/risc-v/src/mpfs/chip.h
index 6c9d32e1ff..6c4d3c7e11 100755
--- a/arch/risc-v/src/mpfs/chip.h
+++ b/arch/risc-v/src/mpfs/chip.h
@@ -29,6 +29,7 @@
#include "mpfs_memorymap.h"
+#include "riscv_internal.h"
#include "riscv_percpu.h"
/****************************************************************************