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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/06/29 16:10:48 UTC
[incubator-nuttx] 02/02: xtensa/esp32s2: Sync GPIO driver implementation with ESP32-S3
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 31cddc922c337b8aa660ba1407db311a00a873aa
Author: Gustavo Henrique Nihei <gu...@espressif.com>
AuthorDate: Wed Jun 15 17:42:51 2022 -0300
xtensa/esp32s2: Sync GPIO driver implementation with ESP32-S3
Sync driver interfaces, also fixes the handling of special pin value for
esp32s2_gpio_matrix_in and esp32s2_gpio_matrix_out functions
Signed-off-by: Gustavo Henrique Nihei <gu...@espressif.com>
---
arch/xtensa/src/esp32s2/esp32s2_gpio.c | 255 +++++++++++++++------
arch/xtensa/src/esp32s2/esp32s2_gpio.h | 148 +++++++++---
arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h | 91 ++++----
.../esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c | 2 +-
4 files changed, 337 insertions(+), 159 deletions(-)
diff --git a/arch/xtensa/src/esp32s2/esp32s2_gpio.c b/arch/xtensa/src/esp32s2/esp32s2_gpio.c
index c95d86701c..cfe8baf516 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_gpio.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_gpio.c
@@ -24,20 +24,18 @@
#include <nuttx/config.h>
-#include <sys/types.h>
-#include <stdint.h>
#include <assert.h>
#include <debug.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <sys/types.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
-#include <arch/irq.h>
#include "xtensa.h"
#include "esp32s2_gpio.h"
-#ifdef CONFIG_ESP32S2_GPIO_IRQ
#include "esp32s2_irq.h"
-#endif
#include "hardware/esp32s2_gpio.h"
#include "hardware/esp32s2_iomux.h"
@@ -45,9 +43,7 @@
* Pre-processor Definitions
****************************************************************************/
-#define NGPIO_HPINS (ESP32S2_NIRQ_GPIO - 32)
-#define NGPIO_HMASK ((1ul << NGPIO_HPINS) - 1)
-#define _NA_ 0xff
+#define ESP32S2_NPINS 47
/****************************************************************************
* Private Data
@@ -61,27 +57,55 @@ static int g_gpio_cpuint;
* Private Functions
****************************************************************************/
+/****************************************************************************
+ * Name: is_valid_gpio
+ *
+ * Description:
+ * Check if the requested pin is a valid GPIO pin.
+ *
+ * Input Parameters:
+ * pin - Pin to be checked for validity.
+ *
+ * Returned Value:
+ * True if the requested pin is a valid GPIO pin, false otherwise.
+ *
+ ****************************************************************************/
+
+static inline bool is_valid_gpio(uint32_t pin)
+{
+ /* ESP32-S2 has 43 GPIO pins numbered from 0 to 21 and 26 to 46 */
+
+ return pin <= 21 || (pin >= 26 && pin < ESP32S2_NPINS);
+}
+
/****************************************************************************
* Name: gpio_dispatch
*
* Description:
* Second level dispatch for GPIO interrupt handling.
*
+ * Input Parameters:
+ * irq - GPIO IRQ number.
+ * status - Value from the GPIO interrupt status clear register.
+ * regs - Saved CPU context.
+ *
+ * Returned Value:
+ * None.
+ *
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs)
{
uint32_t mask;
- int i;
/* Check each bit in the status register */
- for (i = 0; i < 32 && status != 0; i++)
+ for (int i = 0; i < 32 && status != 0; i++)
{
/* Check if there is an interrupt pending for this pin */
- mask = (1ul << i);
+ mask = UINT32_C(1) << i;
if ((status & mask) != 0)
{
/* Yes... perform the second level dispatch */
@@ -104,6 +128,15 @@ static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs)
* Description:
* GPIO interrupt handler.
*
+ * Input Parameters:
+ * irq - Identifier of the interrupt request.
+ * context - Context data from the ISR.
+ * arg - Opaque pointer to the internal driver state structure.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
@@ -122,7 +155,7 @@ static int gpio_interrupt(int irq, void *context, void *arg)
/* Read and clear the upper GPIO interrupt status */
- status = getreg32(GPIO_STATUS1_REG) & NGPIO_HMASK;
+ status = getreg32(GPIO_STATUS1_REG) & GPIO_STATUS1_INTERRUPT_M;
putreg32(status, GPIO_STATUS1_W1TC_REG);
/* Dispatch pending interrupts in the lower GPIO status register */
@@ -142,6 +175,20 @@ static int gpio_interrupt(int irq, void *context, void *arg)
* Description:
* Configure a GPIO pin based on encoded pin attributes.
*
+ * Input Parameters:
+ * pin - GPIO pin to be configured.
+ * attr - Attributes to be configured for the selected GPIO pin.
+ * The following attributes are accepted:
+ * - Direction (OUTPUT or INPUT)
+ * - Pull (PULLUP, PULLDOWN or OPENDRAIN)
+ * - Function (if not provided, assume function GPIO by
+ * default)
+ * - Drive strength (if not provided, assume DRIVE_2 by
+ * default)
+ *
+ * Returned Value:
+ * Zero (OK) on success, or -1 (ERROR) in case of failure.
+ *
****************************************************************************/
int esp32s2_configgpio(int pin, gpio_pinattr_t attr)
@@ -151,22 +198,22 @@ int esp32s2_configgpio(int pin, gpio_pinattr_t attr)
uint32_t cntrl;
uint32_t pin2func;
- DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS);
-
- /* Handle input pins */
+ DEBUGASSERT(is_valid_gpio(pin));
func = 0;
cntrl = 0;
+ /* Handle input pins */
+
if ((attr & INPUT) != 0)
{
if (pin < 32)
{
- putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG);
+ putreg32(UINT32_C(1) << pin, GPIO_ENABLE_W1TC_REG);
}
else
{
- putreg32((1ul << (pin - 32)), GPIO_ENABLE1_W1TC_REG);
+ putreg32(UINT32_C(1) << (pin - 32), GPIO_ENABLE1_W1TC_REG);
}
/* Input enable */
@@ -177,7 +224,7 @@ int esp32s2_configgpio(int pin, gpio_pinattr_t attr)
{
func |= FUN_PU;
}
- else if (attr & PULLDOWN)
+ else if ((attr & PULLDOWN) != 0)
{
func |= FUN_PD;
}
@@ -189,34 +236,45 @@ int esp32s2_configgpio(int pin, gpio_pinattr_t attr)
{
if (pin < 32)
{
- putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG);
+ putreg32(UINT32_C(1) << pin, GPIO_ENABLE_W1TS_REG);
}
else
{
- putreg32((1ul << (pin - 32)), GPIO_ENABLE1_W1TS_REG);
+ putreg32(UINT32_C(1) << (pin - 32), GPIO_ENABLE1_W1TS_REG);
}
}
- /* Add drivers */
-
- func |= (uint32_t)(2ul << FUN_DRV_S);
-
- /* Select the pad's function. If no function was given, consider it a
- * normal input or output (i.e. function3).
- */
+ /* Configure the pad's function */
if ((attr & FUNCTION_MASK) != 0)
{
- func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S);
+ uint32_t val = ((attr & FUNCTION_MASK) >> FUNCTION_SHIFT) - 1;
+ func |= val << MCU_SEL_S;
}
else
{
+ /* Function not provided, assuming function GPIO by default */
+
func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S);
}
+ /* Configure the pad's drive strength */
+
+ if ((attr & DRIVE_MASK) != 0)
+ {
+ uint32_t val = ((attr & DRIVE_MASK) >> DRIVE_SHIFT) - 1;
+ func |= val << FUN_DRV_S;
+ }
+ else
+ {
+ /* Drive strength not provided, assuming strength 2 by default */
+
+ func |= UINT32_C(2) << FUN_DRV_S;
+ }
+
if ((attr & OPEN_DRAIN) != 0)
{
- cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S);
+ cntrl |= UINT32_C(1) << GPIO_PIN_PAD_DRIVER_S;
}
pin2func = (pin + 1) * 4;
@@ -232,34 +290,42 @@ int esp32s2_configgpio(int pin, gpio_pinattr_t attr)
* Name: esp32s2_gpiowrite
*
* Description:
- * Write one or zero to the selected GPIO pin
+ * Write one or zero to the selected GPIO pin.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be written.
+ * value - Value to be written to the GPIO pin. True will output
+ * 1 (one) to the GPIO, while false will output 0 (zero).
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
void esp32s2_gpiowrite(int pin, bool value)
{
- DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS);
+ DEBUGASSERT(is_valid_gpio(pin));
if (value)
{
if (pin < 32)
{
- putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TS_REG);
+ putreg32(UINT32_C(1) << pin, GPIO_OUT_W1TS_REG);
}
else
{
- putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TS_REG);
+ putreg32(UINT32_C(1) << (pin - 32), GPIO_OUT1_W1TS_REG);
}
}
else
{
if (pin < 32)
{
- putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TC_REG);
+ putreg32(UINT32_C(1) << pin, GPIO_OUT_W1TC_REG);
}
else
{
- putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TC_REG);
+ putreg32(UINT32_C(1) << (pin - 32), GPIO_OUT1_W1TC_REG);
}
}
}
@@ -268,7 +334,14 @@ void esp32s2_gpiowrite(int pin, bool value)
* Name: esp32s2_gpioread
*
* Description:
- * Read one or zero from the selected GPIO pin
+ * Read one or zero from the selected GPIO pin.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be read.
+ *
+ * Returned Value:
+ * True in case the read value is 1 (one). If 0 (zero), then false will be
+ * returned.
*
****************************************************************************/
@@ -276,7 +349,7 @@ bool esp32s2_gpioread(int pin)
{
uint32_t regval;
- DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS);
+ DEBUGASSERT(is_valid_gpio(pin));
if (pin < 32)
{
@@ -297,6 +370,12 @@ bool esp32s2_gpioread(int pin)
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
@@ -319,7 +398,14 @@ void esp32s2_gpioirqinitialize(void)
* Name: esp32s2_gpioirqenable
*
* Description:
- * Enable the COPY interrupt for specified GPIO IRQ
+ * Enable the interrupt for the specified GPIO IRQ.
+ *
+ * Input Parameters:
+ * irq - Identifier of the interrupt request.
+ * intrtype - Interrupt type, select from gpio_intrtype_t.
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
@@ -336,30 +422,24 @@ void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype)
pin = ESP32S2_IRQ2PIN(irq);
- /* Get the address of the GPIO PIN register for this pin */
+ /* Disable the GPIO interrupt during the configuration. */
up_disable_irq(ESP32S2_IRQ_GPIO_INT_PRO);
+ /* Get the address of the GPIO PIN register for this pin */
+
regaddr = GPIO_REG(pin);
regval = getreg32(regaddr);
regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M);
- /* Set the pin ENA field:
- *
- * Bit 0: APP CPU interrupt enable
- * Bit 1: APP CPU non-maskable interrupt enable
- * Bit 3: PRO CPU interrupt enable
- * Bit 4: PRO CPU non-maskable interrupt enable
- * Bit 5: SDIO's extent interrupt enable.
- */
-
- /* PRO_CPU */
+ /* Set the pin ENA field */
- regval |= ((1 << 2) << GPIO_PIN_INT_ENA_S);
-
- regval |= (intrtype << GPIO_PIN_INT_TYPE_S);
+ regval |= GPIO_PIN_INT_ENA_M;
+ regval |= (uint32_t)intrtype << GPIO_PIN_INT_TYPE_S;
putreg32(regval, regaddr);
+ /* Configuration done. Re-enable the GPIO interrupt. */
+
up_enable_irq(ESP32S2_IRQ_GPIO_INT_PRO);
}
#endif
@@ -368,7 +448,13 @@ void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype)
* Name: esp32s2_gpioirqdisable
*
* Description:
- * Disable the interrupt for specified GPIO IRQ
+ * Disable the interrupt for the specified GPIO IRQ.
+ *
+ * Input Parameters:
+ * irq - Identifier of the interrupt request.
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
@@ -385,15 +471,19 @@ void esp32s2_gpioirqdisable(int irq)
pin = ESP32S2_IRQ2PIN(irq);
- /* Get the address of the GPIO PIN register for this pin */
+ /* Disable the GPIO interrupt during the configuration. */
up_disable_irq(ESP32S2_IRQ_GPIO_INT_PRO);
+ /* Reset the pin ENA and TYPE fields */
+
regaddr = GPIO_REG(pin);
regval = getreg32(regaddr);
regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M);
putreg32(regval, regaddr);
+ /* Configuration done. Re-enable the GPIO interrupt. */
+
up_enable_irq(ESP32S2_IRQ_GPIO_INT_PRO);
}
#endif
@@ -402,25 +492,35 @@ void esp32s2_gpioirqdisable(int irq)
* Name: esp32s2_gpio_matrix_in
*
* Description:
- * Set gpio input to a signal
- * NOTE: one gpio can input to several signals
- * If gpio == 0x30, cancel input to the signal, input 0 to signal
- * If gpio == 0x38, cancel input to the signal, input 1 to signal,
- * for I2C pad
+ * Set GPIO input to a signal.
+ * NOTE: one GPIO can receive inputs from several signals.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be configured.
+ * - If pin == 0x3c, cancel input to the signal, input 0
+ * to signal.
+ * - If pin == 0x3a, input nothing to signal.
+ * - If pin == 0x38, cancel input to the signal, input 1
+ * to signal.
+ * signal_idx - Signal index.
+ * inv - Flag indicating whether the signal is inverted.
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
-void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv)
+void esp32s2_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv)
{
uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4);
- uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S);
+ uint32_t regval = pin << GPIO_FUNC0_IN_SEL_S;
if (inv)
{
regval |= GPIO_FUNC0_IN_INV_SEL;
}
- if (gpio != 0x34)
+ if (pin != 0x3a)
{
regval |= GPIO_SIG0_IN_SEL;
}
@@ -432,30 +532,37 @@ void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv)
* Name: esp32s2_gpio_matrix_out
*
* Description:
- * Set signal output to gpio
- * NOTE: one signal can output to several gpios
- * If signal_idx == 0x100, cancel output put to the gpio
+ * Set signal output to GPIO.
+ * NOTE: one signal can output to several GPIOs.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be configured.
+ * signal_idx - Signal index.
+ * - If signal_idx == 0x100, cancel output to the GPIO.
+ * out_inv - Flag indicating whether the signal output is inverted.
+ * oen_inv - Flag indicating whether the signal output enable is
+ * inverted.
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
-void esp32s2_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
+void esp32s2_gpio_matrix_out(uint32_t pin, uint32_t signal_idx,
bool out_inv, bool oen_inv)
{
- uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4);
+ uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (pin * 4);
uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S;
- if (gpio >= GPIO_PIN_COUNT)
- {
- return;
- }
+ DEBUGASSERT(is_valid_gpio(pin));
- if (gpio < 32)
+ if (pin < 32)
{
- putreg32((1ul << gpio), GPIO_ENABLE_W1TS_REG);
+ putreg32(UINT32_C(1) << pin, GPIO_ENABLE_W1TS_REG);
}
else
{
- putreg32((1ul << (gpio - 32)), GPIO_ENABLE1_W1TS_REG);
+ putreg32(UINT32_C(1) << (pin - 32), GPIO_ENABLE1_W1TS_REG);
}
if (out_inv)
diff --git a/arch/xtensa/src/esp32s2/esp32s2_gpio.h b/arch/xtensa/src/esp32s2/esp32s2_gpio.h
index b83f0214a0..7e3d2aff4b 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_gpio.h
+++ b/arch/xtensa/src/esp32s2/esp32s2_gpio.h
@@ -27,15 +27,15 @@
#include <nuttx/config.h>
-#include <stdint.h>
#include <stdbool.h>
+#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */
-#define MATRIX_DETACH_IN_LOW_PIN 0x30 /* Detach non-inverted INPUT sig */
+#define MATRIX_DETACH_IN_LOW_PIN 0x3c /* Detach non-inverted INPUT sig */
#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */
/* Bit-encoded input to esp32s2_configgpio() ********************************/
@@ -47,15 +47,18 @@
* FN FN FN OD PD PU F O I
*/
-#define PINMODE_SHIFT 0
-#define PINMODE_MASK (7 << PINMODE_SHIFT)
+#define MODE_SHIFT 0
+#define MODE_MASK (7 << MODE_SHIFT)
# define INPUT (1 << 0)
# define OUTPUT (1 << 1)
# define FUNCTION (1 << 2)
-#define PULLUP (1 << 3)
-#define PULLDOWN (1 << 4)
-#define OPEN_DRAIN (1 << 5)
+#define PULL_SHIFT 3
+#define PULL_MASK (7 << PULL_SHIFT)
+# define PULLUP (1 << 3)
+# define PULLDOWN (1 << 4)
+# define OPEN_DRAIN (1 << 5)
+
#define FUNCTION_SHIFT 6
#define FUNCTION_MASK (7 << FUNCTION_SHIFT)
# define FUNCTION_1 (1 << FUNCTION_SHIFT)
@@ -65,6 +68,13 @@
# define FUNCTION_5 (5 << FUNCTION_SHIFT)
# define FUNCTION_6 (6 << FUNCTION_SHIFT)
+#define DRIVE_SHIFT 9
+#define DRIVE_MASK (7 << DRIVE_SHIFT)
+# define DRIVE_0 (1 << DRIVE_SHIFT)
+# define DRIVE_1 (2 << DRIVE_SHIFT)
+# define DRIVE_2 (3 << DRIVE_SHIFT)
+# define DRIVE_3 (4 << DRIVE_SHIFT)
+
#define INPUT_PULLUP (INPUT | PULLUP)
#define INPUT_PULLDOWN (INPUT | PULLDOWN)
#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN)
@@ -83,17 +93,6 @@
# define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5)
# define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6)
-/* Interrupt type used with esp32s2_gpioirqenable() */
-
-#define DISABLED 0x00
-#define RISING 0x01
-#define FALLING 0x02
-#define CHANGE 0x03
-#define ONLOW 0x04
-#define ONHIGH 0x05
-#define ONLOW_WE 0x0c
-#define ONHIGH_WE 0x0d
-
/****************************************************************************
* Public Types
****************************************************************************/
@@ -103,7 +102,16 @@
/* Must be big enough to hold the above encodings */
typedef uint16_t gpio_pinattr_t;
-typedef uint8_t gpio_intrtype_t;
+
+typedef enum gpio_intrtype_e
+{
+ GPIO_INTR_DISABLE = 0, /* Disable GPIO interrupt */
+ GPIO_INTR_POSEDGE = 1, /* Rising edge */
+ GPIO_INTR_NEGEDGE = 2, /* Falling edge */
+ GPIO_INTR_ANYEDGE = 3, /* Both rising and falling edge */
+ GPIO_INTR_LOW_LEVEL = 4, /* Input low level trigger */
+ GPIO_INTR_HIGH_LEVEL = 5 /* Input high level trigger */
+} gpio_intrtype_t;
/****************************************************************************
* Public Data
@@ -118,10 +126,6 @@ extern "C"
#define EXTERN extern
#endif
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
@@ -133,6 +137,12 @@ extern "C"
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
@@ -147,6 +157,20 @@ void esp32s2_gpioirqinitialize(void);
* Description:
* Configure a GPIO pin based on encoded pin attributes.
*
+ * Input Parameters:
+ * pin - GPIO pin to be configured.
+ * attr - Attributes to be configured for the selected GPIO pin.
+ * The following attributes are accepted:
+ * - Direction (OUTPUT or INPUT)
+ * - Pull (PULLUP, PULLDOWN or OPENDRAIN)
+ * - Function (if not provided, assume function GPIO by
+ * default)
+ * - Drive strength (if not provided, assume DRIVE_2 by
+ * default)
+ *
+ * Returned Value:
+ * Zero (OK) on success, or -1 (ERROR) in case of failure.
+ *
****************************************************************************/
int esp32s2_configgpio(int pin, gpio_pinattr_t attr);
@@ -155,7 +179,15 @@ int esp32s2_configgpio(int pin, gpio_pinattr_t attr);
* Name: esp32s2_gpiowrite
*
* Description:
- * Write one or zero to the selected GPIO pin
+ * Write one or zero to the selected GPIO pin.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be written.
+ * value - Value to be written to the GPIO pin. True will output
+ * 1 (one) to the GPIO, while false will output 0 (zero).
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
@@ -165,7 +197,14 @@ void esp32s2_gpiowrite(int pin, bool value);
* Name: esp32s2_gpioread
*
* Description:
- * Read one or zero from the selected GPIO pin
+ * Read one or zero from the selected GPIO pin.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be read.
+ *
+ * Returned Value:
+ * True in case the read value is 1 (one). If 0 (zero), then false will be
+ * returned.
*
****************************************************************************/
@@ -175,7 +214,14 @@ bool esp32s2_gpioread(int pin);
* Name: esp32s2_gpioirqenable
*
* Description:
- * Enable the interrupt for specified GPIO IRQ
+ * Enable the interrupt for the specified GPIO IRQ.
+ *
+ * Input Parameters:
+ * irq - Identifier of the interrupt request.
+ * intrtype - Interrupt type, select from gpio_intrtype_t.
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
@@ -189,7 +235,13 @@ void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype);
* Name: esp32s2_gpioirqdisable
*
* Description:
- * Disable the interrupt for specified GPIO IRQ
+ * Disable the interrupt for the specified GPIO IRQ.
+ *
+ * Input Parameters:
+ * irq - Identifier of the interrupt request.
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
@@ -203,28 +255,48 @@ void esp32s2_gpioirqdisable(int irq);
* Name: esp32s2_gpio_matrix_in
*
* Description:
- * Set gpio input to a signal
- * NOTE: one gpio can input to several signals
- * If gpio == 0x30, cancel input to the signal, input 0 to signal
- * If gpio == 0x38, cancel input to the signal, input 1 to signal,
- * for I2C pad
+ * Set GPIO input to a signal.
+ * NOTE: one GPIO can receive inputs from several signals.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be configured.
+ * - If pin == 0x3c, cancel input to the signal, input 0
+ * to signal.
+ * - If pin == 0x3a, input nothing to signal.
+ * - If pin == 0x38, cancel input to the signal, input 1
+ * to signal.
+ * signal_idx - Signal index.
+ * inv - Flag indicating whether the signal is inverted.
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
-void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
+void esp32s2_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv);
/****************************************************************************
* Name: esp32s2_gpio_matrix_out
*
* Description:
- * Set signal output to gpio
- * NOTE: one signal can output to several gpios
- * If signal_idx == 0x100, cancel output put to the gpio
+ * Set signal output to GPIO.
+ * NOTE: one signal can output to several GPIOs.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be configured.
+ * signal_idx - Signal index.
+ * - If signal_idx == 0x100, cancel output to the GPIO.
+ * out_inv - Flag indicating whether the signal output is inverted.
+ * oen_inv - Flag indicating whether the signal output enable is
+ * inverted.
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
-void esp32s2_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
- bool out_inv, bool oen_inv);
+void esp32s2_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv,
+ bool oen_inv);
#ifdef __cplusplus
}
diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h
index cf19d69e8f..b35a1ac4f8 100644
--- a/arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h
+++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h
@@ -132,52 +132,51 @@
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
-#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
-#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
-#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
-#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U
-#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U
-#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U
-#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
-#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
-#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
-#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
-#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U
-#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
-#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
-#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U
-#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U
-#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U
-#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U
-#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U
-#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
-#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
-#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U
-#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U
-#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U
-#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U
-#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U
-#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U
-#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U
-#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U
-#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
-#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
-#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
-#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
-#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
-#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
-#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U
-#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U
-#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U
-#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U
-#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U
-#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U
-#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U
-#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U
-
-#define FUNC_GPIO_GPIO 1
-#define PIN_FUNC_GPIO 1
+#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
+#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
+#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U
+#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U
+#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U
+#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
+#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U
+#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
+#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
+#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U
+#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U
+#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U
+#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
+#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
+#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U
+#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U
+#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
+#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
+#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
+#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
+#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
+#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
+#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U
+#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U
+#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U
+
+#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c
index 10e18f703f..9c66d0b2d4 100644
--- a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c
+++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c
@@ -374,7 +374,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable)
/* Configure the interrupt for rising edge */
- esp32s2_gpioirqenable(irq, RISING);
+ esp32s2_gpioirqenable(irq, GPIO_INTR_POSEDGE);
}
}
else