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Posted to commits@nuttx.apache.org by xi...@apache.org on 2021/11/04 03:50:24 UTC
[incubator-nuttx] branch master updated: stm32h7 sdmmc: do not
enable power saving configuration bit (in SD 4-bit mode) because the SDIO
clock is not enabled when the bus goes to the idle state, that, in turn,
breaks IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 60de445 stm32h7 sdmmc: do not enable power saving configuration bit (in SD 4-bit mode) because the SDIO clock is not enabled when the bus goes to the idle state, that, in turn, breaks IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.
60de445 is described below
commit 60de445ab38d477188dd2292751785cd3dd6d889
Author: Alexander Lunev <al...@mail.ru>
AuthorDate: Thu Nov 4 04:13:49 2021 +0300
stm32h7 sdmmc: do not enable power saving configuration bit (in SD 4-bit mode) because
the SDIO clock is not enabled when the bus goes to the idle state, that, in turn, breaks
IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.
---
arch/arm/src/stm32h7/stm32_sdmmc.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c
index 40b52e3..6cba0b5 100644
--- a/arch/arm/src/stm32h7/stm32_sdmmc.c
+++ b/arch/arm/src/stm32h7/stm32_sdmmc.c
@@ -212,10 +212,21 @@
STM32_SDMMC_CLKCR_EDGE | \
STM32_SDMMC_CLKCR_PWRSAV | \
STM32_SDMMC_CLKCR_WIDBUS_D1)
-#define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \
- STM32_SDMMC_CLKCR_EDGE | \
- STM32_SDMMC_CLKCR_PWRSAV | \
- STM32_SDMMC_CLKCR_WIDBUS_D4)
+#ifdef HAVE_SDMMC_SDIO_MODE
+/* Do not enable power saving configuration bit (in SD 4-bit mode) because
+ * the SDIO clock is not enabled when the bus goes to the idle state.
+ * This condition breaks interrupts delivering mechanism over DAT[1]/IRQ
+ * SDIO line to the host.
+ */
+# define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \
+ STM32_SDMMC_CLKCR_EDGE | \
+ STM32_SDMMC_CLKCR_WIDBUS_D4)
+#else
+# define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \
+ STM32_SDMMC_CLKCR_EDGE | \
+ STM32_SDMMC_CLKCR_PWRSAV | \
+ STM32_SDMMC_CLKCR_WIDBUS_D4)
+#endif
/* Timing */