[GitHub] [tvm] masahi commented on a diff in pull request #12785: [Hexagon] 2-Stage Pipeline; Lower Async TIR primitives to Hexagon User DMA

[GitBox <gi...@apache.org>]

masahi commented on code in PR #12785:
URL: https://github.com/apache/tvm/pull/12785#discussion_r971701650


##########
include/tvm/tir/builtin.h:
##########
@@ -720,6 +720,16 @@ TVM_DLL const Op& texture2d_load();
  */
 TVM_DLL const Op& mem_copy();
 
+/*!
+ * \brief Initiate a non-blocking DMA copy from source to destination
+ */
+TVM_DLL const Op& dma_copy();
+
+/*!
+ * \brief Wait until the number of DMAs in flight is less than or equal to some maximum
+ */
+TVM_DLL const Op& dma_wait();

Review Comment:
   I think it is fine to have Hexagon-specific intrinsics here, rather than trying to be more generic than necessary.
   
   For CUDA we have specific copy / wait intrins in https://github.com/apache/tvm/blob/c4aab62c6d588ed06f60b0db9691271f5883dc66/include/tvm/tir/builtin.h#L635-L652  



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