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Posted to commits@nuttx.apache.org by xi...@apache.org on 2024/04/10 07:00:50 UTC
(nuttx) branch master updated (9847c6219d -> 01aeeaeac6)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
from 9847c6219d add libuv and cmocka test cases with file system on sim and qemu on CI
new b864522b65 ESP32S3 I2S BCLK, WSPIN, DINPIN, DOUTPIN pin range changed to 0 48
new 4c744f1c0e ESP32S3 configuring gpio pin 19 or 20 ( USB_D+/- ) for any purposes
new 01aeeaeac6 ESP32S3 I2S GPIO selection master/slave hase same range for BCLK,WS pin
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/xtensa/src/esp32s3/Kconfig | 24 ++++++++++--------------
arch/xtensa/src/esp32s3/esp32s3_gpio.c | 12 ++++++++++++
2 files changed, 22 insertions(+), 14 deletions(-)
(nuttx) 01/03: ESP32S3 I2S BCLK, WSPIN, DINPIN, DOUTPIN pin range changed to 0 48
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit b864522b65357aabec2bfbdd4308f28d3c4d4226
Author: Omar <om...@gmail.com>
AuthorDate: Sat Apr 6 03:53:05 2024 +0600
ESP32S3 I2S BCLK, WSPIN, DINPIN, DOUTPIN pin range changed to 0 48
---
arch/xtensa/src/esp32s3/Kconfig | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig
index 11067fb97f..d2bc321c3a 100644
--- a/arch/xtensa/src/esp32s3/Kconfig
+++ b/arch/xtensa/src/esp32s3/Kconfig
@@ -366,26 +366,26 @@ config ESP32S3_I2S0_SAMPLE_RATE
config ESP32S3_I2S0_BCLKPIN
int "I2S0 BCLK pin"
default 4
- range 0 33 if ESP32S3_I2S0_ROLE_MASTER
- range 0 39 if ESP32S3_I2S0_ROLE_SLAVE
+ range 0 48 if ESP32S3_I2S0_ROLE_MASTER
+ range 0 48 if ESP32S3_I2S0_ROLE_SLAVE
config ESP32S3_I2S0_WSPIN
int "I2S0 WS pin"
default 5
- range 0 33 if ESP32S3_I2S0_ROLE_MASTER
- range 0 39 if ESP32S3_I2S0_ROLE_SLAVE
+ range 0 48 if ESP32S3_I2S0_ROLE_MASTER
+ range 0 48 if ESP32S3_I2S0_ROLE_SLAVE
config ESP32S3_I2S0_DINPIN
int "I2S0 DIN pin"
depends on ESP32S3_I2S0_RX
default 19
- range 0 39
+ range 0 48
config ESP32S3_I2S0_DOUTPIN
int "I2S0 DOUT pin"
depends on ESP32S3_I2S0_TX
default 18
- range 0 33
+ range 0 48
config ESP32S3_I2S0_MCLK
bool "Enable I2S Master Clock"
@@ -398,7 +398,7 @@ config ESP32S3_I2S0_MCLKPIN
int "I2S MCLK pin"
depends on ESP32S3_I2S0_MCLK
default 0
- range 0 39
+ range 0 48
endif #ESP32S3_I2S0
@@ -478,26 +478,26 @@ config ESP32S3_I2S1_SAMPLE_RATE
config ESP32S3_I2S1_BCLKPIN
int "I2S1 BCLK pin"
default 22
- range 0 33 if ESP32S3_I2S1_ROLE_MASTER
- range 0 39 if ESP32S3_I2S1_ROLE_SLAVE
+ range 0 48 if ESP32S3_I2S1_ROLE_MASTER
+ range 0 48 if ESP32S3_I2S1_ROLE_SLAVE
config ESP32S3_I2S1_WSPIN
int "I2S1 WS pin"
default 23
- range 0 33 if ESP32S3_I2S1_ROLE_MASTER
- range 0 39 if ESP32S3_I2S1_ROLE_SLAVE
+ range 0 48 if ESP32S3_I2S1_ROLE_MASTER
+ range 0 48 if ESP32S3_I2S1_ROLE_SLAVE
config ESP32S3_I2S1_DINPIN
int "I2S1 DIN pin"
depends on ESP32S3_I2S1_RX
default 26
- range 0 39
+ range 0 48
config ESP32S3_I2S1_DOUTPIN
int "I2S1 DOUT pin"
depends on ESP32S3_I2S1_TX
default 25
- range 0 33
+ range 0 48
config ESP32S3_I2S1_MCLK
bool "Enable I2S Master Clock"
@@ -510,7 +510,7 @@ config ESP32S3_I2S1_MCLKPIN
int "I2S MCLK pin"
depends on ESP32S3_I2S1_MCLK
default 1
- range 0 39
+ range 0 48
endif #ESP32S3_I2S1
(nuttx) 03/03: ESP32S3 I2S GPIO selection master/slave hase same range for BCLK,WS pin
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 01aeeaeac62a47ff3e713ed13c866e34841b96fc
Author: Omar <om...@gmail.com>
AuthorDate: Wed Apr 10 00:56:46 2024 +0600
ESP32S3 I2S GPIO selection master/slave hase same range for BCLK,WS pin
---
arch/xtensa/src/esp32s3/Kconfig | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig
index d2bc321c3a..6ed15a33bb 100644
--- a/arch/xtensa/src/esp32s3/Kconfig
+++ b/arch/xtensa/src/esp32s3/Kconfig
@@ -366,14 +366,12 @@ config ESP32S3_I2S0_SAMPLE_RATE
config ESP32S3_I2S0_BCLKPIN
int "I2S0 BCLK pin"
default 4
- range 0 48 if ESP32S3_I2S0_ROLE_MASTER
- range 0 48 if ESP32S3_I2S0_ROLE_SLAVE
+ range 0 48
config ESP32S3_I2S0_WSPIN
int "I2S0 WS pin"
default 5
- range 0 48 if ESP32S3_I2S0_ROLE_MASTER
- range 0 48 if ESP32S3_I2S0_ROLE_SLAVE
+ range 0 48
config ESP32S3_I2S0_DINPIN
int "I2S0 DIN pin"
@@ -478,14 +476,12 @@ config ESP32S3_I2S1_SAMPLE_RATE
config ESP32S3_I2S1_BCLKPIN
int "I2S1 BCLK pin"
default 22
- range 0 48 if ESP32S3_I2S1_ROLE_MASTER
- range 0 48 if ESP32S3_I2S1_ROLE_SLAVE
+ range 0 48
config ESP32S3_I2S1_WSPIN
int "I2S1 WS pin"
default 23
- range 0 48 if ESP32S3_I2S1_ROLE_MASTER
- range 0 48 if ESP32S3_I2S1_ROLE_SLAVE
+ range 0 48
config ESP32S3_I2S1_DINPIN
int "I2S1 DIN pin"
(nuttx) 02/03: ESP32S3 configuring gpio pin 19 or 20 ( USB_D+/- ) for any purposes
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 4c744f1c0eb8370e981a533de80d97491166754f
Author: Omar <om...@gmail.com>
AuthorDate: Sat Apr 6 03:56:07 2024 +0600
ESP32S3 configuring gpio pin 19 or 20 ( USB_D+/- ) for any purposes
---
arch/xtensa/src/esp32s3/esp32s3_gpio.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/xtensa/src/esp32s3/esp32s3_gpio.c b/arch/xtensa/src/esp32s3/esp32s3_gpio.c
index d36b951b9f..d89799ac23 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_gpio.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_gpio.c
@@ -41,6 +41,7 @@
#include "esp32s3_irq.h"
#include "hardware/esp32s3_gpio.h"
#include "hardware/esp32s3_iomux.h"
+#include "hardware/esp32s3_usb_serial_jtag.h"
/****************************************************************************
* Pre-processor Definitions
@@ -207,6 +208,17 @@ int esp32s3_configgpio(uint32_t pin, gpio_pinattr_t attr)
func = 0;
cntrl = 0;
+ /* if pin 19 or 20 disable the USB/JTAG function and pull-up */
+
+ if (pin == 19 || pin == 20)
+ {
+ uint32_t regval;
+ regval = getreg32(USB_SERIAL_JTAG_CONF0_REG);
+ regval &= ~(USB_SERIAL_JTAG_USB_PAD_ENABLE |
+ USB_SERIAL_JTAG_DP_PULLUP);
+ putreg32(regval, USB_SERIAL_JTAG_CONF0_REG);
+ }
+
/* Handle input pins */
if ((attr & INPUT) != 0)