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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/03/14 04:37:16 UTC
[GitHub] [incubator-nuttx] anchao opened a new pull request #5734: arm/armv7-a/r: set the default CPU mode to System
anchao opened a new pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734
## Summary
In SVC mode, the banked register will be inconsistent with the user mode register:
```
arch/arm/src/armv7-a/arm_vectors.S
276 .globl arm_syscall
277 .globl arm_vectorsvc
278 .type arm_vectorsvc, %function
279
280 arm_vectorsvc:
...
286 sub sp, sp, #XCPTCONTEXT_SIZE **// < SVC mode SP**
...
308 stmia r0, {r13, r14}^ **// < USR mode SP/LR**
...
```
```
[ 2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[ 2.200000] [ 4] [ ALERT] R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[ 2.200000] [ 4] [ ALERT] R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[ 2.200000] [ 4] [ ALERT] CPSR: 00000073
[ 2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[ 2.200000] [ 4] [ ALERT] R0: 1 80202018 1 80202018 0 0 0 802027d0
[ 2.200000] [ 4] [ ALERT] R8: 0 0 0 0 0 802027d0 1080f710 80001229
[ 2.200000] [ 4] [ ALERT] CPSR: 00000070
```
SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE
```
[ 2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[ 2.200000] [ 4] [ ALERT] R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[ 2.200000] [ 4] [ ALERT] R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[ 2.200000] [ 4] [ ALERT] CPSR: 00000070
[ 2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[ 2.200000] [ 4] [ ALERT] R0: 2b 0 80202780 0 0 0 0 80202710
[ 2.200000] [ 4] [ ALERT] R8: 0 0 0 0 0 10843d80 800039d5 10801425
[ 2.200000] [ 4] [ ALERT] CPSR: 00000073
```
SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode
This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.
Signed-off-by: chao.an <an...@xiaomi.com>
## Impact
armv7-a/r: PSR_MODE_SVC -> PSR_MODE_SYS
## Testing
sabre-6quad/netknsh (/mnt/nfs/bin/getprime)
sabre-6quad/smp(ostest)
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[GitHub] [incubator-nuttx] masayuki2009 commented on a change in pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
masayuki2009 commented on a change in pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#discussion_r825602682
##########
File path: arch/arm/src/armv7-a/arm_vectors.S
##########
@@ -279,53 +220,39 @@ arm_vectorirq:
arm_vectorsvc:
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r13 /* Switch to SYS mode */
+
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0 /* Switch back IRQ mode */
Review comment:
`Switch back to SVC mode` ?
##########
File path: arch/arm/src/arm/arm_vectors.S
##########
@@ -207,54 +147,33 @@ arm_vectorirq:
.type arm_vectorsvc, %function
arm_vectorsvc:
+ /* On entry, we are in IRQ mode. We are free to use the IRQ mode r13
+ * and r14.
Review comment:
`IRQ mode` -> `SVC mode` ?
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#discussion_r825642693
##########
File path: arch/arm/src/armv7-r/arm_schedulesigaction.c
##########
@@ -167,7 +167,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
- tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
+ tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
Review comment:
```suggestion
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT;
```
##########
File path: arch/arm/src/armv7-r/arm_schedulesigaction.c
##########
@@ -131,7 +131,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
- CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
+ CURRENT_REGS[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
Review comment:
```suggestion
CURRENT_REGS[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT;
```
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[GitHub] [incubator-nuttx] anchao commented on a change in pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
anchao commented on a change in pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#discussion_r825620627
##########
File path: arch/arm/src/armv7-r/arm_vectors.S
##########
@@ -233,53 +174,39 @@ arm_vectorirq:
arm_vectorsvc:
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r13 /* Switch to SYS mode */
+
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0 /* Switch back IRQ mode */
/* Get the values for r15(pc) and CPSR in r3 and r4 */
mov r3, r14 /* Save r14 as the PC as well */
mrs r4, spsr /* Get the saved CPSR */
-#ifdef CONFIG_BUILD_PROTECTED
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Lsvcentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Lsvccontinue
-
-.Lsvcentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Lsvccontinue:
-
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
#else
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0
+
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
Done
##########
File path: arch/arm/src/armv7-a/arm_vectors.S
##########
@@ -279,53 +220,39 @@ arm_vectorirq:
arm_vectorsvc:
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r13 /* Switch to SYS mode */
+
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0 /* Switch back IRQ mode */
/* Get the values for r15(pc) and CPSR in r3 and r4 */
mov r3, r14 /* Save r14 as the PC as well */
mrs r4, spsr /* Get the saved CPSR */
-#ifdef CONFIG_BUILD_KERNEL
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Lsvcentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Lsvccontinue
-
-.Lsvcentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Lsvccontinue:
-
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
#else
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0
+
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
Done
##########
File path: arch/arm/src/armv7-a/arm_vectors.S
##########
@@ -141,50 +141,15 @@ arm_vectorirq:
sub r3, lr, #4
mrs r4, spsr
- /* Then switch back to SVC mode */
+ /* Then switch back to SYS mode */
#ifdef CONFIG_ARMV7A_DECODEFIQ
- orr r0, r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
#else
- orr r0, r0, #(PSR_MODE_SVC | PSR_I_BIT)
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT)
#endif
msr cpsr_c, r0
-#ifdef CONFIG_BUILD_KERNEL
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Lirqentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Lirqcontinue
-
-.Lirqentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Lirqcontinue:
-
-#else
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
Done
##########
File path: arch/arm/src/arm/arm_vectors.S
##########
@@ -346,46 +240,11 @@ arm_vectordata:
sub r3, lr, #8
mrs r4, spsr
- /* Then switch back to SVC mode */
+ /* Then switch back to SYS mode */
- mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+ mov r0, #(PSR_MODE_SYS | PSR_I_BIT)
msr cpsr_c, r0
-#ifdef CONFIG_BUILD_KERNEL
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Ldabtentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Ldabtcontinue
-
-.Ldabtentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Ldabtcontinue:
-
-#else
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
Done
##########
File path: arch/arm/src/armv7-a/arm_vectors.S
##########
@@ -279,53 +220,39 @@ arm_vectorirq:
arm_vectorsvc:
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r13 /* Switch to SYS mode */
+
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0 /* Switch back IRQ mode */
Review comment:
Done
##########
File path: arch/arm/src/arm/arm_vectors.S
##########
@@ -207,54 +147,33 @@ arm_vectorirq:
.type arm_vectorsvc, %function
arm_vectorsvc:
+ /* On entry, we are in IRQ mode. We are free to use the IRQ mode r13
+ * and r14.
Review comment:
Done
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#discussion_r825712761
##########
File path: arch/arm/src/armv7-a/arm_schedulesigaction.c
##########
@@ -137,7 +137,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
- CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
+ CURRENT_REGS[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
Review comment:
ok.
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[GitHub] [incubator-nuttx] anchao commented on a change in pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
anchao commented on a change in pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#discussion_r825700309
##########
File path: arch/arm/src/arm/arm_vectors.S
##########
@@ -207,55 +147,34 @@ arm_vectorirq:
.type arm_vectorsvc, %function
arm_vectorsvc:
+ /* On entry, we are in SVC mode. We are free to use the IRQ mode r13
Review comment:
Done
##########
File path: arch/arm/src/arm/arm_vectors.S
##########
@@ -207,55 +147,34 @@ arm_vectorirq:
.type arm_vectorsvc, %function
arm_vectorsvc:
+ /* On entry, we are in SVC mode. We are free to use the IRQ mode r13
+ * and r14.
+ */
+
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+ msr cpsr_c, r13 /* Switch to SYS mode */
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+ msr cpsr_c, r0 /* Switch back IRQ mode */
Review comment:
Done
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[GitHub] [incubator-nuttx] pkarashchenko commented on pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#issuecomment-1066443079
@anchao could you please take a look if https://github.com/apache/incubator-nuttx/pull/5558/files#r824257401 is relevant?
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#discussion_r825643859
##########
File path: arch/arm/src/arm/arm_vectors.S
##########
@@ -207,55 +147,34 @@ arm_vectorirq:
.type arm_vectorsvc, %function
arm_vectorsvc:
+ /* On entry, we are in SVC mode. We are free to use the IRQ mode r13
Review comment:
```suggestion
/* On entry, we are in SVC mode. We are free to use the SVC mode r13
```
##########
File path: arch/arm/src/arm/arm_vectors.S
##########
@@ -207,55 +147,34 @@ arm_vectorirq:
.type arm_vectorsvc, %function
arm_vectorsvc:
+ /* On entry, we are in SVC mode. We are free to use the IRQ mode r13
+ * and r14.
+ */
+
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+ msr cpsr_c, r13 /* Switch to SYS mode */
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+ msr cpsr_c, r0 /* Switch back IRQ mode */
Review comment:
```suggestion
msr cpsr_c, r0 /* Switch back SVC mode */
```
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#issuecomment-1066622950
@masayuki2009 let's merge this patch?
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[GitHub] [incubator-nuttx] pkarashchenko removed a comment on pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
pkarashchenko removed a comment on pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#issuecomment-1066443079
@anchao could you please take a look if https://github.com/apache/incubator-nuttx/pull/5558/files#r824257401 is relevant?
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#discussion_r825640466
##########
File path: arch/arm/src/armv7-a/arm_schedulesigaction.c
##########
@@ -137,7 +137,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
- CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
+ CURRENT_REGS[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
Review comment:
```suggestion
CURRENT_REGS[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT;
```
##########
File path: arch/arm/src/armv7-a/arm_schedulesigaction.c
##########
@@ -259,7 +259,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
- tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
+ tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
Review comment:
```suggestion
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT;
```
##########
File path: arch/arm/src/armv7-a/arm_schedulesigaction.c
##########
@@ -172,7 +172,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
- tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
+ tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT);
Review comment:
```suggestion
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT;
```
##########
File path: arch/arm/src/armv7-a/arm_schedulesigaction.c
##########
@@ -349,7 +349,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
- tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
+ tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT);
Review comment:
```suggestion
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT;
```
##########
File path: arch/arm/src/armv7-a/arm_schedulesigaction.c
##########
@@ -285,7 +285,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
- CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
+ CURRENT_REGS[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
Review comment:
```suggestion
CURRENT_REGS[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT;
```
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[GitHub] [incubator-nuttx] anchao commented on pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
anchao commented on pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#issuecomment-1077021585
> > I noticed that this PR does not work with the sabre-6quad dev board (QEMU works fine though)
@masayuki2009 san,
I need some time to confirm this issue, I will reply you later.
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[GitHub] [incubator-nuttx] masayuki2009 commented on pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
masayuki2009 commented on pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#issuecomment-1077008379
@anchao
>I noticed that this PR does not work with the sabre-6quad dev board (QEMU works fine though)
sabre-6quad:nsh dev board with debug build
```
ABDGHIJKPQ
[ 0.000000] arm_prefetchabort: Prefetch abort. PC: 1080180c IFAR: 1080180c IFSR: 0000000d
[ 0.000000] up_assert: Assertion failed at file:armv7-a/arm_prefetchabort.c line: 134 task: Idle Task
[ 0.000000] arm_registerdump: R0: 00000000 R1: 00000000 R2: 00000000 R3: 00000000
[ 0.000000] arm_registerdump: R4: 00000000 R5: 00000000 R6: 00000000 FP: 00000000
[ 0.000000] arm_registerdump: R8: 00000000 SB: 00000000 SL: 00000000 R11: 00000000
[ 0.000000] arm_registerdump: IP: 00000000 SP: 10824a38 LR: 00000000 PC: 1080180c
[ 0.000000] arm_registerdump: CPSR: 00000010
[ 0.000000] arm_dump_stack: IRQ Stack:
[ 0.000000] arm_dump_stack: sp: 10824930
[ 0.000000] arm_dump_stack: base: 10820988
[ 0.000000] arm_dump_stack: size: 00000800
[ 0.000000] arm_dump_stack: ERROR: IRQ Stack pointer is not within the stack
[ 0.000000] arm_stackdump: 10820980: 00000000 deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108209a0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108209c0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108209e0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820a00: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820a20: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820a40: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820a60: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820a80: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820aa0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820ac0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820ae0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820b00: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820b20: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820b40: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820b60: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820b80: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820ba0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820bc0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820be0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820c00: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820c20: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820c40: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820c60: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820c80: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820ca0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820cc0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820ce0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820d00: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820d20: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820d40: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820d60: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820d80: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820da0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820dc0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820de0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820e00: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820e20: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820e40: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820e60: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820e80: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820ea0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820ec0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820ee0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820f00: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820f20: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820f40: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820f60: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820f80: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820fa0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820fc0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10820fe0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10821000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10821020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10821040: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10821060: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10821080: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108210a0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108210c0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108210e0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10821100: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10821120: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10821140: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10821160: deadbeef deadbeef 10823e68 108232a4 0000015f 10800b89 10821184 10800294
[ 0.000000] arm_dump_stack: User Stack:
[ 0.000000] arm_dump_stack: sp: 10824a38
[ 0.000000] arm_dump_stack: base: 10822fa8
[ 0.000000] arm_dump_stack: size: 000003e8
[ 0.000000] arm_dump_stack: ERROR: User Stack pointer is not within the stack
[ 0.000000] arm_stackdump: 10822fa0: 00000000 00000000 deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10822fc0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10822fe0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823040: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823060: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823080: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108230a0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108230c0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108230e0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823100: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823120: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823140: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823160: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823180: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108231a0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108231c0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 108231e0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823200: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
[ 0.000000] arm_stackdump: 10823220: deadbeef deadbeef 00000000 10823390 1082094a 00000000 10823d40 10801dfb
[ 0.000000] arm_stackdump: 10823240: 00000006 00000000 00000000 10802ef1 00000000 10820138 00000010 1082329c
[ 0.000000] arm_stackdump: 10823260: 00000000 108030f7 108232ac 00000010 00000000 10823390 1082094a 00000000
[ 0.000000] arm_stackdump: 10823280: 10823d40 10801dfb 00000009 00000000 00000000 10802ef1 00000000 10820138
[ 0.000000] arm_stackdump: 108232a0: 00000012 00000002 10821c0c 10823e68 10821c0c 10821b94 0000015f 10821d14
[ 0.000000] arm_stackdump: 108232c0: 10821b8c 276006fc 00000000 275ffd3e 00000000 00000003 1082336c 10801365
[ 0.000000] arm_stackdump: 108232e0: 10805724 000001ff 00000000 68736e00 69616d5f 0000006e 10824a40 1080d693
[ 0.000000] arm_stackdump: 10823300: 00000000 10821b94 10824a40 108056d3 10824a40 0000015f 00000064 10801807
[ 0.000000] arm_stackdump: 10823320: 10824d40 00000002 10824a40 10801487 00000800 10805979 00000000 00000000
[ 0.000000] arm_stackdump: 10823340: 00000000 10821d04 10823df0 10821b94 10821d14 10821d14 10821b8c 108055af
[ 0.000000] arm_stackdump: 10823360: 10821b94 0000015f 10821d14 10801365 10821b94 10821d04 10821d00 108011a7
[ 0.000000] arm_showtasks: PID PRI USED STACK FILLED COMMAND
[ 0.000000] arm_showtasks: ---- ---- 32 2048 1.5% irq
[ 0.000000] arm_dump_task: 0 0 360 1000 36.0% Idle Task
[ 0.000000] arm_dump_task: 1 192 620 2016 30.7% hpwork
[ 0.000000] arm_dump_task: 2 100 0 2024 0.0% nsh_main
```
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[GitHub] [incubator-nuttx] anchao commented on pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
anchao commented on pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#issuecomment-1080894299
> > > I noticed that this PR does not work with the sabre-6quad dev board (QEMU works fine though)
>
> @masayuki2009 san, I need some time to confirm this issue, I will reply you later.
@masayuki2009 san, could you plz try this PR?
https://github.com/apache/incubator-nuttx/pull/5896
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[GitHub] [incubator-nuttx] anchao commented on a change in pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
anchao commented on a change in pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#discussion_r825700064
##########
File path: arch/arm/src/armv7-a/arm_schedulesigaction.c
##########
@@ -137,7 +137,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
- CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT |
+ CURRENT_REGS[REG_CPSR] = (PSR_MODE_SYS | PSR_I_BIT |
PSR_F_BIT);
Review comment:
I think there is no problem with parentheses, if formatting changes are necessary, which should be a separate PR.
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[GitHub] [incubator-nuttx] masayuki2009 merged pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
masayuki2009 merged pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on a change in pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#discussion_r825605528
##########
File path: arch/arm/src/armv7-a/arm_vectors.S
##########
@@ -279,53 +220,39 @@ arm_vectorirq:
arm_vectorsvc:
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r13 /* Switch to SYS mode */
+
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0 /* Switch back IRQ mode */
/* Get the values for r15(pc) and CPSR in r3 and r4 */
mov r3, r14 /* Save r14 as the PC as well */
mrs r4, spsr /* Get the saved CPSR */
-#ifdef CONFIG_BUILD_KERNEL
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Lsvcentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Lsvccontinue
-
-.Lsvcentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Lsvccontinue:
-
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
#else
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0
+
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
SVC->USR/SYS
##########
File path: arch/arm/src/arm/arm_vectors.S
##########
@@ -346,46 +240,11 @@ arm_vectordata:
sub r3, lr, #8
mrs r4, spsr
- /* Then switch back to SVC mode */
+ /* Then switch back to SYS mode */
- mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+ mov r0, #(PSR_MODE_SYS | PSR_I_BIT)
msr cpsr_c, r0
-#ifdef CONFIG_BUILD_KERNEL
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Ldabtentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Ldabtcontinue
-
-.Ldabtentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Ldabtcontinue:
-
-#else
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
SVC->USR/SYS
##########
File path: arch/arm/src/armv7-r/arm_vectors.S
##########
@@ -233,53 +174,39 @@ arm_vectorirq:
arm_vectorsvc:
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r13 /* Switch to SYS mode */
+
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0 /* Switch back IRQ mode */
/* Get the values for r15(pc) and CPSR in r3 and r4 */
mov r3, r14 /* Save r14 as the PC as well */
mrs r4, spsr /* Get the saved CPSR */
-#ifdef CONFIG_BUILD_PROTECTED
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Lsvcentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Lsvccontinue
-
-.Lsvcentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Lsvccontinue:
-
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
#else
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0
+
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
SVC->USR/SYS
##########
File path: arch/arm/src/armv7-a/arm_vectors.S
##########
@@ -141,50 +141,15 @@ arm_vectorirq:
sub r3, lr, #4
mrs r4, spsr
- /* Then switch back to SVC mode */
+ /* Then switch back to SYS mode */
#ifdef CONFIG_ARMV7A_DECODEFIQ
- orr r0, r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
#else
- orr r0, r0, #(PSR_MODE_SVC | PSR_I_BIT)
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT)
#endif
msr cpsr_c, r0
-#ifdef CONFIG_BUILD_KERNEL
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Lirqentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Lirqcontinue
-
-.Lirqentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Lirqcontinue:
-
-#else
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
SVC->USR/SYS
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[GitHub] [incubator-nuttx] masayuki2009 commented on pull request #5734: arm/armv7-a/r: set the default CPU mode to System
Posted by GitBox <gi...@apache.org>.
masayuki2009 commented on pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#issuecomment-1076223466
@xiaoxiang781216 @anchao
Did you test this PR with your Cortex-A-based boards?
I noticed that this PR does not work with the sabre-6quad dev board (QEMU works fine though)
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