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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2020/05/14 21:57:47 UTC
[GitHub] [incubator-nuttx] hartmannathan opened a new pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
hartmannathan opened a new pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051
## Summary
Add support for the STM32G474 family of microcontrollers and the B-G474E-DPOW1 Discovery Board, which features a STM32G474RET6.
## Impact
This is a major pull request as it adds support for an entirely new family of STM32. This support is implemented in arch/arm/src/stm32 and shares implementation with other STM32 families supported by that code, such as the 'L15xx, 'F10xx, 'F20xx, 'F3xxx, and 'F4xxx.
## Testing
The B-G474E-DPOW1 Discovery Board boots successfully through to the NSH prompt. NSH runs and is responsive.
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[GitHub] [incubator-nuttx] davids5 commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
davids5 commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426248011
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
Review comment:
```suggestion
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
```
Is the CS check passing?
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or Time Stamp (see STM32_IRQ_TIMESTAMP) */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
+#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
+#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
+#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
+#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
+#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
+#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
+#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt (see also STM32_IRQ_ADC2) */
+#define STM32_IRQ_USBHP (STM32_IRQ_FIRST+19) /* 19: USB High priority interrupt */
+
+#define STM32_IRQ_USBLP (STM32_IRQ_FIRST+20) /* 20: USB Low priority interrupt */
+#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST+21) /* 21: FDCAN1 interrupt 0 */
+#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST+22) /* 22: FDCAN1 interrupt 1 */
+#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt (see also STM32_IRQ_TIM1BRK) */
+#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt (see also STM32_IRQ_TIM1UP) */
+#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt (see also STM32_IRQ_TIM1TRGCOM) */
+#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+
+#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
+#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
+#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
+#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
+#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+
+#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST+42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */
+#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break, Transition error, Index error */
+#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
+#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */
+#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
+#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
+#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */
+#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST+49) /* 49: LPTIM1 interrupt */
+
+#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
+#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
+#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
+#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
+#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt (see also STM32_IRQ_DAC1, STM32_IRQ_DAC3) */
+#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt (see also STM32_IRQ_DAC2, STM32_IRQ_DAC4) */
+#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST+56) /* 56: DMA2 channel 1 global interrupt */
+#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST+57) /* 57: DMA2 channel 2 global interrupt */
+#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST+58) /* 58: DMA2 channel 3 global interrupt */
+#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST+59) /* 59: DMA2 channel 4 global interrupt */
+
+#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST+60) /* 60: DMA2 channel 5 global interrupt */
+#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST+61) /* 61: ADC4 global interrupt */
+#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST+62) /* 62: ADC5 global interrupt */
+#define STM32_IRQ_UCPD (STM32_IRQ_FIRST+63) /* 63: UCPD global interrupt */
+#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST+64) /* 64: COMP1, COMP2, and COMP3 interrupts */
+#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST+65) /* 65: COMP4, COMP5, and COMP6 interrupts */
+#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST+66) /* 66: COMPP7 interrupt */
+#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST+67) /* 67: HRTIM1 master timer interrupt */
+#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST+68) /* 68: HRTIM1 timer A interrupt */
+#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST+69) /* 69: HRTIM1 timer B interrupt */
+
+#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST+70) /* 70: HRTIM1 timer C interrupt */
+#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST+71) /* 71: HRTIM1 timer D interrupt */
+#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST+72) /* 72: HRTIM1 timer E interrupt */
+#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST+73) /* 73: HRTIM1 fault interrupt */
+#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST+74) /* 74: HRTIM1 timer E interrupt */
+#define STM32_IRQ_CRS (STM32_IRQ_FIRST+75) /* 75: CRS (Clock Recovery System) global interrupt */
+#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+76) /* 76: SAI4 global interrupt */
+#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST+77) /* 77: TIM20 Break, Transition error, Index error interrupt */
+#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST+78) /* 78: TIM20 Update interrupt */
+#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST+79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */
+
+#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST+80) /* 80: TIM20 Capture Compare interrupt */
+#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+82) /* 82: I2C4 event interrupt */
+#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+83) /* 83: I2C4 error interrupt */
+#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
+#define STM32_IRQ_AES (STM32_IRQ_FIRST+85) /* 85: AES global interrupt */
+#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST+86) /* 86: FDCAN2 interrupt 0 */
+#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST+87) /* 87: FDCAN2 interrupt 1 */
+#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST+88) /* 88: FDCAN3 interrupt 0 */
+#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST+89) /* 89: FDCAN3 interrupt 1 */
+
+#define STM32_IRQ_RNG (STM32_IRQ_FIRST+90) /* 90: RNG global interrupt */
+#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST+91) /* 91: LPUART1 */
Review comment:
The reference manual drops the 1 describes this as LPUART global interrupt
##########
File path: arch/arm/src/stm32/hardware/stm32_dma_v1.h
##########
@@ -64,6 +64,9 @@
#define DMA_CHAN5 (4)
#define DMA_CHAN6 (5)
#define DMA_CHAN7 (6)
+#if defined(CONFIG_STM32_STM32G47XX)
Review comment:
Yes this is critical - think feature set not chip. Condition things on features, then the chip defines that is HAS or HAVE the feature. This keep code churn and if def rash to the bare minimum.
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_pwr.h
##########
@@ -0,0 +1,485 @@
+/****************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_pwr.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32_PWR_CR1_OFFSET 0x0000 /* PWR Power Control Register 1 */
+#define STM32_PWR_CR2_OFFSET 0x0004 /* PWR Power Control Register 2 */
+#define STM32_PWR_CR3_OFFSET 0x0008 /* PWR Power Control Register 3 */
+#define STM32_PWR_CR4_OFFSET 0x000c /* PWR Power Control Register 4 */
+#define STM32_PWR_SR1_OFFSET 0x0010 /* PWR Power Status Register 1 */
+#define STM32_PWR_SR2_OFFSET 0x0014 /* PWR Power Status Register 2 */
+#define STM32_PWR_SCR_OFFSET 0x0018 /* PWR Power Status Reset Register */
+ /* Offset 0x001c Reserved */
+#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A Pull Up Control Register */
+#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A Pull Down Control Register */
+#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B Pull Up Control Register */
+#define STM32_PWR_PDCRB_OFFSET 0x002c /* Power Port B Pull Down Control Register */
+#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C Pull Up Control Register */
+#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C Pull Down Control Register */
+#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D Pull Up Control Register */
+#define STM32_PWR_PDCRD_OFFSET 0x003c /* Power Port D Pull Down Control Register */
+#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E Pull Up Control Register */
+#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E Pull Down Control Register */
+#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F Pull Up Control Register */
+#define STM32_PWR_PDCRF_OFFSET 0x004c /* Power Port F Pull Down Control Register */
+#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G Pull Up Control Register */
+#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G Pull Down Control Register */
+ /* Offset 0x0058 Reserved */
+ /* Offset 0x005C Reserved */
+ /* Offset 0x0060 Reserved */
+ /* Offset 0x0064 Reserved */
+ /* Offset 0x0068 Reserved */
+ /* Offset 0x006C Reserved */
+ /* Offset 0x0070 Reserved */
+ /* Offset 0x0074 Reserved */
+ /* Offset 0x0078 Reserved */
+ /* Offset 0x007C Reserved */
+#define STM32_PWR_CR5_OFFSET 0x0080 /* PWR Power Control Register 5 */
+
+/* Register Addresses *******************************************************/
+
+#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET)
+#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET)
+#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET)
+#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET)
+#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET)
+#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET)
+#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET)
+#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET)
+#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET)
+#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET)
+#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET)
+#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET)
+#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET)
+#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET)
+#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET)
+#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET)
+#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET)
+#define STM32_PWR_PUCRF (STM32_PWR_BASE + STM32_PWR_PUCRF_OFFSET)
+#define STM32_PWR_PDCRF (STM32_PWR_BASE + STM32_PWR_PDCRF_OFFSET)
+#define STM32_PWR_PUCRG (STM32_PWR_BASE + STM32_PWR_PUCRG_OFFSET)
+#define STM32_PWR_PDCRG (STM32_PWR_BASE + STM32_PWR_PDCRG_OFFSET)
+#define STM32_PWR_CR5 (STM32_PWR_BASE + STM32_PWR_CR5_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* PWR Power Control Register 1 (CR1) */
+
+#define PWR_CR1_LPR_SHIFT (14) /* Low Power Run */
+#define PWR_CR1_LPR (0x1 << PWR_CR1_LPR_SHIFT)
+#define PWR_CR1_VOS_SHIFT (9) /* Voltage Scaling Range Selection */
+#define PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_SHIFT)
+# define PWR_CR1_VOS_RANGE_1 (0x1 << PWR_CR1_VOS_SHIFT)
+# define PWR_CR1_VOS_RANGE_2 (0x2 << PWR_CR1_VOS_SHIFT)
+#define PWR_CR1_DBP_SHIFT (8) /* Disable Backup Domain Write Protection */
+#define PWR_CR1_DBP (0x1 << PWR_CR1_DBP_SHIFT)
+#define PWR_CR1_LPMS_SHIFT (0) /* Low Power Mode Selection */
+#define PWR_CR1_LPMS_MASK (0x7 << PWR_CR1_LPMS_SHIFT)
+# define PWR_CR1_LPMS_STOP_0 (0x0 << PWR_CR1_LPMS_SHIFT) /* Stop 0 Mode */
+# define PWR_CR1_LPMS_STOP_1 (0x1 << PWR_CR1_LPMS_SHIFT) /* Stop 1 Mode */
+# define PWR_CR1_LPMS_STANDBY (0x3 << PWR_CR1_LPMS_SHIFT) /* Standby Mode */
+# define PWR_CR1_LPMS_SHUTDOWN (0x4 << PWR_CR1_LPMS_SHIFT) /* Shutdown Mode */
+
+/* PWR Power Control Register 2 (CR2) */
+
+#define PWR_CR2_PVMEN2_SHIFT (7) /* Peripheral Voltage Monitoring 4 Enable (VDDA vs DAC 1Msps or 15Msps Minimum Voltage) */
+#define PWR_CR2_PVMEN2 (0x1 << PWR_CR2_PVMEN2_SHIFT)
+#define PWR_CR2_PVMEN1_SHIFT (6) /* Peripheral Voltage Monitoring 3 Enable (VDDA vs ADC or COMP Minimum Voltage) */
+#define PWR_CR2_PVMEN1 (0x1 << PWR_CR2_PVMEN1_SHIFT)
+#define PWR_CR2_PLS_SHIFT (1) /* Power Voltage Detector Level Selection */
+#define PWR_CR2_PLS_MASK (0x7 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_0 (0x0 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_1 (0x1 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_2 (0x2 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_3 (0x3 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_4 (0x4 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_5 (0x5 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_6 (0x6 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_7 (0x7 << PWR_CR2_PLS_SHIFT)
+#define PWR_CR2_PVDE_SHIFT (0) /* Power Voltage Detector Enable */
+#define PWR_CR2_PVDE (0x1 << PWR_CR2_PVDE_SHIFT)
+
+/* PWR Power Control Register 3 (CR3) */
+
+#define PWR_CR3_EIWUL_SHIFT (15) /* Enable Internal Wake Up Line */
+#define PWR_CR3_EIWUL (0x1 << PWR_CR3_EIWUL_SHIFT)
+#define PWR_CR3_UCPD1_DBDIS_SHIFT (14) /* USB Type C And Power Delivery Dead Battery Disable */
+#define PWR_CR3_UCPD1_DBDIS (0x1 << PWR_CR3_UCPD1_DBDIS_SHIFT)
+#define PWR_CR3_UCPD1_STDBY_SHIFT (13) /* USB Type C And Power Delivery Standby Mode */
+#define PWR_CR3_UCPD1_STDBY (0x1 << PWR_CR3_UCPD1_STDBY_SHIFT)
+#define PWR_CR3_APC_SHIFT (10) /* Apply Pull Up And Pull Down Configuration */
+#define PWR_CR3_APC (0x1 << PWR_CR3_APC_SHIFT)
+#define PWR_CR3_RRS_SHIFT (8) /* SRAM2 Retention In Standby Mode */
+#define PWR_CR3_RRS (0x1 << PWR_CR3_RRS_SHIFT)
+#define PWR_CR3_EWUP5_SHIFT (4) /* Enable Wake Up Pin WKUP5 */
+#define PWR_CR3_EWUP5 (0x1 << PWR_CR3_EWUP5_SHIFT)
+#define PWR_CR3_EWUP4_SHIFT (3) /* Enable Wake Up Pin WKUP4 */
+#define PWR_CR3_EWUP4 (0x1 << PWR_CR3_EWUP4_SHIFT)
+#define PWR_CR3_EWUP3_SHIFT (2) /* Enable Wake Up Pin WKUP3 */
+#define PWR_CR3_EWUP3 (0x1 << PWR_CR3_EWUP3_SHIFT)
+#define PWR_CR3_EWUP2_SHIFT (1) /* Enable Wake Up Pin WKUP2 */
+#define PWR_CR3_EWUP2 (0x1 << PWR_CR3_EWUP2_SHIFT)
+#define PWR_CR3_EWUP1_SHIFT (0) /* Enable Wake Up Pin WKUP1 */
+#define PWR_CR3_EWUP1 (0x1 << PWR_CR3_EWUP1_SHIFT)
+
+/* PWR Power Control Register 4 (CR4) */
+
+#define PWR_CR4_VBRS_SHIFT (9) /* VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBRS (0x1 << PWR_CR4_VBRS_SHIFT)
+#define PWR_CR4_VBE_SHIFT (8) /* VBAT Battery charging Enable */
+#define PWR_CR4_VBE (0x1 << PWR_CR4_VBE_SHIFT)
+#define PWR_CR4_WP5_SHIFT (4) /* Wake Up Pin WKUP5 polarity */
+#define PWR_CR4_WP5 (0x1 << PWR_CR4_WP5_SHIFT)
+#define PWR_CR4_WP4_SHIFT (3) /* Wake Up Pin WKUP4 polarity */
+#define PWR_CR4_WP4 (0x1 << PWR_CR4_WP4_SHIFT)
+#define PWR_CR4_WP3_SHIFT (2) /* Wake Up Pin WKUP3 polarity */
+#define PWR_CR4_WP3 (0x1 << PWR_CR4_WP3_SHIFT)
+#define PWR_CR4_WP2_SHIFT (1) /* Wake Up Pin WKUP2 polarity */
+#define PWR_CR4_WP2 (0x1 << PWR_CR4_WP2_SHIFT)
+#define PWR_CR4_WP1_SHIFT (0) /* Wake Up Pin WKUP1 polarity */
+#define PWR_CR4_WP1 (0x1 << PWR_CR4_WP1_SHIFT)
+
+/* PWR Power Status Register 1 (SR1) */
+
+#define PWR_SR1_WUFI_SHIFT (15) /* Wake Up Flag Internal */
+#define PWR_SR1_WUFI (0x1 << PWR_SR1_WUFI_SHIFT)
+#define PWR_SR1_SBF_SHIFT (8) /* Stand-By Flag */
+#define PWR_SR1_SBF (0x1 << PWR_SR1_SBF_SHIFT)
+#define PWR_SR1_WUF_SHIFT (0) /* Wake Up Flags */
+#define PWR_SR1_WUF_MASK (0x1f << PWR_SR1_WUF_SHIFT)
+# define PWR_SR1_WUF5 (0x10 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 5 */
+# define PWR_SR1_WUF4 (0x8 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 4 */
+# define PWR_SR1_WUF3 (0x4 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 3 */
+# define PWR_SR1_WUF2 (0x2 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 2 */
+# define PWR_SR1_WUF1 (0x1 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 1 */
+
+/* PWR Power Status Register 2 (SR2) */
+
+#define PWR_SR2_PVMO4_SHIFT (15) /* Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO4 (0x1 << PWR_SR2_PVMO4_SHIFT)
+#define PWR_SR2_PVMO3_SHIFT (14) /* Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO3 (0x1 << PWR_SR2_PVMO3_SHIFT)
+#define PWR_SR2_PVMO2_SHIFT (13) /* Peripheral Voltage Monitoring Output 2 */
+#define PWR_SR2_PVMO2 (0x1 << PWR_SR2_PVMO2_SHIFT)
+#define PWR_SR2_PVMO1_SHIFT (12) /* Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVMO1 (0x1 << PWR_SR2_PVMO1_SHIFT)
+#define PWR_SR2_PVDO_SHIFT (11) /* Power Voltage Detector Output */
+#define PWR_SR2_PVDO (0x1 << PWR_SR2_PVDO_SHIFT)
+#define PWR_SR2_VOSF_SHIFT (10) /* Voltage Scaling Flag */
+#define PWR_SR2_VOSF (0x1 << PWR_SR2_VOSF_SHIFT)
+#define PWR_SR2_REGLPF_SHIFT (9) /* Low-power Regulator Flag */
+#define PWR_SR2_REGLPF (0x1 << PWR_SR2_REGLPF_SHIFT)
+#define PWR_SR2_REGLPS_SHIFT (8) /* Low-power Regulator Started */
+#define PWR_SR2_REGLPS (0x1 << PWR_SR2_REGLPS_SHIFT)
+#define PWR_SR2_FLASHRDY_SHIFT (7) /* Flash Ready Flag */
+#define PWR_SR2_FLASHRDY (0x1 << PWR_SR2_FLASHRDY_SHIFT)
+
+/* PWR Power Status Reset Register (SCR) */
+
+#define PWR_SCR_CSBF_SHIFT (8) /* Clear Standby Flag */
Review comment:
line then up please
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_rcc.h
##########
@@ -0,0 +1,677 @@
+/****************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_rcc.h
+ * Register offsets, addresses, and bitfield defines for STM32G47xxx RCC
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_RCC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_RCC_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Abbreviations:
+ * HSE - High Speed External (clock)
+ * HSI - High Speed Internal (clock)
+ * POR - Power On Reset
+ * RCC - Reset and Clock Control
+ */
+
+/* Register Offsets *********************************************************/
+
+#define STM32_RCC_CR_OFFSET 0x0000 /* RCC Clock Control */
+#define STM32_RCC_ICSCR_OFFSET 0x0004 /* RCC Internal Clock Sources Calibration */
+#define STM32_RCC_CFGR_OFFSET 0x0008 /* RCC Clock Configuration */
+#define STM32_RCC_PLLCFGR_OFFSET 0x000c /* RCC PLL configuration register */
+ /* Offset 0x0010 Reserved */
+ /* Offset 0x0014 Reserved */
+#define STM32_RCC_CIER_OFFSET 0x0018 /* RCC Clock Interrupt Enable */
+#define STM32_RCC_CIFR_OFFSET 0x001c /* RCC Clock Interrupt Flag */
+#define STM32_RCC_CICR_OFFSET 0x0020 /* RCC Clock Interrupt Clear */
+ /* Offset 0x0024 Reserved */
+#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* RCC AHB1 Peripheral Reset */
+#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* RCC AHB2 Peripheral Reset */
+#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* RCC AHB3 Peripheral Reset */
+ /* Offset 0x0034 Reserved */
+#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* RCC APB1 Peripheral Reset Register 1 */
+#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* RCC APB1 Peripheral Reset Register 2 */
+#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* RCC APB2 Peripheral Reset */
+ /* Offset 0x0044 Reserved */
+#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* RCC AHB1 Peripheral Clock Enable */
+#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* RCC AHB2 Peripheral Clock Enable */
+#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* RCC AHB3 Peripheral Clock Enable */
+ /* Offset 0x0054 Reserved */
+#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* RCC APB1 Peripheral Clock Enable Register 1 */
+#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* RCC APB1 Peripheral Clock Enable Register 2 */
+#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* RCC APB2 Peripheral Clock Enable */
+ /* Offset 0x0064 Reserved */
+#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 Peripheral Clock Enable in Sleep/Stop Modes */
+#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 Peripheral Clock Enable in Sleep/Stop Modes */
+#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 Peripheral Clock Enable in Sleep/Stop Modes */
+ /* Offset 0x0074 Reserved */
+#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 Peripheral Clock Enable in Sleep/Stop Modes (1 of 2) */
+#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 Peripheral Clock Enable in Sleep/Stop Modes (2 of 2) */
+#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 Peripheral Clock Enable in Sleep/Stop Modes */
+ /* Offset 0x0084 Reserved */
+#define STM32_RCC_CCIPR_OFFSET 0x0088 /* RCC Peripherals Independent Clock Configuration (1 of 2, see CCIPR2) */
+ /* Offset 0x008c Reserved */
+#define STM32_RCC_BDCR_OFFSET 0x0090 /* RCC RTC Domain Control Register */
+#define STM32_RCC_CSR_OFFSET 0x0094 /* RCC Clock Control / Status Register */
+#define STM32_RCC_CRRCR_OFFSET 0x0098 /* RCC Clock Recovery RC Register */
+#define STM32_RCC_CCIPR2_OFFSET 0x009c /* RCC Peripherals Independent Clock Configuration (2 of 2, see CCIPR) */
+
+/* Register Addresses *******************************************************/
+
+#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET)
+#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET)
+#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET)
+#define STM32_RCC_PLLCFGR (STM32_RCC_BASE + STM32_RCC_PLLCFGR_OFFSET)
+#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET)
+#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET)
+#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET)
+#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET)
+#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET)
+#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET)
+#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET)
+#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET)
+#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET)
+#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET)
+#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET)
+#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET)
+#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET)
+#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET)
+#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET)
+#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET)
+#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET)
+#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET)
+#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET)
+#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET)
+#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET)
+#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET)
+#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET)
+#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET)
+#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET)
+#define STM32_RCC_CCIPR2 (STM32_RCC_BASE + STM32_RCC_CCIPR2_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* CR - Clock Control Register */
+
+#define RCC_CR_HSION (1 << 8) /* Bit 8: HSI16 clock enable */
+#define RCC_CR_HSIKERON (1 << 9) /* Bit 9: HSI16 always enable for peripheral kernel */
+#define RCC_CR_HSIRDY (1 << 10) /* Bit 10: HSI16 clock ready flag */
+#define RCC_CR_HSEON (1 << 16) /* Bit 16: HSE clock enable */
+#define RCC_CR_HSERDY (1 << 17) /* Bit 17: HSE clock ready flag */
+#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: HSE crystal oscillator bypass */
+#define RCC_CR_CSSON (1 << 19) /* Bit 19: HSE clock security system enable */
+#define RCC_CR_PLLON (1 << 24) /* Bit 24: Main PLL enable */
+#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: Main PLL ready */
+
+#define RCC_CR_RESERVED_MASK 0xfcf0f8ff /* Bits 31-26, 23-20, 15-11, and 7-0 should be kept at reset value */
+#define RCC_CR_RESET 0x00000063 /* Value at POR */
+
+/* ICSCR - Internal Clock Sources Calibration Register */
+
+#define RCC_ICSCR_HSICAL_SHIFT (16) /* Bits 23-16: HSI16 calibration (factory programmed, read only) */
+#define RCC_ICSCR_HSICAL_MASK (0xff << RCC_ICSCR_HSICAL_SHIFT)
+
+#define RCC_ICSCR_HSITRIM_SHIFT (24) /* Bits 30-24: HSI16 clock trimming */
+#define RCC_ICSCR_HSITRIM_MASK (0x7f << RCC_ICSCR_HSITRIM_SHIFT)
+#define RCC_ICSCR_HSITRIM_RESET (0x40 << RCC_ICSCR_HSITRIM_SHIFT)
+
+/* CFGR - Clock Configuration Register */
+
+#define RCC_CFGR_SW_SHIFT (0) /* Bits 1-0: System clock switch */
+#define RCC_CFGR_SW_MASK (0x3 << RCC_CFGR_SW_SHIFT)
+# define RCC_CFGR_SW_HSI (1 << RCC_CFGR_SW_SHIFT)
+# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT)
+# define RCC_CFGR_SW_PLL (3 << RCC_CFGR_SW_SHIFT)
+#define RCC_CFGR_SWS_SHIFT (2) /* Bits 3-2: System clock switch status */
+#define RCC_CFGR_SWS_MASK (0x3 << RCC_CFGR_SWS_SHIFT)
+# define RCC_CFGR_SWS_HSI (1 << RCC_CFGR_SWS_SHIFT)
+# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT)
+# define RCC_CFGR_SWS_PLL (3 << RCC_CFGR_SWS_SHIFT)
+#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 7-4: AHB prescaler */
+#define RCC_CFGR_HPRE_MASK (0xf << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT)
+#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 10-8: AHB1 prescaler */
+#define RCC_CFGR_PPRE1_MASK (0x7 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT)
+#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 13-11: AHB2 prescaler */
+#define RCC_CFGR_PPRE2_MASK (0x7 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT)
+ /* Bits 23-14: Reserved */
+#define RCC_CFGR_MCOSEL_SHIFT (24) /* Bits 27-24: MCU clock output*/
+#define RCC_CFGR_MCOSEL_MASK (0xf << RCC_CFGR_MCOSEL_SHIFT)
+#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bit 28: */
+#define RCC_CFGR_MCOPRE_MASK (0x7 << RCC_CFGR_MCOPRE_SHIFT)
+ /* Bit 31: Reserved */
+
+#define RCC_CFGR_RESERVED_MASK 0x00ffc000 /* Bits 23-14 should be kept at reset value */
+#define RCC_CFGR_RESET 0x00000001 /* It's actually 0x5 but bits 3-2 are read only */
+
+/* PLLCFGR - System PLL Configuration Register */
+
+#define RCC_PLLCFGR_PLLSRC_SHIFT (0) /* Bits 1-0: Main PLL entry clock source */
+#define RCC_PLLCFGR_PLLSRC_MASK (3 << RCC_PLLCFGR_PLLSRC_SHIFT)
+# define RCC_PLLCFGR_PLLSRC_NOCLK (0 << RCC_PLLCFGR_PLLSRC_SHIFT)
+# define RCC_PLLCFGR_PLLSRC_HSI (2 << RCC_PLLCFGR_PLLSRC_SHIFT)
+# define RCC_PLLCFGR_PLLSRC_HSE (3 << RCC_PLLCFGR_PLLSRC_SHIFT)
+ /* Bits 3-2: Reserved */
+#define RCC_PLLCFGR_PLLM_SHIFT (4) /* Bits 7-4: Division factor M of main PLL input clock */
+#define RCC_PLLCFGR_PLLM_MASK (0xf << RCC_PLLCFGR_PLLM_SHIFT)
+#define RCC_PLLCFGR_PLLM(n) ((((n) - 1) << RCC_PLLCFGR_PLLM_SHIFT) & RCC_PLLCFGR_PLLM_MASK) /* n=1..16 */
+
+#define RCC_PLLCFGR_PLLN_SHIFT (8) /* Bits 14-8: Main PLL multiplication factor N for VCO */
+#define RCC_PLLCFGR_PLLN_MASK (0x7f << RCC_PLLCFGR_PLLN_SHIFT)
+#define RCC_PLLCFGR_PLLN(n) (((n) << RCC_PLLCFGR_PLLN_SHIFT) & RCC_PLLCFGR_PLLN_MASK) /* n=8..127 */
+ /* Bit 15: Reserved */
+#define RCC_PLLCFGR_PLLPEN (1 << 16) /* Bit 16: Main PLL PCLK output enable */
+#define RCC_PLLCFGR_PLLP (1 << 17) /* Bit 17: Main PLL division factor for PLL P clock, 0:PLLP=7, 1:PLLP=17 */
+ /* Bits 19-18: Reserved */
+#define RCC_PLLCFGR_PLLQEN (1 << 20) /* Bit 20: Main PLL Q clock output enable */
+#define RCC_PLLCFGR_PLLQ_SHIFT (21) /* Bits 22-21: Main PLL division factor for PLL Q clock */
+#define RCC_PLLCFGR_PLLQ_MASK (0x3 << RCC_PLLCFGR_PLLQ_SHIFT)
+# define RCC_PLLCFGR_PLLQ_2 (0x0 << RCC_PLLCFGR_PLLQ_SHIFT)
+# define RCC_PLLCFGR_PLLQ_4 (0x1 << RCC_PLLCFGR_PLLQ_SHIFT)
+# define RCC_PLLCFGR_PLLQ_6 (0x2 << RCC_PLLCFGR_PLLQ_SHIFT)
+# define RCC_PLLCFGR_PLLQ_8 (0x3 << RCC_PLLCFGR_PLLQ_SHIFT)
+ /* Bits 23: Reserved */
+#define RCC_PLLCFGR_PLLREN (1 << 24) /* Bit 24: PLL R clock output enable */
+#define RCC_PLLCFGR_PLLR_SHIFT (25) /* Bits 26-25: Main PLL division factor for PLL R clock (system clock) */
+#define RCC_PLLCFGR_PLLR_MASK (3 << RCC_PLLCFGR_PLLR_SHIFT)
+# define RCC_PLLCFGR_PLLR_2 (0x0 << RCC_PLLCFGR_PLLR_SHIFT)
+# define RCC_PLLCFGR_PLLR_4 (0x1 << RCC_PLLCFGR_PLLR_SHIFT)
+# define RCC_PLLCFGR_PLLR_6 (0x2 << RCC_PLLCFGR_PLLR_SHIFT)
+# define RCC_PLLCFGR_PLLR_8 (0x3 << RCC_PLLCFGR_PLLR_SHIFT)
+
+#define RCC_PLLCFGR_PLLPDIV_SHIFT (27) /* Bits 31-27: Main PLL division factor for PLL P clock */
+#define RCC_PLLCFGR_PLLPDIV_MASK (0x1f << RCC_PLLCFGR_PLLPDIV_SHIFT)
+#define RCC_PLLCFGR_PLLPDIV(n) (((n) << RCC_PLLCFGR_PLLPDIV_SHIFT) & RCC_PLLCFGR_PLLPDIV_MASK) /* n=2..31 */
+
+#define RCC_PLLCFGR_RESERVED_MASK 0x008c800c /* Bits 23, 19-18, 15, and 3-2 should be kept at reset value */
+#define RCC_PLLCFGR_RESET 0x00001000
+
+/* CIER - Clock Interrupt Enable Register */
+
Review comment:
I try to do this files as a representation of the reference manual at the version I am working off of. It is a PITA but keeping the names and the comments consistent with the manual help to speed development and catch the bugs as the docs evolve. "Oh this is what we thought it does, but now the new rev of the manual says it does this"
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -2577,7 +2863,7 @@ config STM32_SPI6
config STM32_SYSCFG
bool "SYSCFG"
default y
- depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F33XX || STM32_STM32F37XX || STM32_STM32F20XX || STM32_STM32F4XXX || STM32_CONNECTIVITYLINE
+ depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F33XX || STM32_STM32F37XX || STM32_STM32F20XX || STM32_STM32F4XXX || STM32_STM32G47XX || STM32_CONNECTIVITYLINE
Review comment:
I understand this is not the result off adding this chip, but this would be better served with the `STM32_HAVE_SYSCFG` in the chips feature list and then make this depends on `STM32_HAVE_SYSCFG`
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_gpio.h
##########
@@ -0,0 +1,340 @@
+/****************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_GPIO_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_GPIO_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STM32_NGPIO_PORTS (7) /* GPIOA-G */
+
+/* Register Offsets *********************************************************/
+
+#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
+#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
+#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
+#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
+#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
+#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
+#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
+#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
+#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
+#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
+#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
+
+/* Register Addresses *******************************************************/
+
+#if (STM32_NGPIO_PORTS > 0)
+# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 1)
+# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 2)
+# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 3)
+# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 4)
+# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 5)
+# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 6)
+# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ********************************************/
+
+/* GPIO port mode register */
+
+#define GPIO_MODER_INPUT (0x0) /* Input mode */
+#define GPIO_MODER_OUTPUT (0x1) /* General purpose output mode */
+#define GPIO_MODER_ALT (0x2) /* Alternate mode */
+#define GPIO_MODER_ANALOG (0x3) /* Analog mode (reset state) */
+
+#define GPIO_MODER_SHIFT(n) ((n) << 1)
+#define GPIO_MODER_MASK(n) (0x3 << GPIO_MODER_SHIFT(n))
+
Review comment:
I admire your used of the macros. However this is very inconsistent with how all the STMs are done. So this fall in the shortcuts vr. consistency realm. If we ask others, I am not sure what answer you would get on what day. But I usually **strive** for consistency .
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1129,15 +1129,80 @@ config ARCH_CHIP_STM32F469N
select STM32_STM32F469
select STM32_HAVE_ETHMAC
+config ARCH_CHIP_STM32G474C
Review comment:
+1
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or Time Stamp (see STM32_IRQ_TIMESTAMP) */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
+#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
+#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
+#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
+#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
+#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
+#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
+#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt (see also STM32_IRQ_ADC2) */
+#define STM32_IRQ_USBHP (STM32_IRQ_FIRST+19) /* 19: USB High priority interrupt */
+
+#define STM32_IRQ_USBLP (STM32_IRQ_FIRST+20) /* 20: USB Low priority interrupt */
+#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST+21) /* 21: FDCAN1 interrupt 0 */
+#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST+22) /* 22: FDCAN1 interrupt 1 */
+#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt (see also STM32_IRQ_TIM1BRK) */
+#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt (see also STM32_IRQ_TIM1UP) */
+#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt (see also STM32_IRQ_TIM1TRGCOM) */
+#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+
+#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
+#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
+#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
+#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
+#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+
+#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST+42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */
+#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break, Transition error, Index error */
+#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
+#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */
+#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
+#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
+#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */
+#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST+49) /* 49: LPTIM1 interrupt */
+
+#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
+#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
+#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
+#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
+#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt (see also STM32_IRQ_DAC1, STM32_IRQ_DAC3) */
+#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt (see also STM32_IRQ_DAC2, STM32_IRQ_DAC4) */
+#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST+56) /* 56: DMA2 channel 1 global interrupt */
+#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST+57) /* 57: DMA2 channel 2 global interrupt */
+#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST+58) /* 58: DMA2 channel 3 global interrupt */
+#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST+59) /* 59: DMA2 channel 4 global interrupt */
+
+#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST+60) /* 60: DMA2 channel 5 global interrupt */
+#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST+61) /* 61: ADC4 global interrupt */
+#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST+62) /* 62: ADC5 global interrupt */
+#define STM32_IRQ_UCPD (STM32_IRQ_FIRST+63) /* 63: UCPD global interrupt */
+#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST+64) /* 64: COMP1, COMP2, and COMP3 interrupts */
+#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST+65) /* 65: COMP4, COMP5, and COMP6 interrupts */
+#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST+66) /* 66: COMPP7 interrupt */
+#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST+67) /* 67: HRTIM1 master timer interrupt */
+#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST+68) /* 68: HRTIM1 timer A interrupt */
+#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST+69) /* 69: HRTIM1 timer B interrupt */
+
+#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST+70) /* 70: HRTIM1 timer C interrupt */
+#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST+71) /* 71: HRTIM1 timer D interrupt */
+#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST+72) /* 72: HRTIM1 timer E interrupt */
+#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST+73) /* 73: HRTIM1 fault interrupt */
+#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST+74) /* 74: HRTIM1 timer E interrupt */
+#define STM32_IRQ_CRS (STM32_IRQ_FIRST+75) /* 75: CRS (Clock Recovery System) global interrupt */
+#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+76) /* 76: SAI4 global interrupt */
+#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST+77) /* 77: TIM20 Break, Transition error, Index error interrupt */
+#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST+78) /* 78: TIM20 Update interrupt */
+#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST+79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */
+
+#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST+80) /* 80: TIM20 Capture Compare interrupt */
+#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+82) /* 82: I2C4 event interrupt */
+#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+83) /* 83: I2C4 error interrupt */
+#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
+#define STM32_IRQ_AES (STM32_IRQ_FIRST+85) /* 85: AES global interrupt */
+#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST+86) /* 86: FDCAN2 interrupt 0 */
+#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST+87) /* 87: FDCAN2 interrupt 1 */
+#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST+88) /* 88: FDCAN3 interrupt 0 */
+#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST+89) /* 89: FDCAN3 interrupt 1 */
+
+#define STM32_IRQ_RNG (STM32_IRQ_FIRST+90) /* 90: RNG global interrupt */
+#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST+91) /* 91: LPUART1 */
+#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+92) /* 92: I2C3 event interrupt */
+#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+93) /* 93: I2C3 error interrupt */
+#define STM32_IRQ_DMAMUXOV (STM32_IRQ_FIRST+94) /* 94: DMAMUX overrun interrupt */
+#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+95) /* 95: QuadSPI global interrupt */
+#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST+96) /* 96: DMA1 channel 8 global interrupt */
+#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST+97) /* 97: DMA2 channel 6 global interrupt */
+#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST+98) /* 98: DMA2 channel 7 global interrupt */
+#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST+99) /* 99: DMA2 channel 8 global interrupt */
+
+#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST+100) /* 100: CORDIC trigonometric accelerator interrupt */
+#define STM32_IRQ_FMAC (STM32_IRQ_FIRST+101) /* 101: FMAC filter math acclerator interrupt */
+
+#define STM32_IRQ_NEXTINT (102)
+#define NR_IRQS (STM32_IRQ_FIRST+102)
+
+/* Interrupt vectors that are shared with numbers defined above: */
Review comment:
+1
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1810,6 +1876,100 @@ config STM32_STM32F469
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
+config STM32_STM32G47XX
+ bool
+ default n
+ select ARCH_CORTEXM4
+ select ARCH_HAVE_FPU
+ select STM32_HAVE_ADC2
+ select STM32_HAVE_ADC3
+ select STM32_HAVE_ADC4
+ select STM32_HAVE_ADC5
+ select STM32_HAVE_CCM
+ select STM32_HAVE_COMP1
+ select STM32_HAVE_COMP2
+ select STM32_HAVE_COMP3
+ select STM32_HAVE_COMP4
+ select STM32_HAVE_COMP5
+ select STM32_HAVE_COMP6
+ select STM32_HAVE_COMP7
+ select STM32_HAVE_CORDIC
+ select STM32_HAVE_CRS
+ select STM32_HAVE_DAC1
+ select STM32_HAVE_DAC2
+ select STM32_HAVE_DAC3
+ select STM32_HAVE_DAC4
+ select STM32_HAVE_FSMC
+ select STM32_HAVE_FMAC
+ select STM32_HAVE_FDCAN
Review comment:
On the FDCAN side I can see that not all the 7xx have 3 CANFD - but I do not see that reflected here
##########
File path: arch/arm/src/stm32/hardware/stm32_flash.h
##########
@@ -253,6 +274,24 @@
# define STM32_FLASH_WRPR2_OFFSET 0x0080
# define STM32_FLASH_WRPR3_OFFSET 0x0084
# define STM32_FLASH_WRPR4_OFFSET 0x0088
+#elif defined(CONFIG_STM32_STM32G47XX)
Review comment:
I think the L15XX addition set a bad precedence here and you have followed down that wrong path. This would be better served by separate the include files. The common defines stay here, Lines 0-248, then include the chip header based on selection.
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
##########
@@ -0,0 +1,2627 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "stm32_gpio.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Alternate Pin Functions. All members of the STM32G47xxx family share the
+ * same pin multiplexing (although they differ in the pins physically
+ * available).
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if CAN1_RX connects via PA11 on some board, then the following
+ * definitions should appear in the board.h header file for that board:
+ *
+ * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
+ *
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
+ */
+
+/* ADC - Analog Digital Converter *******************************************************************/
+
+/* ADC1 has IN1-IN5, IN10-IN12, IN14-IN15 on all STM32G474(C-M-Q-R-V)xxx P/Ns
+ * and also has IN6-9 on STM32G474(M-Q-R-V)xxx P/Ns:
+ */
+
+#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN0)
+#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
Review comment:
In general when the compiler can catch a bug we should let it. But again this sort of thing should be based on a feature not a chip.
EDIT:As I scrolled and see the number of #ifdefs I think this would better as a more defined set of files, dropping more x's and duplication of the files - the answer to what is the differences if `diff` - yes it is replication. yes bugs will be needed to be fixed in many files. But it will keep this much cleaner and avoided time spent in the debugger because the compiler will tell you, you you can not do that.
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
##########
@@ -0,0 +1,194 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* STM32G47xxx Address Blocks ***********************************************************************/
+
+#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM */
+ /* 0x70000000-0x7fffffff: Reserved */
+#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
+#define STM32_QSPI_BANK1 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
+
+#define STM32_FMC_QSPI_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 256Mb FMC and QUADSPI registers */
+ /* 0xc0000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
+
+#define STM32_REGION_MASK Warning Not Cleared! 0xf0000000
+#define STM32_IS_SRAM(a) Warning Not Cleared! ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
+
+/* Code Base Addresses ******************************************************************************/
+
+#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x0007ffff: Aliased boot memory */
+ /* 0x00080000-0x07ffffff: Reserved */
+#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x807ffff: Up to 512Kb FLASH memory */
+ /* 0x08080000-0xfffffff: Reserved */
+#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x10007fff: 32Kb CCM data SRAM */
+ /* 0x10008000-0x1ffeffff: Reserved */
+#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: 28Kb System memory */
+#define STM32_OTP_AREA_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: 1Kb OTP area */
+ /* 0x1fff7400-0x1fff77ff: Reserved */
+#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: 16 Option bytes */
+ /* 0x1fff7810-0x1fff7fff: Reserved */
+#define STM32_SYSMEM_BASE2 0x1fff8000 /* 0x1fff8000-0x1fffefff: 28Kb System memory */
+ /* 0x1ffff000-0x1ffff7ff: Reserved */
+#define STM32_OPTION_BASE2 0x1ffff800 /* 0x1ffff800-0x1ffff80f: 16 Option bytes */
+ /* 0x1fff7810-0x1fff7fff: Reserved */
+
+/* System Memory Addresses **************************************************************************/
+
+#define STM32_PACKAGE_INFO 0x1fff7500 /* Package data register */
+#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
+#define STM32_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of
+ * the device Flash memory expressed in
+ * Kbytes. Example: 0x040 corresponds
+ * to 64 Kbytes
+ */
+
+/* Peripheral Base Addresses ************************************************************************/
+
+#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */
+ /* 0x40009800-0x4000ffff: Reserved */
+#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */
+ /* 0x40016400-0x4001ffff: Reserved */
+#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
+ /* 0x40024400-0x47ffffff: Reserved */
+#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */
+ /* 0x50060c00-0x5fffffff: Reserved */
+
+/* APB1 Base Addresses ******************************************************************************/
+
Review comment:
The address space is fully defined
What are the 0x________ for, are you planning of filling this in to match the docs?
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_uart.h
##########
@@ -0,0 +1,420 @@
+/****************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_uart.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_UART_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_UART_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */
+#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */
+#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */
+#define STM32_USART_BRR_OFFSET 0x000c /* BAUD Rate Register */
+#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */
+#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */
+#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */
+#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */
+#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt Flag Clear Register */
+#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */
+#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */
+#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */
+
+/* Register Addresses *******************************************************/
+
+#if (STM32_NUSART > 0)
+# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
+# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
+# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
+# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
+# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
+# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
+# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
+# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
+# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
+# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
+# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
+# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET)
+#endif
+
+#if (STM32_NUSART > 1)
+# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
+# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
+# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
+# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
+# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
+# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
+# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
+# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
+# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
+# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
+# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
+# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET)
+#endif
+
+#if (STM32_NUSART > 2)
+# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
+# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
+# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
+# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
+# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
+# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
+# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
+# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
+# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
+# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
+# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
+# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET)
+#endif
+
+#if (STM32_NUSART > 3)
+# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET)
+# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET)
+# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET)
+# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET)
+# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET)
+# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET)
+# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET)
+# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET)
+# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET)
+# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET)
+# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET)
+# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET)
+#endif
+
+#if (STM32_NUSART > 4)
+# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET)
+# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET)
+# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET)
+# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET)
+# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET)
+# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET)
+# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET)
+# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET)
+# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET)
+# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET)
+# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET)
+# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Control Register 1 */
+
+#define USART_CR1_UE (1 << 0) /* Bit 0 - USART Enable */
+#define USART_CR1_UESM (1 << 1) /* Bit 1 - USART Enable in low power Mode */
+#define USART_CR1_RE (1 << 2) /* Bit 2 - Receiver Enable */
+#define USART_CR1_TE (1 << 3) /* Bit 3 - Transmitter Enable */
+#define USART_CR1_IDLEIE (1 << 4) /* Bit 4 - IDLE Interrupt Enable */
+#define USART_CR1_RXFNEIE (1 << 5) /* Bit 5 in FIFO mode - Rx FIFO Not Empty Interrupt Enable */
+#define USART_CR1_RXNEIE (1 << 5) /* Bit 5 in Non-FIFO mode - Rx Data Register Not Empty Interrupt Enable */
+#define USART_CR1_TCIE (1 << 6) /* Bit 6 - Transmission Complete Interrupt Enable */
+#define USART_CR1_TXFNFIE (1 << 7) /* Bit 7 in FIFO mode - Tx FIFO Not Full Interrupt Enable */
+#define USART_CR1_TXEIE (1 << 7) /* Bit 7 in Non-FIFO mode - Tx Data Register Empty Interrupt Enable */
+#define USART_CR1_PEIE (1 << 8) /* Bit 8 - PE Interrupt Enable */
+#define USART_CR1_PS (1 << 9) /* Bit 9 - Parity Selection */
+#define USART_CR1_PCE (1 << 10) /* Bit 10 - Parity Control Enable */
+#define USART_CR1_WAKE (1 << 11) /* Bit 11 - Receiver Wakeup method */
+#define USART_CR1_M0 (1 << 12) /* Bit 12 - Word length - Bit 0 */
+#define USART_CR1_MME (1 << 13) /* Bit 13 - Mute Mode Enable */
+#define USART_CR1_CMIE (1 << 14) /* Bit 14 - Character match interrupt enable */
+#define USART_CR1_OVER8 (1 << 15) /* Bit 15 - Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_SHIFT (16) /* Bits 20:16 - Driver Enable Deassertion Time, in 1/16ths or 1/8ths bit time */
+#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
+# define USART_CR1_DEDT(n) (((n) << USART_CR1_DEDT_SHIFT) & USART_CR1_DEDT_MASK)
+#define USART_CR1_DEAT_SHIFT (21) /* Bits 25:21 - Driver Enable Assertion Time, in 1/16ths or 1/8ths bit time */
+#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
+# define USART_CR1_DEAT(n) (((n) << USART_CR1_DEAT_SHIFT) & USART_CR1_DEAT_MASK)
+#define USART_CR1_RTOIE (1 << 26) /* Bit 26 - Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE (1 << 27) /* Bit 27 - End of Block interrupt enable */
+#define USART_CR1_M1 (1 << 28) /* Bit 28 - Word length - Bit 1 */
+#define USART_CR1_FIFOEN (1 << 29) /* Bit 29 - FIFO mode enable */
+#define USART_CR1_TXFEIE (1 << 30) /* Bit 30 - TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE (1 << 31) /* Bit 31 - RXFIFO Full interrupt enable */
+
+#define USART_CR1_M_MASK (USART_CR1_M0 | USART_CR1_M1)
+
+#define USART_CR1_ALLINTS \
+ (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \
+ USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_RTOIE | \
+ USART_CR1_EOBIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE)
+
+/* Control Register 2 */
+
+#define USART_CR2_SLVEN (1 << 0) /* Synchronous Slave Mode Enable */
+#define USART_CR2_DIS_NSS (1 << 3) /* Slave Select (NSS) Pin Ignore For SPI */
+#define USART_CR2_ADDM7 (1 << 4) /* 7-Bit / 4-Bit Address Detection */
+#define USART_CR2_LBDL (1 << 5) /* LIN Break Detection Length */
+#define USART_CR2_LBDIE (1 << 6) /* LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL (1 << 8) /* Last Bit Clock pulse */
+#define USART_CR2_CPHA (1 << 9) /* Clock Phase */
+#define USART_CR2_CPOL (1 << 10) /* Clock Polarity */
+#define USART_CR2_CLKEN (1 << 11) /* Clock Enable */
+#define USART_CR2_STOP_SHIFT (12) /* Stop Bit Mode */
+#define USART_CR2_STOP_MASK (0x3 << USART_CR2_STOP_SHIFT)
+# define USART_CR2_STOP1 (0x0 << USART_CR2_STOP_SHIFT) /* 1 Stop Bit */
+# define USART_CR2_STOP0p5 (0x1 << USART_CR2_STOP_SHIFT) /* 0.5 Stop Bit */
+# define USART_CR2_STOP2 (0x2 << USART_CR2_STOP_SHIFT) /* 2 Stop Bits */
+# define USART_CR2_STOP1p5 (0x3 << USART_CR2_STOP_SHIFT) /* 1.5 Stop Bits */
+#define USART_CR2_LINEN (1 << 14) /* LIN Mode Enable */
+#define USART_CR2_SWAP (1 << 15) /* Swap TX/RX Pins */
+#define USART_CR2_RXINV (1 << 16) /* RX Pin Active Level Inversion */
+#define USART_CR2_TXINV (1 << 17) /* TX Pin Active Level Inversion */
+#define USART_CR2_DATAINV (1 << 18) /* Binary Data Inversion */
+#define USART_CR2_MSBFIRST (1 << 19) /* MSB First */
+#define USART_CR2_ABREN (1 << 20) /* Auto BAUD-Rate Enable */
+#define USART_CR2_ABRMOD_SHIFT (21) /* Auto BAUD-Rate Detection Mode */
+#define USART_CR2_ABRMOD_MASK (0x3 << USART_CR2_ABRMOD_SHIFT)
+# define USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT) /* Measurement of Start Bit */
+# define USART_CR2_ABRMOD_FALLEDGE (0x1 << USART_CR2_ABRMOD_SHIFT) /* Falling Edge To Falling Edge */
+# define USART_CR2_ABRMOD_7F_FRAME (0x2 << USART_CR2_ABRMOD_SHIFT) /* 0X7F Frame Detection */
+# define USART_CR2_ABRMOD_55_FRAME (0x3 << USART_CR2_ABRMOD_SHIFT) /* 0X55 Frame Detection */
+#define USART_CR2_RTOEN (1 << 23) /* Receiver Time-Out Enable */
+#define USART_CR2_ADD8_SHIFT (24) /* Address of the USART Node */
+#define USART_CR2_ADD8_MASK (0xff << USART_CR2_ADD8_SHIFT)
+
+/* Control Register 3 */
+
+#define USART_CR3_EIE (1 << 0) /* Error Interrupt Enable */
+#define USART_CR3_IREN (1 << 1) /* IrDA Mode Enable */
+#define USART_CR3_IRLP (1 << 2) /* IrDA Low-Power */
+#define USART_CR3_HDSEL (1 << 3) /* Half-Duplex Selection */
+#define USART_CR3_NACK (1 << 4) /* SmartCard NACK Enable */
+#define USART_CR3_SCEN (1 << 5) /* SmartCard Mode Enable */
+#define USART_CR3_DMAR (1 << 6) /* DMA Enable Receiver */
+#define USART_CR3_DMAT (1 << 7) /* DMA Enable Transmitter */
+#define USART_CR3_RTSE (1 << 8) /* RTS Enable */
+#define USART_CR3_CTSE (1 << 9) /* CTS Enable */
+#define USART_CR3_CTSIE (1 << 10) /* CTS Interrupt Enable */
+#define USART_CR3_ONEBIT (1 << 11) /* One Sample Bit Method Enable */
+#define USART_CR3_OVRDIS (1 << 12) /* Overrun Disable */
+#define USART_CR3_DDRE (1 << 13) /* DMA Disable on Reception Error */
+#define USART_CR3_DEM (1 << 14) /* Driver Enable Mode */
+#define USART_CR3_DEP (1 << 15)
+#define USART_CR3_SCARCNT_SHIFT (17) /* SmartCard Auto-Retry Count */
+#define USART_CR3_SCARCNT_MASK (0x7 << USART_CR3_SCARCNT_SHIFT)
+# define USART_CR3_SCARCNT(n) (((n) << USART_CR3_SCARCNT_SHIFT) & USART_CR3_SCARCNT_MASK)
+#define USART_CR3_WUS_SHIFT (20) /* Wake Up From Low Power Mode Interrupt Flag Selection) */
+#define USART_CR3_WUS_MASK (0x3 << USART_CR3_WUS_SHIFT)
+# define USART_CR3_WUS_ADDR (0x0 << USART_CR3_WUS_SHIFT) /* On Address Match */
+# define USART_CR3_WUS_STARTBIT (0x2 << USART_CR3_WUS_SHIFT) /* On Start Bit Detection */
+# define USART_CR3_WUS_RXFNE (0x3 << USART_CR3_WUS_SHIFT) /* On RXNE/RXFNE */
+#define USART_CR3_WUFIE (1 << 22) /* Wake Up From Low Power Mode Interrupt Enable */
+#define USART_CR3_TXFTIE (1 << 23) /* Transmit FIFO Threshold Interrupt Enable */
+#define USART_CR3_TCBGTIE (1 << 24) /* Transmit Complete Before Guard Time Interrupt Enable */
+#define USART_CR3_RXFTCFG_SHIFT (25) /* Receive FIFO Threshold Configuration */
+#define USART_CR3_RXFTCFG_MASK (0x7 << USART_CR3_RXFTCFG_SHIFT)
+# define USART_CR3_RXFTCFG_1_8 (0x0 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/8Th Depth */
+# define USART_CR3_RXFTCFG_1_4 (0x1 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/4Th Depth */
+# define USART_CR3_RXFTCFG_1_2 (0x2 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/2 Depth */
+# define USART_CR3_RXFTCFG_3_4 (0x3 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 3/4Ths Depth */
+# define USART_CR3_RXFTCFG_7_8 (0x4 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 7/8Ths Depth */
+# define USART_CR3_RXFTCFG_FULL (0x5 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Is Full */
+#define USART_CR3_RXFTIE (1 << 28) /* Receive FIFO Threshold Interrupt Enable */
+#define USART_CR3_TXFTCFG_SHIFT (29) /* Transmit FIFO Threshold Configuration */
+#define USART_CR3_TXFTCFG_MASK (0x7 << USART_CR3_TXFTCFG_SHIFT)
+# define USART_CR3_TXFTCFG_1_8 (0x0 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/8Th Depth */
+# define USART_CR3_TXFTCFG_1_4 (0x1 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/4Th Depth */
+# define USART_CR3_TXFTCFG_1_2 (0x2 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/2 Depth */
+# define USART_CR3_TXFTCFG_3_4 (0x3 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 3/4Ths Depth */
+# define USART_CR3_TXFTCFG_7_8 (0x4 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 7/8Ths Depth */
+# define USART_CR3_TXFTCFG_FULL (0x5 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Is Full */
+
+/* BAUD Rate Register */
+
+/* Full BRR field */
+
+#define USART_BRR_SHIFT (0)
+#define USART_BRR_MASK (0xffff << USART_BRR_BRR_SHIFT)
+# define USART_BRR(n) (((n) << USART_BRR_BRR_SHIFT) & USART_BRR_BRR_MASK)
+
+/* Partial BRR field BRR[3:0]:
+ *
+ * When OVER8 = 0: BRR[3:0] = USARTDIV[3:0]
+ *
+ * When OVER8 = 1: BRR[2:0] = (USARTDIV[3:0] >> 1) and
+ * BRR[3] must be kept cleared.
+ */
+
+#define USART_BRR_0_3_SHIFT (0)
+#define USART_BRR_0_3_MASK (0xf << USART_BRR_0_3_SHIFT)
+# define USART_BRR_0_3(n) (((n) << USART_BRR_0_3_SHIFT) & USART_BRR_0_3_MASK)
+
+/* Partial BRR field BRR[15:4]:
+ * BRR[15:4] = USARTDIV[15:4]
+ */
+
+#define USART_BRR_4_15_SHIFT (4)
+#define USART_BRR_4_15_MASK (0xfff << USART_BRR_4_15_SHIFT)
+# define USART_BRR_4_15(n) (((n) << USART_BRR_4_15_SHIFT) & USART_BRR_4_15_MASK)
+
+/* Guard Time and Prescaler Register */
+
+#define USART_GTPR_PSC_SHIFT (0) /* Prescaler Value */
+#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
+# define USART_GTPR_PSC(n) (((n) << USART_GTPR_PSC_SHIFT) & USART_GTPR_PSC_MASK)
+#define USART_GTPR_GT_SHIFT (8) /* Guard Time Value */
+#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
+# define USART_GTPR_GT(n) (((n) << USART_GTPR_GT_SHIFT) & USART_GTPR_GT_MASK)
+
+/* Receiver Timeout Register */
+
+#define USART_RTOR_RTO_SHIFT (0) /* Receiver Time Out Value */
+#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
+# define USART_RTOR_RTO(n) (((n) << USART_RTOR_RTO_SHIFT) & USART_RTOR_RTO_MASK)
+#define USART_RTOR_BLEN_SHIFT (24) /* Block Length */
+#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
+# define USART_RTOR_BLEN(n) (((n) << USART_RTOR_BLEN_SHIFT) & USART_RTOR_BLEN_MASK)
+
+/* Request Register */
+
+#define USART_RQR_ABRRQ (1 << 0) /* Bit 0 - Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ (1 << 1) /* Bit 1 - Send Break Request */
+#define USART_RQR_MMRQ (1 << 2) /* Bit 2 - Mute Mode Request */
+#define USART_RQR_RXFRQ (1 << 3) /* Bit 3 - Receive Data Flush Request */
+#define USART_RQR_TXFRQ (1 << 4) /* Bit 4 - Transmit Data Flush Request */
+
+/* Interrupt and Status Register */
+
+#define USART_ISR_PE (1 << 0) /* Bit 0 - Parity Error */
+#define USART_ISR_FE (1 << 1) /* Bit 1 - Framing Error */
+#define USART_ISR_NE (1 << 2) /* Bit 2 - Noise Detected Flag */
+#define USART_ISR_ORE (1 << 3) /* Bit 3 - Overrun Error */
+#define USART_ISR_IDLE (1 << 4) /* Bit 4 - Idle Line Detected */
+#define USART_ISR_RXFNE (1 << 5) /* Bit 5 (When FIFO in use) - Rx FIFO Not Empty */
+#define USART_ISR_RXNE (1 << 5) /* Bit 5 (When FIFO not in use) - Rx Data Register Not Empty */
+#define USART_ISR_TC (1 << 6) /* Bit 6 - Transmission Complete */
+#define USART_ISR_TXFNF (1 << 7) /* Bit 7 (When FIFO in use) - Tx FIFO Not Full */
+#define USART_ISR_TXE (1 << 7) /* Bit 7 (When FIFO not in use) - Tx Data Register Empty */
+#define USART_ISR_LBDF (1 << 8) /* Bit 8 - LIN Break Detection Flag */
+#define USART_ISR_CTSIF (1 << 9) /* Bit 9 - CTS Interrupt Flag */
+#define USART_ISR_CTS (1 << 10) /* Bit 10 - CTS Flag */
+#define USART_ISR_RTOF (1 << 11) /* Bit 11 - Receiver Time Out */
+#define USART_ISR_EOBF (1 << 12) /* Bit 12 - End of Block Flag */
+#define USART_ISR_UDR (1 << 13) /* Bit 13 - SPI Slave Underrun Error Flag */
+#define USART_ISR_ABRE (1 << 14) /* Bit 14 - Auto BAUD Rate Error */
+#define USART_ISR_ABRF (1 << 15) /* Bit 15 - Auto BAUD Rate Flag */
+#define USART_ISR_BUSY (1 << 16) /* Bit 16 - Busy Flag */
+#define USART_ISR_CMF (1 << 17) /* Bit 17 - Character Match Flag */
+#define USART_ISR_SBKF (1 << 18) /* Bit 18 - Send Break Flag */
+#define USART_ISR_RWU (1 << 19) /* Bit 19 - Receive Wake Up From Mute Mode Flag */
+#define USART_ISR_WUF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Flag */
+#define USART_ISR_TEACK (1 << 21) /* Bit 21 - Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK (1 << 22) /* Bit 22 - Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE (1 << 23) /* Bit 23 (When FIFO in use) - Tx FIFO Empty */
+#define USART_ISR_RXFF (1 << 24) /* Bit 24 (When FIFO in use) - Rx FIFO Full */
+#define USART_ISR_TCBGT (1 << 25) /* Bit 25 - Transmission Complete Before Guard Time Completion */
+#define USART_ISR_RXFT (1 << 26) /* Bit 26 (When FIFO in use) - Rx FIFO Threshold Flag */
+#define USART_ISR_TXFT (1 << 27) /* Bit 27 (When FIFO in use) - Tx FIFO Threshold Flag */
+
+#define USART_ISR_ALLBITS (0x0fffffff)
+
+/* Interrupt Flag Clear Register */
+
+#define USART_ICR_PECF (1 << 0) /* Bit 0 - Parity Error Clear Flag */
+#define USART_ICR_FECF (1 << 1) /* Bit 1 - Framing Error Clear Flag */
+#define USART_ICR_NCF (1 << 2) /* Bit 2 - Noise detected Clear Flag */
+#define USART_ICR_ORECF (1 << 3) /* Bit 3 - OverRun Error Clear Flag */
+#define USART_ICR_IDLECF (1 << 4) /* Bit 4 - Idle Line Detected Clear Flag */
+#define USART_ICR_TXFECF (1 << 5) /* Bit 5 - Tx FIFO Empty Clear Flag */
+#define USART_ICR_TCCF (1 << 6) /* Bit 6 - Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7 - Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF (1 << 8) /* Bit 8 - LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF (1 << 9) /* Bit 9 - CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF (1 << 11) /* Bit 11 - Receiver Timeout Clear Flag */
+#define USART_ICR_EOBCF (1 << 12) /* Bit 12 - End of Block Clear Flag */
+#define USART_ICR_UDRCF (1 << 13) /* Bit 13 - SPI Slave Underrun Clear Flag */
+#define USART_ICR_CMCF (1 << 17) /* Bit 17 - Character Match Clear Flag */
+#define USART_ICR_WUCF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Clear Flag */
+
+/* Receive Data Register */
+
+#define USART_RDR_SHIFT (0)
+#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT)
+# define USART_RDR(n) (((n) << USART_RDR_SHIFT) & USART_RDR_MASK)
+
+/* Transmit Data Register */
+
+#define USART_TDR_SHIFT (0)
+#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
+# define USART_TDR(n) (((n) << USART_TDR_SHIFT) & USART_TDR_MASK)
+
+/* Prescaler Register */
+
+#define USART_PRESC_PRESCALER_SHIFT (0)
+#define USART_PRESC_PRESCALER_MASK (0xf << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_1 (0x0 << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_2 (0x1 << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_4 (0x2 << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_6 (0x3 << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_8 (0x4 << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_10 (0x5 << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_12 (0x6 << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_16 (0x7 << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_32 (0x8 << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_64 (0x9 << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_128 (0xa << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_256 (0xb << USART_PRESC_PRESCALER_SHIFT)
+
+/* Compatibility definitions ************************************************/
+
+/* Compatibility with F1/F2/F4 Status Register names */
+
+#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET
+
+#define USART_SR_PE USART_ISR_PE /* Parity Error */
+#define USART_SR_FE USART_ISR_FE /* Framing error */
+#define USART_SR_NE USART_ISR_NE /* Noise detected flag */
+#define USART_SR_ORE USART_ISR_ORE /* Overrun error */
+#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */
+#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */
+#define USART_SR_TC USART_ISR_TC /* Transmission Complete */
+#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */
+#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */
+#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */
+
+#define USART_SR_ALLBITS USART_ISR_ALLBITS
+
+#define USART_CR1_M USART_CR1_M0
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_UART_H */
Review comment:
Wow Nathan! - you did a a lot of work. Stopping here for now, will do more later.
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
##########
@@ -0,0 +1,2627 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "stm32_gpio.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Alternate Pin Functions. All members of the STM32G47xxx family share the
+ * same pin multiplexing (although they differ in the pins physically
+ * available).
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if CAN1_RX connects via PA11 on some board, then the following
+ * definitions should appear in the board.h header file for that board:
+ *
+ * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
+ *
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
+ */
+
+/* ADC - Analog Digital Converter *******************************************************************/
+
+/* ADC1 has IN1-IN5, IN10-IN12, IN14-IN15 on all STM32G474(C-M-Q-R-V)xxx P/Ns
+ * and also has IN6-9 on STM32G474(M-Q-R-V)xxx P/Ns:
+ */
+
+#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN0)
+#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_ADC1_IN6 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
+# define GPIO_ADC1_IN7 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
+# define GPIO_ADC1_IN8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_ADC1_IN9 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
+#endif
+
+/* ADC2 has IN1-IN4, IN10, IN12-IN15, IN17 on all STM32G474(C-M-Q-R-V)xxx
+ * P/Ns. STM32G474CxUx also has IN5. STM32G474(M-Q-R-V)xxx P/Ns also have
+ * IN5-IN9 and IN11.
+ */
+
+# define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_ADC2_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN1)
+# define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+# define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN11)
+# define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
+# define GPIO_ADC2_IN17 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) && defined(CONFIG_STM32_STM32G474C_U)
+# define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
+# define GPIO_ADC2_IN6 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
+# define GPIO_ADC2_IN7 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
+# define GPIO_ADC2_IN8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_ADC2_IN9 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
+# define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+#endif
+
+/* ADC3 has IN1, IN5, IN12 on all STM32G474(C-M-Q-R-V)xxx P/Ns.
+ * STM32G474(M-Q-V)xxx P/Ns also have IN2-IN4, IN6-IN7, IN14-IN16.
+ * STM32G474MxYx P/Ns also have IN8. STM32G474(Q-V)xxx P/Ns also have
+ * IN8-IN11.
+ */
+
+#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9)
+# define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_ADC3_IN4 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7)
+# define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8)
+# define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10)
+# define GPIO_ADC3_IN14 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN10)
+# define GPIO_ADC3_IN15 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_ADC3_IN16 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) && defined(CONFIG_STM32_STM32G474M_Y)
+# define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14)
+#endif
+
+/* ADC4 has IN3-IN5 on all STM32G474(C-M-Q-R-V)xxx P/Ns.
+ * STM32G474(M-Q-V)xxx P/Ns also have IN1-IN2, IN6-IN7, IN12-IN16.
+ * STM32G474MxYx P/Ns also have IN8. STM32G474(Q-V)xxx P/Ns also have
+ * IN8-IN11.
+ */
+
+#define GPIO_ADC4_IN3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_ADC4_IN4 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_ADC4_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_ADC4_IN1 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_ADC4_IN2 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN15)
+# define GPIO_ADC4_IN6 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8)
+# define GPIO_ADC4_IN7 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10)
+# define GPIO_ADC4_IN12 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8)
+# define GPIO_ADC4_IN13 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9)
+# define GPIO_ADC4_IN14 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN10)
+# define GPIO_ADC4_IN15 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_ADC4_IN16 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) && defined(CONFIG_STM32_STM32G474M_Y)
+# define GPIO_ADC4_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_ADC4_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_ADC4_IN9 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_ADC4_IN10 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_ADC4_IN11 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14)
+#endif
+
+/* ADC4 has IN1-IN2 on all STM32G474(C-M-Q-R-V)xxx P/Ns. STM32G474(M-Q-V)xxx
+ * P/Ns also have IN6-IN7 and IN12-IN16. STM32G474MxYx P/Ns also have IN8.
+ * STM32G474(Q-V)xxx P/Ns also have IN8-IN11.
+ */
+
+#define GPIO_ADC5_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_ADC5_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN9)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_ADC5_IN6 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8)
+# define GPIO_ADC5_IN7 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10)
+# define GPIO_ADC5_IN12 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8)
+# define GPIO_ADC5_IN13 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9)
+# define GPIO_ADC5_IN14 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN10)
+# define GPIO_ADC5_IN15 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_ADC5_IN16 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) && defined(CONFIG_STM32_STM32G474M_Y)
+# define GPIO_ADC5_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_ADC5_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_ADC5_IN9 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_ADC5_IN10 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_ADC5_IN11 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14)
+#endif
+
+/* COMP - Comparator ********************************************************************************/
+
+/* COMP1 has four alternates on STM32G474(C-M-R-V)xxx P/Ns, and five
+ * alternates on STM32G474Qxxx P/Ns:
+ */
+
+#define GPIO_COMP1_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_COMP1_OUT_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_COMP1_OUT_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_COMP1_OUT_4 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN8)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_COMP1_OUT_5 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN4)
+#endif
+
+/* COMP2 has four alternates on all STM32G474(C-M-Q-R-V)xxx P/Ns: */
+
+#define GPIO_COMP2_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_COMP2_OUT_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_COMP2_OUT_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_COMP2_OUT_4 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN9)
+
+/* COMP3 has two alternates on STM32G474Cxxx P/Ns, and three alternates on
+ * STM32G474(M-Q-R-V)xxx P/Ns:
+ */
+
+#define GPIO_COMP3_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_COMP3_OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_COMP3_OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN2)
+#endif
+
+/* COMP4 has three alternates on all STM32G474(C-M-Q-R-V)xxx P/Ns: */
+
+#define GPIO_COMP4_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_COMP4_OUT_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_COMP4_OUT_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN14)
+
+/* COMP5 has one possible output pin on STM32G474Cxxx P/Ns and two alternates
+ * on STM32G474(M-Q-R-V)xxx P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_COMP5_OUT (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN9)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_COMP5_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_COMP5_OUT_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN7)
+#endif
+
+/* COMP6 has one possible output pin on STM32G474CxTx and two alternates on
+ * on STM32G474CxUx and STM32G474(M-Q-R-V)xxx P/Ns
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# if defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_COMP6_OUT (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN10)
+# elif defined(CONFIG_STM32_STM32G474C_U)
+# define GPIO_COMP6_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_COMP6_OUT_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN6)
+# endif
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_COMP6_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_COMP6_OUT_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN6)
+#endif
+
+/* COMP7 has one possible output pin on STM32G474Cxxx P/Ns and two alternates
+ * on STM32G474(M-Q-R-V)xxx P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_COMP7_OUT (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN8)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_COMP7_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_COMP7_OUT_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN8)
+#endif
+
+/* CRS **********************************************************************************************/
+
+/* REVISIT: Clock Recovery System (CRS_SYNC signal exposed to pin(s)?)
+ * Before using the following defines, make sure they are correct!
+ */
+
+#if 0
+# define GPIO_USB_CRS_SYNC (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_UCPD1_CRS_SYNC (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN3)
+#endif
+
+/* DAC **********************************************************************************************/
+
+/* All STM32G474(C-M-Q-R-V)xxx P/Ns have seven 12-bit DAC channels, of which
+ * three are buffered and exposed to external pins and four are unbuffered and
+ * available only for interconnection to other analog peripherals internal to
+ * the chip, such as ADC, COMP, or OPAMP.
+ *
+ * The external DAC signals include two output channels from DAC1 and one
+ * output channel from DAC2 and are available on the same pins on all
+ * STM32G474(C-M-Q-R-V)xxx P/Ns:
+ */
+
+#define GPIO_DAC1_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC1_OUT2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_DAC2_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
+
+/* Clocks outputs ***********************************************************************************/
+
+/* All STM32G474(C-M-Q-R-V)xxx P/Ns have two alternates for MCO (MCU clock
+ * output) on PA8 and PG10-NRST.
+ */
+
+#define GPIO_MCO_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_MCO_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTG|GPIO_PIN10)
+
+/* Event outputs ************************************************************************************/
+
+/* All STM32G474(C-M-Q-R-V)xxx P/Ns have the following EVENTOUT signals: */
+
+#define GPIO_PA0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_PA1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_PA2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_PA3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_PA4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_PA5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_PA6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_PA7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_PA8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_PA9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_PA10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_PA11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_PA12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_PA13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_PA14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_PA15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN15)
+
+#define GPIO_PB0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_PB1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_PB2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_PB3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_PB4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_PB5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_PB6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_PB7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_PB8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_PB9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_PB10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_PB11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_PB12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_PB13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_PB14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_PB15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN15)
+
+#define GPIO_PC13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN13)
+#define GPIO_PC14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN14)
+#define GPIO_PC15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN15)
+
+#define GPIO_PF0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN0)
+#define GPIO_PF1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN1)
+
+#define GPIO_PG10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN10)
+
+/* All STM32G474(C-M-Q-R-V)xxx P/Ns except STM32G474CxTx have the following
+ * EVENTOUT signals:
+ */
+
+#if !defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_PC4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN4)
+# define GPIO_PC6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_PC10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN10)
+# define GPIO_PC11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN11)
+#endif
+
+/* STM32G474(M-Q-R-V)xxx P/Ns have the following EVENTOUT signals: */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_PC0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN0)
+# define GPIO_PC1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN1)
+# define GPIO_PC2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_PC3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN3)
+# define GPIO_PC5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_PC7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_PC8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_PC9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_PC12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN12)
+
+# define GPIO_PD2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN2)
+#endif
+
+/* STM32G474(M-Q-V)xxx P/Ns have the following EVENTOUT signals: */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_PD0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN0)
+# define GPIO_PD1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN1)
+# define GPIO_PD8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN8)
+# define GPIO_PD9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN9)
+# define GPIO_PD10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN10)
+
+# define GPIO_PE7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN7)
+# define GPIO_PE8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN8)
+# define GPIO_PE9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN9)
+# define GPIO_PE10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN10)
+# define GPIO_PE11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_PE12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN12)
+# define GPIO_PE13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_PE14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_PE15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN15)
+#endif
+
+/* STM32G474(Q-V)xxx P/Ns have the following EVENTOUT signals: */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_PD3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_PD4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_PD5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN5)
+# define GPIO_PD6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_PD7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_PD11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_PD12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_PD13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_PD14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN14)
+# define GPIO_PD15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN15)
+
+# define GPIO_PE0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_PE1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN1)
+# define GPIO_PE2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN2)
+# define GPIO_PE3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN3)
+# define GPIO_PE4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN4)
+# define GPIO_PE5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN5)
+# define GPIO_PE6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN6)
+
+# define GPIO_PF2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN2)
+# define GPIO_PF9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_PF10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN10)
+#endif
+
+/* STM32G474MxYx P/Ns have the following EVENTOUT signal: */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) && defined(CONFIG_STM32_STM32G474M_Y)
+# define GPIO_PD11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN11)
+#endif
+
+/* STM32G474Qxxx P/Ns have the following EVENTOUT signals: */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_PF3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN3)
+# define GPIO_PF4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN4)
+# define GPIO_PF5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN5)
+# define GPIO_PF6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN6)
+# define GPIO_PF7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN7)
+# define GPIO_PF8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN8)
+# define GPIO_PF11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN11)
+# define GPIO_PF12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN12)
+# define GPIO_PF13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN13)
+# define GPIO_PF14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN14)
+# define GPIO_PF15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN15)
+
+# define GPIO_PG0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN0)
+# define GPIO_PG1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN1)
+# define GPIO_PG2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN2)
+# define GPIO_PG3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN3)
+# define GPIO_PG4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN4)
+# define GPIO_PG5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN5)
+# define GPIO_PG6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN6)
+# define GPIO_PG7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN7)
+# define GPIO_PG8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN8)
+# define GPIO_PG9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN9)
+#endif
+
+/* FDCAN ********************************************************************************************/
+
+/* FDCAN signals that are available on all STM32G474(C-M-Q-R-V)xxx P/Ns: */
+
+#define GPIO_FDCAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_FDCAN1_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_FDCAN1_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_FDCAN1_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_FDCAN2_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_FDCAN2_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_FDCAN2_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_FDCAN2_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_FDCAN3_RX_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_FDCAN3_RX_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_FDCAN3_TX_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_FDCAN3_TX_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
+
+/* FDCAN signals that have a third alternate on STM32G474(M-Q-V)xxx P/Ns: */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_FDCAN1_RX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0)
+# define GPIO_FDCAN1_TX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1)
+#endif
+
+/* FMC/FSMC - Flexible Static Memory Controller *****************************************************/
+
+/* FMC/FSMC signals are only exposed on STM32G474(Q-V)xxx P/Ns. The following
+ * signals are the same on STM32G474(Q-V)xxx P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_FMC_D0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN14)
+# define GPIO_FMC_D1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN15)
+# define GPIO_FMC_D2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN0)
+# define GPIO_FMC_D3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN1)
+# define GPIO_FMC_D4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN7)
+# define GPIO_FMC_D5 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN8)
+# define GPIO_FMC_D6 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN9)
+# define GPIO_FMC_D7 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN10)
+# define GPIO_FMC_D8 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_FMC_D9 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN12)
+# define GPIO_FMC_D10 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_FMC_D11 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_FMC_D12 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN15)
+# define GPIO_FMC_D13 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN8)
+# define GPIO_FMC_D14 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN9)
+# define GPIO_FMC_D15 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN10)
+# define GPIO_FMC_DA0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN14)
+# define GPIO_FMC_DA1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN15)
+# define GPIO_FMC_DA2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN0)
+# define GPIO_FMC_DA3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN1)
+# define GPIO_FMC_DA4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN7)
+# define GPIO_FMC_DA5 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN8)
+# define GPIO_FMC_DA6 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN9)
+# define GPIO_FMC_DA7 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN10)
+# define GPIO_FMC_DA8 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_FMC_DA9 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN12)
+# define GPIO_FMC_DA10 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_FMC_DA11 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_FMC_DA12 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN15)
+# define GPIO_FMC_DA13 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN8)
+# define GPIO_FMC_DA14 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN9)
+# define GPIO_FMC_DA15 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN10)
+# define GPIO_FMC_CLK (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_FMC_NBL0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_FMC_NBL1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN1)
+# define GPIO_FMC_NE1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_FMC_NL (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTB|GPIO_PIN7)
+# define GPIO_FMC_NOE (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_FMC_NWAIT (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_FMC_NWE (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN5)
+#endif
+
+/* FMC signals that are available differently on STM32G474(Q-V)xxx P/Ns: */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_FMC_A0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN10)
+# define GPIO_FMC_A1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN7)
+# define GPIO_FMC_A2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN2)
+# define GPIO_FMC_A3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN3)
+# define GPIO_FMC_A4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN4)
+# define GPIO_FMC_A5 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN5)
+# define GPIO_FMC_A6 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN12)
+# define GPIO_FMC_A7 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN13)
+# define GPIO_FMC_A8 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN14)
+# define GPIO_FMC_A9 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN15)
+# define GPIO_FMC_A10 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTG|GPIO_PIN0)
+# define GPIO_FMC_A11 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTG|GPIO_PIN1)
+# define GPIO_FMC_A12 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTG|GPIO_PIN2)
+# define GPIO_FMC_A13 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTG|GPIO_PIN3)
+# define GPIO_FMC_A14 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTG|GPIO_PIN4)
+# define GPIO_FMC_A15 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTG|GPIO_PIN5)
+# define GPIO_FMC_A16 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_FMC_A17 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_FMC_A18 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_FMC_A19 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN3)
+# define GPIO_FMC_A20 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN4)
+# define GPIO_FMC_A21 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN5)
+# define GPIO_FMC_A22 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN6)
+# define GPIO_FMC_A23 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN2)
+# define GPIO_FMC_A24 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN8)
+# define GPIO_FMC_A25 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_FMC_NCE_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_FMC_NCE_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTG|GPIO_PIN9)
+# define GPIO_FMC_NE2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTG|GPIO_PIN9)
+# define GPIO_FMC_NE3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTG|GPIO_PIN8)
+# define GPIO_FMC_NE4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN11)
+# define GPIO_FMC_INT_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_PORTG|GPIO_PIN6)
+# define GPIO_FMC_INT_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_PORTG|GPIO_PIN7)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_FMC_A0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN10)
+# define GPIO_FMC_A2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN2)
+# define GPIO_FMC_A16 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_FMC_A17 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_FMC_A18 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_FMC_A19 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN3)
+# define GPIO_FMC_A20 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN4)
+# define GPIO_FMC_A21 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN5)
+# define GPIO_FMC_A22 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN6)
+# define GPIO_FMC_A23 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTE|GPIO_PIN2)
+# define GPIO_FMC_A25 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_FMC_NCE (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_120MHz|GPIO_PORTD|GPIO_PIN7)
+#endif
+
+/* HRTIM - High-Resolution Timer ********************************************************************/
+
+/* HRTIM1 signals that are available on all STM32G474(C-M-Q-R-V)xxx P/Ns: */
+
+#define GPIO_HRTIM1_CHA1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_HRTIM1_CHA2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_HRTIM1_CHB1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_HRTIM1_CHB2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_HRTIM1_CHC1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_HRTIM1_CHC2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_HRTIM1_CHD1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_HRTIM1_CHD2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_HRTIM1_EEV3 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_HRTIM1_EEV4 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_HRTIM1_EEV5 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_HRTIM1_EEV6 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_HRTIM1_EEV7 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_HRTIM1_EEV8 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_HRTIM1_EEV9 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_HRTIM1_FLT1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_HRTIM1_FLT2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_HRTIM1_FLT3 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_HRTIM1_FLT4 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_HRTIM1_SCIN_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_HRTIM1_SCIN_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_HRTIM1_SCOUT_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_HRTIM1_SCOUT_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN3)
+
+/* The following three signals are exposed to pins on STM32G474(C-M-Q-R-V)xxx
+ * P/Ns, but not on STM32G474CxTx.
+ */
+
+#if !defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_HRTIM1_CHF1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_HRTIM1_EEV2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_HRTIM1_FLT6 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN10)
+#endif
+
+/* HRTIM1 signals that are available only on STM32G474(M-Q-R-V)xxx P/Ns: */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_HRTIM1_CHE1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_HRTIM1_CHE2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_HRTIM1_CHF2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_HRTIM1_EEV1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN12)
+#endif
+
+/* HRTIM1 signals that are available differently on STM32G474Cxxx than on
+ * STM32G474(M-Q-R-V)xxx P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_HRTIM1_EEV10_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_HRTIM1_EEV10_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_HRTIM1_FLT5_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_HRTIM1_FLT5_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN7)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_HRTIM1_EEV10 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_HRTIM1_FLT5 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN0)
+#endif
+
+/* I2C **********************************************************************************************/
+
+/* I2C1 has three alternates for SCL, three alternates for SDA, and only one
+ * possible pin for SMBA, on all STM32G474(C-M-Q-R-V)xxx P/Ns:
+ */
+
+#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
+
+/* I2C2 signals are available differently on different STM32G474(C-M-Q-R-V)xxx
+ * P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# if defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_I2C2_SCL (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0)
+# define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
+# elif defined(CONFIG_STM32_STM32G474C_U)
+# define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN4)
+# define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0)
+# define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
+# endif
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN4)
+# define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0)
+# define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN4)
+# define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN6)
+# define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0)
+# define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2)
+#endif
+
+/* I2C3 signals are available differently on different STM32G474(C-M-Q-R-V)xxx
+ * P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# if defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_I2C3_SCL (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_I2C3_SDA (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2)
+# elif defined(CONFIG_STM32_STM32G474C_U)
+# define GPIO_I2C3_SCL (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2)
+# endif
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_I2C3_SDA_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_I2C3_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN3)
+# define GPIO_I2C3_SCL_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN7)
+# define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_I2C3_SDA_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_I2C3_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN4)
+# define GPIO_I2C3_SDA_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN8)
+# define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_I2C3_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_I2C3_SDA_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2)
+#endif
+
+/* I2C4 signals are available differently on different STM32G474(C-M-Q-R-V)xxx
+ * P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# if defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_I2C4_SCL (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN13)
+# define GPIO_I2C4_SDA (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+# define GPIO_I2C4_SMBA (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN14)
+# elif defined(CONFIG_STM32_STM32G474C_U)
+# define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN13)
+# define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_I2C4_SDA (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+# define GPIO_I2C4_SMBA (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN14)
+# endif
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M)
+# if defined(CONFIG_STM32_STM32G474M_T)
+# define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN13)
+# define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+# define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_I2C4_SMBA (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN14)
+# elif defined(CONFIG_STM32_STM32G474M_Y)
+# define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN13)
+# define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+# define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN14)
+# define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN11)
+# endif
+#elif defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN13)
+# define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+# define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_I2C4_SMBA (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN14)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN13)
+# define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN14)
+# define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN3)
+# define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+# define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15)
+# define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN4)
+# define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN14)
+# define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN13)
+# define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+# define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN14)
+# define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN11)
+#endif
+
+/* I2S **********************************************************************************************/
+
+/* I2S: STM32G474(M-Q-R-V)xxx P/Ns have two alternates each for I2S_MCK,
+ * I2S_SD, and I2S_CKIN. STM32G474Cxxx P/Ns have only one each of I2S_MCK,
+ * I2S_SD, and I2S_CKIN.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_I2S3_MCK (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2S3_SD (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_I2S_CKIN (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN12)
+#else
+# define GPIO_I2S3_MCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2S3_MCK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_I2S3_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_I2S3_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12)
+# define GPIO_I2S_CKIN_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN12)
+# define GPIO_I2S_CKIN_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN9)
+#endif
+
+/* I2S2: All STM32G474(C-M-Q-R-V)xxx P/Ns have two alternates each for
+ * I2S2_CK, I2S2_SD, and I2S2_WS. STM32G474CxTx P/Ns have only one I2S2_MCK
+ * while STM32G474(C-M-Q-R-V)xxx P/Ns except STM32G474CxTx have two alternates
+ * for I2S2_MCK.
+ */
+
+#define GPIO_I2S2_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_I2S2_CK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN1)
+#define GPIO_I2S2_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_I2S2_SD_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_I2S2_WS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_I2S2_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN0)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) && defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_I2S2_MCK (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN8)
+#else
+# define GPIO_I2S2_MCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_I2S2_MCK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN6)
+#endif
+
+/* I2S3: All STM32G474(C-M-Q-R-V)xxx have two alternates each for I2S3_WS.
+ * STM32G474(M-Q-R-V)xxx P/Ns have two alternates for I2S3_CK. STM32G474CxTx
+ * P/Ns have only one I2S3_CK while STM32G474(C-M-Q-R-V)xxx P/Ns except
+ * STM32G474CxTx have two alternates for I2S3_CK. STM32G474(M-Q-R-V)xxx P/Ns
+ * have two alternates each for I2S3_MCK, I2S3_SD while STM32G474Cxxx P/Ns
+ * have only one each of I2S3_MCK, I2S3_SD.
+ */
+
+#define GPIO_I2S3_WS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_I2S3_WS_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN15)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) && defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_I2S3_CK (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN3)
+#else
+# define GPIO_I2S3_CK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_I2S3_CK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN10)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_I2S3_MCK (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2S3_SD (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
+#else
+# define GPIO_I2S3_MCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_I2S3_MCK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_I2S3_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_I2S3_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12)
+#endif
+
+/* IR - Infrared with TIM16 channel 1 and TIM17 channel 1 *******************************************/
+
+/* All STM32G474(C-M-Q-R-V)xxx have two alternates for IR_OUT: */
+
+#define GPIO_IR_OUT_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_IR_OUT_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN9)
+
+/* LPTIM - Low Power Timer **************************************************************************/
+
+/* STM32G474(M-Q-R-V)xxx P/Ns have two alternates each for LPTIM1_ETR,
+ * LPTIM1_IN1, and LPTIM1_IN2, and three alternates for LPTIM1_OUT.
+ * STM32G474Cxxx P/Ns have only one possible LPTIM1_ETR, LPTIM1_IN1,
+ * LPTIM1_IN2, and two alternates for LPTIM1_OUT.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_LPTIM1_ETR (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN6)
+# define GPIO_LPTIM1_IN1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_LPTIM1_IN2 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN7)
+#else
+# define GPIO_LPTIM1_ETR_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN6)
+# define GPIO_LPTIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN3)
+# define GPIO_LPTIM1_IN1_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_LPTIM1_IN1_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN0)
+# define GPIO_LPTIM1_IN2_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN7)
+# define GPIO_LPTIM1_IN2_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN2)
+#endif
+
+#define GPIO_LPTIM1_OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_LPTIM1_OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN2)
+
+#if !defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_LPTIM1_OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN1)
+#endif
+
+/* LPUART - Low-Power Universal Asynchronous Receiver Transmitter ***********************************/
+
+/* LPUART1: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least two alternates each
+ * for TX, RX, DE, CTS, and RTS. STM32G474(M-Q-R-V)xxx P/Ns offer a third
+ * alternate for each of TX and RX. STM32G474Qxxx P/Ns offer a third alternate
+ * for each of DE, CTS, and RTS, and a fourth alternate for TX and RX.
+ */
+
+#define GPIO_LPUART1_TX_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_LPUART1_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_LPUART1_RX_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_LPUART1_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_LPUART1_DE_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_LPUART1_DE_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_LPUART1_CTS_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_LPUART1_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_LPUART1_RTS_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_LPUART1_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN12)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_LPUART1_TX_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN1)
+# define GPIO_LPUART1_RX_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN0)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_LPUART1_TX_4 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN7)
+# define GPIO_LPUART1_RX_4 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN8)
+# define GPIO_LPUART1_DE_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN6)
+# define GPIO_LPUART1_CTS_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN5)
+# define GPIO_LPUART1_RTS_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN6)
+#endif
+
+/* JTAG *********************************************************************************************/
+
+#define GPIO_JTCK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_JTDI (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_JTDO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_JTMS (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_NJTRST (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_SWCLK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_SWDIO (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
+
+/* OPAMP ********************************************************************************************/
+
+/* OPAMP1: All STM32G474(C-M-Q-R-V)xxx P/Ns have three alternates each for
+ * VINP and VINP_SEC, and one possible VOUT. STM32G474Cxxx P/Ns have only one
+ * possible pinout for VINM, VINM0, VINM1, and VINM_SEC, while all other P/Ns
+ * have two alternates each for those signals.
+ */
+
+#define GPIO_OPAMP1_VINP_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_OPAMP1_VINP_2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_OPAMP1_VINP_3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_OPAMP1_VINP_SEC_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_OPAMP1_VINP_SEC_2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_OPAMP1_VINP_SEC_3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_OPAMP1_VOUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_OPAMP1_VINM (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_OPAMP1_VINM0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_OPAMP1_VINM1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_OPAMP1_VINM_SEC (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_OPAMP1_VINM0_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_OPAMP1_VINM0_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_OPAMP1_VINM1_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_OPAMP1_VINM1_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_OPAMP1_VINM_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_OPAMP1_VINM_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_OPAMP1_VINM_SEC_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_OPAMP1_VINM_SEC_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+#endif
+
+/* OPAMP2: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least three alternates
+ * each for VINP and VINP_SEC, and one possible VOUT. STM32G474(Q-V)xxx P/Ns
+ * add a fourth alternate for VINP and VINP_SEC. STM32G474Cxxx P/Ns have only
+ * one possible pinout for VINM, VINM0, VINM1, and VINM_SEC, while all other
+ * P/Ns have two alternates each for those signals.
+ */
+
+#define GPIO_OPAMP2_VINP_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_OPAMP2_VINP_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_OPAMP2_VINP_3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_OPAMP2_VINP_SEC_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_OPAMP2_VINP_SEC_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_OPAMP2_VINP_SEC_3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_OPAMP2_VOUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_OPAMP2_VINP_4 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14)
+# define GPIO_OPAMP2_VINP_SEC_4 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_OPAMP2_VINM (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+# define GPIO_OPAMP2_VINM0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+# define GPIO_OPAMP2_VINM1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+# define GPIO_OPAMP2_VINM_SEC (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_OPAMP2_VINM0_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+# define GPIO_OPAMP2_VINM0_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_OPAMP2_VINM1_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+# define GPIO_OPAMP2_VINM1_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_OPAMP2_VINM_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+# define GPIO_OPAMP2_VINM_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_OPAMP2_VINM_SEC_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+# define GPIO_OPAMP2_VINM_SEC_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+#endif
+
+/* OPAMP3: All signals are exposed identically on all STM32G474(C-M-Q-R-V)xxx
+ * P/Ns.
+ */
+
+#define GPIO_OPAMP3_VINM0_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_OPAMP3_VINM0_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_OPAMP3_VINM1_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_OPAMP3_VINM1_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_OPAMP3_VINM_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_OPAMP3_VINM_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_OPAMP3_VINM_SEC_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_OPAMP3_VINM_SEC_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_OPAMP3_VINP_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_OPAMP3_VINP_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_OPAMP3_VINP_3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_OPAMP3_VINP_SEC_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_OPAMP3_VINP_SEC_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_OPAMP3_VINP_SEC_3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_OPAMP3_VOUT (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+
+/* OPAMP4: All STM32G474(C-M-Q-R-V)xxx P/Ns have two alternates each for VINP
+ * and VINP_SEC, and one possible VOUT. STM32G474(Q-V)xxx P/Ns and
+ * STM32G474MxYx offer a third alternate for each of VINP and VINP_SEC.
+ * STM32G474(C-R)xxx P/Ns have only one possible pinout for each of VINM,
+ * VINM_SEC, VINM0, and VINM1, while STM32G474(M-Q-V)xxx P/Ns have two
+ * alternates for each of VINM, VINM_SEC, VINM0, and VINM1.
+ */
+
+#define GPIO_OPAMP4_VINP_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_OPAMP4_VINP_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_OPAMP4_VINP_SEC_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_OPAMP4_VINP_SEC_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_OPAMP4_VOUT (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) && defined(CONFIG_STM32_STM32G474M_Y)
+# define GPIO_OPAMP4_VINP_3 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_OPAMP4_VINP_SEC_3 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_OPAMP4_VINP_3 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_OPAMP4_VINP_SEC_3 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_OPAMP4_VINM (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_OPAMP4_VINM_SEC (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_OPAMP4_VINM0 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_OPAMP4_VINM1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_OPAMP4_VINM_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_OPAMP4_VINM_2 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8)
+# define GPIO_OPAMP4_VINM_SEC_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_OPAMP4_VINM_SEC_2 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8)
+# define GPIO_OPAMP4_VINM0_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_OPAMP4_VINM0_2 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8)
+# define GPIO_OPAMP4_VINM1_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10)
+# define GPIO_OPAMP4_VINM1_2 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8)
+#endif
+
+/* OPAMP5: All STM32G474(C-M-Q-R-V)xxx P/Ns have two alternates for each of
+ * VINM, VINM_SEC, VINM0, and VINM1, and one possible pinout for VOUT.
+ * STM32G474Cxxx P/Ns have one possible pinout for VINP and VINP_SEC,
+ * STM32G474(M-Q-R-V)xxx P/Ns have two alternates for VINP and VINP_SEC, and
+ * STM32G474(Q-V)xxx P/Ns offer a third alternative for VINP and VINP_SEC.
+ */
+
+#define GPIO_OPAMP5_VINM_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_OPAMP5_VINM_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_OPAMP5_VINM_SEC_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_OPAMP5_VINM_SEC_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_OPAMP5_VINM0_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_OPAMP5_VINM0_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_OPAMP5_VINM1_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_OPAMP5_VINM1_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_OPAMP5_VOUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN8)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_OPAMP5_VINP (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+# define GPIO_OPAMP5_VINP_SEC (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_OPAMP5_VINP_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+# define GPIO_OPAMP5_VINP_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
+# define GPIO_OPAMP5_VINP_SEC_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+# define GPIO_OPAMP5_VINP_SEC_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_OPAMP5_VINP_3 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_OPAMP5_VINP_SEC_3 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12)
+#endif
+
+/* OPAMP6: All STM32G474(C-M-Q-R-V)xxx P/Ns have two alternates for each of
+ * VINM, VINM_SEC, VINP, VINP_SEC, VINM0, and VINM1, and one possible pinout
+ * for VOUT. STM32G474(M-Q-V)xxx P/Ns add a third alternate for VINP and
+ * VINP_SEC.
+ */
+
+#define GPIO_OPAMP6_VINM_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_OPAMP6_VINM_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_OPAMP6_VINM_SEC_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_OPAMP6_VINM_SEC_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_OPAMP6_VINP_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_OPAMP6_VINP_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_OPAMP6_VINP_SEC_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_OPAMP6_VINP_SEC_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_OPAMP6_VINM0_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_OPAMP6_VINM0_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_OPAMP6_VINM1_1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_OPAMP6_VINM1_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_OPAMP6_VOUT (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN11)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_OPAMP6_VINP_3 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9)
+# define GPIO_OPAMP6_VINP_SEC_3 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9)
+#endif
+
+/* QUADSPI ******************************************************************************************/
+
+/* QUADSPI signals that are available on all STM32G474(C-M-Q-R-V)xxx P/Ns: */
+
+#define GPIO_QUADSPI1_BK1_NCS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_QUADSPI1_BK1_NCS_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_QUADSPI1_CLK_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_QUADSPI1_CLK_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
+
+/* QUADSPI signals that are available differently on each of
+ * STM32G474(C-M-Q-R-V)xxx P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_QUADSPI1_BK1_IO0 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
+# define GPIO_QUADSPI1_BK1_IO1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_QUADSPI1_BK1_IO2 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_QUADSPI1_BK1_IO3 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_QUADSPI1_BK2_IO1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_QUADSPI1_BK2_IO1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_QUADSPI1_BK2_IO3 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN4)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M)
+# define GPIO_QUADSPI1_BK1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
+# define GPIO_QUADSPI1_BK1_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
+# define GPIO_QUADSPI1_BK1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_QUADSPI1_BK1_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_QUADSPI1_BK1_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_QUADSPI1_BK1_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_QUADSPI1_BK1_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_QUADSPI1_BK1_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15)
+# define GPIO_QUADSPI1_BK1_NCS_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_QUADSPI1_BK2_IO0 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN1)
+# define GPIO_QUADSPI1_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_QUADSPI1_BK2_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_QUADSPI1_BK2_IO2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
+# define GPIO_QUADSPI1_BK2_IO3 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN4)
+# define GPIO_QUADSPI1_CLK_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_QUADSPI1_BK1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
+# define GPIO_QUADSPI1_BK1_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
+# define GPIO_QUADSPI1_BK1_IO0_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN8)
+# define GPIO_QUADSPI1_BK1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_QUADSPI1_BK1_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_QUADSPI1_BK1_IO1_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_QUADSPI1_BK1_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_QUADSPI1_BK1_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_QUADSPI1_BK1_IO2_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN7)
+# define GPIO_QUADSPI1_BK1_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_QUADSPI1_BK1_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15)
+# define GPIO_QUADSPI1_BK1_IO3_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN6)
+# define GPIO_QUADSPI1_BK1_NCS_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_QUADSPI1_BK2_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN1)
+# define GPIO_QUADSPI1_BK2_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_QUADSPI1_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_QUADSPI1_BK2_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_QUADSPI1_BK2_IO1_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN5)
+# define GPIO_QUADSPI1_BK2_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
+# define GPIO_QUADSPI1_BK2_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_QUADSPI1_BK2_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN4)
+# define GPIO_QUADSPI1_BK2_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_QUADSPI1_BK2_NCS (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_QUADSPI1_CLK_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
+# define GPIO_QUADSPI1_CLK_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN10)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_QUADSPI1_BK1_IO0 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
+# define GPIO_QUADSPI1_BK1_IO1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_QUADSPI1_BK1_IO2 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_QUADSPI1_BK1_IO3 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_QUADSPI1_BK2_IO0 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN1)
+# define GPIO_QUADSPI1_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_QUADSPI1_BK2_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_QUADSPI1_BK2_IO2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
+# define GPIO_QUADSPI1_BK2_IO3 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN4)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_QUADSPI1_BK1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
+# define GPIO_QUADSPI1_BK1_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
+# define GPIO_QUADSPI1_BK1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_QUADSPI1_BK1_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_QUADSPI1_BK1_IO1_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_QUADSPI1_BK1_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
+# define GPIO_QUADSPI1_BK1_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_QUADSPI1_BK1_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
+# define GPIO_QUADSPI1_BK1_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15)
+# define GPIO_QUADSPI1_BK1_NCS_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_QUADSPI1_BK2_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN1)
+# define GPIO_QUADSPI1_BK2_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_QUADSPI1_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_QUADSPI1_BK2_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_QUADSPI1_BK2_IO1_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN5)
+# define GPIO_QUADSPI1_BK2_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
+# define GPIO_QUADSPI1_BK2_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_QUADSPI1_BK2_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN4)
+# define GPIO_QUADSPI1_BK2_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_QUADSPI1_BK2_NCS (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_QUADSPI1_CLK_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
+# define GPIO_QUADSPI1_CLK_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN10)
+#endif
+
+/* RTC **********************************************************************************************/
+
+/* RTC: All STM32G474(C-M-Q-R-V)xxx P/Ns have the following signals
+ * identically:
+ */
+
+#define GPIO_RTC_OUT2 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_RTC_REFIN_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_RTC_REFIN_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN15)
+
+#if 0
+
+/* REVISIT: How do you actually enable OUT1, TAMP1, TAMP2, TS? The datasheet
+ * (DS12288 Rev 2, page 54) shows OUT1, TS, and TAMP1 as "additional
+ * functions" for PC13 on all STM32G474(C-M-Q-R-V)xxx P/Ns, but the alternate
+ * function table (on page 72) makes no mention of these. Meanwhile, page 56
+ * shows TAMP2 as an "additional function" but the same conundrum applies (for
+ * now). Granted, these are in the "additional function" column, not the
+ * "alternate function" column.
+ */
+
+# define GPIO_RTC_OUT1 (GPIO_PORTC|GPIO_PIN13)
+# define GPIO_RTC_TS (GPIO_PORTC|GPIO_PIN13)
+# define GPIO_RTC_TAMP1 (GPIO_PORTC|GPIO_PIN13)
+# define GPIO_RTC_TAMP2 (GPIO_PORTA|GPIO_PIN0)
+
+/* The same question applies to TAMP3. This signal is available only on
+ * STM32G474(Q-V)xxx P/Ns.
+ */
+
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_RTC_TAMP3 (GPIO_PORTE|GPIO_PIN6)
+# endif
+
+#endif
+
+/* SAI - Serial Audio Interface *********************************************************************/
+
+/* SAI CK1: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least two alternates.
+ * STM32G474(Q-V)xxx P/Ns have a third alternate, and STM32G474Qxxx have a
+ * fourth alternate.
+ */
+
+#define GPIO_SAI1_CK1_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_SAI1_CK1_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN8)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_CK1_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN2)
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_SAI1_CK1_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTG|GPIO_PIN7)
+# endif
+#endif
+
+/* SAI CK2: STM32G474(C-M-R)xxx P/Ns have only one possible pinout for CK2.
+ * STM32G474(Q-V)xxx P/Ns have two alternates.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_SAI1_CK2 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN8)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_CK2_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_SAI1_CK2_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN5)
+#endif
+
+/* SAI SCK_A: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least two alternates.
+ * STM32G474(Q-V)xxx P/Ns have a third alternate.
+ */
+
+#define GPIO_SAI1_SCK_A_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_SAI1_SCK_A_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN10)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_SCK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN5)
+#endif
+
+/* SAI SCK_B: STM32G474(C-R)xxx P/Ns have only one possible pinout for SCK_B.
+ * STM32G474(M-Q-V)xxx P/Ns have at least two alternates. STM32G474Qxxx P/Ns
+ * offer a third alternate.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_SAI1_SCK_B (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN3)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_SCK_B_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_SAI1_SCK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN8)
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_SAI1_SCK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN8)
+# endif
+#endif
+
+/* SAI MCLK_A: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least two alternates
+ * for MCLK_A. STM32G474(Q-V)xxx P/Ns have a third alternate, and
+ * STM32G474Qxxx P/Ns have a fourth alternate.
+ */
+
+#define GPIO_SAI1_MCLK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_SAI1_MCLK_A_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN8)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_MCLK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN2)
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_SAI1_MCLK_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN7)
+# endif
+#endif
+
+/* SAI MCLK_B: STM32G474(C-R)xxx P/Ns have only one possible pinout for
+ * MCLK_B. STM32G474(M-Q-V)xxx P/Ns have two alternates, and STM32G474Qxxx
+ * P/Ns have a third alternate.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_SAI1_MCLK_B (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN4)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_MCLK_B_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_SAI1_MCLK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN10)
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_SAI1_MCLK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN7)
+# endif
+#endif
+
+/* SAI FS_A: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least two alternates
+ * for FS_A. STM32G474(Q-V)xxx P/Ns have a third alternate.
+ */
+
+#define GPIO_SAI1_FS_A_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_SAI1_FS_A_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN9)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_FS_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN4)
+#endif
+
+/* SAI FS_B: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least three alternates
+ * for FS_B. STM32G474(M-Q-V)xxx P/Ns have a third alternate.
+ * STM32G474(Q-V)xxx P/Ns have fourth and fifth alternates.
+ */
+
+#define GPIO_SAI1_FS_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_SAI1_FS_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_SAI1_FS_B_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN6)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_FS_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN9)
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_FS_B_5 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN9)
+# endif
+#endif
+
+/* SAI SD_A: STM32G474Cxxx P/Ns have only one possible pinout for SD_A.
+ * STM32G474(M-Q-R-V)xxx P/Ns have three alternates. STM32G474(Q-V)xxx P/Ns
+ * add fourth and fifth alternates as well.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_SAI1_SD_A (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN10)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN1)
+# define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN3)
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_SD_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_SAI1_SD_A_5 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN6)
+# endif
+#endif
+
+/* SAI SD_B: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least two alternates.
+ * STM32G474Mxxx P/Ns add a third alternate. STM32G474(Q-V)xxx P/Ns have a
+ * fourth alternate, and STM32G474Qxxx have a fifth alternate.
+ */
+
+#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN5)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M)
+# define GPIO_SAI1_SD_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN7)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_SD_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN3)
+# define GPIO_SAI1_SD_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN7)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_SAI1_SD_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN3)
+# define GPIO_SAI1_SD_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN7)
+# define GPIO_SAI1_SD_B_5 (GPIO_ALT|GPIO_AF3|GPIO_PORTF|GPIO_PIN6)
+#endif
+
+/* SAI D1: STM32G474Cxxx P/Ns have only one possible pinout for D1.
+ * STM32G474(M-Q-R-V)xxx P/Ns have at least two alternates, with
+ * STM32G474(Q-V)xxx P/Ns having a third and fourth alternate.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_SAI1_D1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN10)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_D1_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_SAI1_D1_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN3)
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_D1_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_SAI1_D1_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN6)
+# endif
+#endif
+
+/* SAI D2: STM32G474(C-M-R)xxx P/Ns have only one possible pinout for D2.
+ * STM32G474(Q-V)xxx P/Ns have two alternates.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_SAI1_D2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN9)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_D2_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_SAI1_D2_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN4)
+#endif
+
+/* SAI D3: STM32G474(M-R)xxx P/Ns have only one possible pinout for D2.
+ * STM32G474(Q-V)xxx P/Ns have two alternates. STM32G474Cxxx P/Ns do not
+ * expose D3 to pins.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_SAI1_D3 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN5)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SAI1_D3_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_SAI1_D3_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN10)
+#endif
+
+/* SPI - Serial Peripheral Interface ****************************************************************/
+
+/* SPI1 signals that are available on all STM32G474(C-M-Q-R-V)xxx P/Ns: */
+
+#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
+
+/* SPI1 has a third alternate on STM32G474Qxxx P/Ns: */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_SPI1_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN3)
+# define GPIO_SPI1_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN4)
+# define GPIO_SPI1_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN2)
+# define GPIO_SPI1_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN5)
+#endif
+
+/* SPI2 signals that are available on all STM32G474(C-M-Q-R-V)xxx P/Ns: */
+
+#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN1)
+#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN0)
+
+/* SPI2 has a third NSS alternate, and third and fourth SCK alternates on
+ * STM32G474(Q-V)xxx P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN10)
+# define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN0)
+#endif
+
+/* SPI3 signals that are available on all STM32G474(C-M-Q-R-V)xxx P/Ns: */
+
+#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
+
+/* SPI3 signals that are available differently on each of
+ * STM32G474(C-M-Q-R-V)xxx P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# if defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_SPI3_MISO (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
+# elif defined(CONFIG_STM32_STM32G474C_U)
+# define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10)
+# endif
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
+# define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12)
+# define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10)
+#endif
+
+/* SPI3 SCK has a third alternate on STM32G474Qxxx P/Ns: */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_SPI3_SCK_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN9)
+#endif
+
+/* SPI4 is only available on STM32G474(M-Q-V)xxx P/Ns, with only one possible
+ * pin assignment on STM32G474Mxxx P/Ns and two alternates (three for NSS) on
+ * STM32G474(Q-V)xxx P/Ns:
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M)
+# define GPIO_SPI4_MISO (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_SPI4_MOSI (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_SPI4_SCK (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN12)
+# define GPIO_SPI4_NSS (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN11)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_SPI4_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN5)
+# define GPIO_SPI4_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_SPI4_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN6)
+# define GPIO_SPI4_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_SPI4_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN2)
+# define GPIO_SPI4_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN12)
+# define GPIO_SPI4_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN3)
+# define GPIO_SPI4_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN4)
+# define GPIO_SPI4_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN11)
+#endif
+
+/* TIM - Timers *************************************************************************************/
+
+/* TIM1: */
+
+#define GPIO_TIM1_CH1NIN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM1_CH1NIN_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_TIM1_CH1NIN_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_TIM1_CH1NIN_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN13)
+
+#define GPIO_TIM1_CH1NOUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM1_CH1NOUT_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_TIM1_CH1NOUT_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_TIM1_CH1NOUT_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN13)
+
+#define GPIO_TIM1_CH2NIN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_TIM1_CH2NIN_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TIM1_CH2NIN_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
+
+#define GPIO_TIM1_CH2NOUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_TIM1_CH2NOUT_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TIM1_CH2NOUT_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
+
+#define GPIO_TIM1_CH3NIN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM1_CH3NIN_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_TIM1_CH3NIN_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_TIM1_CH3NIN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN12)
+
+#define GPIO_TIM1_CH3NOUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM1_CH3NOUT_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_TIM1_CH3NOUT_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_TIM1_CH3NOUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12)
+
+#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_TIM1_BKIN_4 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM1_BKIN_5 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_TIM1_BKIN_6 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_TIM1_BKIN_7 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN13)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_TIM1_CH1IN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
+
+# define GPIO_TIM1_CH2IN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
+
+# define GPIO_TIM1_CH3IN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
+
+# define GPIO_TIM1_CH4IN (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_CH4IN (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
+
+# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
+
+# define GPIO_TIM1_BKIN2 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN11)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN0)
+# define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
+# define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0)
+
+# define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN1)
+# define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1)
+
+# define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
+# define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2)
+
+# define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN3)
+# define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
+
+# define GPIO_TIM1_BKIN2_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN11)
+# define GPIO_TIM1_BKIN2_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN3)
+
+# define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
+# define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN4)
+# if !defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_TIM1_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9)
+# define GPIO_TIM1_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9)
+# define GPIO_TIM1_CH1NIN_5 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN8)
+# define GPIO_TIM1_CH1NOUT_5 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8)
+
+# define GPIO_TIM1_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_TIM1_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
+# define GPIO_TIM1_CH2NIN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN10)
+# define GPIO_TIM1_CH2NOUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN10)
+
+# define GPIO_TIM1_CH3IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_TIM1_CH3OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
+# define GPIO_TIM1_CH3NIN_5 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN0)
+# define GPIO_TIM1_CH3NOUT_5 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN0)
+
+# define GPIO_TIM1_CH4IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_TIM1_CH4OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14)
+# define GPIO_TIM1_CH4NIN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_TIM1_CH4NIN_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN15)
+# define GPIO_TIM1_CH4NOUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_TIM1_CH4NOUT_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN15)
+
+# define GPIO_TIM1_BKIN_8 (GPIO_ALT|GPIO_AF2|GPIO_PORTE|GPIO_PIN15)
+# define GPIO_TIM1_BKIN2_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN14)
+
+# define GPIO_TIM1_ETR_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN7)
+# endif
+# if defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_TIM1_CH4NOUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
+# endif
+#endif
+
+#if defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_TIM1_CH4NIN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_TIM1_ETR (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
+#elif defined(CONFIG_STM32_STM32G474C_U)
+# define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
+# define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN4)
+#endif
+
+/* TIM2 */
+
+#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
+
+#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
+
+#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_TIM2_CH3IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_TIM2_CH3OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
+
+#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM2_CH4IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM2_CH4OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
+
+#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM2_CH1IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_TIM2_CH1IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_TIM2_CH1IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_TIM2_CH1IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN3)
+
+# define GPIO_TIM2_CH1OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_TIM2_CH1OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_TIM2_CH1OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_TIM2_CH1OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3)
+
+# define GPIO_TIM2_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_TIM2_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_TIM2_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_TIM2_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN4)
+
+# define GPIO_TIM2_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_TIM2_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_TIM2_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_TIM2_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN4)
+
+# define GPIO_TIM2_CH3IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_TIM2_CH3IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_TIM2_CH3IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_TIM2_CH3IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN7)
+
+# define GPIO_TIM2_CH3OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_TIM2_CH3OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_TIM2_CH3OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7)
+# define GPIO_TIM2_CH3OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7)
+
+# define GPIO_TIM2_CH4IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_TIM2_CH4IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_TIM2_CH4IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_TIM2_CH4IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN6)
+
+# define GPIO_TIM2_CH4OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_TIM2_CH4OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_TIM2_CH4OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_TIM2_CH4OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
+
+# define GPIO_TIM2_ETR_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_TIM2_ETR_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_TIM2_ETR_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_TIM2_ETR_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN3)
+#endif
+
+/* TIM3 */
+
+#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
+
+#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
+
+#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
+
+#if !defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_TIM3_CH3IN (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_ETR (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM3_CH2IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_TIM3_CH2OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
+
+# define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
+# define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
+
+# define GPIO_TIM3_CH4IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_TIM3_CH4OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
+
+# define GPIO_TIM3_ETR_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
+# define GPIO_TIM3_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN2)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM3_CH1IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN2)
+# define GPIO_TIM3_CH1OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN2)
+
+# define GPIO_TIM3_CH2IN_5 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN3)
+# define GPIO_TIM3_CH2OUT_5 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN3)
+
+# define GPIO_TIM3_CH3IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN4)
+# define GPIO_TIM3_CH3OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4)
+
+# define GPIO_TIM3_CH4IN_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5)
+# define GPIO_TIM3_CH4OUT_4 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
+#endif
+
+/* TIM4 */
+
+#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
+
+#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
+
+#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
+
+#define GPIO_TIM4_ETR_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_TIM4_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_TIM4_CH4IN (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM4_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_TIM4_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_TIM4_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_TIM4_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12)
+
+# define GPIO_TIM4_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_TIM4_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_TIM4_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_TIM4_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
+
+# define GPIO_TIM4_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_TIM4_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_TIM4_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_TIM4_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13)
+
+# define GPIO_TIM4_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_TIM4_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_TIM4_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
+# define GPIO_TIM4_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
+
+# define GPIO_TIM4_CH3IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14)
+# define GPIO_TIM4_CH3IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14)
+# define GPIO_TIM4_CH3IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14)
+# define GPIO_TIM4_CH3IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14)
+
+# define GPIO_TIM4_CH3OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14)
+# define GPIO_TIM4_CH3OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14)
+# define GPIO_TIM4_CH3OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14)
+# define GPIO_TIM4_CH3OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14)
+
+# define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
+
+# define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15)
+# define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15)
+# define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15)
+# define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15)
+
+# define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+
+# define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15)
+# define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15)
+# define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15)
+# define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15)
+
+# define GPIO_TIM4_ETR_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM4_ETR_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM4_ETR_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM4_ETR_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_TIM4_CH4OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
+# define GPIO_TIM4_CH4IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6)
+#endif
+
+/* TIM5 */
+
+#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_TIM5_CH2IN (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM5_CH2IN (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_TIM5_CH3IN (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM5_CH3IN (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM5_CH3IN (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
+
+# define GPIO_TIM5_CH4IN (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM5_CH4IN (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM5_CH4IN (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN12)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN12)
+# define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN8)
+# define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
+# define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8)
+
+# define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9)
+# define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
+# define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9)
+
+# if !defined(CONFIG_STM32_STM32G474M_T)
+# define GPIO_TIM5_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_TIM5_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_TIM5_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_TIM5_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_TIM5_ETR_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN12)
+
+# define GPIO_TIM5_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_TIM5_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_TIM5_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_TIM5_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_TIM5_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN11)
+# endif
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM5_CH4IN_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM5_CH4IN_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM5_CH4IN_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM5_CH4IN_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
+
+# define GPIO_TIM5_CH4OUT_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM5_CH4OUT_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM5_CH4OUT_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM5_CH4OUT_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_TIM5_CH1IN_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6)
+# define GPIO_TIM5_CH1OUT_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
+
+# define GPIO_TIM5_CH2IN_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7)
+# define GPIO_TIM5_CH2OUT_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7)
+
+# define GPIO_TIM5_CH3IN_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8)
+# define GPIO_TIM5_CH3OUT_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8)
+
+# define GPIO_TIM5_ETR_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6)
+#endif
+
+/* TIM8 */
+
+#define GPIO_TIM8_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_TIM8_CH1IN_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_TIM8_CH1OUT_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_TIM8_CH1NIN_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM8_CH1NIN_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_TIM8_CH1NOUT_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM8_CH1NOUT_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
+
+#define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_TIM8_CH2IN_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_TIM8_CH2OUT_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM8_CH2NIN_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TIM8_CH2NIN_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_TIM8_CH2NOUT_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TIM8_CH2NOUT_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
+
+#define GPIO_TIM8_CH3NIN_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM8_CH3NIN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM8_CH3NOUT_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM8_CH3NOUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
+
+#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM8_BKIN_3 (GPIO_ALT|GPIO_AF11|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM8_BKIN_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN7)
+
+#define GPIO_TIM8_ETR_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM8_ETR_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6)
+
+#if !defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_TIM8_CH1IN_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_TIM8_CH1OUT_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
+# define GPIO_TIM8_CH1NIN_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN10)
+# define GPIO_TIM8_CH1NOUT_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
+
+# define GPIO_TIM8_CH2NIN_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_TIM8_CH2NOUT_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_TIM8_BKIN2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
+# define GPIO_TIM8_BKIN2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
+
+# define GPIO_TIM8_CH3IN (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM8_CH3IN (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
+
+# define GPIO_TIM8_CH3OUT (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM8_CH3OUT (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_TIM8_CH4NIN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN13)
+# define GPIO_TIM8_CH4NOUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN13)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_TIM8_CH4IN (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_TIM8_CH4OUT (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM8_CH2IN_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_TIM8_CH2OUT_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
+# define GPIO_TIM8_CH3IN_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM8_CH3IN_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+# define GPIO_TIM8_CH3OUT_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_TIM8_CH3NIN_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN12)
+# define GPIO_TIM8_CH3NOUT_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12)
+
+# define GPIO_TIM8_BKIN_5 (GPIO_ALT|GPIO_AF4|GPIO_PORTD|GPIO_PIN2)
+# define GPIO_TIM8_BKIN2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6)
+# define GPIO_TIM8_BKIN2_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM8_CH4IN_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_TIM8_CH4IN_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN1)
+# define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
+# define GPIO_TIM8_CH4OUT_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1)
+# define GPIO_TIM8_CH4NIN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN13)
+# define GPIO_TIM8_CH4NIN_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN0)
+# define GPIO_TIM8_CH4NOUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN13)
+# define GPIO_TIM8_CH4NOUT_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0)
+
+# define GPIO_TIM8_BKIN2_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN1)
+#endif
+
+/* TIM15 */
+
+#define GPIO_TIM15_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM15_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM15_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_TIM15_CH1NIN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM15_CH1NIN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_TIM15_CH1NOUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM15_CH1NOUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
+
+#define GPIO_TIM15_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM15_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM15_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_TIM15_BKIN (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM15_BKIN (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN9)
+# define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN9)
+
+# define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN5)
+# define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTC|GPIO_PIN5)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM15_CH1IN_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM15_CH1IN_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM15_CH1IN_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM15_CH1IN_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
+
+# define GPIO_TIM15_CH1OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM15_CH1OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM15_CH1OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM15_CH1OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
+
+# define GPIO_TIM15_CH2IN_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN10)
+# define GPIO_TIM15_CH2IN_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN10)
+# define GPIO_TIM15_CH2IN_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN10)
+# define GPIO_TIM15_CH2IN_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN10)
+
+# define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10)
+# define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10)
+# define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10)
+# define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_TIM15_CH1NIN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN9)
+# define GPIO_TIM15_CH1NOUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9)
+#endif
+
+/* TIM16 */
+
+#define GPIO_TIM16_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM16_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_TIM16_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_TIM16_CH1IN_4 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_TIM16_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_TIM16_CH1OUT_4 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM16_CH1NIN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_TIM16_CH1NIN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_TIM16_CH1NOUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_TIM16_CH1NOUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
+
+#define GPIO_TIM16_BKIN (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN5)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM16_CH1IN_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM16_CH1IN_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM16_CH1IN_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM16_CH1IN_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+
+# define GPIO_TIM16_CH1OUT_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM16_CH1OUT_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM16_CH1OUT_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM16_CH1OUT_5 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
+#endif
+
+/* TIM17 */
+
+#define GPIO_TIM17_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM17_CH1IN_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM17_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM17_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_TIM17_CH1NIN (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM17_CH1NOUT (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
+
+#define GPIO_TIM17_BKIN_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM17_BKIN_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN4)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM17_CH1IN_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1)
+# define GPIO_TIM17_CH1OUT_4 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
+#endif
+
+/* TIM20 */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_TIM20_CH1IN (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_TIM20_CH1OUT (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_TIM20_CH2IN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_TIM20_CH2OUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2)
+
+# define GPIO_TIM20_CH3IN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_TIM20_CH3OUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM20_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_TIM20_CH1IN_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN2)
+# define GPIO_TIM20_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2)
+# define GPIO_TIM20_CH1OUT_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN2)
+
+# define GPIO_TIM20_CH2IN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_TIM20_CH2IN_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN3)
+# define GPIO_TIM20_CH2OUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2)
+# define GPIO_TIM20_CH2OUT_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN3)
+
+# define GPIO_TIM20_CH3IN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_TIM20_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN2)
+# define GPIO_TIM20_CH3OUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
+# define GPIO_TIM20_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_TIM20_CH1NIN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN4)
+# define GPIO_TIM20_CH1NOUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4)
+
+# define GPIO_TIM20_CH2NIN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5)
+# define GPIO_TIM20_CH2NOUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
+
+# define GPIO_TIM20_CH3NIN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6)
+# define GPIO_TIM20_CH3NOUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
+
+# define GPIO_TIM20_CH4IN (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1)
+# define GPIO_TIM20_CH4OUT (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
+# define GPIO_TIM20_CH4NIN (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM20_CH4NOUT (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
+
+# define GPIO_TIM20_BKIN (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM20_BKIN2 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN10)
+
+# define GPIO_TIM20_ETR (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_TIM20_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN12)
+# define GPIO_TIM20_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN12)
+# define GPIO_TIM20_CH1NIN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN4)
+# define GPIO_TIM20_CH1NIN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN4)
+# define GPIO_TIM20_CH1NIN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN0)
+# define GPIO_TIM20_CH1NOUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4)
+# define GPIO_TIM20_CH1NOUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN4)
+# define GPIO_TIM20_CH1NOUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN0)
+
+# define GPIO_TIM20_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN13)
+# define GPIO_TIM20_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13)
+# define GPIO_TIM20_CH2NIN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5)
+# define GPIO_TIM20_CH2NIN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN5)
+# define GPIO_TIM20_CH2NIN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN1)
+# define GPIO_TIM20_CH2NOUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
+# define GPIO_TIM20_CH2NOUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN5)
+# define GPIO_TIM20_CH2NOUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN1)
+
+# define GPIO_TIM20_CH3IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN14)
+# define GPIO_TIM20_CH3OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN14)
+# define GPIO_TIM20_CH3NIN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6)
+# define GPIO_TIM20_CH3NIN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN2)
+# define GPIO_TIM20_CH3NOUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
+# define GPIO_TIM20_CH3NOUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN2)
+
+# define GPIO_TIM20_CH4IN_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1)
+# define GPIO_TIM20_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN3)
+# define GPIO_TIM20_CH4IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN15)
+# define GPIO_TIM20_CH4OUT_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
+# define GPIO_TIM20_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN3)
+# define GPIO_TIM20_CH4OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN15)
+# define GPIO_TIM20_CH4NIN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM20_CH4NIN_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN3)
+# define GPIO_TIM20_CH4NOUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM20_CH4NOUT_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN3)
+
+# define GPIO_TIM20_BKIN_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN7)
+# define GPIO_TIM20_BKIN_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN9)
+# define GPIO_TIM20_BKIN_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTG|GPIO_PIN3)
+# define GPIO_TIM20_BKIN_4 (GPIO_ALT|GPIO_AF2|GPIO_PORTG|GPIO_PIN6)
+
+# define GPIO_TIM20_BKIN2_1 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN8)
+# define GPIO_TIM20_BKIN2_2 (GPIO_ALT|GPIO_AF2|GPIO_PORTF|GPIO_PIN10)
+# define GPIO_TIM20_BKIN2_3 (GPIO_ALT|GPIO_AF2|GPIO_PORTG|GPIO_PIN4)
+
+# define GPIO_TIM20_ETR_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
+# define GPIO_TIM20_ETR_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN11)
+# define GPIO_TIM20_ETR_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN5)
+#endif
+
+/* UARTs/USARTs *************************************************************************************/
+
+/* USART1: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least two alternates for
+ * TX, at least two alternates for RX, and one pin each for DE, RTS, CTS, CK,
+ * and NSS. All except STM32G474CxTx P/Ns have a third TX alternate.
+ * STM32G474(Q-V)xxx P/Ns have a fourth TX alternate and STM32G474Qxxx P/Ns
+ * have a fifth TX alternate. STM32G474(M-Q-R-V)xxx P/Ns have a third RX
+ * alternate, and STM32G474(Q-V)xxx P/Ns have a fourth RX alternate.
+ */
+
+#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_USART1_DE (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_USART1_NSS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11)
+
+#if !defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_USART1_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN4)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_USART1_TX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTE|GPIO_PIN0)
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_USART1_TX_5 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN9)
+# endif
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_USART1_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN5)
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_USART1_RX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTE|GPIO_PIN1)
+# endif
+#endif
+
+/* USART2: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least three alternates for
+ * TX, at least three alternates for RX, and at least two alternates for CK.
+ * STM32G474(C-M-R)xxx P/Ns have only one possible pinout for each of DE, RTS,
+ * CTS, and NSS, while STM32G474(Q-V)xxx P/Ns have two alternates for each of
+ * these. STM32G474(Q-V)xxx P/Ns also have a third alternate for CK.
+ */
+
+#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_USART2_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_USART2_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN5)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_USART2_TX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN5)
+# define GPIO_USART2_RX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN6)
+# define GPIO_USART2_CK_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_USART2_DE (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_USART2_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_USART2_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_USART2_NSS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_USART2_DE_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_USART2_DE_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_USART2_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
+# define GPIO_USART2_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4)
+# define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3)
+# define GPIO_USART2_NSS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0)
+# define GPIO_USART2_NSS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3)
+#endif
+
+/* USART3: All STM32G474(C-M-Q-R-V)xxx P/Ns have at least two alternates for
+ * each of TX, RX, CTS, and NSS. All STM32G474(C-M-Q-R-V)xxx P/Ns except
+ * STM32G474CxTx have a third TX and RX alternate, and STM32G474(M-Q-V)xxx
+ * P/Ns have a fourth TX alternate and a fourth and fifth RX alternate.
+ * STM32G474Cxxx P/Ns have only one possible CK but STM32G474(M-Q-R-V)xxx P/Ns
+ * have two alternates, and STM32G474(M-Q-V)xxx P/Ns offer a third alternate.
+ * STM32G474(Q-V)xxx and STM32G474MxYx P/Ns offer a third alternate for CTS
+ * and NSS. STM32G474(C-M-R)xxx P/Ns offer only one possible pinout for DE and
+ * RTS, while STM32G474(Q-V)xxx P/Ns offer two alternates (and STM32G474Qxxx
+ * P/Ns offer a third RTS).
+ */
+
+#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_USART3_NSS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_USART3_NSS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13)
+
+#if !defined(CONFIG_STM32_STM32G474C_T)
+# define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN10)
+# define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN11)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_USART3_TX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN8)
+# define GPIO_USART3_RX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN9)
+# define GPIO_USART3_RX_5 (GPIO_ALT|GPIO_AF7|GPIO_PORTE|GPIO_PIN15)
+# if !defined(CONFIG_STM32_STM32G474M_T)
+# define GPIO_USART3_CTS_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11)
+# define GPIO_USART3_NSS_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11)
+# endif
+# define GPIO_USART3_CK_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN10)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R)
+# define GPIO_USART3_DE (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
+# define GPIO_USART3_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_USART3_DE_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
+# define GPIO_USART3_DE_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12)
+# define GPIO_USART3_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
+# define GPIO_USART3_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12)
+# if defined(CONFIG_ARCH_CHIP_STM32G474Q)
+# define GPIO_USART3_RTS_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTF|GPIO_PIN6)
+# endif
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474C)
+# define GPIO_USART3_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12)
+#elif defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12)
+# define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12)
+#endif
+
+/* UART4 and UART5 are only available on STM32G474(M-Q-R-V)xxx P/Ns, with only
+ * one possible pinout for each of TX, RX, DE, RTS, CTS.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474Q) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474R) || \
+ defined(CONFIG_ARCH_CHIP_STM32G474V)
+# define GPIO_UART4_TX (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN10)
+# define GPIO_UART4_RX (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN11)
+# define GPIO_UART4_DE (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_UART4_RTS (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15)
+# define GPIO_UART4_CTS (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN7)
+
+# define GPIO_UART5_TX (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN12)
+# define GPIO_UART5_RX (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN2)
+# define GPIO_UART5_DE (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_UART5_RTS (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN4)
+# define GPIO_UART5_CTS (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN5)
+#endif
+
+/* USB Device Full Speed ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H */
Review comment:
You can uses something like `sunifdef` to fix this,
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-629831671
When I finish making all the changes you requested, will it be easier for you if I squash the commits? Or leave them separate?
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-632781214
FYI the above weirdness with changing base branch from 'master' to 'SocketCAN' and back to 'master' is because I force-pushed to the branch and GitHub did not update the PR. By changing the base branch, and changing it back, GitHub recognized the force push.
What changed in the force push:
- Rebased on latest master.
- Fixed some coding style issues found by davids5.
- Updated commit messages.
- No functional changes.
I confirmed that the board boots and runs with all the cumulative changes since I opened this PR.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426265023
##########
File path: arch/arm/src/stm32/hardware/stm32_adc_v2.h
##########
@@ -86,18 +86,24 @@
/* Base addresses ***********************************************************************************/
-#define STM32_ADC1_OFFSET 0x0000
-#define STM32_ADC2_OFFSET 0x0100
-#define STM32_ADC3_OFFSET 0x0000
-#define STM32_ADC4_OFFSET 0x0100
-#define STM32_ADCCMN_OFFSET 0x0300
+/* G47x has the ADC base addresses are defined in stm32g47xxx_memorymap.h.
+ * Other P/Ns have ADC base addresses are defined here.
+ */
-#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */
-#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */
-#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */
-#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */
-#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */
-#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */
+#if !defined(CONFIG_STM32_STM32G47XX)
Review comment:
Can you tell me why the ADC driver is different from all other drivers? For all other drivers, peripheral base addresses are defined in the memorymap header.
It is less work to define ADC base addresses for G4 in stm32_adc_v2.h like you suggest. But I think it is more consistent with other drivers to move them all to the memorymap headers, unless there is a good reason not to.
I'll take your suggestion and move the defines to stm32_adc_v2.h for now, but we should consider moving all of them to the memorymap header in a later PR.
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[GitHub] [incubator-nuttx] Ouss4 commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
Ouss4 commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r428325418
##########
File path: boards/arm/stm32/b-g474e-dpow1/src/Make.defs
##########
@@ -0,0 +1,38 @@
+############################################################################
+# boards/arm/stm32/b-g474e-dpow1/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
Review comment:
```suggestion
include $(TOPDIR)/Make.defs
```
To make it consistent with the recent changes to other makefiles. (#1088)
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426273405
##########
File path: arch/arm/src/stm32/hardware/stm32_adc_v2.h
##########
@@ -86,18 +86,24 @@
/* Base addresses ***********************************************************************************/
-#define STM32_ADC1_OFFSET 0x0000
-#define STM32_ADC2_OFFSET 0x0100
-#define STM32_ADC3_OFFSET 0x0000
-#define STM32_ADC4_OFFSET 0x0100
-#define STM32_ADCCMN_OFFSET 0x0300
+/* G47x has the ADC base addresses are defined in stm32g47xxx_memorymap.h.
+ * Other P/Ns have ADC base addresses are defined here.
+ */
-#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */
-#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */
-#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */
-#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */
-#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */
-#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */
+#if !defined(CONFIG_STM32_STM32G47XX)
Review comment:
That is OK, but why are the base address defines supposed to be in stm32_adc_v2.h and not in the memory map headers?
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[GitHub] [incubator-nuttx] davids5 commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
davids5 commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r427225684
##########
File path: arch/arm/src/stm32/hardware/stm32_dma_v1.h
##########
@@ -54,6 +54,10 @@
#define DMA1 (0)
#define DMA2 (1)
+#if defined(CONFIG_STM32_STM32G47XX)
+# define HAVE_DMA_CHAN8
+#endif
Review comment:
This should come in from chip.h or Kconfig.
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426136043
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
##########
@@ -0,0 +1,2627 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "stm32_gpio.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Alternate Pin Functions. All members of the STM32G47xxx family share the
+ * same pin multiplexing (although they differ in the pins physically
+ * available).
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if CAN1_RX connects via PA11 on some board, then the following
+ * definitions should appear in the board.h header file for that board:
+ *
+ * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
+ *
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
+ */
+
+/* ADC - Analog Digital Converter *******************************************************************/
+
+/* ADC1 has IN1-IN5, IN10-IN12, IN14-IN15 on all STM32G474(C-M-Q-R-V)xxx P/Ns
+ * and also has IN6-9 on STM32G474(M-Q-R-V)xxx P/Ns:
+ */
+
+#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN0)
+#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
Review comment:
We should remove #if's like this one and don't care if selected chip variant support given pin or not. This is user responsibility to select appropriate pin. These excessive conditions make the file difficult to read and difficult to maintain.
##########
File path: arch/arm/src/stm32/hardware/stm32_adc_v2.h
##########
@@ -86,18 +86,24 @@
/* Base addresses ***********************************************************************************/
-#define STM32_ADC1_OFFSET 0x0000
-#define STM32_ADC2_OFFSET 0x0100
-#define STM32_ADC3_OFFSET 0x0000
-#define STM32_ADC4_OFFSET 0x0100
-#define STM32_ADCCMN_OFFSET 0x0300
+/* G47x has the ADC base addresses are defined in stm32g47xxx_memorymap.h.
+ * Other P/Ns have ADC base addresses are defined here.
+ */
-#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */
-#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */
-#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */
-#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */
-#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */
-#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */
+#if !defined(CONFIG_STM32_STM32G47XX)
Review comment:
I don't like this. We should define the ADC base addresses for G4 here or update all other families to define this in memorymap headers. I prefer the first option and we should modify stm32_adc_v2.h logic to support ADC345CMN variant.
Support for ADC5 requires a little more work, so it's better to ignore ADC5 at this time and leave this logic unchanged.
##########
File path: arch/arm/src/stm32/stm32_lowputc.c
##########
@@ -235,12 +235,18 @@
# endif
# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
- defined(CONFIG_STM32_STM32F37XX)
+ defined(CONFIG_STM32_STM32F37XX)
# define USART_CR1_CLRBITS\
(USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME | \
USART_CR1_OVER8 | USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | \
USART_CR1_ALLINTS)
+# elif defined(CONFIG_STM32_STM32G47XX)
Review comment:
Should this not be combined with the above condition? The USART_CR1_M1 bit is not used in the current implementation anyway and it will match all other modified #ifdef's in this file
##########
File path: arch/arm/src/stm32/hardware/stm32_dma_v1.h
##########
@@ -64,6 +64,9 @@
#define DMA_CHAN5 (4)
#define DMA_CHAN6 (5)
#define DMA_CHAN7 (6)
+#if defined(CONFIG_STM32_STM32G47XX)
Review comment:
It's better to introduce a new definition in this file like this
#if defined(CONFIG_STM32_STM32G47XX)
#define HAVE_DMA_CHAN8
#endif
We should avoid chip-specific #ifdef's if possible.
##########
File path: arch/arm/src/stm32/stm32_dma_v1.c
##########
@@ -106,80 +114,132 @@ struct stm32_dma_s
static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
{
+#if DMA1_NCHANNELS > 0
{
.chan = 0,
.irq = STM32_IRQ_DMA1CH1,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
},
+#if DMA1_NCHANNELS > 1
{
.chan = 1,
.irq = STM32_IRQ_DMA1CH2,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
},
+#if DMA1_NCHANNELS > 2
{
.chan = 2,
.irq = STM32_IRQ_DMA1CH3,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
},
+#if DMA1_NCHANNELS > 3
{
.chan = 3,
.irq = STM32_IRQ_DMA1CH4,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
},
+#if DMA1_NCHANNELS > 4
{
.chan = 4,
.irq = STM32_IRQ_DMA1CH5,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
},
+#if DMA1_NCHANNELS > 5
{
.chan = 5,
.irq = STM32_IRQ_DMA1CH6,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
},
+#if DMA1_NCHANNELS > 6
{
.chan = 6,
.irq = STM32_IRQ_DMA1CH7,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
},
+#if DMA1_NCHANNELS > 7
+ {
+ .chan = 7,
+ .irq = STM32_IRQ_DMA1CH8,
+ .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7),
+ },
+#endif /* DMA1_NCHANNELS > 7 */
Review comment:
Is there a reason why these conditions are nested? It looks strange :)
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426143409
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
##########
@@ -0,0 +1,194 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* STM32G47xxx Address Blocks ***********************************************************************/
+
+#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM */
+ /* 0x70000000-0x7fffffff: Reserved */
+#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
+#define STM32_QSPI_BANK1 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
+
+#define STM32_FMC_QSPI_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 256Mb FMC and QUADSPI registers */
+ /* 0xc0000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
+
+#define STM32_REGION_MASK Warning Not Cleared! 0xf0000000
Review comment:
#define STM32_REGION_MASK 0xf0000000
is OK.
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[GitHub] [incubator-nuttx] davids5 commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
davids5 commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-630289289
> When I finish making all the changes you requested, will it be easier for you if I squash the commits? Or leave them separate?
@hartmannathan - you can use [mv-changes](https://github.com/MikhailGolubtsov/git-mv-changes) ti regroup by subject (i.e. pinmap, adc) or squash by file.
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-632192154
> Looks good to me. Good job Nathan ;]
Thank you so much for taking the time to make your detailed review!!
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426281875
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_pwr.h
##########
@@ -0,0 +1,485 @@
+/****************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_pwr.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32_PWR_CR1_OFFSET 0x0000 /* PWR Power Control Register 1 */
+#define STM32_PWR_CR2_OFFSET 0x0004 /* PWR Power Control Register 2 */
+#define STM32_PWR_CR3_OFFSET 0x0008 /* PWR Power Control Register 3 */
+#define STM32_PWR_CR4_OFFSET 0x000c /* PWR Power Control Register 4 */
+#define STM32_PWR_SR1_OFFSET 0x0010 /* PWR Power Status Register 1 */
+#define STM32_PWR_SR2_OFFSET 0x0014 /* PWR Power Status Register 2 */
+#define STM32_PWR_SCR_OFFSET 0x0018 /* PWR Power Status Reset Register */
+ /* Offset 0x001c Reserved */
+#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A Pull Up Control Register */
+#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A Pull Down Control Register */
+#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B Pull Up Control Register */
+#define STM32_PWR_PDCRB_OFFSET 0x002c /* Power Port B Pull Down Control Register */
+#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C Pull Up Control Register */
+#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C Pull Down Control Register */
+#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D Pull Up Control Register */
+#define STM32_PWR_PDCRD_OFFSET 0x003c /* Power Port D Pull Down Control Register */
+#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E Pull Up Control Register */
+#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E Pull Down Control Register */
+#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F Pull Up Control Register */
+#define STM32_PWR_PDCRF_OFFSET 0x004c /* Power Port F Pull Down Control Register */
+#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G Pull Up Control Register */
+#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G Pull Down Control Register */
+ /* Offset 0x0058 Reserved */
+ /* Offset 0x005C Reserved */
+ /* Offset 0x0060 Reserved */
+ /* Offset 0x0064 Reserved */
+ /* Offset 0x0068 Reserved */
+ /* Offset 0x006C Reserved */
+ /* Offset 0x0070 Reserved */
+ /* Offset 0x0074 Reserved */
+ /* Offset 0x0078 Reserved */
+ /* Offset 0x007C Reserved */
+#define STM32_PWR_CR5_OFFSET 0x0080 /* PWR Power Control Register 5 */
+
+/* Register Addresses *******************************************************/
+
+#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET)
+#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET)
+#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET)
+#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET)
+#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET)
+#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET)
+#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET)
+#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET)
+#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET)
+#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET)
+#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET)
+#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET)
+#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET)
+#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET)
+#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET)
+#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET)
+#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET)
+#define STM32_PWR_PUCRF (STM32_PWR_BASE + STM32_PWR_PUCRF_OFFSET)
+#define STM32_PWR_PDCRF (STM32_PWR_BASE + STM32_PWR_PDCRF_OFFSET)
+#define STM32_PWR_PUCRG (STM32_PWR_BASE + STM32_PWR_PUCRG_OFFSET)
+#define STM32_PWR_PDCRG (STM32_PWR_BASE + STM32_PWR_PDCRG_OFFSET)
+#define STM32_PWR_CR5 (STM32_PWR_BASE + STM32_PWR_CR5_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* PWR Power Control Register 1 (CR1) */
+
+#define PWR_CR1_LPR_SHIFT (14) /* Low Power Run */
+#define PWR_CR1_LPR (0x1 << PWR_CR1_LPR_SHIFT)
+#define PWR_CR1_VOS_SHIFT (9) /* Voltage Scaling Range Selection */
+#define PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_SHIFT)
+# define PWR_CR1_VOS_RANGE_1 (0x1 << PWR_CR1_VOS_SHIFT)
+# define PWR_CR1_VOS_RANGE_2 (0x2 << PWR_CR1_VOS_SHIFT)
+#define PWR_CR1_DBP_SHIFT (8) /* Disable Backup Domain Write Protection */
+#define PWR_CR1_DBP (0x1 << PWR_CR1_DBP_SHIFT)
+#define PWR_CR1_LPMS_SHIFT (0) /* Low Power Mode Selection */
+#define PWR_CR1_LPMS_MASK (0x7 << PWR_CR1_LPMS_SHIFT)
+# define PWR_CR1_LPMS_STOP_0 (0x0 << PWR_CR1_LPMS_SHIFT) /* Stop 0 Mode */
+# define PWR_CR1_LPMS_STOP_1 (0x1 << PWR_CR1_LPMS_SHIFT) /* Stop 1 Mode */
+# define PWR_CR1_LPMS_STANDBY (0x3 << PWR_CR1_LPMS_SHIFT) /* Standby Mode */
+# define PWR_CR1_LPMS_SHUTDOWN (0x4 << PWR_CR1_LPMS_SHIFT) /* Shutdown Mode */
+
+/* PWR Power Control Register 2 (CR2) */
+
+#define PWR_CR2_PVMEN2_SHIFT (7) /* Peripheral Voltage Monitoring 4 Enable (VDDA vs DAC 1Msps or 15Msps Minimum Voltage) */
+#define PWR_CR2_PVMEN2 (0x1 << PWR_CR2_PVMEN2_SHIFT)
+#define PWR_CR2_PVMEN1_SHIFT (6) /* Peripheral Voltage Monitoring 3 Enable (VDDA vs ADC or COMP Minimum Voltage) */
+#define PWR_CR2_PVMEN1 (0x1 << PWR_CR2_PVMEN1_SHIFT)
+#define PWR_CR2_PLS_SHIFT (1) /* Power Voltage Detector Level Selection */
+#define PWR_CR2_PLS_MASK (0x7 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_0 (0x0 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_1 (0x1 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_2 (0x2 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_3 (0x3 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_4 (0x4 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_5 (0x5 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_6 (0x6 << PWR_CR2_PLS_SHIFT)
+# define PWR_CR2_PLS_7 (0x7 << PWR_CR2_PLS_SHIFT)
+#define PWR_CR2_PVDE_SHIFT (0) /* Power Voltage Detector Enable */
+#define PWR_CR2_PVDE (0x1 << PWR_CR2_PVDE_SHIFT)
+
+/* PWR Power Control Register 3 (CR3) */
+
+#define PWR_CR3_EIWUL_SHIFT (15) /* Enable Internal Wake Up Line */
+#define PWR_CR3_EIWUL (0x1 << PWR_CR3_EIWUL_SHIFT)
+#define PWR_CR3_UCPD1_DBDIS_SHIFT (14) /* USB Type C And Power Delivery Dead Battery Disable */
+#define PWR_CR3_UCPD1_DBDIS (0x1 << PWR_CR3_UCPD1_DBDIS_SHIFT)
+#define PWR_CR3_UCPD1_STDBY_SHIFT (13) /* USB Type C And Power Delivery Standby Mode */
+#define PWR_CR3_UCPD1_STDBY (0x1 << PWR_CR3_UCPD1_STDBY_SHIFT)
+#define PWR_CR3_APC_SHIFT (10) /* Apply Pull Up And Pull Down Configuration */
+#define PWR_CR3_APC (0x1 << PWR_CR3_APC_SHIFT)
+#define PWR_CR3_RRS_SHIFT (8) /* SRAM2 Retention In Standby Mode */
+#define PWR_CR3_RRS (0x1 << PWR_CR3_RRS_SHIFT)
+#define PWR_CR3_EWUP5_SHIFT (4) /* Enable Wake Up Pin WKUP5 */
+#define PWR_CR3_EWUP5 (0x1 << PWR_CR3_EWUP5_SHIFT)
+#define PWR_CR3_EWUP4_SHIFT (3) /* Enable Wake Up Pin WKUP4 */
+#define PWR_CR3_EWUP4 (0x1 << PWR_CR3_EWUP4_SHIFT)
+#define PWR_CR3_EWUP3_SHIFT (2) /* Enable Wake Up Pin WKUP3 */
+#define PWR_CR3_EWUP3 (0x1 << PWR_CR3_EWUP3_SHIFT)
+#define PWR_CR3_EWUP2_SHIFT (1) /* Enable Wake Up Pin WKUP2 */
+#define PWR_CR3_EWUP2 (0x1 << PWR_CR3_EWUP2_SHIFT)
+#define PWR_CR3_EWUP1_SHIFT (0) /* Enable Wake Up Pin WKUP1 */
+#define PWR_CR3_EWUP1 (0x1 << PWR_CR3_EWUP1_SHIFT)
+
+/* PWR Power Control Register 4 (CR4) */
+
+#define PWR_CR4_VBRS_SHIFT (9) /* VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBRS (0x1 << PWR_CR4_VBRS_SHIFT)
+#define PWR_CR4_VBE_SHIFT (8) /* VBAT Battery charging Enable */
+#define PWR_CR4_VBE (0x1 << PWR_CR4_VBE_SHIFT)
+#define PWR_CR4_WP5_SHIFT (4) /* Wake Up Pin WKUP5 polarity */
+#define PWR_CR4_WP5 (0x1 << PWR_CR4_WP5_SHIFT)
+#define PWR_CR4_WP4_SHIFT (3) /* Wake Up Pin WKUP4 polarity */
+#define PWR_CR4_WP4 (0x1 << PWR_CR4_WP4_SHIFT)
+#define PWR_CR4_WP3_SHIFT (2) /* Wake Up Pin WKUP3 polarity */
+#define PWR_CR4_WP3 (0x1 << PWR_CR4_WP3_SHIFT)
+#define PWR_CR4_WP2_SHIFT (1) /* Wake Up Pin WKUP2 polarity */
+#define PWR_CR4_WP2 (0x1 << PWR_CR4_WP2_SHIFT)
+#define PWR_CR4_WP1_SHIFT (0) /* Wake Up Pin WKUP1 polarity */
+#define PWR_CR4_WP1 (0x1 << PWR_CR4_WP1_SHIFT)
+
+/* PWR Power Status Register 1 (SR1) */
+
+#define PWR_SR1_WUFI_SHIFT (15) /* Wake Up Flag Internal */
+#define PWR_SR1_WUFI (0x1 << PWR_SR1_WUFI_SHIFT)
+#define PWR_SR1_SBF_SHIFT (8) /* Stand-By Flag */
+#define PWR_SR1_SBF (0x1 << PWR_SR1_SBF_SHIFT)
+#define PWR_SR1_WUF_SHIFT (0) /* Wake Up Flags */
+#define PWR_SR1_WUF_MASK (0x1f << PWR_SR1_WUF_SHIFT)
+# define PWR_SR1_WUF5 (0x10 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 5 */
+# define PWR_SR1_WUF4 (0x8 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 4 */
+# define PWR_SR1_WUF3 (0x4 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 3 */
+# define PWR_SR1_WUF2 (0x2 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 2 */
+# define PWR_SR1_WUF1 (0x1 << PWR_SR1_WUF_SHIFT) /* Wake Up Flag 1 */
+
+/* PWR Power Status Register 2 (SR2) */
+
+#define PWR_SR2_PVMO4_SHIFT (15) /* Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO4 (0x1 << PWR_SR2_PVMO4_SHIFT)
+#define PWR_SR2_PVMO3_SHIFT (14) /* Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO3 (0x1 << PWR_SR2_PVMO3_SHIFT)
+#define PWR_SR2_PVMO2_SHIFT (13) /* Peripheral Voltage Monitoring Output 2 */
+#define PWR_SR2_PVMO2 (0x1 << PWR_SR2_PVMO2_SHIFT)
+#define PWR_SR2_PVMO1_SHIFT (12) /* Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVMO1 (0x1 << PWR_SR2_PVMO1_SHIFT)
+#define PWR_SR2_PVDO_SHIFT (11) /* Power Voltage Detector Output */
+#define PWR_SR2_PVDO (0x1 << PWR_SR2_PVDO_SHIFT)
+#define PWR_SR2_VOSF_SHIFT (10) /* Voltage Scaling Flag */
+#define PWR_SR2_VOSF (0x1 << PWR_SR2_VOSF_SHIFT)
+#define PWR_SR2_REGLPF_SHIFT (9) /* Low-power Regulator Flag */
+#define PWR_SR2_REGLPF (0x1 << PWR_SR2_REGLPF_SHIFT)
+#define PWR_SR2_REGLPS_SHIFT (8) /* Low-power Regulator Started */
+#define PWR_SR2_REGLPS (0x1 << PWR_SR2_REGLPS_SHIFT)
+#define PWR_SR2_FLASHRDY_SHIFT (7) /* Flash Ready Flag */
+#define PWR_SR2_FLASHRDY (0x1 << PWR_SR2_FLASHRDY_SHIFT)
+
+/* PWR Power Status Reset Register (SCR) */
+
+#define PWR_SCR_CSBF_SHIFT (8) /* Clear Standby Flag */
Review comment:
Fixed in 076cceb7b7da7510a6c7aed40cae7789343956c0.
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[GitHub] [incubator-nuttx] acassis commented on pull request #1051: Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
acassis commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-633037248
Ok, go ahead!
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-628908231
### Note about nxstyle:
The pre-checks are going to fail on nxstyle errors. I am aware of this and am working to resolve the nxstyle issues. In particular, I am going to put the nxstyle fixes into a separate commit, because they are going to change a lot of unrelated lines that will make reviewing more difficult.
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-632795203
> > > I confirmed that the board boots and runs with all the cumulative changes since I opened this PR.
> >
> >
> > Are there other boards this affects? Have you tested them as well?
>
> I don't have those boards. Do you mean build testing? I can build test some boards that use other processors in this directory.
@davids5 , actually, I do have a nucleo-f302r8 board. The stm32 directory handles the f302r8 MCU. I'll go ahead and make sure that builds, boots, and runs...
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426279441
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1810,6 +1876,100 @@ config STM32_STM32F469
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
+config STM32_STM32G47XX
+ bool
+ default n
+ select ARCH_CORTEXM4
+ select ARCH_HAVE_FPU
+ select STM32_HAVE_ADC2
+ select STM32_HAVE_ADC3
+ select STM32_HAVE_ADC4
+ select STM32_HAVE_ADC5
+ select STM32_HAVE_CCM
+ select STM32_HAVE_COMP1
+ select STM32_HAVE_COMP2
+ select STM32_HAVE_COMP3
+ select STM32_HAVE_COMP4
+ select STM32_HAVE_COMP5
+ select STM32_HAVE_COMP6
+ select STM32_HAVE_COMP7
+ select STM32_HAVE_CORDIC
+ select STM32_HAVE_CRS
+ select STM32_HAVE_DAC1
+ select STM32_HAVE_DAC2
+ select STM32_HAVE_DAC3
+ select STM32_HAVE_DAC4
+ select STM32_HAVE_FSMC
+ select STM32_HAVE_FMAC
+ select STM32_HAVE_FDCAN
Review comment:
Good catch! Fixed in 6cae597457f5d0ceca7fce23d43cfb1805fa99be.
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426143586
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
##########
@@ -0,0 +1,194 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* STM32G47xxx Address Blocks ***********************************************************************/
+
+#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM */
+ /* 0x70000000-0x7fffffff: Reserved */
+#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
+#define STM32_QSPI_BANK1 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
+
+#define STM32_FMC_QSPI_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 256Mb FMC and QUADSPI registers */
+ /* 0xc0000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
+
+#define STM32_REGION_MASK Warning Not Cleared! 0xf0000000
+#define STM32_IS_SRAM(a) Warning Not Cleared! ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
Review comment:
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-633238247
Thanks to everyone for taking the time to review and for all your great finds and suggestions!
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426285681
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_rcc.h
##########
@@ -0,0 +1,677 @@
+/****************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_rcc.h
+ * Register offsets, addresses, and bitfield defines for STM32G47xxx RCC
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_RCC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_RCC_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Abbreviations:
+ * HSE - High Speed External (clock)
+ * HSI - High Speed Internal (clock)
+ * POR - Power On Reset
+ * RCC - Reset and Clock Control
+ */
+
+/* Register Offsets *********************************************************/
+
+#define STM32_RCC_CR_OFFSET 0x0000 /* RCC Clock Control */
+#define STM32_RCC_ICSCR_OFFSET 0x0004 /* RCC Internal Clock Sources Calibration */
+#define STM32_RCC_CFGR_OFFSET 0x0008 /* RCC Clock Configuration */
+#define STM32_RCC_PLLCFGR_OFFSET 0x000c /* RCC PLL configuration register */
+ /* Offset 0x0010 Reserved */
+ /* Offset 0x0014 Reserved */
+#define STM32_RCC_CIER_OFFSET 0x0018 /* RCC Clock Interrupt Enable */
+#define STM32_RCC_CIFR_OFFSET 0x001c /* RCC Clock Interrupt Flag */
+#define STM32_RCC_CICR_OFFSET 0x0020 /* RCC Clock Interrupt Clear */
+ /* Offset 0x0024 Reserved */
+#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* RCC AHB1 Peripheral Reset */
+#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* RCC AHB2 Peripheral Reset */
+#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* RCC AHB3 Peripheral Reset */
+ /* Offset 0x0034 Reserved */
+#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* RCC APB1 Peripheral Reset Register 1 */
+#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* RCC APB1 Peripheral Reset Register 2 */
+#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* RCC APB2 Peripheral Reset */
+ /* Offset 0x0044 Reserved */
+#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* RCC AHB1 Peripheral Clock Enable */
+#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* RCC AHB2 Peripheral Clock Enable */
+#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* RCC AHB3 Peripheral Clock Enable */
+ /* Offset 0x0054 Reserved */
+#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* RCC APB1 Peripheral Clock Enable Register 1 */
+#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* RCC APB1 Peripheral Clock Enable Register 2 */
+#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* RCC APB2 Peripheral Clock Enable */
+ /* Offset 0x0064 Reserved */
+#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 Peripheral Clock Enable in Sleep/Stop Modes */
+#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 Peripheral Clock Enable in Sleep/Stop Modes */
+#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 Peripheral Clock Enable in Sleep/Stop Modes */
+ /* Offset 0x0074 Reserved */
+#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 Peripheral Clock Enable in Sleep/Stop Modes (1 of 2) */
+#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 Peripheral Clock Enable in Sleep/Stop Modes (2 of 2) */
+#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 Peripheral Clock Enable in Sleep/Stop Modes */
+ /* Offset 0x0084 Reserved */
+#define STM32_RCC_CCIPR_OFFSET 0x0088 /* RCC Peripherals Independent Clock Configuration (1 of 2, see CCIPR2) */
+ /* Offset 0x008c Reserved */
+#define STM32_RCC_BDCR_OFFSET 0x0090 /* RCC RTC Domain Control Register */
+#define STM32_RCC_CSR_OFFSET 0x0094 /* RCC Clock Control / Status Register */
+#define STM32_RCC_CRRCR_OFFSET 0x0098 /* RCC Clock Recovery RC Register */
+#define STM32_RCC_CCIPR2_OFFSET 0x009c /* RCC Peripherals Independent Clock Configuration (2 of 2, see CCIPR) */
+
+/* Register Addresses *******************************************************/
+
+#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET)
+#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET)
+#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET)
+#define STM32_RCC_PLLCFGR (STM32_RCC_BASE + STM32_RCC_PLLCFGR_OFFSET)
+#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET)
+#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET)
+#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET)
+#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET)
+#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET)
+#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET)
+#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET)
+#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET)
+#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET)
+#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET)
+#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET)
+#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET)
+#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET)
+#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET)
+#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET)
+#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET)
+#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET)
+#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET)
+#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET)
+#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET)
+#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET)
+#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET)
+#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET)
+#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET)
+#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET)
+#define STM32_RCC_CCIPR2 (STM32_RCC_BASE + STM32_RCC_CCIPR2_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* CR - Clock Control Register */
+
+#define RCC_CR_HSION (1 << 8) /* Bit 8: HSI16 clock enable */
+#define RCC_CR_HSIKERON (1 << 9) /* Bit 9: HSI16 always enable for peripheral kernel */
+#define RCC_CR_HSIRDY (1 << 10) /* Bit 10: HSI16 clock ready flag */
+#define RCC_CR_HSEON (1 << 16) /* Bit 16: HSE clock enable */
+#define RCC_CR_HSERDY (1 << 17) /* Bit 17: HSE clock ready flag */
+#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: HSE crystal oscillator bypass */
+#define RCC_CR_CSSON (1 << 19) /* Bit 19: HSE clock security system enable */
+#define RCC_CR_PLLON (1 << 24) /* Bit 24: Main PLL enable */
+#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: Main PLL ready */
+
+#define RCC_CR_RESERVED_MASK 0xfcf0f8ff /* Bits 31-26, 23-20, 15-11, and 7-0 should be kept at reset value */
+#define RCC_CR_RESET 0x00000063 /* Value at POR */
+
+/* ICSCR - Internal Clock Sources Calibration Register */
+
+#define RCC_ICSCR_HSICAL_SHIFT (16) /* Bits 23-16: HSI16 calibration (factory programmed, read only) */
+#define RCC_ICSCR_HSICAL_MASK (0xff << RCC_ICSCR_HSICAL_SHIFT)
+
+#define RCC_ICSCR_HSITRIM_SHIFT (24) /* Bits 30-24: HSI16 clock trimming */
+#define RCC_ICSCR_HSITRIM_MASK (0x7f << RCC_ICSCR_HSITRIM_SHIFT)
+#define RCC_ICSCR_HSITRIM_RESET (0x40 << RCC_ICSCR_HSITRIM_SHIFT)
+
+/* CFGR - Clock Configuration Register */
+
+#define RCC_CFGR_SW_SHIFT (0) /* Bits 1-0: System clock switch */
+#define RCC_CFGR_SW_MASK (0x3 << RCC_CFGR_SW_SHIFT)
+# define RCC_CFGR_SW_HSI (1 << RCC_CFGR_SW_SHIFT)
+# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT)
+# define RCC_CFGR_SW_PLL (3 << RCC_CFGR_SW_SHIFT)
+#define RCC_CFGR_SWS_SHIFT (2) /* Bits 3-2: System clock switch status */
+#define RCC_CFGR_SWS_MASK (0x3 << RCC_CFGR_SWS_SHIFT)
+# define RCC_CFGR_SWS_HSI (1 << RCC_CFGR_SWS_SHIFT)
+# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT)
+# define RCC_CFGR_SWS_PLL (3 << RCC_CFGR_SWS_SHIFT)
+#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 7-4: AHB prescaler */
+#define RCC_CFGR_HPRE_MASK (0xf << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT)
+#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 10-8: AHB1 prescaler */
+#define RCC_CFGR_PPRE1_MASK (0x7 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT)
+#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 13-11: AHB2 prescaler */
+#define RCC_CFGR_PPRE2_MASK (0x7 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT)
+ /* Bits 23-14: Reserved */
+#define RCC_CFGR_MCOSEL_SHIFT (24) /* Bits 27-24: MCU clock output*/
+#define RCC_CFGR_MCOSEL_MASK (0xf << RCC_CFGR_MCOSEL_SHIFT)
+#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bit 28: */
+#define RCC_CFGR_MCOPRE_MASK (0x7 << RCC_CFGR_MCOPRE_SHIFT)
+ /* Bit 31: Reserved */
+
+#define RCC_CFGR_RESERVED_MASK 0x00ffc000 /* Bits 23-14 should be kept at reset value */
+#define RCC_CFGR_RESET 0x00000001 /* It's actually 0x5 but bits 3-2 are read only */
+
+/* PLLCFGR - System PLL Configuration Register */
+
+#define RCC_PLLCFGR_PLLSRC_SHIFT (0) /* Bits 1-0: Main PLL entry clock source */
+#define RCC_PLLCFGR_PLLSRC_MASK (3 << RCC_PLLCFGR_PLLSRC_SHIFT)
+# define RCC_PLLCFGR_PLLSRC_NOCLK (0 << RCC_PLLCFGR_PLLSRC_SHIFT)
+# define RCC_PLLCFGR_PLLSRC_HSI (2 << RCC_PLLCFGR_PLLSRC_SHIFT)
+# define RCC_PLLCFGR_PLLSRC_HSE (3 << RCC_PLLCFGR_PLLSRC_SHIFT)
+ /* Bits 3-2: Reserved */
+#define RCC_PLLCFGR_PLLM_SHIFT (4) /* Bits 7-4: Division factor M of main PLL input clock */
+#define RCC_PLLCFGR_PLLM_MASK (0xf << RCC_PLLCFGR_PLLM_SHIFT)
+#define RCC_PLLCFGR_PLLM(n) ((((n) - 1) << RCC_PLLCFGR_PLLM_SHIFT) & RCC_PLLCFGR_PLLM_MASK) /* n=1..16 */
+
+#define RCC_PLLCFGR_PLLN_SHIFT (8) /* Bits 14-8: Main PLL multiplication factor N for VCO */
+#define RCC_PLLCFGR_PLLN_MASK (0x7f << RCC_PLLCFGR_PLLN_SHIFT)
+#define RCC_PLLCFGR_PLLN(n) (((n) << RCC_PLLCFGR_PLLN_SHIFT) & RCC_PLLCFGR_PLLN_MASK) /* n=8..127 */
+ /* Bit 15: Reserved */
+#define RCC_PLLCFGR_PLLPEN (1 << 16) /* Bit 16: Main PLL PCLK output enable */
+#define RCC_PLLCFGR_PLLP (1 << 17) /* Bit 17: Main PLL division factor for PLL P clock, 0:PLLP=7, 1:PLLP=17 */
+ /* Bits 19-18: Reserved */
+#define RCC_PLLCFGR_PLLQEN (1 << 20) /* Bit 20: Main PLL Q clock output enable */
+#define RCC_PLLCFGR_PLLQ_SHIFT (21) /* Bits 22-21: Main PLL division factor for PLL Q clock */
+#define RCC_PLLCFGR_PLLQ_MASK (0x3 << RCC_PLLCFGR_PLLQ_SHIFT)
+# define RCC_PLLCFGR_PLLQ_2 (0x0 << RCC_PLLCFGR_PLLQ_SHIFT)
+# define RCC_PLLCFGR_PLLQ_4 (0x1 << RCC_PLLCFGR_PLLQ_SHIFT)
+# define RCC_PLLCFGR_PLLQ_6 (0x2 << RCC_PLLCFGR_PLLQ_SHIFT)
+# define RCC_PLLCFGR_PLLQ_8 (0x3 << RCC_PLLCFGR_PLLQ_SHIFT)
+ /* Bits 23: Reserved */
+#define RCC_PLLCFGR_PLLREN (1 << 24) /* Bit 24: PLL R clock output enable */
+#define RCC_PLLCFGR_PLLR_SHIFT (25) /* Bits 26-25: Main PLL division factor for PLL R clock (system clock) */
+#define RCC_PLLCFGR_PLLR_MASK (3 << RCC_PLLCFGR_PLLR_SHIFT)
+# define RCC_PLLCFGR_PLLR_2 (0x0 << RCC_PLLCFGR_PLLR_SHIFT)
+# define RCC_PLLCFGR_PLLR_4 (0x1 << RCC_PLLCFGR_PLLR_SHIFT)
+# define RCC_PLLCFGR_PLLR_6 (0x2 << RCC_PLLCFGR_PLLR_SHIFT)
+# define RCC_PLLCFGR_PLLR_8 (0x3 << RCC_PLLCFGR_PLLR_SHIFT)
+
+#define RCC_PLLCFGR_PLLPDIV_SHIFT (27) /* Bits 31-27: Main PLL division factor for PLL P clock */
+#define RCC_PLLCFGR_PLLPDIV_MASK (0x1f << RCC_PLLCFGR_PLLPDIV_SHIFT)
+#define RCC_PLLCFGR_PLLPDIV(n) (((n) << RCC_PLLCFGR_PLLPDIV_SHIFT) & RCC_PLLCFGR_PLLPDIV_MASK) /* n=2..31 */
+
+#define RCC_PLLCFGR_RESERVED_MASK 0x008c800c /* Bits 23, 19-18, 15, and 3-2 should be kept at reset value */
+#define RCC_PLLCFGR_RESET 0x00001000
+
+/* CIER - Clock Interrupt Enable Register */
+
Review comment:
Agreed, and I tried to do the same wherever possible. What isn't consistent with the manual here?
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r429340575
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
Review comment:
I went ahead and fixed operator spacing. All binary operators are surrounded by a single space per the coding standard.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426314665
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1129,15 +1129,80 @@ config ARCH_CHIP_STM32F469N
select STM32_STM32F469
select STM32_HAVE_ETHMAC
+config ARCH_CHIP_STM32G474C
Review comment:
> Also I don't think that we need a distinction between LQFP/UFQFPN and LQFP/BGA packages.
> This does'nt affect OS in any way
I removed distinction between LQFP/UFQFPN and LQFP/BGA packages in cc206e81b3b3d920c8031c025cbf6a368325febc.
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r427250928
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1129,15 +1129,80 @@ config ARCH_CHIP_STM32F469N
select STM32_STM32F469
select STM32_HAVE_ETHMAC
+config ARCH_CHIP_STM32G474C
Review comment:
Looks good.
But I'm not sure if we need additional options for STM32_STM32G474M, STM32_STM32G474R, etc.
Shouldn't we keep chip-specific options just under ARCH_CHIP_STM32G474M, ARCH_CHIP_STM32G474R, etc ?
Then leave only STM32_STM32G47XX as the common configuration for the G47XX familly.
There is currently no consistency regarding this in Kconfig
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426298204
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1129,15 +1129,80 @@ config ARCH_CHIP_STM32F469N
select STM32_STM32F469
select STM32_HAVE_ETHMAC
+config ARCH_CHIP_STM32G474C
Review comment:
If I do what you suggest, the second letter determines the flash size:
STM32G474x**E** = 512Kbyte
STM32G474x**C** = 256Kbyte
STM32G474x**B** = 128Kbyte
How do I handle that? Like this:
```suggestion
config ARCH_CHIP_STM32G474CB
bool "STM32G474CB"
select STM32_STM32G47XX
select STM32_STM32G474C
select STM32_FLASH_CONFIG_B
```
Note that STM32_FLASH_CONFIG_B is part of a 'choice' and I don't see any other chip doing it that way.
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-631652629
Woohoo! All checks have passed!
@davids5, @raiden00pl, please let me know if you're finished reviewing, or are continuing.
Meanwhile, I'm going to do one more build to verify it still works on hardware.
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[GitHub] [incubator-nuttx] acassis merged pull request #1051: Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
acassis merged pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r428720469
##########
File path: boards/arm/stm32/b-g474e-dpow1/src/Make.defs
##########
@@ -0,0 +1,38 @@
+############################################################################
+# boards/arm/stm32/b-g474e-dpow1/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
Review comment:
Good catch! Thank you reviewing and noticing that. I'll push a commit that fixes it soon...
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426288585
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
##########
@@ -0,0 +1,194 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* STM32G47xxx Address Blocks ***********************************************************************/
+
+#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM */
+ /* 0x70000000-0x7fffffff: Reserved */
+#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
+#define STM32_QSPI_BANK1 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
+
+#define STM32_FMC_QSPI_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 256Mb FMC and QUADSPI registers */
+ /* 0xc0000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
+
+#define STM32_REGION_MASK Warning Not Cleared! 0xf0000000
+#define STM32_IS_SRAM(a) Warning Not Cleared! ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
+
+/* Code Base Addresses ******************************************************************************/
+
+#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x0007ffff: Aliased boot memory */
+ /* 0x00080000-0x07ffffff: Reserved */
+#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x807ffff: Up to 512Kb FLASH memory */
+ /* 0x08080000-0xfffffff: Reserved */
+#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x10007fff: 32Kb CCM data SRAM */
+ /* 0x10008000-0x1ffeffff: Reserved */
+#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: 28Kb System memory */
+#define STM32_OTP_AREA_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: 1Kb OTP area */
+ /* 0x1fff7400-0x1fff77ff: Reserved */
+#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: 16 Option bytes */
+ /* 0x1fff7810-0x1fff7fff: Reserved */
+#define STM32_SYSMEM_BASE2 0x1fff8000 /* 0x1fff8000-0x1fffefff: 28Kb System memory */
+ /* 0x1ffff000-0x1ffff7ff: Reserved */
+#define STM32_OPTION_BASE2 0x1ffff800 /* 0x1ffff800-0x1ffff80f: 16 Option bytes */
+ /* 0x1fff7810-0x1fff7fff: Reserved */
+
+/* System Memory Addresses **************************************************************************/
+
+#define STM32_PACKAGE_INFO 0x1fff7500 /* Package data register */
+#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
+#define STM32_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of
+ * the device Flash memory expressed in
+ * Kbytes. Example: 0x040 corresponds
+ * to 64 Kbytes
+ */
+
+/* Peripheral Base Addresses ************************************************************************/
+
+#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */
+ /* 0x40009800-0x4000ffff: Reserved */
+#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */
+ /* 0x40016400-0x4001ffff: Reserved */
+#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
+ /* 0x40024400-0x47ffffff: Reserved */
+#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */
+ /* 0x50060c00-0x5fffffff: Reserved */
+
+/* APB1 Base Addresses ******************************************************************************/
+
Review comment:
Fixed in c293babe6827d9f9c45dd2781fdeb1d167d1a814.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426273007
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or Time Stamp (see STM32_IRQ_TIMESTAMP) */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
+#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
+#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
+#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
+#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
+#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
+#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
+#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt (see also STM32_IRQ_ADC2) */
Review comment:
Good catch! Fixed in db33458048443413ea95313d3959ace7fb6e5183. Thank you.
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[GitHub] [incubator-nuttx] davids5 commented on pull request #1051: Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
davids5 commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-633036063
@acassis - Do you have time to take a pass? If not please remove yourself and I will merge it.
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[GitHub] [incubator-nuttx] davids5 edited a comment on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
davids5 edited a comment on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-630289289
> When I finish making all the changes you requested, will it be easier for you if I squash the commits? Or leave them separate?
@hartmannathan - you can use [mv-changes](https://github.com/MikhailGolubtsov/git-mv-changes) to regroup by subject (i.e. pinmap, adc) or squash by file.
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[GitHub] [incubator-nuttx] davids5 commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
davids5 commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-631724739
@hartmannathan - I can look at it again this weekend.
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426276735
##########
File path: arch/arm/src/stm32/hardware/stm32_adc_v2.h
##########
@@ -86,18 +86,24 @@
/* Base addresses ***********************************************************************************/
-#define STM32_ADC1_OFFSET 0x0000
-#define STM32_ADC2_OFFSET 0x0100
-#define STM32_ADC3_OFFSET 0x0000
-#define STM32_ADC4_OFFSET 0x0100
-#define STM32_ADCCMN_OFFSET 0x0300
+/* G47x has the ADC base addresses are defined in stm32g47xxx_memorymap.h.
+ * Other P/Ns have ADC base addresses are defined here.
+ */
-#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */
-#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */
-#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */
-#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */
-#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */
-#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */
+#if !defined(CONFIG_STM32_STM32G47XX)
Review comment:
ADCx and ADCy offsets in the ADCxy memory region is an ADC IP block property, not a memory map property (and this approach matches the memory map table from the ST reference manual ;) )
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426276855
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
Review comment:
Yes, it is. I think it is not checking for operator spacing in defines.
I did it this way because looking at other code, it seems that's how it is being done elsewhere.
WDYT?
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426269714
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
##########
@@ -0,0 +1,194 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* STM32G47xxx Address Blocks ***********************************************************************/
+
+#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM */
+ /* 0x70000000-0x7fffffff: Reserved */
+#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
+#define STM32_QSPI_BANK1 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
+
+#define STM32_FMC_QSPI_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 256Mb FMC and QUADSPI registers */
+ /* 0xc0000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
+
+#define STM32_REGION_MASK Warning Not Cleared! 0xf0000000
Review comment:
Thank you!
Fixed in commit 8266c945d93cd0282dc7b8acbb0305f45933521e.
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
##########
@@ -0,0 +1,194 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* STM32G47xxx Address Blocks ***********************************************************************/
+
+#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM */
+ /* 0x70000000-0x7fffffff: Reserved */
+#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
+#define STM32_QSPI_BANK1 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
+
+#define STM32_FMC_QSPI_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 256Mb FMC and QUADSPI registers */
+ /* 0xc0000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
+
+#define STM32_REGION_MASK Warning Not Cleared! 0xf0000000
+#define STM32_IS_SRAM(a) Warning Not Cleared! ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
Review comment:
Thank you!
Fixed in commit 8266c945d93cd0282dc7b8acbb0305f45933521e.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426279611
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
##########
@@ -0,0 +1,194 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_MEMORYMAP_H
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* STM32G47xxx Address Blocks ***********************************************************************/
+
+#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM */
+ /* 0x70000000-0x7fffffff: Reserved */
+#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
+#define STM32_QSPI_BANK1 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
+
+#define STM32_FMC_QSPI_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 256Mb FMC and QUADSPI registers */
+ /* 0xc0000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
+
+#define STM32_REGION_MASK Warning Not Cleared! 0xf0000000
+#define STM32_IS_SRAM(a) Warning Not Cleared! ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
+
+/* Code Base Addresses ******************************************************************************/
+
+#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x0007ffff: Aliased boot memory */
+ /* 0x00080000-0x07ffffff: Reserved */
+#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x807ffff: Up to 512Kb FLASH memory */
+ /* 0x08080000-0xfffffff: Reserved */
+#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x10007fff: 32Kb CCM data SRAM */
+ /* 0x10008000-0x1ffeffff: Reserved */
+#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: 28Kb System memory */
+#define STM32_OTP_AREA_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: 1Kb OTP area */
+ /* 0x1fff7400-0x1fff77ff: Reserved */
+#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: 16 Option bytes */
+ /* 0x1fff7810-0x1fff7fff: Reserved */
+#define STM32_SYSMEM_BASE2 0x1fff8000 /* 0x1fff8000-0x1fffefff: 28Kb System memory */
+ /* 0x1ffff000-0x1ffff7ff: Reserved */
+#define STM32_OPTION_BASE2 0x1ffff800 /* 0x1ffff800-0x1ffff80f: 16 Option bytes */
+ /* 0x1fff7810-0x1fff7fff: Reserved */
+
+/* System Memory Addresses **************************************************************************/
+
+#define STM32_PACKAGE_INFO 0x1fff7500 /* Package data register */
+#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
+#define STM32_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of
+ * the device Flash memory expressed in
+ * Kbytes. Example: 0x040 corresponds
+ * to 64 Kbytes
+ */
+
+/* Peripheral Base Addresses ************************************************************************/
+
+#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */
+ /* 0x40009800-0x4000ffff: Reserved */
+#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */
+ /* 0x40016400-0x4001ffff: Reserved */
+#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
+ /* 0x40024400-0x47ffffff: Reserved */
+#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */
+ /* 0x50060c00-0x5fffffff: Reserved */
+
+/* APB1 Base Addresses ******************************************************************************/
+
Review comment:
Yup, I was planning to, but forgot...
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426128098
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or Time Stamp (see STM32_IRQ_TIMESTAMP) */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
+#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
+#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
+#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
+#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
+#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
+#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
+#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt (see also STM32_IRQ_ADC2) */
Review comment:
This should be called STM32_IRQ_ADC12. Otherwise, it will not work with the current ADC implementation.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426277177
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or Time Stamp (see STM32_IRQ_TIMESTAMP) */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
+#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
+#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
+#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
+#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
+#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
+#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
+#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt (see also STM32_IRQ_ADC2) */
+#define STM32_IRQ_USBHP (STM32_IRQ_FIRST+19) /* 19: USB High priority interrupt */
+
+#define STM32_IRQ_USBLP (STM32_IRQ_FIRST+20) /* 20: USB Low priority interrupt */
+#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST+21) /* 21: FDCAN1 interrupt 0 */
+#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST+22) /* 22: FDCAN1 interrupt 1 */
+#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt (see also STM32_IRQ_TIM1BRK) */
+#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt (see also STM32_IRQ_TIM1UP) */
+#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt (see also STM32_IRQ_TIM1TRGCOM) */
+#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+
+#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
+#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
+#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
+#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
+#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+
+#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST+42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */
+#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break, Transition error, Index error */
+#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
+#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */
+#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
+#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
+#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */
+#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST+49) /* 49: LPTIM1 interrupt */
+
+#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
+#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
+#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
+#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
+#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt (see also STM32_IRQ_DAC1, STM32_IRQ_DAC3) */
+#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt (see also STM32_IRQ_DAC2, STM32_IRQ_DAC4) */
+#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST+56) /* 56: DMA2 channel 1 global interrupt */
+#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST+57) /* 57: DMA2 channel 2 global interrupt */
+#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST+58) /* 58: DMA2 channel 3 global interrupt */
+#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST+59) /* 59: DMA2 channel 4 global interrupt */
+
+#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST+60) /* 60: DMA2 channel 5 global interrupt */
+#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST+61) /* 61: ADC4 global interrupt */
+#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST+62) /* 62: ADC5 global interrupt */
+#define STM32_IRQ_UCPD (STM32_IRQ_FIRST+63) /* 63: UCPD global interrupt */
+#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST+64) /* 64: COMP1, COMP2, and COMP3 interrupts */
+#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST+65) /* 65: COMP4, COMP5, and COMP6 interrupts */
+#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST+66) /* 66: COMPP7 interrupt */
+#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST+67) /* 67: HRTIM1 master timer interrupt */
+#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST+68) /* 68: HRTIM1 timer A interrupt */
+#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST+69) /* 69: HRTIM1 timer B interrupt */
+
+#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST+70) /* 70: HRTIM1 timer C interrupt */
+#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST+71) /* 71: HRTIM1 timer D interrupt */
+#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST+72) /* 72: HRTIM1 timer E interrupt */
+#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST+73) /* 73: HRTIM1 fault interrupt */
+#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST+74) /* 74: HRTIM1 timer E interrupt */
+#define STM32_IRQ_CRS (STM32_IRQ_FIRST+75) /* 75: CRS (Clock Recovery System) global interrupt */
+#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+76) /* 76: SAI4 global interrupt */
+#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST+77) /* 77: TIM20 Break, Transition error, Index error interrupt */
+#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST+78) /* 78: TIM20 Update interrupt */
+#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST+79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */
+
+#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST+80) /* 80: TIM20 Capture Compare interrupt */
+#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+82) /* 82: I2C4 event interrupt */
+#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+83) /* 83: I2C4 error interrupt */
+#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
+#define STM32_IRQ_AES (STM32_IRQ_FIRST+85) /* 85: AES global interrupt */
+#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST+86) /* 86: FDCAN2 interrupt 0 */
+#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST+87) /* 87: FDCAN2 interrupt 1 */
+#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST+88) /* 88: FDCAN3 interrupt 0 */
+#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST+89) /* 89: FDCAN3 interrupt 1 */
+
+#define STM32_IRQ_RNG (STM32_IRQ_FIRST+90) /* 90: RNG global interrupt */
+#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST+91) /* 91: LPUART1 */
Review comment:
Good catch! Fixed in d8f29f6263e4d22f0c3eb15547f14bae6f890eb2
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426815435
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_gpio.h
##########
@@ -0,0 +1,340 @@
+/****************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_GPIO_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_GPIO_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STM32_NGPIO_PORTS (7) /* GPIOA-G */
+
+/* Register Offsets *********************************************************/
+
+#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
+#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
+#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
+#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
+#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
+#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
+#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
+#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
+#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
+#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
+#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
+
+/* Register Addresses *******************************************************/
+
+#if (STM32_NGPIO_PORTS > 0)
+# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 1)
+# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 2)
+# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 3)
+# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 4)
+# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 5)
+# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+#if (STM32_NGPIO_PORTS > 6)
+# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET)
+# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET)
+# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET)
+# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET)
+# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET)
+# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET)
+# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET)
+# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ********************************************/
+
+/* GPIO port mode register */
+
+#define GPIO_MODER_INPUT (0x0) /* Input mode */
+#define GPIO_MODER_OUTPUT (0x1) /* General purpose output mode */
+#define GPIO_MODER_ALT (0x2) /* Alternate mode */
+#define GPIO_MODER_ANALOG (0x3) /* Analog mode (reset state) */
+
+#define GPIO_MODER_SHIFT(n) ((n) << 1)
+#define GPIO_MODER_MASK(n) (0x3 << GPIO_MODER_SHIFT(n))
+
Review comment:
Done in 637afd3d4c5762f81db49cfce9f6e1b2527bf3a5.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r427300138
##########
File path: arch/arm/src/stm32/hardware/stm32_dma_v1.h
##########
@@ -54,6 +54,10 @@
#define DMA1 (0)
#define DMA2 (1)
+#if defined(CONFIG_STM32_STM32G47XX)
+# define HAVE_DMA_CHAN8
+#endif
Review comment:
> This should come in from chip.h or Kconfig.
I think there should there be **two** defines from Kconfig: HAVE_DMA1_CHAN8 and HAVE_DMA2_CHAN678.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426282320
##########
File path: arch/arm/src/stm32/hardware/stm32_adc_v2.h
##########
@@ -86,18 +86,24 @@
/* Base addresses ***********************************************************************************/
-#define STM32_ADC1_OFFSET 0x0000
-#define STM32_ADC2_OFFSET 0x0100
-#define STM32_ADC3_OFFSET 0x0000
-#define STM32_ADC4_OFFSET 0x0100
-#define STM32_ADCCMN_OFFSET 0x0300
+/* G47x has the ADC base addresses are defined in stm32g47xxx_memorymap.h.
+ * Other P/Ns have ADC base addresses are defined here.
+ */
-#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */
-#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */
-#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */
-#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */
-#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */
-#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */
+#if !defined(CONFIG_STM32_STM32G47XX)
Review comment:
OK this makes sense now. I will move these defines.
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-632787760
> @hartmannathan - I can look at it again this weekend.
@davids5 - Thanks! Once you finish reviewing, assuming it looks good, feel free to remove the [DO NOT MERGE] from the title and do the honors!
I've confirmed that it still builds, flash-programs, and runs on the board, following all the cumulative changes made since I opened the PR. It's already rebased on latest master (as of this writing)...
Thanks for all your work so far!
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426276693
##########
File path: arch/arm/src/stm32/stm32_lowputc.c
##########
@@ -235,12 +235,18 @@
# endif
# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
- defined(CONFIG_STM32_STM32F37XX)
+ defined(CONFIG_STM32_STM32F37XX)
# define USART_CR1_CLRBITS\
(USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME | \
USART_CR1_OVER8 | USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | \
USART_CR1_ALLINTS)
+# elif defined(CONFIG_STM32_STM32G47XX)
Review comment:
Fixed in 0600f8a4ab7d04b75e3a40d00a0766d087d77dae.
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-632788301
> > I confirmed that the board boots and runs with all the cumulative changes since I opened this PR.
>
> Are there other boards this affects? Have you tested them as well?
I don't have those boards. Do you mean build testing? I can build test some boards that use other processors in this directory.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426273458
##########
File path: arch/arm/src/stm32/hardware/stm32_dma_v1.h
##########
@@ -64,6 +64,9 @@
#define DMA_CHAN5 (4)
#define DMA_CHAN6 (5)
#define DMA_CHAN7 (6)
+#if defined(CONFIG_STM32_STM32G47XX)
Review comment:
This is done in commit 710da07dea7a8ac40c00e1093cb697e63d05fb2a. Please see if that is satisfactory.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426285369
##########
File path: arch/arm/src/stm32/hardware/stm32_adc_v2.h
##########
@@ -86,18 +86,24 @@
/* Base addresses ***********************************************************************************/
-#define STM32_ADC1_OFFSET 0x0000
-#define STM32_ADC2_OFFSET 0x0100
-#define STM32_ADC3_OFFSET 0x0000
-#define STM32_ADC4_OFFSET 0x0100
-#define STM32_ADCCMN_OFFSET 0x0300
+/* G47x has the ADC base addresses are defined in stm32g47xxx_memorymap.h.
+ * Other P/Ns have ADC base addresses are defined here.
+ */
-#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */
-#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */
-#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */
-#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */
-#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */
-#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */
+#if !defined(CONFIG_STM32_STM32G47XX)
Review comment:
Done in 8c037c426a1d4c1e9130d710ec38ed69234c336c.
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-632892148
> > > > I confirmed that the board boots and runs with all the cumulative changes since I opened this PR.
> > >
> > >
> > > Are there other boards this affects? Have you tested them as well?
> >
> >
> > I don't have those boards. Do you mean build testing? I can build test some boards that use other processors in this directory.
>
> @davids5 , actually, I do have a nucleo-f302r8 board. The stm32 directory handles the f302r8 MCU. I'll go ahead and make sure that builds, boots, and runs...
I can confirm that the nucleo-f302r8:nsh configuration builds, flashes, and boots on the Nucleo F302R8 board.
Also, I have successfully built every "nsh" configuration under the boards/arm/stm32 directory. That is, I built these configurations and so I can confirm that my changes are not breaking these builds:
- axoloti:nsh
- b-g474e-dpow1:nsh
- clicker2-stm32:nsh
- cloudctrl:nsh
- fire-stm32v2:nsh
- hymini-stm32v:nsh
- maple:nsh
- mikroe-stm32f4:nsh
- nucleo-f103rb:nsh
- nucleo-f207zg:nsh
- nucleo-f302r8:nsh
- nucleo-f303re:nsh
- nucleo-f303ze:nsh
- nucleo-f334r8:nsh
- nucleo-f410rb:nsh
- nucleo-f429zi:nsh
- nucleo-f446re:nsh
- nucleo-l152re:nsh
- olimexino-stm32:nsh
- olimex-stm32-e407:nsh
- olimex-stm32-h407:nsh
- olimex-stm32-p107:nsh
- olimex-stm32-p207:nsh
- olimex-stm32-p407:nsh
- omnibusf4:nsh
- photon:nsh
- shenzhou:nsh
- stm3210e-eval:nsh
- stm3220g-eval:nsh
- stm3240g-eval:nsh
- stm32butterfly2:nsh
- stm32f103-minimum:nsh
- stm32f334-disco:nsh
- stm32f3discovery:nsh
- stm32f411e-disco:nsh
- stm32f429i-disco:nsh
- stm32f4discovery:nsh
- stm32ldiscovery:nsh
- stm32_tiny:nsh
- stm32vldiscovery:nsh
- viewtool-stm32f107:nsh
All of those configurations built successfully. There were no warnings pertaining to my changes.
This is the extent of testing that I can do on other boards/MCUs, because the only STM32 boards I have access to at this time are the B-G474E-DPOW1 Discovery and the Nucleo F302R8.
I was very careful when editing existing code and I'm confident that my changes are safe. Having said so, I encourage anyone and everyone who is interested in STM32 support to verify the code and to check that your boards and configurations continue to work with these changes applied. Our code quality is paramount.
@acassis you expressed interest in reviewing the code, do you still wish to look at it?
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r427375688
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1129,15 +1129,80 @@ config ARCH_CHIP_STM32F469N
select STM32_STM32F469
select STM32_HAVE_ETHMAC
+config ARCH_CHIP_STM32G474C
Review comment:
I don't have any strong opinion about it, so let's leave it as it is.
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426128709
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or Time Stamp (see STM32_IRQ_TIMESTAMP) */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
+#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
+#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
+#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
+#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
+#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
+#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
+#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt (see also STM32_IRQ_ADC2) */
+#define STM32_IRQ_USBHP (STM32_IRQ_FIRST+19) /* 19: USB High priority interrupt */
+
+#define STM32_IRQ_USBLP (STM32_IRQ_FIRST+20) /* 20: USB Low priority interrupt */
+#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST+21) /* 21: FDCAN1 interrupt 0 */
+#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST+22) /* 22: FDCAN1 interrupt 1 */
+#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt (see also STM32_IRQ_TIM1BRK) */
+#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt (see also STM32_IRQ_TIM1UP) */
+#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt (see also STM32_IRQ_TIM1TRGCOM) */
+#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+
+#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
+#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
+#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
+#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
+#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+
+#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST+42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */
+#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break, Transition error, Index error */
+#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
+#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */
+#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
+#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
+#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */
+#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST+49) /* 49: LPTIM1 interrupt */
+
+#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
+#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
+#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
+#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
+#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt (see also STM32_IRQ_DAC1, STM32_IRQ_DAC3) */
+#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt (see also STM32_IRQ_DAC2, STM32_IRQ_DAC4) */
+#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST+56) /* 56: DMA2 channel 1 global interrupt */
+#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST+57) /* 57: DMA2 channel 2 global interrupt */
+#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST+58) /* 58: DMA2 channel 3 global interrupt */
+#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST+59) /* 59: DMA2 channel 4 global interrupt */
+
+#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST+60) /* 60: DMA2 channel 5 global interrupt */
+#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST+61) /* 61: ADC4 global interrupt */
+#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST+62) /* 62: ADC5 global interrupt */
+#define STM32_IRQ_UCPD (STM32_IRQ_FIRST+63) /* 63: UCPD global interrupt */
+#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST+64) /* 64: COMP1, COMP2, and COMP3 interrupts */
+#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST+65) /* 65: COMP4, COMP5, and COMP6 interrupts */
+#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST+66) /* 66: COMPP7 interrupt */
+#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST+67) /* 67: HRTIM1 master timer interrupt */
+#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST+68) /* 68: HRTIM1 timer A interrupt */
+#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST+69) /* 69: HRTIM1 timer B interrupt */
+
+#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST+70) /* 70: HRTIM1 timer C interrupt */
+#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST+71) /* 71: HRTIM1 timer D interrupt */
+#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST+72) /* 72: HRTIM1 timer E interrupt */
+#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST+73) /* 73: HRTIM1 fault interrupt */
+#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST+74) /* 74: HRTIM1 timer E interrupt */
+#define STM32_IRQ_CRS (STM32_IRQ_FIRST+75) /* 75: CRS (Clock Recovery System) global interrupt */
+#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+76) /* 76: SAI4 global interrupt */
+#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST+77) /* 77: TIM20 Break, Transition error, Index error interrupt */
+#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST+78) /* 78: TIM20 Update interrupt */
+#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST+79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */
+
+#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST+80) /* 80: TIM20 Capture Compare interrupt */
+#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+82) /* 82: I2C4 event interrupt */
+#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+83) /* 83: I2C4 error interrupt */
+#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
+#define STM32_IRQ_AES (STM32_IRQ_FIRST+85) /* 85: AES global interrupt */
+#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST+86) /* 86: FDCAN2 interrupt 0 */
+#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST+87) /* 87: FDCAN2 interrupt 1 */
+#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST+88) /* 88: FDCAN3 interrupt 0 */
+#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST+89) /* 89: FDCAN3 interrupt 1 */
+
+#define STM32_IRQ_RNG (STM32_IRQ_FIRST+90) /* 90: RNG global interrupt */
+#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST+91) /* 91: LPUART1 */
+#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+92) /* 92: I2C3 event interrupt */
+#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+93) /* 93: I2C3 error interrupt */
+#define STM32_IRQ_DMAMUXOV (STM32_IRQ_FIRST+94) /* 94: DMAMUX overrun interrupt */
+#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+95) /* 95: QuadSPI global interrupt */
+#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST+96) /* 96: DMA1 channel 8 global interrupt */
+#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST+97) /* 97: DMA2 channel 6 global interrupt */
+#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST+98) /* 98: DMA2 channel 7 global interrupt */
+#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST+99) /* 99: DMA2 channel 8 global interrupt */
+
+#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST+100) /* 100: CORDIC trigonometric accelerator interrupt */
+#define STM32_IRQ_FMAC (STM32_IRQ_FIRST+101) /* 101: FMAC filter math acclerator interrupt */
+
+#define STM32_IRQ_NEXTINT (102)
+#define NR_IRQS (STM32_IRQ_FIRST+102)
+
+/* Interrupt vectors that are shared with numbers defined above: */
Review comment:
I think we should organize the file like other STM32 chips. So if we have a IRQ number shared between peripherals, we put the definitions one by one.
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426132456
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1129,15 +1129,80 @@ config ARCH_CHIP_STM32F469N
select STM32_STM32F469
select STM32_HAVE_ETHMAC
+config ARCH_CHIP_STM32G474C
Review comment:
It seems to me that this is not correct. You should use chip names from [here](https://www.st.com/content/ccc/fragment/product_related/line_information/line_level_diagram/group0/cc/a2/82/c1/1b/2a/45/35/stm32g4x4_line_ln2130/files/stm32g4x4_line_ln2130.jpg/_jcr_content/translations/en.stm32g4x4_line_ln2130.jpg) (eg. STM32G474**CE**, STM32G474**CC** ... not STM32G474**C**)
Each chip version should be a single entry in the "STM32 Chip Selection" choice menu.
Also I don't think that we need a distinction between LQFP/UFQFPN and LQFP/BGA packages.
This does'nt affect OS in any way
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426314348
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
##########
@@ -0,0 +1,2627 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "stm32_gpio.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Alternate Pin Functions. All members of the STM32G47xxx family share the
+ * same pin multiplexing (although they differ in the pins physically
+ * available).
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if CAN1_RX connects via PA11 on some board, then the following
+ * definitions should appear in the board.h header file for that board:
+ *
+ * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
+ *
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
+ */
+
+/* ADC - Analog Digital Converter *******************************************************************/
+
+/* ADC1 has IN1-IN5, IN10-IN12, IN14-IN15 on all STM32G474(C-M-Q-R-V)xxx P/Ns
+ * and also has IN6-9 on STM32G474(M-Q-R-V)xxx P/Ns:
+ */
+
+#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN0)
+#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
Review comment:
I went ahead and made this change in cc206e81b3b3d920c8031c025cbf6a368325febc. The pinmap is much simplified.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r429343835
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or Time Stamp (see STM32_IRQ_TIMESTAMP) */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
+#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
+#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
+#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
+#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
+#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
+#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
+#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt (see also STM32_IRQ_ADC2) */
+#define STM32_IRQ_USBHP (STM32_IRQ_FIRST+19) /* 19: USB High priority interrupt */
+
+#define STM32_IRQ_USBLP (STM32_IRQ_FIRST+20) /* 20: USB Low priority interrupt */
+#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST+21) /* 21: FDCAN1 interrupt 0 */
+#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST+22) /* 22: FDCAN1 interrupt 1 */
+#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt (see also STM32_IRQ_TIM1BRK) */
+#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt (see also STM32_IRQ_TIM1UP) */
+#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt (see also STM32_IRQ_TIM1TRGCOM) */
+#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+
+#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
+#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
+#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
+#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
+#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+
+#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST+42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */
+#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break, Transition error, Index error */
+#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
+#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */
+#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
+#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
+#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */
+#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST+49) /* 49: LPTIM1 interrupt */
+
+#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
+#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
+#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
+#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
+#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt (see also STM32_IRQ_DAC1, STM32_IRQ_DAC3) */
+#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt (see also STM32_IRQ_DAC2, STM32_IRQ_DAC4) */
+#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST+56) /* 56: DMA2 channel 1 global interrupt */
+#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST+57) /* 57: DMA2 channel 2 global interrupt */
+#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST+58) /* 58: DMA2 channel 3 global interrupt */
+#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST+59) /* 59: DMA2 channel 4 global interrupt */
+
+#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST+60) /* 60: DMA2 channel 5 global interrupt */
+#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST+61) /* 61: ADC4 global interrupt */
+#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST+62) /* 62: ADC5 global interrupt */
+#define STM32_IRQ_UCPD (STM32_IRQ_FIRST+63) /* 63: UCPD global interrupt */
+#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST+64) /* 64: COMP1, COMP2, and COMP3 interrupts */
+#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST+65) /* 65: COMP4, COMP5, and COMP6 interrupts */
+#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST+66) /* 66: COMPP7 interrupt */
+#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST+67) /* 67: HRTIM1 master timer interrupt */
+#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST+68) /* 68: HRTIM1 timer A interrupt */
+#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST+69) /* 69: HRTIM1 timer B interrupt */
+
+#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST+70) /* 70: HRTIM1 timer C interrupt */
+#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST+71) /* 71: HRTIM1 timer D interrupt */
+#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST+72) /* 72: HRTIM1 timer E interrupt */
+#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST+73) /* 73: HRTIM1 fault interrupt */
+#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST+74) /* 74: HRTIM1 timer E interrupt */
+#define STM32_IRQ_CRS (STM32_IRQ_FIRST+75) /* 75: CRS (Clock Recovery System) global interrupt */
+#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+76) /* 76: SAI4 global interrupt */
+#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST+77) /* 77: TIM20 Break, Transition error, Index error interrupt */
+#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST+78) /* 78: TIM20 Update interrupt */
+#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST+79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */
+
+#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST+80) /* 80: TIM20 Capture Compare interrupt */
+#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+82) /* 82: I2C4 event interrupt */
+#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+83) /* 83: I2C4 error interrupt */
+#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
+#define STM32_IRQ_AES (STM32_IRQ_FIRST+85) /* 85: AES global interrupt */
+#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST+86) /* 86: FDCAN2 interrupt 0 */
+#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST+87) /* 87: FDCAN2 interrupt 1 */
+#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST+88) /* 88: FDCAN3 interrupt 0 */
+#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST+89) /* 89: FDCAN3 interrupt 1 */
+
+#define STM32_IRQ_RNG (STM32_IRQ_FIRST+90) /* 90: RNG global interrupt */
+#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST+91) /* 91: LPUART1 */
Review comment:
> @hartmannathan - I can look at it again this weekend.
@davids5 - Thanks! Once you finish reviewing, assuming it looks good, feel free to remove the [DO NOT MERGE] from the title and do the honors!
I've confirmed that it still builds, flash-programs, and runs on the board, following all the cumulative changes made since I opened the PR. It's already rebased on latest master (as of this writing)...
Thanks for all your work so far!
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r427378186
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1129,15 +1129,80 @@ config ARCH_CHIP_STM32F469N
select STM32_STM32F469
select STM32_HAVE_ETHMAC
+config ARCH_CHIP_STM32G474C
Review comment:
OK
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426265533
##########
File path: arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
##########
@@ -0,0 +1,2627 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32g47xxx_pinmap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G47XXX_PINMAP_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "stm32_gpio.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Alternate Pin Functions. All members of the STM32G47xxx family share the
+ * same pin multiplexing (although they differ in the pins physically
+ * available).
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if CAN1_RX connects via PA11 on some board, then the following
+ * definitions should appear in the board.h header file for that board:
+ *
+ * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
+ *
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
+ */
+
+/* ADC - Analog Digital Converter *******************************************************************/
+
+/* ADC1 has IN1-IN5, IN10-IN12, IN14-IN15 on all STM32G474(C-M-Q-R-V)xxx P/Ns
+ * and also has IN6-9 on STM32G474(M-Q-R-V)xxx P/Ns:
+ */
+
+#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN0)
+#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+
+#if defined(CONFIG_ARCH_CHIP_STM32G474M) || \
Review comment:
@davids5, let's make sure I understand your suggestion:
We would have several files:
- stm32g47mxx_pinmap.h
- stm32g47cxx_pinmap.h
- etc.
Each of those files is a complete pinmap for that variant.
Then, stm32g47xxx_pinmap.h would choose which one to include.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r427303457
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1129,15 +1129,80 @@ config ARCH_CHIP_STM32F469N
select STM32_STM32F469
select STM32_HAVE_ETHMAC
+config ARCH_CHIP_STM32G474C
Review comment:
> Looks good.
> But I'm not sure if we need additional options for STM32_STM32G474M, STM32_STM32G474R, etc.
> Shouldn't we keep chip-specific options just under ARCH_CHIP_STM32G474M, ARCH_CHIP_STM32G474R, etc ?
> Then leave only STM32_STM32G47XX as the common configuration for the G47XX familly.
> There is currently no consistency regarding this in Kconfig
Yes, Kconfig is inconsistent. I tried to follow what most other chips were doing.
What would your preference be?
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426268361
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -1129,15 +1129,80 @@ config ARCH_CHIP_STM32F469N
select STM32_STM32F469
select STM32_HAVE_ETHMAC
+config ARCH_CHIP_STM32G474C
Review comment:
I'm working on this change...
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426275766
##########
File path: arch/arm/src/stm32/stm32_dma_v1.c
##########
@@ -106,80 +114,132 @@ struct stm32_dma_s
static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
{
+#if DMA1_NCHANNELS > 0
{
.chan = 0,
.irq = STM32_IRQ_DMA1CH1,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
},
+#if DMA1_NCHANNELS > 1
{
.chan = 1,
.irq = STM32_IRQ_DMA1CH2,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
},
+#if DMA1_NCHANNELS > 2
{
.chan = 2,
.irq = STM32_IRQ_DMA1CH3,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
},
+#if DMA1_NCHANNELS > 3
{
.chan = 3,
.irq = STM32_IRQ_DMA1CH4,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
},
+#if DMA1_NCHANNELS > 4
{
.chan = 4,
.irq = STM32_IRQ_DMA1CH5,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
},
+#if DMA1_NCHANNELS > 5
{
.chan = 5,
.irq = STM32_IRQ_DMA1CH6,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
},
+#if DMA1_NCHANNELS > 6
{
.chan = 6,
.irq = STM32_IRQ_DMA1CH7,
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
},
+#if DMA1_NCHANNELS > 7
+ {
+ .chan = 7,
+ .irq = STM32_IRQ_DMA1CH8,
+ .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7),
+ },
+#endif /* DMA1_NCHANNELS > 7 */
Review comment:
Fixed in 71070d32dacc8c39f104f3f9faa71280704c0d51.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426282164
##########
File path: arch/arm/src/stm32/Kconfig
##########
@@ -2577,7 +2863,7 @@ config STM32_SPI6
config STM32_SYSCFG
bool "SYSCFG"
default y
- depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F33XX || STM32_STM32F37XX || STM32_STM32F20XX || STM32_STM32F4XXX || STM32_CONNECTIVITYLINE
+ depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F33XX || STM32_STM32F37XX || STM32_STM32F20XX || STM32_STM32F4XXX || STM32_STM32G47XX || STM32_CONNECTIVITYLINE
Review comment:
Should this be a separate PR after we complete this one? I think we should not pull in too many unrelated changes in one huge commit.
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426270135
##########
File path: arch/arm/src/stm32/hardware/stm32_adc_v2.h
##########
@@ -86,18 +86,24 @@
/* Base addresses ***********************************************************************************/
-#define STM32_ADC1_OFFSET 0x0000
-#define STM32_ADC2_OFFSET 0x0100
-#define STM32_ADC3_OFFSET 0x0000
-#define STM32_ADC4_OFFSET 0x0100
-#define STM32_ADCCMN_OFFSET 0x0300
+/* G47x has the ADC base addresses are defined in stm32g47xxx_memorymap.h.
+ * Other P/Ns have ADC base addresses are defined here.
+ */
-#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */
-#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */
-#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */
-#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */
-#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */
-#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */
+#if !defined(CONFIG_STM32_STM32G47XX)
Review comment:
If you look at the memory map in reference manual, you'll see that the ADCs are grouped into blocks. We have only two independent ADC blocks: ADC12 and ADC345. This means that ADC1 and ADC2 (or ADC3, ADC4 and ADC5) are not separate units that can be controlled independently, but they are closely related. So basically there is no peripherals such as ADC1 or ADC2, but it is ADC12 and this should be reflected in the memory map.
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[GitHub] [incubator-nuttx] davids5 commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
davids5 commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-629339145
@hartmannathan - I will need the weekend to give this mind share.
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[GitHub] [incubator-nuttx] davids5 commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
davids5 commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-632783586
> I confirmed that the board boots and runs with all the cumulative changes since I opened this PR.
Are there other boards this affects? Have you tested them as well?
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-629340041
> @hartmannathan - I will need the weekend to give this mind share.
Thanks! Take your time...
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r426287216
##########
File path: arch/arm/include/stm32/stm32g47xxx_irq.h
##########
@@ -0,0 +1,204 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32g47xxx_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32G47XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence
+ * map directly to bits in the NVIC. This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15) are common to all STM32 parts are are
+ * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here.
+ *
+ * Other interrupts (vectors >= 16) are defined below.
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or Time Stamp (see STM32_IRQ_TIMESTAMP) */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
+#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
+#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
+#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
+#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
+#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
+#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
+#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt (see also STM32_IRQ_ADC2) */
+#define STM32_IRQ_USBHP (STM32_IRQ_FIRST+19) /* 19: USB High priority interrupt */
+
+#define STM32_IRQ_USBLP (STM32_IRQ_FIRST+20) /* 20: USB Low priority interrupt */
+#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST+21) /* 21: FDCAN1 interrupt 0 */
+#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST+22) /* 22: FDCAN1 interrupt 1 */
+#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt (see also STM32_IRQ_TIM1BRK) */
+#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt (see also STM32_IRQ_TIM1UP) */
+#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt (see also STM32_IRQ_TIM1TRGCOM) */
+#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+
+#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
+#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
+#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
+#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
+#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+
+#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST+42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */
+#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break, Transition error, Index error */
+#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
+#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */
+#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
+#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
+#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */
+#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST+49) /* 49: LPTIM1 interrupt */
+
+#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
+#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
+#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
+#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
+#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt (see also STM32_IRQ_DAC1, STM32_IRQ_DAC3) */
+#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt (see also STM32_IRQ_DAC2, STM32_IRQ_DAC4) */
+#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST+56) /* 56: DMA2 channel 1 global interrupt */
+#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST+57) /* 57: DMA2 channel 2 global interrupt */
+#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST+58) /* 58: DMA2 channel 3 global interrupt */
+#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST+59) /* 59: DMA2 channel 4 global interrupt */
+
+#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST+60) /* 60: DMA2 channel 5 global interrupt */
+#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST+61) /* 61: ADC4 global interrupt */
+#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST+62) /* 62: ADC5 global interrupt */
+#define STM32_IRQ_UCPD (STM32_IRQ_FIRST+63) /* 63: UCPD global interrupt */
+#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST+64) /* 64: COMP1, COMP2, and COMP3 interrupts */
+#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST+65) /* 65: COMP4, COMP5, and COMP6 interrupts */
+#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST+66) /* 66: COMPP7 interrupt */
+#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST+67) /* 67: HRTIM1 master timer interrupt */
+#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST+68) /* 68: HRTIM1 timer A interrupt */
+#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST+69) /* 69: HRTIM1 timer B interrupt */
+
+#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST+70) /* 70: HRTIM1 timer C interrupt */
+#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST+71) /* 71: HRTIM1 timer D interrupt */
+#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST+72) /* 72: HRTIM1 timer E interrupt */
+#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST+73) /* 73: HRTIM1 fault interrupt */
+#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST+74) /* 74: HRTIM1 timer E interrupt */
+#define STM32_IRQ_CRS (STM32_IRQ_FIRST+75) /* 75: CRS (Clock Recovery System) global interrupt */
+#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+76) /* 76: SAI4 global interrupt */
+#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST+77) /* 77: TIM20 Break, Transition error, Index error interrupt */
+#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST+78) /* 78: TIM20 Update interrupt */
+#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST+79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */
+
+#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST+80) /* 80: TIM20 Capture Compare interrupt */
+#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+82) /* 82: I2C4 event interrupt */
+#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+83) /* 83: I2C4 error interrupt */
+#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
+#define STM32_IRQ_AES (STM32_IRQ_FIRST+85) /* 85: AES global interrupt */
+#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST+86) /* 86: FDCAN2 interrupt 0 */
+#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST+87) /* 87: FDCAN2 interrupt 1 */
+#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST+88) /* 88: FDCAN3 interrupt 0 */
+#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST+89) /* 89: FDCAN3 interrupt 1 */
+
+#define STM32_IRQ_RNG (STM32_IRQ_FIRST+90) /* 90: RNG global interrupt */
+#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST+91) /* 91: LPUART1 */
+#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+92) /* 92: I2C3 event interrupt */
+#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+93) /* 93: I2C3 error interrupt */
+#define STM32_IRQ_DMAMUXOV (STM32_IRQ_FIRST+94) /* 94: DMAMUX overrun interrupt */
+#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+95) /* 95: QuadSPI global interrupt */
+#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST+96) /* 96: DMA1 channel 8 global interrupt */
+#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST+97) /* 97: DMA2 channel 6 global interrupt */
+#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST+98) /* 98: DMA2 channel 7 global interrupt */
+#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST+99) /* 99: DMA2 channel 8 global interrupt */
+
+#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST+100) /* 100: CORDIC trigonometric accelerator interrupt */
+#define STM32_IRQ_FMAC (STM32_IRQ_FIRST+101) /* 101: FMAC filter math acclerator interrupt */
+
+#define STM32_IRQ_NEXTINT (102)
+#define NR_IRQS (STM32_IRQ_FIRST+102)
+
+/* Interrupt vectors that are shared with numbers defined above: */
Review comment:
Done in fade67cca2d31a39ad8e746da83b5c65e57e1add.
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#issuecomment-630293084
> > When I finish making all the changes you requested, will it be easier for you if I squash the commits? Or leave them separate?
>
> @hartmannathan - you can use [mv-changes](https://github.com/MikhailGolubtsov/git-mv-changes) to regroup by subject (i.e. pinmap, adc) or squash by file.
@davids5 -- ok... I'll wait until you and @raiden00pl tell me that you're ready, because rearranging commits will make it harder to see which change is related to which comment above...
Meanwhile I found and fixed some other issues, like filling in the missing ADC EXTSEL/JEXTSEL defines.
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[GitHub] [incubator-nuttx] hartmannathan commented on a change in pull request #1051: [DO NOT MERGE] Add support for STM32G474 family
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on a change in pull request #1051:
URL: https://github.com/apache/incubator-nuttx/pull/1051#discussion_r427385366
##########
File path: arch/arm/src/stm32/hardware/stm32_dma_v1.h
##########
@@ -54,6 +54,10 @@
#define DMA1 (0)
#define DMA2 (1)
+#if defined(CONFIG_STM32_STM32G47XX)
+# define HAVE_DMA_CHAN8
+#endif
Review comment:
Done in b5910332e199ae2d9aeabbe1e1341198f43f7b9c.
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