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Posted to commits@mynewt.apache.org by ma...@apache.org on 2017/04/13 18:11:15 UTC
[1/7] incubator-mynewt-core git commit: improved context switches for
MIPS and PIC32
Repository: incubator-mynewt-core
Updated Branches:
refs/heads/master c527b867a -> 119818800
improved context switches for MIPS and PIC32
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/039dd455
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/039dd455
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/039dd455
Branch: refs/heads/master
Commit: 039dd455326ef76a02f3fa9fa985c2e246a750e8
Parents: c527b86
Author: julian <ju...@imgtec.com>
Authored: Thu Apr 13 15:28:31 2017 +0100
Committer: julian <ju...@imgtec.com>
Committed: Thu Apr 13 15:29:39 2017 +0100
----------------------------------------------------------------------
hw/bsp/pic32mx470_6LP_clicker/bsp.yml | 2 +-
hw/bsp/pic32mz2048_wi-fire/bsp.yml | 2 +-
hw/bsp/pic32mz2048_wi-fire/syscfg.yml | 2 +-
.../pic32mx470F512H/include/mcu/pic32.h | 25 +++
.../pic32mx470F512H/include/mcu/pic32mx470.h | 25 ---
.../pic32mz2048efg100/include/mcu/pic32.h | 25 +++
.../pic32mz2048efg100/include/mcu/pic32mz2048.h | 25 ---
kernel/os/include/os/arch/pic32/os/os_arch.h | 83 +++++++
kernel/os/include/os/arch/pic32mx/os/os_arch.h | 84 -------
kernel/os/include/os/arch/pic32mz/os/os_arch.h | 84 -------
kernel/os/src/arch/mips/asm/ctx.S | 16 +-
kernel/os/src/arch/mips/os_arch_mips.c | 2 +-
kernel/os/src/arch/pic32/asm/ctx.S | 189 ++++++++++++++++
kernel/os/src/arch/pic32/os_arch_pic32.c | 221 +++++++++++++++++++
kernel/os/src/arch/pic32/os_fault.c | 122 ++++++++++
kernel/os/src/arch/pic32mx/asm/ctx.S | 163 --------------
kernel/os/src/arch/pic32mx/os_arch_pic32mx.c | 213 ------------------
kernel/os/src/arch/pic32mx/os_fault.c | 122 ----------
kernel/os/src/arch/pic32mz/asm/ctx.S | 163 --------------
kernel/os/src/arch/pic32mz/os_arch_pic32mz.c | 213 ------------------
kernel/os/src/arch/pic32mz/os_fault.c | 122 ----------
21 files changed, 681 insertions(+), 1222 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/hw/bsp/pic32mx470_6LP_clicker/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/bsp.yml b/hw/bsp/pic32mx470_6LP_clicker/bsp.yml
index a898cd0..c1d3d4c 100644
--- a/hw/bsp/pic32mx470_6LP_clicker/bsp.yml
+++ b/hw/bsp/pic32mx470_6LP_clicker/bsp.yml
@@ -17,7 +17,7 @@
# under the License.
#
-bsp.arch: pic32mx
+bsp.arch: pic32
bsp.compiler: compiler/xc32
bsp.flash_map:
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/hw/bsp/pic32mz2048_wi-fire/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mz2048_wi-fire/bsp.yml b/hw/bsp/pic32mz2048_wi-fire/bsp.yml
index 742b89d..c1d3d4c 100644
--- a/hw/bsp/pic32mz2048_wi-fire/bsp.yml
+++ b/hw/bsp/pic32mz2048_wi-fire/bsp.yml
@@ -17,7 +17,7 @@
# under the License.
#
-bsp.arch: pic32mz
+bsp.arch: pic32
bsp.compiler: compiler/xc32
bsp.flash_map:
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/hw/bsp/pic32mz2048_wi-fire/syscfg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mz2048_wi-fire/syscfg.yml b/hw/bsp/pic32mz2048_wi-fire/syscfg.yml
index 5c082e4..107b808 100644
--- a/hw/bsp/pic32mz2048_wi-fire/syscfg.yml
+++ b/hw/bsp/pic32mz2048_wi-fire/syscfg.yml
@@ -17,7 +17,7 @@
# under the License.
#
-# Package: hw/bsp/pic32mx470_6LP_clicker
+# Package: hw/bsp/pic32mx2048_wi-fire
syscfg.defs:
CLOCK_FREQ:
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32.h b/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32.h
new file mode 100644
index 0000000..6dccd82
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32.h
@@ -0,0 +1,25 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_PIC32_H__
+#define __MCU_PIC32_H__
+
+#define OS_TICKS_PER_SEC (1000)
+
+#endif /* __MCU_PIC32_H__ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32mx470.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32mx470.h b/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32mx470.h
deleted file mode 100644
index 6dccd82..0000000
--- a/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32mx470.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#ifndef __MCU_PIC32_H__
-#define __MCU_PIC32_H__
-
-#define OS_TICKS_PER_SEC (1000)
-
-#endif /* __MCU_PIC32_H__ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32.h b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32.h
new file mode 100644
index 0000000..6dccd82
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32.h
@@ -0,0 +1,25 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_PIC32_H__
+#define __MCU_PIC32_H__
+
+#define OS_TICKS_PER_SEC (1000)
+
+#endif /* __MCU_PIC32_H__ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32mz2048.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32mz2048.h b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32mz2048.h
deleted file mode 100644
index 6dccd82..0000000
--- a/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32mz2048.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#ifndef __MCU_PIC32_H__
-#define __MCU_PIC32_H__
-
-#define OS_TICKS_PER_SEC (1000)
-
-#endif /* __MCU_PIC32_H__ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/include/os/arch/pic32/os/os_arch.h
----------------------------------------------------------------------
diff --git a/kernel/os/include/os/arch/pic32/os/os_arch.h b/kernel/os/include/os/arch/pic32/os/os_arch.h
new file mode 100644
index 0000000..6bc20b2
--- /dev/null
+++ b/kernel/os/include/os/arch/pic32/os/os_arch.h
@@ -0,0 +1,83 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _OS_ARCH_H
+#define _OS_ARCH_H
+
+#include <stdint.h>
+#include <xc.h>
+
+#include "mcu/pic32.h"
+
+struct os_task;
+
+/* Run in priviliged or unprivileged Thread mode */
+/* only priv currently supported */
+#define OS_RUN_PRIV (0)
+#define OS_RUN_UNPRIV (1)
+
+/* CPU status register */
+typedef uint32_t os_sr_t;
+/* Stack type, aligned to a 32-bit word. */
+#define OS_STACK_PATTERN (0xdeadbeef)
+
+typedef uint32_t os_stack_t;
+#define OS_ALIGNMENT (4)
+#define OS_STACK_ALIGNMENT (8)
+
+#define OS_SR_IPL_BITS (0xE0)
+
+/*
+ * Stack sizes for common OS tasks
+ */
+#define OS_SANITY_STACK_SIZE (64)
+#define OS_IDLE_STACK_SIZE (64)
+
+#define OS_STACK_ALIGN(__nmemb) \
+ (OS_ALIGN((__nmemb), OS_STACK_ALIGNMENT))
+
+/* Enter a critical section, save processor state, and block interrupts */
+#define OS_ENTER_CRITICAL(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
+ __builtin_disable_interrupts();} while(0)
+
+/* Exit a critical section, restore processor state and unblock interrupts */
+#define OS_EXIT_CRITICAL(__os_sr) __builtin_set_isr_state(__os_sr)
+/* This is not the only way interrupts can be disabled */
+#define OS_IS_CRITICAL() ((__builtin_get_isr_state() & 1) == 0)
+#define OS_ASSERT_CRITICAL() assert(OS_IS_CRITICAL())
+
+os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int);
+void timer_handler(void);
+void os_arch_ctx_sw(struct os_task *);
+os_sr_t os_arch_save_sr(void);
+void os_arch_restore_sr(os_sr_t);
+int os_arch_in_critical(void);
+void os_arch_init(void);
+uint32_t os_arch_start(void);
+os_error_t os_arch_os_init(void);
+os_error_t os_arch_os_start(void);
+void os_set_env(os_stack_t *);
+void os_arch_init_task_stack(os_stack_t *sf);
+void os_default_irq_asm(void);
+
+/* External function prototypes supplied by BSP */
+void os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio);
+void os_bsp_ctx_sw(void);
+
+#endif /* _OS_ARCH_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/include/os/arch/pic32mx/os/os_arch.h
----------------------------------------------------------------------
diff --git a/kernel/os/include/os/arch/pic32mx/os/os_arch.h b/kernel/os/include/os/arch/pic32mx/os/os_arch.h
deleted file mode 100644
index 5cd30ff..0000000
--- a/kernel/os/include/os/arch/pic32mx/os/os_arch.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#ifndef _OS_ARCH_PIC32MX_H
-#define _OS_ARCH_PIC32MX_H
-
-#include <stdint.h>
-#include <xc.h>
-
-// is this req'd? It seems a little odd to include up the tree
-#include "mcu/pic32mx470.h"
-
-struct os_task;
-
-/* Run in priviliged or unprivileged Thread mode */
-/* only priv currently supported */
-#define OS_RUN_PRIV (0)
-#define OS_RUN_UNPRIV (1)
-
-/* CPU status register */
-typedef uint32_t os_sr_t;
-/* Stack type, aligned to a 32-bit word. */
-#define OS_STACK_PATTERN (0xdeadbeef)
-
-typedef uint32_t os_stack_t;
-#define OS_ALIGNMENT (4)
-#define OS_STACK_ALIGNMENT (8)
-
-#define OS_SR_IPL_BITS (0xE0)
-
-/*
- * Stack sizes for common OS tasks
- */
-#define OS_SANITY_STACK_SIZE (64)
-#define OS_IDLE_STACK_SIZE (64)
-
-#define OS_STACK_ALIGN(__nmemb) \
- (OS_ALIGN((__nmemb), OS_STACK_ALIGNMENT))
-
-/* Enter a critical section, save processor state, and block interrupts */
-#define OS_ENTER_CRITICAL(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
- __builtin_disable_interrupts();} while(0)
-
-/* Exit a critical section, restore processor state and unblock interrupts */
-#define OS_EXIT_CRITICAL(__os_sr) __builtin_set_isr_state(__os_sr)
-/* This is not the only way interrupts can be disabled */
-#define OS_IS_CRITICAL() ((__builtin_get_isr_state() & 1) == 0)
-#define OS_ASSERT_CRITICAL() assert(OS_IS_CRITICAL())
-
-os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int);
-void timer_handler(void);
-void os_arch_ctx_sw(struct os_task *);
-os_sr_t os_arch_save_sr(void);
-void os_arch_restore_sr(os_sr_t);
-int os_arch_in_critical(void);
-void os_arch_init(void);
-uint32_t os_arch_start(void);
-os_error_t os_arch_os_init(void);
-os_error_t os_arch_os_start(void);
-void os_set_env(os_stack_t *);
-void os_arch_init_task_stack(os_stack_t *sf);
-void os_default_irq_asm(void);
-
-/* External function prototypes supplied by BSP */
-void os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio);
-void os_bsp_ctx_sw(void);
-
-#endif /* _OS_ARCH_PIC32MX_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/include/os/arch/pic32mz/os/os_arch.h
----------------------------------------------------------------------
diff --git a/kernel/os/include/os/arch/pic32mz/os/os_arch.h b/kernel/os/include/os/arch/pic32mz/os/os_arch.h
deleted file mode 100644
index bf3017f..0000000
--- a/kernel/os/include/os/arch/pic32mz/os/os_arch.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#ifndef _OS_ARCH_PIC32MZ_H
-#define _OS_ARCH_PIC32MZ_H
-
-#include <stdint.h>
-#include <xc.h>
-
-// is this req'd? It seems a little odd to include up the tree
-#include "mcu/pic32mz2048.h"
-
-struct os_task;
-
-/* Run in priviliged or unprivileged Thread mode */
-/* only priv currently supported */
-#define OS_RUN_PRIV (0)
-#define OS_RUN_UNPRIV (1)
-
-/* CPU status register */
-typedef uint32_t os_sr_t;
-/* Stack type, aligned to a 32-bit word. */
-#define OS_STACK_PATTERN (0xdeadbeef)
-
-typedef uint32_t os_stack_t;
-#define OS_ALIGNMENT (4)
-#define OS_STACK_ALIGNMENT (8)
-
-#define OS_SR_IPL_BITS (0xE0)
-
-/*
- * Stack sizes for common OS tasks
- */
-#define OS_SANITY_STACK_SIZE (64)
-#define OS_IDLE_STACK_SIZE (64)
-
-#define OS_STACK_ALIGN(__nmemb) \
- (OS_ALIGN((__nmemb), OS_STACK_ALIGNMENT))
-
-/* Enter a critical section, save processor state, and block interrupts */
-#define OS_ENTER_CRITICAL(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
- __builtin_disable_interrupts();} while(0)
-
-/* Exit a critical section, restore processor state and unblock interrupts */
-#define OS_EXIT_CRITICAL(__os_sr) __builtin_set_isr_state(__os_sr)
-/* This is not the only way interrupts can be disabled */
-#define OS_IS_CRITICAL() ((__builtin_get_isr_state() & 1) == 0)
-#define OS_ASSERT_CRITICAL() assert(OS_IS_CRITICAL())
-
-os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int);
-void timer_handler(void);
-void os_arch_ctx_sw(struct os_task *);
-os_sr_t os_arch_save_sr(void);
-void os_arch_restore_sr(os_sr_t);
-int os_arch_in_critical(void);
-void os_arch_init(void);
-uint32_t os_arch_start(void);
-os_error_t os_arch_os_init(void);
-os_error_t os_arch_os_start(void);
-void os_set_env(os_stack_t *);
-void os_arch_init_task_stack(os_stack_t *sf);
-void os_default_irq_asm(void);
-
-/* External function prototypes supplied by BSP */
-void os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio);
-void os_bsp_ctx_sw(void);
-
-#endif /* _OS_ARCH_PIC32MZ_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/mips/asm/ctx.S
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/mips/asm/ctx.S b/kernel/os/src/arch/mips/asm/ctx.S
index a851f90..9377b95 100644
--- a/kernel/os/src/arch/mips/asm/ctx.S
+++ b/kernel/os/src/arch/mips/asm/ctx.S
@@ -33,10 +33,16 @@
#include <mips/cpu.h>
#include <mips/hal.h>
+#define OS_STACK_ALIGNMENT (8)
+
+#define CTX_ALIGNED_SIZE ((((CTX_SIZE - 1) / OS_STACK_ALIGNMENT) + 1) * \
+ OS_STACK_ALIGNMENT)
+
# note that k0 is not saved when using these macros.
# The cause register is saved but not resored.
# saves to location k0
+
.macro _gpctx_save
REG_S $1, CTX_REG(1) (k0)
REG_S $2, CTX_REG(2) (k0)
@@ -69,7 +75,7 @@
REG_S $29, CTX_REG(29)(k0)
REG_S $30, CTX_REG(30)(k0)
REG_S $31, CTX_REG(31)(k0)
- PTR_S $0, CTX_LINK(k0) # Clear the link field
+ PTR_S $0, CTX_LINK(k0) # Clear the link field
#if (__mips_isa_rev < 6)
mfhi $9
@@ -79,7 +85,8 @@
#endif
# cp0
- REG_S ra, CTX_EPC(k0)
+ PTR_MFC0 $9, C0_EPC
+ REG_S $9, CTX_EPC(k0)
PTR_MFC0 $9, C0_BADVADDR
REG_S $9, CTX_BADVADDR(k0)
mfc0 $9, C0_SR
@@ -145,6 +152,7 @@
REG_L $31, CTX_REG(31)(a0)
di
+
REG_L k0, CTX_EPC(a0)
PTR_MTC0 k0, C0_EPC
lw k0, CTX_STATUS(a0)
@@ -175,8 +183,8 @@ _mips_isr_sw0:
# context switch
.set noat
# save k0
- REG_S $26, (CTX_REG(25) - CTX_SIZE) (sp)
- addi k0, sp, -((((CTX_SIZE - 1) / 8) + 1) * 8)
+ REG_S $26, (CTX_REG(25) - CTX_ALIGNED_SIZE)(sp)
+ addi k0, sp, -CTX_ALIGNED_SIZE
_gpctx_save # save the context
.set at
lw t0, g_current_task # get current task
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/mips/os_arch_mips.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/mips/os_arch_mips.c b/kernel/os/src/arch/mips/os_arch_mips.c
index bdc9e5e..348fae0 100644
--- a/kernel/os/src/arch/mips/os_arch_mips.c
+++ b/kernel/os/src/arch/mips/os_arch_mips.c
@@ -101,7 +101,7 @@ os_stack_t *
os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size)
{
os_stack_t *s = stack_top - ((((sizeof(struct gpctx) - 1) /
- OS_STACK_ALIGNMENT) + 1) * 2);
+ OS_STACK_ALIGNMENT) + 1) * (OS_STACK_ALIGNMENT/sizeof(os_stack_t)));
struct gpctx ctx = {
.r = {
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/pic32/asm/ctx.S
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32/asm/ctx.S b/kernel/os/src/arch/pic32/asm/ctx.S
new file mode 100644
index 0000000..1985f81
--- /dev/null
+++ b/kernel/os/src/arch/pic32/asm/ctx.S
@@ -0,0 +1,189 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <xc.h>
+#include "syscfg/syscfg.h"
+
+#define OS_STACK_ALIGNMENT (8)
+
+#define CTX_ALIGNED_SIZE ((((CTX_SIZE - 1) / OS_STACK_ALIGNMENT) + 1) * \
+ OS_STACK_ALIGNMENT)
+#define CTX_OFFS(r) (((r) * 4) - CTX_ALIGNED_SIZE)
+
+#if (__mips_isa_rev < 6)
+ #define CTX_SIZE (36 * 4)
+ #define CTX_LO CTX_OFFS(34)
+ #define CTX_HI CTX_OFFS(35)
+#else
+ #define CTX_SIZE (34 * 4)
+#endif
+
+# relative to the stack pointer
+#define CTX_REG(r) CTX_OFFS((r) - 1)
+#define CTX_EPC CTX_OFFS(30)
+#define CTX_BADVADDR CTX_OFFS(31)
+#define CTX_STATUS CTX_OFFS(32)
+#define CTX_CAUSE CTX_OFFS(33)
+
+.macro _gpctx_save
+ .set push
+ .set noat
+ sw $1, CTX_REG(1)(sp)
+ .set at
+ sw v0, CTX_REG(2)(sp)
+ sw v1, CTX_REG(3)(sp)
+ sw a0, CTX_REG(4)(sp)
+ sw a1, CTX_REG(5)(sp)
+ sw a2, CTX_REG(6)(sp)
+ sw a3, CTX_REG(7)(sp)
+ sw t0, CTX_REG(8)(sp)
+ sw t1, CTX_REG(9)(sp)
+ sw t2, CTX_REG(10)(sp)
+ sw t3, CTX_REG(11)(sp)
+ sw t4, CTX_REG(12)(sp)
+ sw t5, CTX_REG(13)(sp)
+ sw t6, CTX_REG(14)(sp)
+ sw t7, CTX_REG(15)(sp)
+ sw s0, CTX_REG(16)(sp)
+ sw s1, CTX_REG(17)(sp)
+ sw s2, CTX_REG(18)(sp)
+ sw s3, CTX_REG(19)(sp)
+ sw s4, CTX_REG(20)(sp)
+ sw s5, CTX_REG(21)(sp)
+ sw s6, CTX_REG(22)(sp)
+ sw s7, CTX_REG(23)(sp)
+ sw t8, CTX_REG(24)(sp)
+ sw t9, CTX_REG(25)(sp)
+ sw k0, CTX_REG(26)(sp)
+ sw k1, CTX_REG(27)(sp)
+ sw gp, CTX_REG(28)(sp)
+ # don't bother saving sp
+ sw fp, CTX_REG(29)(sp)
+ sw ra, CTX_REG(30)(sp)
+
+#if (__mips_isa_rev < 6)
+ mfhi k0
+ sw k0, CTX_HI(sp)
+ mflo k0
+ sw k0, CTX_LO(sp)
+#endif
+
+ # cp0
+ mfc0 k0, _CP0_EPC
+ sw k0, CTX_EPC(sp)
+ mfc0 k0, _CP0_BADVADDR
+ sw k0, CTX_BADVADDR(sp)
+ mfc0 k0, _CP0_STATUS
+ sw k0, CTX_STATUS(sp)
+ mfc0 k0, _CP0_CAUSE
+ sw k0, CTX_CAUSE(sp)
+ .set pop
+.endm
+
+.macro _gpctx_load
+ .set push
+ .set noat
+ lw $1, CTX_REG(1)(sp)
+ lw v0, CTX_REG(2)(sp)
+ lw v1, CTX_REG(3)(sp)
+ lw a0, CTX_REG(4)(sp)
+ lw a1, CTX_REG(5)(sp)
+ lw a2, CTX_REG(6)(sp)
+ lw a3, CTX_REG(7)(sp)
+ lw t0, CTX_REG(8)(sp)
+ lw t1, CTX_REG(9)(sp)
+ lw t2, CTX_REG(10)(sp)
+ lw t3, CTX_REG(11)(sp)
+ lw t4, CTX_REG(12)(sp)
+ lw t5, CTX_REG(13)(sp)
+ lw t6, CTX_REG(14)(sp)
+ lw t7, CTX_REG(15)(sp)
+ lw s0, CTX_REG(16)(sp)
+ lw s1, CTX_REG(17)(sp)
+ lw s2, CTX_REG(18)(sp)
+ lw s3, CTX_REG(19)(sp)
+ lw s4, CTX_REG(20)(sp)
+ lw s5, CTX_REG(21)(sp)
+ lw s6, CTX_REG(22)(sp)
+ lw s7, CTX_REG(23)(sp)
+ lw t8, CTX_REG(24)(sp)
+ lw t9, CTX_REG(25)(sp)
+ # restore k0 last
+ lw k1, CTX_REG(27)(sp)
+ lw gp, CTX_REG(28)(sp)
+ # sp already restored
+ lw fp, CTX_REG(29)(sp)
+ lw ra, CTX_REG(30)(sp)
+
+ di
+
+#if (__mips_isa_rev < 6)
+ lw k0, CTX_HI(sp)
+ mthi k0
+ lw k0, CTX_LO(sp)
+ mtlo k0
+#endif
+
+ # cp0
+ lw k0, CTX_EPC(sp)
+ mtc0 k0, _CP0_EPC
+ lw k0, CTX_STATUS(sp)
+ # STATUS here will have EXL set
+ mtc0 k0, _CP0_STATUS
+ ehb
+ # restore k0
+ lw k0, CTX_REG(26)(sp)
+ .set pop
+.endm
+
+.text
+.global get_global_pointer
+.ent get_global_pointer
+get_global_pointer:
+ .set noat
+ move v0, gp
+ jr ra
+.end
+
+.text
+.global isr_sw0
+.ent isr_sw0
+isr_sw0:
+ .set noat
+ rdpgpr sp, sp
+
+ # context switch
+ _gpctx_save # save the context
+ .set at
+ lw k0, g_current_task # get current task
+ beqz k0, 1f # if there is a current task
+ sw sp, 0(k0) # update stored sp
+1:
+ li k0, _IFS0_CS0IF_MASK # clear sw interrupt
+ sw k0, IFS0CLR
+
+ lw k0, g_os_run_list # get new task
+ sw k0, g_current_task # g_current_task = g_os_run_list
+
+ lw sp, 0(k0) # restore sp
+ .set noat
+ _gpctx_load
+ wrpgpr sp, sp
+ eret
+.end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/pic32/os_arch_pic32.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32/os_arch_pic32.c b/kernel/os/src/arch/pic32/os_arch_pic32.c
new file mode 100644
index 0000000..0255905
--- /dev/null
+++ b/kernel/os/src/arch/pic32/os_arch_pic32.c
@@ -0,0 +1,221 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "os/os.h"
+#include "os/os_arch.h"
+#include "syscfg/syscfg.h"
+#include <hal/hal_bsp.h>
+#include <hal/hal_os_tick.h>
+
+#include "os_priv.h"
+
+#include <string.h>
+
+#define OS_TICK_PERIOD ((MYNEWT_VAL(CLOCK_FREQ) / 2) / OS_TICKS_PER_SEC)
+
+extern void SVC_Handler(void);
+extern void PendSV_Handler(void);
+extern void SysTick_Handler(void);
+
+struct ctx {
+ uint32_t regs[30];
+ uint32_t epc;
+ uint32_t badvaddr;
+ uint32_t status;
+ uint32_t cause;
+#if (__mips_isa_rev < 6)
+ uint32_t lo;
+ uint32_t hi;
+#endif
+};
+
+/* XXX: determine how to deal with running un-privileged */
+/* only priv currently supported */
+uint32_t os_flags = OS_RUN_PRIV;
+
+extern struct os_task g_idle_task;
+
+struct os_task *g_fpu_task;
+
+/* core timer interrupt */
+void __attribute__((interrupt(IPL1AUTO),
+vector(_CORE_TIMER_VECTOR))) isr_core_timer(void)
+{
+ timer_handler();
+ _CP0_SET_COMPARE(_CP0_GET_COMPARE() + OS_TICK_PERIOD);
+ IFS0CLR = _IFS0_CTIF_MASK;
+}
+
+/* context switch interrupt, in ctx.S */
+void __attribute__((interrupt(IPL1AUTO),
+vector(_CORE_SOFTWARE_0_VECTOR))) isr_sw0(void);
+
+static int
+os_in_isr(void)
+{
+ /* check the EXL bit */
+ return (_CP0_GET_STATUS() & _CP0_STATUS_EXL_MASK) ? 1 : 0;
+}
+
+void
+timer_handler(void)
+{
+ os_time_advance(1);
+}
+
+void
+os_arch_ctx_sw(struct os_task *t)
+{
+ if ((os_sched_get_current_task() != 0) && (t != 0)) {
+ os_sched_ctx_sw_hook(t);
+ }
+
+ IFS0SET = _IFS0_CS0IF_MASK;
+}
+
+os_sr_t
+os_arch_save_sr(void)
+{
+ os_sr_t sr;
+ OS_ENTER_CRITICAL(sr);
+ return sr;
+}
+
+void
+os_arch_restore_sr(os_sr_t isr_ctx)
+{
+ OS_EXIT_CRITICAL(isr_ctx);
+}
+
+int
+os_arch_in_critical(void)
+{
+ return OS_IS_CRITICAL();
+}
+
+uint32_t get_global_pointer(void);
+
+/* assumes stack_top will be 8 aligned */
+
+os_stack_t *
+os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size)
+{
+ stack_top -= 4; /* space for incoming arguments */
+ os_stack_t *s = stack_top - ((((sizeof(struct ctx) - 1) /
+ OS_STACK_ALIGNMENT) + 1) * (OS_STACK_ALIGNMENT/sizeof(os_stack_t)));
+
+ struct ctx ctx;
+
+ ctx.regs[3] = (uint32_t)t->t_arg;
+ ctx.regs[27] = get_global_pointer();
+ ctx.status = _CP0_GET_STATUS() | _CP0_STATUS_IE_MASK;
+ ctx.cause = _CP0_GET_CAUSE();
+ ctx.epc = (uint32_t)t->t_func;
+ /* copy struct onto the stack */
+ memcpy(s, &ctx, sizeof(ctx));
+
+ return (uint32_t)stack_top;
+}
+
+void
+os_arch_init(void)
+{
+ os_init_idle_task();
+}
+
+os_error_t
+os_arch_os_init(void)
+{
+ os_error_t err;
+
+ err = OS_ERR_IN_ISR;
+ if (os_in_isr() == 0) {
+ err = OS_OK;
+ os_sr_t sr;
+ OS_ENTER_CRITICAL(sr);
+
+ _CP0_BIC_STATUS(_CP0_STATUS_IPL_MASK);
+ /* multi vector mode */
+ INTCONSET = _INTCON_MVEC_MASK;
+ /* vector spacing 0x20 */
+ _CP0_SET_INTCTL(_CP0_GET_INTCTL() | (1 << _CP0_INTCTL_VS_POSITION));
+
+ /* enable core timer interrupt */
+ IEC0SET = _IEC0_CTIE_MASK;
+ /* set interrupt priority */
+ IPC0CLR = _IPC0_CTIP_MASK;
+ IPC0SET = (1 << _IPC0_CTIP_POSITION); /* priority 1 */
+ /* set interrupt subpriority */
+ IPC0CLR = _IPC0_CTIS_MASK;
+ IPC0SET = (0 << _IPC0_CTIS_POSITION); /* subpriority 0 */
+
+ /* enable software interrupt 0 */
+ IEC0SET = _IEC0_CS0IE_MASK;
+ /* set interrupt priority */
+ IPC0CLR = _IPC0_CS0IP_MASK;
+ IPC0SET = (1 << _IPC0_CS0IP_POSITION); /* priority 1 */
+ /* set interrupt subpriority */
+ IPC0CLR = _IPC0_CS0IS_MASK;
+ IPC0SET = (0 << _IPC0_CS0IS_POSITION); /* subpriority 0 */
+
+ OS_EXIT_CRITICAL(sr);
+
+ /* should be in kernel mode here */
+ os_arch_init();
+ }
+ return err;
+}
+
+uint32_t
+os_arch_start(void)
+{
+ struct os_task *t;
+
+ /* Get the highest priority ready to run to set the current task */
+ t = os_sched_next_task();
+
+ /* set the core timer compare register */
+ _CP0_SET_COMPARE(_CP0_GET_COUNT() + OS_TICK_PERIOD);
+
+ /* global interrupt enable */
+ __builtin_enable_interrupts();
+
+ /* Mark the OS as started, right before we run our first task */
+ g_os_started = 1;
+
+ /* Perform context switch to first task */
+ os_arch_ctx_sw(t);
+
+ return (uint32_t)(t->t_arg);
+}
+
+os_error_t
+os_arch_os_start(void)
+{
+ os_error_t err;
+
+ err = OS_ERR_IN_ISR;
+ if (os_in_isr() == 0) {
+ err = OS_OK;
+ /* should be in kernel mode here */
+ os_arch_start();
+ }
+
+ return err;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/pic32/os_fault.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32/os_fault.c b/kernel/os/src/arch/pic32/os_fault.c
new file mode 100644
index 0000000..5dc952a
--- /dev/null
+++ b/kernel/os/src/arch/pic32/os_fault.c
@@ -0,0 +1,122 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <console/console.h>
+#include <hal/hal_system.h>
+#ifdef COREDUMP_PRESENT
+#include <coredump/coredump.h>
+#endif
+#include "os/os.h"
+
+#include <stdint.h>
+#include <unistd.h>
+
+struct exception_frame {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t psr;
+};
+
+struct trap_frame {
+ struct exception_frame *ef;
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+ uint32_t lr; /* this LR holds EXC_RETURN */
+};
+
+struct coredump_regs {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+ uint32_t r12;
+ uint32_t sp;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t psr;
+};
+
+#ifdef COREDUMP_PRESENT
+static void
+trap_to_coredump(struct trap_frame *tf, struct coredump_regs *regs)
+{
+}
+#endif
+
+void
+__assert_func(const char *file, int line, const char *func, const char *e)
+{
+ int sr;
+
+ OS_ENTER_CRITICAL(sr);
+ (void)sr;
+ console_blocking_mode();
+ console_printf("Assert @ 0x%x\n",
+ (unsigned int)__builtin_return_address(0));
+ if (hal_debugger_connected()) {
+ /*
+ * If debugger is attached, breakpoint before the trap.
+ */
+ }
+ hal_system_reset();
+}
+
+void
+os_default_irq(struct trap_frame *tf)
+{
+#ifdef COREDUMP_PRESENT
+ struct coredump_regs regs;
+#endif
+
+ console_blocking_mode();
+ console_printf("Unhandled interrupt, exception sp 0x%08lx\n",
+ (uint32_t)tf->ef);
+ console_printf(" r0:0x%08lx r1:0x%08lx r2:0x%08lx r3:0x%08lx\n",
+ tf->ef->r0, tf->ef->r1, tf->ef->r2, tf->ef->r3);
+ console_printf(" r4:0x%08lx r5:0x%08lx r6:0x%08lx r7:0x%08lx\n",
+ tf->r4, tf->r5, tf->r6, tf->r7);
+ console_printf(" r8:0x%08lx r9:0x%08lx r10:0x%08lx r11:0x%08lx\n",
+ tf->r8, tf->r9, tf->r10, tf->r11);
+ console_printf("r12:0x%08lx lr:0x%08lx pc:0x%08lx psr:0x%08lx\n",
+ tf->ef->r12, tf->ef->lr, tf->ef->pc, tf->ef->psr);
+#ifdef COREDUMP_PRESENT
+ trap_to_coredump(tf, ®s);
+ coredump_dump(®s, sizeof(regs));
+#endif
+ hal_system_reset();
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/pic32mx/asm/ctx.S
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mx/asm/ctx.S b/kernel/os/src/arch/pic32mx/asm/ctx.S
deleted file mode 100644
index e14c131..0000000
--- a/kernel/os/src/arch/pic32mx/asm/ctx.S
+++ /dev/null
@@ -1,163 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <xc.h>
-
-#define CTX_SIZE (35*4)
-#define CTX_EPC (31*4)
-#define CTX_BADVADDR (32*4)
-#define CTX_STATUS (33*4)
-#define CTX_CAUSE (34*4)
-
-# note that k0 is not saved when using these macros.
-# The cause register is saved but not resored.
-
-# saves to location k0
-.macro _gpctx_save
- sw $1, 0(k0)
- sw $2, 4(k0)
- sw $3, 8(k0)
- sw $4, 12(k0)
- sw $5, 16(k0)
- sw $6, 20(k0)
- sw $7, 24(k0)
- sw $8, 28(k0)
- sw $9, 32(k0)
- sw $10, 36(k0)
- sw $11, 40(k0)
- sw $12, 44(k0)
- sw $13, 48(k0)
- sw $14, 52(k0)
- sw $15, 56(k0)
- sw $16, 60(k0)
- sw $17, 64(k0)
- sw $18, 68(k0)
- sw $19, 72(k0)
- sw $20, 76(k0)
- sw $21, 80(k0)
- sw $22, 84(k0)
- sw $23, 88(k0)
- sw $24, 92(k0)
- sw $25, 96(k0)
- # k0 not saved
- sw $27, 104(k0)
- sw $28, 108(k0)
- sw $29, 112(k0)
- sw $30, 116(k0)
- sw $31, 120(k0)
-
- # cp0
- sw ra, CTX_EPC(k0)
- mfc0 $9, _CP0_BADVADDR /* PTR_MFC0? */
- sw $9, CTX_BADVADDR(k0)
- mfc0 $9, _CP0_STATUS
- sw $9, CTX_STATUS(k0)
- mfc0 $9, _CP0_CAUSE
- sw $9, CTX_CAUSE(k0)
-
-.endm
-
-# restores from location a0
-
-.macro _gpctx_load
- lw $1, 0(a0)
- lw $2, 4(a0)
- lw $3, 8(a0)
- # a0 is loaded last
- lw $5, 16(a0)
- lw $6, 20(a0)
- lw $7, 24(a0)
- lw $8, 28(a0)
- lw $9, 32(a0)
- lw $10, 36(a0)
- lw $11, 40(a0)
- lw $12, 44(a0)
- lw $13, 48(a0)
- lw $14, 52(a0)
- lw $15, 56(a0)
- lw $16, 60(a0)
- lw $17, 64(a0)
- lw $18, 68(a0)
- lw $19, 72(a0)
- lw $20, 76(a0)
- lw $21, 80(a0)
- lw $22, 84(a0)
- lw $23, 88(a0)
- lw $24, 92(a0)
- lw $25, 96(a0)
- # restore k0 after interrupts have been disabled
- lw $27, 104(a0)
- lw $28, 108(a0)
- # restore sp after interrupts have been disabled
- lw $30, 116(a0)
- lw $31, 120(a0)
-
- di
- lw k0, CTX_EPC(a0)
- mtc0 k0, _CP0_EPC
- lw k0, CTX_STATUS(a0)
- # STATUS here will have EXL set
- mtc0 k0, _CP0_STATUS
- ehb
-
- # restore k0 and sp as these may be overwritten by nested interrupts
- lw $26, 100(a0)
- lw $29, 112(a0)
- # restore a0 last
- lw $4, 12(a0)
-.endm
-
-.text
-.global get_global_pointer
-.ent get_global_pointer
-get_global_pointer:
- .set noat
- move v0, gp
- jr ra
-.end
-
-.text
-.global isr_sw0
-.ent isr_sw0
-isr_sw0:
- # context switch
- .set noat
- rdpgpr sp, sp
- # save k0 as its not saved in ctx_switch, hardcode values for now
- sw $26, ((25 * 4) - ((((CTX_SIZE - 1) / 8) + 1) * 8))(sp)
- addi k0, sp, -((((CTX_SIZE - 1) / 8) + 1) * 8)
- _gpctx_save # save the context
- .set at
- lw t0, g_current_task # get current task
- beqz t0, 1f
- sw k0, 0(t0) # update stored sp
-1:
- lw t1, g_os_run_list # get new task
- sw t1, g_current_task # g_current_task = g_os_run_list
-
- li k0, _IFS0_CS0IF_MASK
- sw k0, IFS0CLR
-
- lw a0, 0(t1)
- .set noat
- _gpctx_load # updates actual sp
- wrpgpr sp, sp
-
- eret
-.end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/pic32mx/os_arch_pic32mx.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mx/os_arch_pic32mx.c b/kernel/os/src/arch/pic32mx/os_arch_pic32mx.c
deleted file mode 100644
index 0dbddcc..0000000
--- a/kernel/os/src/arch/pic32mx/os_arch_pic32mx.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include "os/os.h"
-#include "os/os_arch.h"
-#include "syscfg/syscfg.h"
-#include <hal/hal_bsp.h>
-#include <hal/hal_os_tick.h>
-
-#include "os_priv.h"
-
-#include <string.h>
-
-extern void SVC_Handler(void);
-extern void PendSV_Handler(void);
-extern void SysTick_Handler(void);
-
-struct ctx {
- uint32_t regs[31];
- uint32_t epc;
- uint32_t badvaddr;
- uint32_t status;
- uint32_t cause;
-};
-
-/* XXX: determine how to deal with running un-privileged */
-/* only priv currently supported */
-uint32_t os_flags = OS_RUN_PRIV;
-
-extern struct os_task g_idle_task;
-
-/* core timer interrupt */
-void __attribute__((interrupt(IPL1AUTO),
-vector(_CORE_TIMER_VECTOR))) isr_core_timer(void)
-{
- timer_handler();
- _CP0_SET_COMPARE(_CP0_GET_COMPARE() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) / 1000));
- IFS0CLR = _IFS0_CTIF_MASK;
-}
-
-/* context switch interrupt, in ctx.S */
-void __attribute__((interrupt(IPL1AUTO),
-vector(_CORE_SOFTWARE_0_VECTOR))) isr_sw0(void);
-
-static int
-os_in_isr(void)
-{
- /* check the EXL bit */
- return (_CP0_GET_STATUS() & _CP0_STATUS_EXL_MASK) ? 1 : 0;
-}
-
-void
-timer_handler(void)
-{
- os_time_advance(1);
-}
-
-void
-os_arch_ctx_sw(struct os_task *t)
-{
- if ((os_sched_get_current_task() != 0) && (t != 0)) {
- os_sched_ctx_sw_hook(t);
- }
-
- IFS0SET = _IFS0_CS0IF_MASK;
-}
-
-os_sr_t
-os_arch_save_sr(void)
-{
- os_sr_t sr;
- OS_ENTER_CRITICAL(sr);
- return sr;
-}
-
-void
-os_arch_restore_sr(os_sr_t isr_ctx)
-{
- OS_EXIT_CRITICAL(isr_ctx);
-}
-
-int
-os_arch_in_critical(void)
-{
- return OS_IS_CRITICAL();
-}
-
-uint32_t get_global_pointer(void);
-
-/* assumes stack_top will be 8 aligned */
-
-os_stack_t *
-os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size)
-{
- os_stack_t *s = stack_top - ((((sizeof(struct ctx) - 1) /
- OS_STACK_ALIGNMENT) + 1) * 2);
-
- struct ctx ctx;
-
- ctx.regs[3] = (uint32_t)t->t_arg;
- ctx.regs[27] = get_global_pointer();
- ctx.regs[28] = (uint32_t)(stack_top - 4);
- ctx.status = _CP0_GET_STATUS() | _CP0_STATUS_IE_MASK;
- ctx.cause = _CP0_GET_CAUSE();
- ctx.epc = (uint32_t)t->t_func;
- /* copy struct onto the stack */
- memcpy(s, &ctx, sizeof(ctx));
-
- return (s);
-}
-
-void
-os_arch_init(void)
-{
- os_init_idle_task();
-}
-
-os_error_t
-os_arch_os_init(void)
-{
- os_error_t err;
-
- err = OS_ERR_IN_ISR;
- if (os_in_isr() == 0) {
- err = OS_OK;
- os_sr_t sr;
- OS_ENTER_CRITICAL(sr);
-
- _CP0_BIC_STATUS(_CP0_STATUS_IPL_MASK);
- /* multi vector mode */
- INTCONSET = _INTCON_MVEC_MASK;
- /* vector spacing 0x20 */
- _CP0_SET_INTCTL(_CP0_GET_INTCTL() | (1 << _CP0_INTCTL_VS_POSITION));
-
- /* enable core timer interrupt */
- IEC0SET = _IEC0_CTIE_MASK;
- /* set interrupt priority */
- IPC0CLR = _IPC0_CTIP_MASK;
- IPC0SET = (1 << _IPC0_CTIP_POSITION); // priority 1
- /* set interrupt subpriority */
- IPC0CLR = _IPC0_CTIS_MASK;
- IPC0SET = (0 << _IPC0_CTIS_POSITION); // subpriority 0
-
- /* enable software interrupt 0 */
- IEC0SET = _IEC0_CS0IE_MASK;
- /* set interrupt priority */
- IPC0CLR = _IPC0_CS0IP_MASK;
- IPC0SET = (1 << _IPC0_CS0IP_POSITION); // priority 1
- /* set interrupt subpriority */
- IPC0CLR = _IPC0_CS0IS_MASK;
- IPC0SET = (0 << _IPC0_CS0IS_POSITION); // subpriority 0
-
- OS_EXIT_CRITICAL(sr);
-
- /* should be in kernel mode here */
- os_arch_init();
- }
- return err;
-}
-
-uint32_t
-os_arch_start(void)
-{
- struct os_task *t;
-
- /* Get the highest priority ready to run to set the current task */
- t = os_sched_next_task();
-
- /* set the core timer compare register */
- _CP0_SET_COMPARE(_CP0_GET_COUNT() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) / 1000));
-
- /* global interrupt enable */
- __builtin_enable_interrupts();
-
- /* Mark the OS as started, right before we run our first task */
- g_os_started = 1;
-
- /* Perform context switch to first task */
- os_arch_ctx_sw(t);
-
- return (uint32_t)(t->t_arg);
-}
-
-os_error_t
-os_arch_os_start(void)
-{
- os_error_t err;
-
- err = OS_OK; // OS_ERR_IN_ISR
- if (os_in_isr() == 0) {
- err = OS_OK;
- /* should be in kernel mode here */
- os_arch_start();
- }
-
- return err;
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/pic32mx/os_fault.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mx/os_fault.c b/kernel/os/src/arch/pic32mx/os_fault.c
deleted file mode 100644
index 5dc952a..0000000
--- a/kernel/os/src/arch/pic32mx/os_fault.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <console/console.h>
-#include <hal/hal_system.h>
-#ifdef COREDUMP_PRESENT
-#include <coredump/coredump.h>
-#endif
-#include "os/os.h"
-
-#include <stdint.h>
-#include <unistd.h>
-
-struct exception_frame {
- uint32_t r0;
- uint32_t r1;
- uint32_t r2;
- uint32_t r3;
- uint32_t r12;
- uint32_t lr;
- uint32_t pc;
- uint32_t psr;
-};
-
-struct trap_frame {
- struct exception_frame *ef;
- uint32_t r4;
- uint32_t r5;
- uint32_t r6;
- uint32_t r7;
- uint32_t r8;
- uint32_t r9;
- uint32_t r10;
- uint32_t r11;
- uint32_t lr; /* this LR holds EXC_RETURN */
-};
-
-struct coredump_regs {
- uint32_t r0;
- uint32_t r1;
- uint32_t r2;
- uint32_t r3;
- uint32_t r4;
- uint32_t r5;
- uint32_t r6;
- uint32_t r7;
- uint32_t r8;
- uint32_t r9;
- uint32_t r10;
- uint32_t r11;
- uint32_t r12;
- uint32_t sp;
- uint32_t lr;
- uint32_t pc;
- uint32_t psr;
-};
-
-#ifdef COREDUMP_PRESENT
-static void
-trap_to_coredump(struct trap_frame *tf, struct coredump_regs *regs)
-{
-}
-#endif
-
-void
-__assert_func(const char *file, int line, const char *func, const char *e)
-{
- int sr;
-
- OS_ENTER_CRITICAL(sr);
- (void)sr;
- console_blocking_mode();
- console_printf("Assert @ 0x%x\n",
- (unsigned int)__builtin_return_address(0));
- if (hal_debugger_connected()) {
- /*
- * If debugger is attached, breakpoint before the trap.
- */
- }
- hal_system_reset();
-}
-
-void
-os_default_irq(struct trap_frame *tf)
-{
-#ifdef COREDUMP_PRESENT
- struct coredump_regs regs;
-#endif
-
- console_blocking_mode();
- console_printf("Unhandled interrupt, exception sp 0x%08lx\n",
- (uint32_t)tf->ef);
- console_printf(" r0:0x%08lx r1:0x%08lx r2:0x%08lx r3:0x%08lx\n",
- tf->ef->r0, tf->ef->r1, tf->ef->r2, tf->ef->r3);
- console_printf(" r4:0x%08lx r5:0x%08lx r6:0x%08lx r7:0x%08lx\n",
- tf->r4, tf->r5, tf->r6, tf->r7);
- console_printf(" r8:0x%08lx r9:0x%08lx r10:0x%08lx r11:0x%08lx\n",
- tf->r8, tf->r9, tf->r10, tf->r11);
- console_printf("r12:0x%08lx lr:0x%08lx pc:0x%08lx psr:0x%08lx\n",
- tf->ef->r12, tf->ef->lr, tf->ef->pc, tf->ef->psr);
-#ifdef COREDUMP_PRESENT
- trap_to_coredump(tf, ®s);
- coredump_dump(®s, sizeof(regs));
-#endif
- hal_system_reset();
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/pic32mz/asm/ctx.S
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mz/asm/ctx.S b/kernel/os/src/arch/pic32mz/asm/ctx.S
deleted file mode 100644
index 0793952..0000000
--- a/kernel/os/src/arch/pic32mz/asm/ctx.S
+++ /dev/null
@@ -1,163 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <xc.h>
-
-#define CTX_SIZE (35*4)
-#define CTX_EPC (31*4)
-#define CTX_BADVADDR (32*4)
-#define CTX_STATUS (33*4)
-#define CTX_CAUSE (34*4)
-
-# note that k0 is not saved when using these macros.
-# The cause register is saved but not resored.
-
-# saves to location k0
-.macro _gpctx_save
- sw $1, 0(k0)
- sw $2, 4(k0)
- sw $3, 8(k0)
- sw $4, 12(k0)
- sw $5, 16(k0)
- sw $6, 20(k0)
- sw $7, 24(k0)
- sw $8, 28(k0)
- sw $9, 32(k0)
- sw $10, 36(k0)
- sw $11, 40(k0)
- sw $12, 44(k0)
- sw $13, 48(k0)
- sw $14, 52(k0)
- sw $15, 56(k0)
- sw $16, 60(k0)
- sw $17, 64(k0)
- sw $18, 68(k0)
- sw $19, 72(k0)
- sw $20, 76(k0)
- sw $21, 80(k0)
- sw $22, 84(k0)
- sw $23, 88(k0)
- sw $24, 92(k0)
- sw $25, 96(k0)
- # k0 not saved
- sw $27, 104(k0)
- sw $28, 108(k0)
- sw $29, 112(k0)
- sw $30, 116(k0)
- sw $31, 120(k0)
-
- # cp0
- sw ra, CTX_EPC(k0)
- mfc0 $9, _CP0_BADVADDR /* PTR_MFC0? */
- sw $9, CTX_BADVADDR(k0)
- mfc0 $9, _CP0_STATUS
- sw $9, CTX_STATUS(k0)
- mfc0 $9, _CP0_CAUSE
- sw $9, CTX_CAUSE(k0)
-
-.endm
-
-# restores from location a0
-
-.macro _gpctx_load
- lw $1, 0(a0)
- lw $2, 4(a0)
- lw $3, 8(a0)
- # a0 is loaded last
- lw $5, 16(a0)
- lw $6, 20(a0)
- lw $7, 24(a0)
- lw $8, 28(a0)
- lw $9, 32(a0)
- lw $10, 36(a0)
- lw $11, 40(a0)
- lw $12, 44(a0)
- lw $13, 48(a0)
- lw $14, 52(a0)
- lw $15, 56(a0)
- lw $16, 60(a0)
- lw $17, 64(a0)
- lw $18, 68(a0)
- lw $19, 72(a0)
- lw $20, 76(a0)
- lw $21, 80(a0)
- lw $22, 84(a0)
- lw $23, 88(a0)
- lw $24, 92(a0)
- lw $25, 96(a0)
- # restore k0 after interrupts have been disabled
- lw $27, 104(a0)
- lw $28, 108(a0)
- # restore sp after interrupts have been disabled
- lw $30, 116(a0)
- lw $31, 120(a0)
-
- di
- lw k0, CTX_EPC(a0)
- mtc0 k0, _CP0_EPC
- lw k0, CTX_STATUS(a0)
- # STATUS here will have EXL set
- mtc0 k0, _CP0_STATUS
- ehb
-
- # restore k0 and sp as these may be overwritten by nested interrupts
- lw $26, 100(a0)
- lw $29, 112(a0)
- # restore a0 last
- lw $4, 12(a0)
-.endm
-
-.text
-.global get_global_pointer
-.ent get_global_pointer
-get_global_pointer:
- .set noat
- move v0, gp
- jr ra
-.end
-
-.text
-.global isr_sw0
-.ent isr_sw0
-isr_sw0:
- # context switch
- .set noat
- rdpgpr sp, sp
- # save k0 as its not saved in ctx_switch, hardcode values for now
- sw $26, ((25 * 4) - ((((CTX_SIZE - 1) / 8) + 1) * 8))(sp)
- addi k0, sp, -((((CTX_SIZE - 1) / 8) + 1) * 8)
- _gpctx_save # save the context
- .set at
- lw t0, g_current_task # get current task
- beqz t0, 1f
- sw k0, 0(t0) # update stored sp
-1:
- lw t1, g_os_run_list # get new task
- sw t1, g_current_task # g_current_task = g_os_run_list
-
- li k0, _IFS0_CS0IF_MASK
- sw k0, IFS0CLR
-
- lw a0, 0(t1)
- .set noat
- _gpctx_load # updates actual sp
- wrpgpr sp, sp
-
- eret
-.end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/pic32mz/os_arch_pic32mz.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mz/os_arch_pic32mz.c b/kernel/os/src/arch/pic32mz/os_arch_pic32mz.c
deleted file mode 100644
index 0dbddcc..0000000
--- a/kernel/os/src/arch/pic32mz/os_arch_pic32mz.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include "os/os.h"
-#include "os/os_arch.h"
-#include "syscfg/syscfg.h"
-#include <hal/hal_bsp.h>
-#include <hal/hal_os_tick.h>
-
-#include "os_priv.h"
-
-#include <string.h>
-
-extern void SVC_Handler(void);
-extern void PendSV_Handler(void);
-extern void SysTick_Handler(void);
-
-struct ctx {
- uint32_t regs[31];
- uint32_t epc;
- uint32_t badvaddr;
- uint32_t status;
- uint32_t cause;
-};
-
-/* XXX: determine how to deal with running un-privileged */
-/* only priv currently supported */
-uint32_t os_flags = OS_RUN_PRIV;
-
-extern struct os_task g_idle_task;
-
-/* core timer interrupt */
-void __attribute__((interrupt(IPL1AUTO),
-vector(_CORE_TIMER_VECTOR))) isr_core_timer(void)
-{
- timer_handler();
- _CP0_SET_COMPARE(_CP0_GET_COMPARE() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) / 1000));
- IFS0CLR = _IFS0_CTIF_MASK;
-}
-
-/* context switch interrupt, in ctx.S */
-void __attribute__((interrupt(IPL1AUTO),
-vector(_CORE_SOFTWARE_0_VECTOR))) isr_sw0(void);
-
-static int
-os_in_isr(void)
-{
- /* check the EXL bit */
- return (_CP0_GET_STATUS() & _CP0_STATUS_EXL_MASK) ? 1 : 0;
-}
-
-void
-timer_handler(void)
-{
- os_time_advance(1);
-}
-
-void
-os_arch_ctx_sw(struct os_task *t)
-{
- if ((os_sched_get_current_task() != 0) && (t != 0)) {
- os_sched_ctx_sw_hook(t);
- }
-
- IFS0SET = _IFS0_CS0IF_MASK;
-}
-
-os_sr_t
-os_arch_save_sr(void)
-{
- os_sr_t sr;
- OS_ENTER_CRITICAL(sr);
- return sr;
-}
-
-void
-os_arch_restore_sr(os_sr_t isr_ctx)
-{
- OS_EXIT_CRITICAL(isr_ctx);
-}
-
-int
-os_arch_in_critical(void)
-{
- return OS_IS_CRITICAL();
-}
-
-uint32_t get_global_pointer(void);
-
-/* assumes stack_top will be 8 aligned */
-
-os_stack_t *
-os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size)
-{
- os_stack_t *s = stack_top - ((((sizeof(struct ctx) - 1) /
- OS_STACK_ALIGNMENT) + 1) * 2);
-
- struct ctx ctx;
-
- ctx.regs[3] = (uint32_t)t->t_arg;
- ctx.regs[27] = get_global_pointer();
- ctx.regs[28] = (uint32_t)(stack_top - 4);
- ctx.status = _CP0_GET_STATUS() | _CP0_STATUS_IE_MASK;
- ctx.cause = _CP0_GET_CAUSE();
- ctx.epc = (uint32_t)t->t_func;
- /* copy struct onto the stack */
- memcpy(s, &ctx, sizeof(ctx));
-
- return (s);
-}
-
-void
-os_arch_init(void)
-{
- os_init_idle_task();
-}
-
-os_error_t
-os_arch_os_init(void)
-{
- os_error_t err;
-
- err = OS_ERR_IN_ISR;
- if (os_in_isr() == 0) {
- err = OS_OK;
- os_sr_t sr;
- OS_ENTER_CRITICAL(sr);
-
- _CP0_BIC_STATUS(_CP0_STATUS_IPL_MASK);
- /* multi vector mode */
- INTCONSET = _INTCON_MVEC_MASK;
- /* vector spacing 0x20 */
- _CP0_SET_INTCTL(_CP0_GET_INTCTL() | (1 << _CP0_INTCTL_VS_POSITION));
-
- /* enable core timer interrupt */
- IEC0SET = _IEC0_CTIE_MASK;
- /* set interrupt priority */
- IPC0CLR = _IPC0_CTIP_MASK;
- IPC0SET = (1 << _IPC0_CTIP_POSITION); // priority 1
- /* set interrupt subpriority */
- IPC0CLR = _IPC0_CTIS_MASK;
- IPC0SET = (0 << _IPC0_CTIS_POSITION); // subpriority 0
-
- /* enable software interrupt 0 */
- IEC0SET = _IEC0_CS0IE_MASK;
- /* set interrupt priority */
- IPC0CLR = _IPC0_CS0IP_MASK;
- IPC0SET = (1 << _IPC0_CS0IP_POSITION); // priority 1
- /* set interrupt subpriority */
- IPC0CLR = _IPC0_CS0IS_MASK;
- IPC0SET = (0 << _IPC0_CS0IS_POSITION); // subpriority 0
-
- OS_EXIT_CRITICAL(sr);
-
- /* should be in kernel mode here */
- os_arch_init();
- }
- return err;
-}
-
-uint32_t
-os_arch_start(void)
-{
- struct os_task *t;
-
- /* Get the highest priority ready to run to set the current task */
- t = os_sched_next_task();
-
- /* set the core timer compare register */
- _CP0_SET_COMPARE(_CP0_GET_COUNT() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) / 1000));
-
- /* global interrupt enable */
- __builtin_enable_interrupts();
-
- /* Mark the OS as started, right before we run our first task */
- g_os_started = 1;
-
- /* Perform context switch to first task */
- os_arch_ctx_sw(t);
-
- return (uint32_t)(t->t_arg);
-}
-
-os_error_t
-os_arch_os_start(void)
-{
- os_error_t err;
-
- err = OS_OK; // OS_ERR_IN_ISR
- if (os_in_isr() == 0) {
- err = OS_OK;
- /* should be in kernel mode here */
- os_arch_start();
- }
-
- return err;
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/039dd455/kernel/os/src/arch/pic32mz/os_fault.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mz/os_fault.c b/kernel/os/src/arch/pic32mz/os_fault.c
deleted file mode 100644
index 5dc952a..0000000
--- a/kernel/os/src/arch/pic32mz/os_fault.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <console/console.h>
-#include <hal/hal_system.h>
-#ifdef COREDUMP_PRESENT
-#include <coredump/coredump.h>
-#endif
-#include "os/os.h"
-
-#include <stdint.h>
-#include <unistd.h>
-
-struct exception_frame {
- uint32_t r0;
- uint32_t r1;
- uint32_t r2;
- uint32_t r3;
- uint32_t r12;
- uint32_t lr;
- uint32_t pc;
- uint32_t psr;
-};
-
-struct trap_frame {
- struct exception_frame *ef;
- uint32_t r4;
- uint32_t r5;
- uint32_t r6;
- uint32_t r7;
- uint32_t r8;
- uint32_t r9;
- uint32_t r10;
- uint32_t r11;
- uint32_t lr; /* this LR holds EXC_RETURN */
-};
-
-struct coredump_regs {
- uint32_t r0;
- uint32_t r1;
- uint32_t r2;
- uint32_t r3;
- uint32_t r4;
- uint32_t r5;
- uint32_t r6;
- uint32_t r7;
- uint32_t r8;
- uint32_t r9;
- uint32_t r10;
- uint32_t r11;
- uint32_t r12;
- uint32_t sp;
- uint32_t lr;
- uint32_t pc;
- uint32_t psr;
-};
-
-#ifdef COREDUMP_PRESENT
-static void
-trap_to_coredump(struct trap_frame *tf, struct coredump_regs *regs)
-{
-}
-#endif
-
-void
-__assert_func(const char *file, int line, const char *func, const char *e)
-{
- int sr;
-
- OS_ENTER_CRITICAL(sr);
- (void)sr;
- console_blocking_mode();
- console_printf("Assert @ 0x%x\n",
- (unsigned int)__builtin_return_address(0));
- if (hal_debugger_connected()) {
- /*
- * If debugger is attached, breakpoint before the trap.
- */
- }
- hal_system_reset();
-}
-
-void
-os_default_irq(struct trap_frame *tf)
-{
-#ifdef COREDUMP_PRESENT
- struct coredump_regs regs;
-#endif
-
- console_blocking_mode();
- console_printf("Unhandled interrupt, exception sp 0x%08lx\n",
- (uint32_t)tf->ef);
- console_printf(" r0:0x%08lx r1:0x%08lx r2:0x%08lx r3:0x%08lx\n",
- tf->ef->r0, tf->ef->r1, tf->ef->r2, tf->ef->r3);
- console_printf(" r4:0x%08lx r5:0x%08lx r6:0x%08lx r7:0x%08lx\n",
- tf->r4, tf->r5, tf->r6, tf->r7);
- console_printf(" r8:0x%08lx r9:0x%08lx r10:0x%08lx r11:0x%08lx\n",
- tf->r8, tf->r9, tf->r10, tf->r11);
- console_printf("r12:0x%08lx lr:0x%08lx pc:0x%08lx psr:0x%08lx\n",
- tf->ef->r12, tf->ef->lr, tf->ef->pc, tf->ef->psr);
-#ifdef COREDUMP_PRESENT
- trap_to_coredump(tf, ®s);
- coredump_dump(®s, sizeof(regs));
-#endif
- hal_system_reset();
-}
[6/7] incubator-mynewt-core git commit: Removed include path,
included specific parts of the Microchip SDK, fixed some errant capitalisation
Posted by ma...@apache.org.
Removed include path, included specific parts of the Microchip SDK, fixed some errant capitalisation
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/2e8de777
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/2e8de777
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/2e8de777
Branch: refs/heads/master
Commit: 2e8de77739024d616c7846a2d224c1d876ce912d
Parents: 039dd45
Author: julian <ju...@imgtec.com>
Authored: Thu Apr 13 16:45:05 2017 +0100
Committer: julian <ju...@imgtec.com>
Committed: Thu Apr 13 16:45:05 2017 +0100
----------------------------------------------------------------------
compiler/xc32/compiler.yml | 2 +-
hw/bsp/pic32mx470_6LP_clicker/bsp.yml | 53 -
hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h | 52 -
.../include/bsp/bsp_sysid.h | 36 -
hw/bsp/pic32mx470_6LP_clicker/pkg.yml | 46 -
hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c | 27 -
hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c | 85 -
hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c | 51 -
hw/bsp/pic32mx470_6LP_clicker/syscfg.yml | 41 -
hw/bsp/pic32mx470_6lp_clicker/bsp.yml | 53 +
hw/bsp/pic32mx470_6lp_clicker/include/bsp/bsp.h | 52 +
.../include/bsp/bsp_sysid.h | 36 +
hw/bsp/pic32mx470_6lp_clicker/pkg.yml | 46 +
hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c | 27 +
hw/bsp/pic32mx470_6lp_clicker/src/os_bsp.c | 85 +
hw/bsp/pic32mx470_6lp_clicker/src/sbrk.c | 51 +
hw/bsp/pic32mx470_6lp_clicker/syscfg.yml | 41 +
.../pic32mx470F512H/include/mcu/mips_bsp.h | 24 -
.../pic32mx470F512H/include/mcu/mips_hal.h | 39 -
.../pic32mx470F512H/include/mcu/pic32.h | 25 -
hw/mcu/microchip/pic32mx470F512H/pkg.yml | 31 -
.../microchip/pic32mx470F512H/src/hal_os_tick.c | 36 -
.../microchip/pic32mx470F512H/src/hal_system.c | 35 -
hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c | 463 -
.../pic32mx470F512H/src/hal_watchdog.c | 39 -
.../microchip/pic32mx470f512h/include/mcu/mcu.h | 25 +
.../pic32mx470f512h/include/mcu/mips_bsp.h | 24 +
.../pic32mx470f512h/include/mcu/mips_hal.h | 39 +
.../pic32mx470f512h/include/mcu/p32mx470f512h.h | 17933 ++++++
.../pic32mx470f512h/include/mcu/pic32.h | 25 +
.../pic32mx470f512h/include/mcu/ppic32mx.h | 1280 +
hw/mcu/microchip/pic32mx470f512h/pkg.yml | 31 +
.../microchip/pic32mx470f512h/src/hal_os_tick.c | 36 +
.../microchip/pic32mx470f512h/src/hal_system.c | 35 +
hw/mcu/microchip/pic32mx470f512h/src/hal_uart.c | 463 +
.../pic32mx470f512h/src/hal_watchdog.c | 39 +
.../pic32mz2048efg100/include/mcu/mcu.h | 25 +
.../include/mcu/p32mz2048efg100.h | 51671 +++++++++++++++++
kernel/os/include/os/arch/pic32/os/cp0defs.h | 1215 +
.../os/include/os/arch/pic32/os/os_arch_defs.h | 60 +
kernel/os/src/arch/pic32/asm/ctx.S | 3 +-
41 files changed, 73295 insertions(+), 1085 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/compiler/xc32/compiler.yml
----------------------------------------------------------------------
diff --git a/compiler/xc32/compiler.yml b/compiler/xc32/compiler.yml
index 8bf1567..611497e 100644
--- a/compiler/xc32/compiler.yml
+++ b/compiler/xc32/compiler.yml
@@ -24,7 +24,7 @@ compiler.path.objdump: "xc32-objdump"
compiler.path.objsize: "xc32-size"
compiler.path.objcopy: "xc32-objcopy"
-compiler.flags.base: -I/opt/microchip/xc32/v1.42/pic32mx/include -std=gnu11
+compiler.flags.base: -std=gnu11
compiler.flags.default: [compiler.flags.base, -O2, -g3]
compiler.flags.optimized: [compiler.flags.base, -Os -g3]
compiler.flags.debug: [compiler.flags.base, -g3]
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6LP_clicker/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/bsp.yml b/hw/bsp/pic32mx470_6LP_clicker/bsp.yml
deleted file mode 100644
index c1d3d4c..0000000
--- a/hw/bsp/pic32mx470_6LP_clicker/bsp.yml
+++ /dev/null
@@ -1,53 +0,0 @@
-#
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements. See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership. The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License. You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied. See the License for the
-# specific language governing permissions and limitations
-# under the License.
-#
-
-bsp.arch: pic32
-bsp.compiler: compiler/xc32
-
-bsp.flash_map:
- areas:
- # System areas.
- FLASH_AREA_BOOTLOADER:
- device: 0
- offset: 0x00000000
- size: 0kB
- FLASH_AREA_IMAGE_0:
- device: 0
- offset: 0x00000000
- size: 0kB
- FLASH_AREA_IMAGE_1:
- device: 0
- offset: 0x00000000
- size: 0kB
- FLASH_AREA_IMAGE_SCRATCH:
- device: 0
- offset: 0x00000000
- size: 0kB
-
- # User areas.
- FLASH_AREA_REBOOT_LOG:
- user_id: 0
- device: 0
- offset: 0x00000000
- size: 0kB
- FLASH_AREA_NFFS:
- user_id: 1
- device: 0
- offset: 0x00000000
- size: 0kB
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h b/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h
deleted file mode 100644
index b3c219e..0000000
--- a/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-#ifndef H_BSP_H
-#define H_BSP_H
-
-#include <inttypes.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Define special stackos sections */
-#define sec_data_core __attribute__((section(".data.core")))
-#define sec_bss_core __attribute__((section(".bss.core")))
-#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
-
-/* More convenient section placement macros. */
-#define bssnz_t sec_bss_nz_core
-
-extern uint8_t _ram_start;
-extern uint8_t _ccram_start;
-
-#define RAM_SIZE (128 * 1024)
-#define CCRAM_SIZE (64 * 1024)
-
-/* UART */
-#define UART_CNT 4
-#define CONSOLE_UART "uart2"
-
-#define NFFS_AREA_MAX (8)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* H_BSP_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp_sysid.h
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp_sysid.h b/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp_sysid.h
deleted file mode 100644
index 7b0a24b..0000000
--- a/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp_sysid.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-#ifndef BSP_SYSID_H
-#define BSP_SYSID_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* stub until this BSP gets new HAL */
-enum system_device_id
-{
- RESERVED,
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* BSP_SYSID_H */
\ No newline at end of file
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6LP_clicker/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/pkg.yml b/hw/bsp/pic32mx470_6LP_clicker/pkg.yml
deleted file mode 100644
index bf2a1ed..0000000
--- a/hw/bsp/pic32mx470_6LP_clicker/pkg.yml
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements. See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership. The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License. You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied. See the License for the
-# specific language governing permissions and limitations
-# under the License.
-#
-
-pkg.name: hw/bsp/pic32mx470_6LP_clicker
-pkg.type: bsp
-pkg.description: BSP definition for the 6LoWPAN Clicker board.
-pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
-pkg.homepage: "http://mynewt.apache.org/"
-pkg.keywords:
- - pic32
- - microchip
- - clicker
-
-pkg.lflags:
- - -Wl,--defsym=_min_heap_size=0x400
-
-pkg.deps:
- - hw/mcu/microchip/pic32mx470f512h
-
-pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
-
-pkg.deps.UART_1:
- - hw/drivers/uart/uart_hal
-
-pkg.deps.UART_2:
- - hw/drivers/uart/uart_hal
-
-pkg.deps.UART_3:
- - hw/drivers/uart/uart_hal
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c b/hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c
deleted file mode 100644
index c1187c6..0000000
--- a/hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-#include "hal/hal_bsp.h"
-#include "bsp/bsp.h"
-#include <assert.h>
-
-const struct hal_flash *
-bsp_flash_dev(uint8_t id)
-{
- return 0;
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c b/hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c
deleted file mode 100644
index 8add7e2..0000000
--- a/hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include "hal/hal_bsp.h"
-#include "syscfg/syscfg.h"
-#include "uart/uart.h"
-#if MYNEWT_VAL(UART_0) || MYNEWT_VAL(UART_1)
-#include "uart_hal/uart_hal.h"
-#endif
-
-#include <xc.h>
-
-#include <assert.h>
-
-#pragma config CP=1, FWDTEN=0, FCKSM=1, FPBDIV=1, OSCIOFNC=1, POSCMOD=1
-/* PLL conf div in: 2, mul: 20, div out: 1 8->4->80->80 */
-#pragma config FNOSC=3, FPLLODIV=0, UPLLEN=1, FPLLMUL=5, FPLLIDIV=1, FSRSSEL=7
-/* PGEC2/PGED2 pair is used */
-#pragma config ICESEL=2
-
-#if MYNEWT_VAL(UART_0)
-static struct uart_dev os_bsp_uart0;
-#endif
-
-#if MYNEWT_VAL(UART_1)
-static struct uart_dev os_bsp_uart1;
-#endif
-
-#if MYNEWT_VAL(UART_2)
-static struct uart_dev os_bsp_uart2;
-#endif
-
-#if MYNEWT_VAL(UART_3)
-static struct uart_dev os_bsp_uart3;
-#endif
-
-void _close(int fd);
-
-void
-hal_bsp_init(void)
-{
- int rc;
-
-#if MYNEWT_VAL(UART_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(UART_1)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart1, "uart1",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(UART_2)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart2, "uart2",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(UART_3)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart3, "uart3",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
- assert(rc == 0);
-#endif
-
- (void)rc;
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c b/hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c
deleted file mode 100644
index d3f99d6..0000000
--- a/hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#define HEAPSIZE (1024)
-
-static char __Heap[HEAPSIZE];
-
-void *
-_sbrk(int incr)
-{
- static char *brk = __Heap;
-
- void *prev_brk;
-
- if (incr < 0) {
- /* Returning memory to the heap. */
- incr = -incr;
- if (brk - incr < __Heap) {
- prev_brk = (void *)-1;
- } else {
- prev_brk = brk;
- brk -= incr;
- }
- } else {
- /* Allocating memory from the heap. */
- if ((__Heap + HEAPSIZE) - brk >= incr) {
- prev_brk = brk;
- brk += incr;
- } else {
- prev_brk = (void *)-1;
- }
- }
-
- return prev_brk;
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6LP_clicker/syscfg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/syscfg.yml b/hw/bsp/pic32mx470_6LP_clicker/syscfg.yml
deleted file mode 100644
index 87c4e47..0000000
--- a/hw/bsp/pic32mx470_6LP_clicker/syscfg.yml
+++ /dev/null
@@ -1,41 +0,0 @@
-#
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements. See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership. The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License. You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied. See the License for the
-# specific language governing permissions and limitations
-# under the License.
-#
-
-# Package: hw/bsp/pic32mx470_6LP_clicker
-
-syscfg.defs:
- CLOCK_FREQ:
- description: 'TBD'
- value: 80000000ul
-
- UART_0:
- description: 'TBD'
- value: 1
-
- UART_1:
- description: 'TBD'
- value: 1
-
- UART_2:
- description: 'TBD'
- value: 1
-
- UART_3:
- description: 'TBD'
- value: 1
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6lp_clicker/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6lp_clicker/bsp.yml b/hw/bsp/pic32mx470_6lp_clicker/bsp.yml
new file mode 100644
index 0000000..c1d3d4c
--- /dev/null
+++ b/hw/bsp/pic32mx470_6lp_clicker/bsp.yml
@@ -0,0 +1,53 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.arch: pic32
+bsp.compiler: compiler/xc32
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x00000000
+ size: 0kB
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6lp_clicker/include/bsp/bsp.h
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6lp_clicker/include/bsp/bsp.h b/hw/bsp/pic32mx470_6lp_clicker/include/bsp/bsp.h
new file mode 100644
index 0000000..b3c219e
--- /dev/null
+++ b/hw/bsp/pic32mx470_6lp_clicker/include/bsp/bsp.h
@@ -0,0 +1,52 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start;
+extern uint8_t _ccram_start;
+
+#define RAM_SIZE (128 * 1024)
+#define CCRAM_SIZE (64 * 1024)
+
+/* UART */
+#define UART_CNT 4
+#define CONSOLE_UART "uart2"
+
+#define NFFS_AREA_MAX (8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6lp_clicker/include/bsp/bsp_sysid.h
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6lp_clicker/include/bsp/bsp_sysid.h b/hw/bsp/pic32mx470_6lp_clicker/include/bsp/bsp_sysid.h
new file mode 100644
index 0000000..7b0a24b
--- /dev/null
+++ b/hw/bsp/pic32mx470_6lp_clicker/include/bsp/bsp_sysid.h
@@ -0,0 +1,36 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef BSP_SYSID_H
+#define BSP_SYSID_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* stub until this BSP gets new HAL */
+enum system_device_id
+{
+ RESERVED,
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_SYSID_H */
\ No newline at end of file
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6lp_clicker/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6lp_clicker/pkg.yml b/hw/bsp/pic32mx470_6lp_clicker/pkg.yml
new file mode 100644
index 0000000..2e4242c
--- /dev/null
+++ b/hw/bsp/pic32mx470_6lp_clicker/pkg.yml
@@ -0,0 +1,46 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/pic32mx470_6lp_clicker
+pkg.type: bsp
+pkg.description: BSP definition for the 6LoWPAN Clicker board.
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+ - microchip
+ - clicker
+
+pkg.lflags:
+ - -Wl,--defsym=_min_heap_size=0x400
+
+pkg.deps:
+ - hw/mcu/microchip/pic32mx470f512h
+
+pkg.deps.UART_0:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_1:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_2:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_3:
+ - hw/drivers/uart/uart_hal
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c b/hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c
new file mode 100644
index 0000000..c1187c6
--- /dev/null
+++ b/hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c
@@ -0,0 +1,27 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include "hal/hal_bsp.h"
+#include "bsp/bsp.h"
+#include <assert.h>
+
+const struct hal_flash *
+bsp_flash_dev(uint8_t id)
+{
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6lp_clicker/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6lp_clicker/src/os_bsp.c b/hw/bsp/pic32mx470_6lp_clicker/src/os_bsp.c
new file mode 100644
index 0000000..8add7e2
--- /dev/null
+++ b/hw/bsp/pic32mx470_6lp_clicker/src/os_bsp.c
@@ -0,0 +1,85 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_bsp.h"
+#include "syscfg/syscfg.h"
+#include "uart/uart.h"
+#if MYNEWT_VAL(UART_0) || MYNEWT_VAL(UART_1)
+#include "uart_hal/uart_hal.h"
+#endif
+
+#include <xc.h>
+
+#include <assert.h>
+
+#pragma config CP=1, FWDTEN=0, FCKSM=1, FPBDIV=1, OSCIOFNC=1, POSCMOD=1
+/* PLL conf div in: 2, mul: 20, div out: 1 8->4->80->80 */
+#pragma config FNOSC=3, FPLLODIV=0, UPLLEN=1, FPLLMUL=5, FPLLIDIV=1, FSRSSEL=7
+/* PGEC2/PGED2 pair is used */
+#pragma config ICESEL=2
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev os_bsp_uart1;
+#endif
+
+#if MYNEWT_VAL(UART_2)
+static struct uart_dev os_bsp_uart2;
+#endif
+
+#if MYNEWT_VAL(UART_3)
+static struct uart_dev os_bsp_uart3;
+#endif
+
+void _close(int fd);
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_2)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart2, "uart2",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_3)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart3, "uart3",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+#endif
+
+ (void)rc;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6lp_clicker/src/sbrk.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6lp_clicker/src/sbrk.c b/hw/bsp/pic32mx470_6lp_clicker/src/sbrk.c
new file mode 100644
index 0000000..d3f99d6
--- /dev/null
+++ b/hw/bsp/pic32mx470_6lp_clicker/src/sbrk.c
@@ -0,0 +1,51 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#define HEAPSIZE (1024)
+
+static char __Heap[HEAPSIZE];
+
+void *
+_sbrk(int incr)
+{
+ static char *brk = __Heap;
+
+ void *prev_brk;
+
+ if (incr < 0) {
+ /* Returning memory to the heap. */
+ incr = -incr;
+ if (brk - incr < __Heap) {
+ prev_brk = (void *)-1;
+ } else {
+ prev_brk = brk;
+ brk -= incr;
+ }
+ } else {
+ /* Allocating memory from the heap. */
+ if ((__Heap + HEAPSIZE) - brk >= incr) {
+ prev_brk = brk;
+ brk += incr;
+ } else {
+ prev_brk = (void *)-1;
+ }
+ }
+
+ return prev_brk;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/bsp/pic32mx470_6lp_clicker/syscfg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6lp_clicker/syscfg.yml b/hw/bsp/pic32mx470_6lp_clicker/syscfg.yml
new file mode 100644
index 0000000..8d0fd17
--- /dev/null
+++ b/hw/bsp/pic32mx470_6lp_clicker/syscfg.yml
@@ -0,0 +1,41 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Package: hw/bsp/pic32mx470_6lp_clicker
+
+syscfg.defs:
+ CLOCK_FREQ:
+ description: 'TBD'
+ value: 80000000ul
+
+ UART_0:
+ description: 'TBD'
+ value: 1
+
+ UART_1:
+ description: 'TBD'
+ value: 1
+
+ UART_2:
+ description: 'TBD'
+ value: 1
+
+ UART_3:
+ description: 'TBD'
+ value: 1
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_bsp.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_bsp.h b/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_bsp.h
deleted file mode 100644
index 01d75f4..0000000
--- a/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_bsp.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-#ifndef H_MIPS_BSP_
-#define H_MIPS_BSP_
-
-extern const struct hal_flash native_flash_dev;
-
-#endif /* H_NATIVE_BSP_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_hal.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_hal.h b/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_hal.h
deleted file mode 100644
index f29bd2a..0000000
--- a/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_hal.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-/* This file defines the HAL implementations within this MCU */
-
-#ifndef MIPS_HAL_H
-#define MIPS_HAL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Helper functions to enable/disable interrupts. */
-#define __HAL_DISABLE_INTERRUPTS(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
- __builtin_disable_interrupts();} while(0)
-
-#define __HAL_ENABLE_INTERRUPTS(__os_sr) __builtin_set_isr_state(__os_sr)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MCU_HAL_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32.h b/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32.h
deleted file mode 100644
index 6dccd82..0000000
--- a/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#ifndef __MCU_PIC32_H__
-#define __MCU_PIC32_H__
-
-#define OS_TICKS_PER_SEC (1000)
-
-#endif /* __MCU_PIC32_H__ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470F512H/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/pkg.yml b/hw/mcu/microchip/pic32mx470F512H/pkg.yml
deleted file mode 100644
index 41abc7d..0000000
--- a/hw/mcu/microchip/pic32mx470F512H/pkg.yml
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements. See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership. The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License. You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied. See the License for the
-# specific language governing permissions and limitations
-# under the License.
-#
-
-pkg.name: hw/mcu/microchip/pic32mx470F512H
-pkg.description: MCU definition for the Microchip PIC32MX470F512H microcontroller.
-pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
-pkg.homepage: "http://mynewt.apache.org/"
-pkg.keywords:
- - pic32
-
-pkg.cflags:
- - -mprocessor=32MX470F512H
-pkg.deps:
- - hw/hal
- - compiler/xc32
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470F512H/src/hal_os_tick.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/src/hal_os_tick.c b/hw/mcu/microchip/pic32mx470F512H/src/hal_os_tick.c
deleted file mode 100644
index 8fc68d6..0000000
--- a/hw/mcu/microchip/pic32mx470F512H/src/hal_os_tick.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include <os/os.h>
-#include <hal/hal_os_tick.h>
-
-/*
- * XXX implement tickless mode.
- */
-void
-os_tick_idle(os_time_t ticks)
-{
- OS_ASSERT_CRITICAL();
-}
-
-void
-os_tick_init(uint32_t os_ticks_per_sec, int prio)
-{
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470F512H/src/hal_system.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/src/hal_system.c b/hw/mcu/microchip/pic32mx470F512H/src/hal_system.c
deleted file mode 100644
index ed6e6a3..0000000
--- a/hw/mcu/microchip/pic32mx470F512H/src/hal_system.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include "hal/hal_system.h"
-
-#include <stdint.h>
-
-void
-hal_system_reset(void)
-{
- while (1) {
- }
-}
-
-int
-hal_debugger_connected(void)
-{
- return 0;
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c b/hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c
deleted file mode 100644
index 93eff5b..0000000
--- a/hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c
+++ /dev/null
@@ -1,463 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include "hal/hal_uart.h"
-#include "bsp/bsp.h"
-#include "syscfg/syscfg.h"
-#include "mcu/mips_hal.h"
-#include <assert.h>
-#include <stdlib.h>
-
-#include <xc.h>
-
-struct hal_uart {
- volatile uint8_t u_rx_stall:1;
- volatile uint8_t u_rx_data;
- hal_uart_rx_char u_rx_func;
- hal_uart_tx_char u_tx_func;
- hal_uart_tx_done u_tx_done;
- void *u_func_arg;
-};
-static struct hal_uart uarts[UART_CNT];
-
-int
-hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
- hal_uart_rx_char rx_func, void *arg)
-{
- uarts[port].u_rx_func = rx_func;
- uarts[port].u_tx_func = tx_func;
- uarts[port].u_tx_done = tx_done;
- uarts[port].u_func_arg = arg;
- return 0;
-}
-
-static void
-uart_disable_tx_int(int port)
-{
- switch (port) {
- case 0:
- IEC1CLR = _IEC1_U1TXIE_MASK;
- break;
- case 1:
- IEC1CLR = _IEC1_U2TXIE_MASK;
- break;
- case 2:
- IEC2CLR = _IEC2_U3TXIE_MASK;
- break;
- case 3:
- IEC2CLR = _IEC2_U4TXIE_MASK;
- break;
- }
-}
-
-static void
-uart_enable_tx_int(int port)
-{
- switch (port) {
- case 0:
- IEC1SET = _IEC1_U1TXIE_MASK;
- break;
- case 1:
- IEC1SET = _IEC1_U2TXIE_MASK;
- break;
- case 2:
- IEC2SET = _IEC2_U3TXIE_MASK;
- break;
- case 3:
- IEC2SET = _IEC2_U4TXIE_MASK;
- break;
- }
-}
-
-static void
-uart_disable_rx_int(int port)
-{
- switch (port) {
- case 0:
- IEC1CLR = _IEC1_U1RXIE_MASK;
- break;
- case 1:
- IEC1CLR = _IEC1_U2RXIE_MASK;
- break;
- case 2:
- IEC1CLR = _IEC1_U3RXIE_MASK;
- break;
- case 3:
- IEC2CLR = _IEC2_U4RXIE_MASK;
- break;
- }
-}
-
-static void
-uart_enable_rx_int(int port)
-{
- switch (port) {
- case 0:
- IEC1SET = _IEC1_U1RXIE_MASK;
- break;
- case 1:
- IEC1SET = _IEC1_U2RXIE_MASK;
- break;
- case 2:
- IEC1SET = _IEC1_U3RXIE_MASK;
- break;
- case 3:
- IEC2SET = _IEC2_U4RXIE_MASK;
- break;
- }
-}
-
-static void
-uart_receive_ready(int port)
-{
- switch (port) {
- case 0:
- uarts[port].u_rx_data = U1RXREG;
- break;
- case 1:
- uarts[port].u_rx_data = U2RXREG;
- break;
- case 2:
- uarts[port].u_rx_data = U3RXREG;
- break;
- case 3:
- uarts[port].u_rx_data = U4RXREG;
- break;
- }
-
- int c = uarts[port].u_rx_func(uarts[port].u_func_arg,
- uarts[port].u_rx_data);
- if (c < 0) {
- uart_disable_rx_int(port);
- uarts[port].u_rx_stall = 1;
- }
-}
-
-static void
-uart_transmit_ready(int port)
-{
- int c = uarts[port].u_tx_func(uarts[port].u_func_arg);
- if (c < 0) {
- uart_disable_tx_int(port);
-
- /* call tx done cb */
- if (uarts[port].u_tx_done) {
- uarts[port].u_tx_done(uarts[port].u_func_arg);
- }
- } else {
- /* write char out */
- switch (port) {
- case 0:
- U1TXREG = (uint32_t)c & 0xff;
- break;
- case 1:
- U2TXREG = (uint32_t)c & 0xff;
- break;
- case 2:
- U3TXREG = (uint32_t)c & 0xff;
- break;
- case 3:
- U4TXREG = (uint32_t)c & 0xff;
- break;
- }
- }
-}
-
-void
-__attribute__((interrupt(IPL1AUTO), vector(_UART_1_VECTOR))) uart_1_isr(void)
-{
- uint32_t sta = U1STA;
- if (sta & _U1STA_URXDA_MASK) {
- uart_receive_ready(0);
- IFS1CLR = _IFS1_U1RXIF_MASK;
- }
- if (sta & _U1STA_TRMT_MASK) {
- uart_transmit_ready(0);
- IFS1CLR = _IFS1_U1TXIF_MASK;
- }
-}
-
-void
-__attribute__((interrupt(IPL1AUTO), vector(_UART_2_VECTOR))) uart_2_isr(void)
-{
- uint32_t sta = U2STA;
- if (sta & _U2STA_URXDA_MASK) {
- uart_receive_ready(1);
- IFS1CLR = _IFS1_U2RXIF_MASK;
- }
- if (sta & _U2STA_TRMT_MASK) {
- uart_transmit_ready(1);
- IFS1CLR = _IFS1_U2TXIF_MASK;
- }
-}
-
-void
-__attribute__((interrupt(IPL1AUTO), vector(_UART_3_VECTOR))) uart_3_isr(void)
-{
- uint32_t sta = U3STA;
- if (sta & _U3STA_URXDA_MASK) {
- uart_receive_ready(2);
- IFS1CLR = _IFS1_U3RXIF_MASK;
- }
- if (sta & _U3STA_TRMT_MASK) {
- uart_transmit_ready(2);
- IFS2CLR = _IFS2_U3TXIF_MASK;
- }
-}
-
-void
-__attribute__((interrupt(IPL1AUTO), vector(_UART_4_VECTOR))) uart_4_isr(void)
-{
- uint32_t sta = U4STA;
- if (sta & _U4STA_URXDA_MASK) {
- uart_receive_ready(3);
- IFS2CLR = _IFS2_U4RXIF_MASK;
- }
- if (sta & _U4STA_TRMT_MASK) {
- uart_transmit_ready(3);
- IFS2CLR = _IFS2_U4TXIF_MASK;
- }
-}
-
-void
-hal_uart_start_rx(int port)
-{
- if (uarts[port].u_rx_stall) {
- /* recover saved data */
- uint32_t sr;
- __HAL_DISABLE_INTERRUPTS(sr);
- int c = uarts[port].u_rx_func(uarts[port].u_func_arg,
- uarts[port].u_rx_data);
- if (c >= 0) {
- uarts[port].u_rx_stall = 0;
- /* enable RX interrupt */
- uart_enable_rx_int(port);
- }
- __HAL_ENABLE_INTERRUPTS(sr);
- }
-}
-
-void
-hal_uart_start_tx(int port)
-{
- uart_enable_tx_int(port);
-}
-
-void
-hal_uart_blocking_tx(int port, uint8_t data)
-{
- switch (port){
- case 0:
- /* wait for transmit holding register to be empty */
- while(!(U1STA & _U1STA_TRMT_MASK)) {
- }
- /* write to transmit register */
- U1TXREG = data;
- break;
- case 1:
- /* wait for transmit holding register to be empty */
- while(!(U2STA & _U2STA_TRMT_MASK)) {
- }
- /* write to transmit register */
- U2TXREG = data;
- break;
- case 2:
- /* wait for transmit holding register to be empty */
- while(!(U3STA & _U3STA_TRMT_MASK)) {
- }
- /* write to transmit register */
- U3TXREG = data;
- break;
- case 3:
- /* wait for transmit holding register to be empty */
- while(!(U4STA & _U4STA_TRMT_MASK)) {
- }
- /* write to transmit register */
- U4TXREG = data;
- break;
- }
-}
-
-int
-hal_uart_init(int port, void *arg)
-{
- return 0;
-}
-
-int
-hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
- enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
-{
- uint32_t peripheral_clk = MYNEWT_VAL(CLOCK_FREQ) / 2;
-
- // check input
- if ((databits < 8) || (databits > 9) || (stopbits < 1) || (stopbits > 2)) {
- return -1;
- }
-
- /* XXX: flow control currently unsupported */
- (void) flow_ctl;
- uarts[port].u_rx_stall = 0;
-
- uint16_t mode = _U1MODE_BRGH_MASK | (stopbits >> 1);
- switch (parity) {
- case HAL_UART_PARITY_NONE:
- if (databits == 9) {
- mode |= _U1MODE_PDSEL_MASK;
- }
- break;
- case HAL_UART_PARITY_ODD:
- if (databits == 9) { // PIC does not do 9 bit data + parity.
- return -1;
- }
- mode |= _U1MODE_PDSEL1_MASK;
- break;
- case HAL_UART_PARITY_EVEN:
- if (databits == 9) {
- return -1;
- }
- mode |= _U1MODE_PDSEL0_MASK;
- break;
- default:
- return -1;
- }
-
- uint16_t divisor = peripheral_clk / (4 * baudrate) - 1;
-
- switch (port) {
- case 0:
- /* disable */
- U1MODE = 0;
- __asm__("nop");
- U1BRG = divisor;
- U1MODE = mode;
- U1STA = _U1STA_URXEN_MASK | _U1STA_UTXEN_MASK;
- /* clear RX interrupt flag */
- IFS1CLR = _IFS1_U1RXIF_MASK;
-
- /* enable RX interrupt */
- IEC1SET = _IEC1_U1RXIE_MASK;
-
- /* set interrupt priority */
- IPC7CLR = _IPC7_U1IP_MASK;
- IPC7SET = (1 << _IPC7_U1IP_POSITION); // priority 1
- /* set interrupt subpriority */
- IPC7CLR = _IPC7_U1IS_MASK;
- IPC7SET = (0 << _IPC7_U1IS_POSITION); // subpriority 0
- U1MODESET = _U1MODE_ON_MASK;
- break;
- case 1:
- /* disable */
- U2MODE = 0;
- __asm__("nop");
- U2BRG = divisor;
- U2MODE = mode;
- U2STA = _U2STA_URXEN_MASK | _U2STA_UTXEN_MASK;
- /* clear RX interrupt flag */
- IFS1CLR = _IFS1_U2RXIF_MASK;
-
- /* enable RX interrupt */
- IEC1SET = _IEC1_U2RXIE_MASK;
-
- /* set interrupt priority */
- IPC9CLR = _IPC9_U2IP_MASK;
- IPC9SET = (1 << _IPC9_U2IP_POSITION); // priority 1
- /* set interrupt subpriority */
- IPC9CLR = _IPC9_U2IS_MASK;
- IPC9SET = (0 << _IPC9_U2IS_POSITION); // subpriority 0
- U2MODESET = _U2MODE_ON_MASK;
- break;
- case 2:
- /* disable */
- U3MODE = 0;
- __asm__("nop");
- U3BRG = divisor;
- U3MODE = mode;
- U3STA = _U3STA_URXEN_MASK | _U3STA_UTXEN_MASK;
- /* clear RX interrupt flag */
- IFS1CLR = _IFS1_U3RXIF_MASK;
-
- /* enable RX interrupt */
- IEC1SET = _IEC1_U3RXIE_MASK;
-
- /* set interrupt priority */
- IPC9CLR = _IPC9_U3IP_MASK;
- IPC9SET = (1 << _IPC9_U3IP_POSITION); // priority 1
- /* set interrupt subpriority */
- IPC9CLR = _IPC9_U3IS_MASK;
- IPC9SET = (0 << _IPC9_U3IS_POSITION); // subpriority 0
- U3MODESET = _U3MODE_ON_MASK;
- break;
- case 3:
- /* disable */
- U4MODE = 0;
- __asm__("nop");
- U4BRG = divisor;
- U4MODE = mode;
- U4STA = _U4STA_URXEN_MASK | _U4STA_UTXEN_MASK;
- /* clear RX interrupt flag */
- IFS2CLR = _IFS2_U4RXIF_MASK;
-
- /* enable RX interrupt */
- IEC2SET = _IEC2_U4RXIE_MASK;
-
- /* set interrupt priority */
- IPC9CLR = _IPC9_U4IP_MASK;
- IPC9SET = (1 << _IPC9_U4IP_POSITION); // priority 1
- /* set interrupt subpriority */
- IPC9CLR = _IPC9_U4IS_MASK;
- IPC9SET = (0 << _IPC9_U4IS_POSITION); // subpriority 0
- U4MODESET = _U4MODE_ON_MASK;
- break;
- }
- return 0;
-}
-
-int
-hal_uart_close(int port)
-{
- switch(port) {
- case 0:
- /* disable */
- U1MODE = 0;
- /* disable RX interrupt */
- IEC1CLR = _IEC1_U1RXIE_MASK;
- break;
- case 1:
- /* disable */
- U2MODE = 0;
- /* disable RX interrupt */
- IEC1CLR = _IEC1_U2RXIE_MASK;
- break;
- case 2:
- U3MODE = 0;
- /* disable RX interrupt */
- IEC1CLR = _IEC1_U3RXIE_MASK;
- break;
- case 3:
- /* disable */
- U4MODE = 0;
- /* disable RX interrupt */
- IEC2CLR = _IEC2_U4RXIE_MASK;
- break;
- default:
- return -1;
- }
- return 0;
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470F512H/src/hal_watchdog.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/src/hal_watchdog.c b/hw/mcu/microchip/pic32mx470F512H/src/hal_watchdog.c
deleted file mode 100644
index 392b967..0000000
--- a/hw/mcu/microchip/pic32mx470F512H/src/hal_watchdog.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include "hal/hal_watchdog.h"
-
-#include <assert.h>
-
-int
-hal_watchdog_init(uint32_t expire_msecs)
-{
- return (0);
-}
-
-void
-hal_watchdog_enable(void)
-{
-}
-
-void
-hal_watchdog_tickle(void)
-{
-}
-
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/include/mcu/mcu.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/include/mcu/mcu.h b/hw/mcu/microchip/pic32mx470f512h/include/mcu/mcu.h
new file mode 100644
index 0000000..a2d7c8b
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/include/mcu/mcu.h
@@ -0,0 +1,25 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_MCU_H_
+#define __MCU_MCU_H_
+
+#include "p32mx470f512h.h"
+
+#endif /* __MCU_MCU_H_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/include/mcu/mips_bsp.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/include/mcu/mips_bsp.h b/hw/mcu/microchip/pic32mx470f512h/include/mcu/mips_bsp.h
new file mode 100644
index 0000000..01d75f4
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/include/mcu/mips_bsp.h
@@ -0,0 +1,24 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_MIPS_BSP_
+#define H_MIPS_BSP_
+
+extern const struct hal_flash native_flash_dev;
+
+#endif /* H_NATIVE_BSP_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/include/mcu/mips_hal.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/include/mcu/mips_hal.h b/hw/mcu/microchip/pic32mx470f512h/include/mcu/mips_hal.h
new file mode 100644
index 0000000..f29bd2a
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/include/mcu/mips_hal.h
@@ -0,0 +1,39 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* This file defines the HAL implementations within this MCU */
+
+#ifndef MIPS_HAL_H
+#define MIPS_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
+ __builtin_disable_interrupts();} while(0)
+
+#define __HAL_ENABLE_INTERRUPTS(__os_sr) __builtin_set_isr_state(__os_sr)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MCU_HAL_H */
[4/7] incubator-mynewt-core git commit: Removed include path,
included specific parts of the Microchip SDK, fixed some errant capitalisation
Posted by ma...@apache.org.
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/include/mcu/pic32.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/include/mcu/pic32.h b/hw/mcu/microchip/pic32mx470f512h/include/mcu/pic32.h
new file mode 100644
index 0000000..6dccd82
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/include/mcu/pic32.h
@@ -0,0 +1,25 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_PIC32_H__
+#define __MCU_PIC32_H__
+
+#define OS_TICKS_PER_SEC (1000)
+
+#endif /* __MCU_PIC32_H__ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/include/mcu/ppic32mx.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/include/mcu/ppic32mx.h b/hw/mcu/microchip/pic32mx470f512h/include/mcu/ppic32mx.h
new file mode 100644
index 0000000..d4dcc0b
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/include/mcu/ppic32mx.h
@@ -0,0 +1,1280 @@
+/*-------------------------------------------------------------------------
+ * MPLAB C for PIC32MX processor defs
+ *
+ * WARNING:
+ * This file is provided for backwards compatibility with old MPLAB C32
+ * source code only. For new projects, use the corresponding macros from
+ * the /proc/<device>.h file instead of the macros from these files.
+ *
+ * ------------------------------------------------------------------------
+ *
+ * This software is developed by Microchip Technology Inc. and its
+ * subsidiaries ("Microchip").
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. Microchip's name may not be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *-------------------------------------------------------------------------*/
+
+#if !defined(_PPIC32MX_H)
+#define _PPIC32MX_H
+
+/*********************************************************************
+ * INT Definitions
+ *********************************************************************/
+/* In future these defines will move to processor header file. */
+#define _TIMER_23_VECTOR 12
+#define _TIMER_45_VECTOR 20
+
+/* From v1.03, all VECTOR symbols use "_x" convention. These */
+/* are provided for backward compatiblity. */
+#define _SPI1_VECTOR _SPI_1_VECTOR
+#define _SPI2_VECTOR _SPI_2_VECTOR
+#define _UART1_VECTOR _UART_1_VECTOR
+#define _UART2_VECTOR _UART_2_VECTOR
+#define _I2C1_VECTOR _I2C_1_VECTOR
+#define _I2C2_VECTOR _I2C_2_VECTOR
+#define _DMA0_VECTOR _DMA_0_VECTOR
+#define _DMA1_VECTOR _DMA_1_VECTOR
+#define _DMA2_VECTOR _DMA_2_VECTOR
+#define _DMA3_VECTOR _DMA_3_VECTOR
+#define _USB1_VECTOR _USB_1_VECTOR
+
+
+
+/*********************************************************************
+ * INTCON bit defines
+ *********************************************************************/
+#define INTCON_FRZ_BIT 0x00004000L
+#define INTCON_INT4EP_BIT 0x00000010L
+#define INTCON_INT3EP_BIT 0x00000008L
+#define INTCON_INT2EP_BIT 0x00000004L
+#define INTCON_INT1EP_BIT 0x00000002L
+#define INTCON_INT0EP_BIT 0x00000001L
+
+#define INTCON_IPTMR_SHIFT 16
+#define INTCON_TPC_SHIFT 8
+
+#define INTCON_MASK 0xFFFF071F
+
+/*********************************************************************
+ * IF0 -IF2
+ *********************************************************************/
+#define IFS0_CT_BIT 0x00000001
+#define IFS0_CS0_BIT 0x00000002
+#define IFS0_CS1_BIT 0x00000004
+#define IFS0_INT0_BIT 0x00000008
+#define IFS0_T1_BIT 0x00000010
+#define IFS0_IC1_BIT 0x00000020
+#define IFS0_OC1_BIT 0x00000040
+#define IFS0_INT1_BIT 0x00000080
+#define IFS0_T2_BIT 0x00000100
+#define IFS0_IC2_BIT 0x00000200
+#define IFS0_OC2_BIT 0x00000400
+#define IFS0_INT2_BIT 0x00000800
+#define IFS0_T3_BIT 0x00001000
+#define IFS0_IC3_BIT 0x00002000
+#define IFS0_OC3_BIT 0x00004000
+#define IFS0_INT3_BIT 0x00008000
+#define IFS0_T4_BIT 0x00010000
+#define IFS0_IC4_BIT 0x00020000
+#define IFS0_OC4_BIT 0x00040000
+#define IFS0_INT4_BIT 0x00080000
+#define IFS0_T5_BIT 0x00100000
+#define IFS0_IC5_BIT 0x00200000
+#define IFS0_OC5_BIT 0x00400000
+#define IFS0_CN_BIT 0x00800000
+#define IFS0_SPI1E_BIT 0x01000000
+#define IFS0_SPI1TX_BIT 0x02000000
+#define IFS0_SPI1RX_BIT 0x04000000
+#define IFS0_U1E_BIT 0x08000000
+#define IFS0_U1RX_BIT 0x10000000
+#define IFS0_U1TX_BIT 0x20000000
+#define IFS0_I2C1BC_BIT 0x40000000
+#define IFS0_I2C1S_BIT 0x80000000
+
+#define IFS0_MASK 0xFFFFFFFF
+
+#define IFS1_I2C1M_BIT 0x00000001
+#define IFS1_AD1_BIT 0x00000002
+#define IFS1_PMP_BIT 0x00000004
+#define IFS1_CMP1_BIT 0x00000008
+#define IFS1_CMP2_BIT 0x00000010
+#define IFS1_SPI2E_BIT 0x00000020
+#define IFS1_SPI2TX_BIT 0x00000040
+#define IFS1_SPI2RX_BIT 0x00000080
+#define IFS1_U2E_BIT 0x00000100
+#define IFS1_U2RX_BIT 0x00000200
+#define IFS1_U2TX_BIT 0x00000400
+#define IFS1_I2C2BC_BIT 0x00000800
+#define IFS1_I2C2S_BIT 0x00001000
+#define IFS1_I2CSM_BIT 0x00002000
+#define IFS1_FSCM_BIT 0x00004000
+#define IFS1_FCE_BIT 0x00008000
+#define IFS1_RTCC_BIT 0x00010000
+#define IFS1_DMA0_BIT 0x00020000
+#define IFS1_DMA1_BIT 0x00040000
+#define IFS1_DMA2_BIT 0x00080000
+#define IFS1_DMA3_BIT 0x00100000
+#define IFS1_DMA4_BIT 0x00200000
+#define IFS1_DMA5_BIT 0x00400000
+#define IFS1_DMA6_BIT 0x00800000
+#define IFS1_DMA7_BIT 0x01000000
+#define IFS1_USB_BIT 0x02000000
+
+#define IFS1_MASK 0x03FFFFFF
+
+
+/*********************************************************************
+ * IE0 -IE2
+ *********************************************************************/
+#define IEC0_CT_BIT 0x00000001
+#define IEC0_CS0_BIT 0x00000002
+#define IEC0_CS1_BIT 0x00000004
+#define IEC0_INT0_BIT 0x00000008
+#define IEC0_T1_BIT 0x00000010
+#define IEC0_IC1_BIT 0x00000020
+#define IEC0_OC1_BIT 0x00000040
+#define IEC0_INT1_BIT 0x00000080
+#define IEC0_T2_BIT 0x00000100
+#define IEC0_IC2_BIT 0x00000200
+#define IEC0_OC2_BIT 0x00000400
+#define IEC0_INT2_BIT 0x00000800
+#define IEC0_T3_BIT 0x00001000
+#define IEC0_IC3_BIT 0x00002000
+#define IEC0_OC3_BIT 0x00004000
+#define IEC0_INT3_BIT 0x00008000
+#define IEC0_T4_BIT 0x00010000
+#define IEC0_IC4_BIT 0x00020000
+#define IEC0_OC4_BIT 0x00040000
+#define IEC0_INT4_BIT 0x00080000
+#define IEC0_T5_BIT 0x00100000
+#define IEC0_IC5_BIT 0x00200000
+#define IEC0_OC5_BIT 0x00400000
+#define IEC0_CN_BIT 0x00800000
+#define IEC0_SPI1E_BIT 0x01000000
+#define IEC0_SPI1TX_BIT 0x02000000
+#define IEC0_SPI1RX_BIT 0x04000000
+#define IEC0_U1E_BIT 0x08000000
+#define IEC0_U1RX_BIT 0x10000000
+#define IEC0_U1TX_BIT 0x20000000
+#define IEC0_I2C1BC_BIT 0x40000000
+#define IEC0_I2C1S_BIT 0x80000000
+
+#define IEC0_MASK 0xFFFFFFFF
+
+#define IEC1_I2C1M_BIT 0x00000001
+#define IEC1_AD1_BIT 0x00000002
+#define IEC1_PMP_BIT 0x00000004
+#define IEC1_CMP1_BIT 0x00000008
+#define IEC1_CMP2_BIT 0x00000010
+#define IEC1_SPI2E_BIT 0x00000020
+#define IEC1_SPI2TX_BIT 0x00000040
+#define IEC1_SPI2RX_BIT 0x00000080
+#define IEC1_U2E_BIT 0x00000100
+#define IEC1_U2RX_BIT 0x00000200
+#define IEC1_U2TX_BIT 0x00000400
+#define IEC1_I2C2BC_BIT 0x00000800
+#define IEC1_I2C2S_BIT 0x00001000
+#define IEC1_I2CSM_BIT 0x00002000
+#define IEC1_FSCM_BIT 0x00004000
+#define IEC1_FCE_BIT 0x00008000
+#define IEC1_RTCC_BIT 0x00010000
+#define IEC1_DMA0_BIT 0x00020000
+#define IEC1_DMA1_BIT 0x00040000
+#define IEC1_DMA2_BIT 0x00080000
+#define IEC1_DMA3_BIT 0x00100000
+#define IEC1_DMA4_BIT 0x00200000
+#define IEC1_DMA5_BIT 0x00400000
+#define IEC1_DMA6_BIT 0x00800000
+#define IEC1_DMA7_BIT 0x01000000
+#define IEC1_USB_BIT 0x02000000
+
+#define IEC1_MASK 0x03FFFFFF
+
+/*********************************************************************
+ * IPC0 -IPC15
+ *********************************************************************/
+#define IPC0_CTIS_SHIFT 0
+#define IPC0_CTIP_SHIFT 2
+#define IPC0_CS0IS_SHIFT 8
+#define IPC0_CS0IP_SHIFT 10
+#define IPC0_CS1IS_SHIFT 16
+#define IPC0_CS1IP_SHIFT 18
+#define IPC0_INT0IS_SHIFT 24
+#define IPC0_INT0IP_SHIFT 26
+
+#define IPC0_MASK 0x1F1F1F1F
+
+#define IPC1_MASK 0x1F1F1F1F
+
+#define IPC2_MASK 0x1F1F1F1F
+
+#define IPC3_MASK 0x1F1F1F1F
+
+#define IPC4_MASK 0x1F1F1F1F
+
+#define IPC5_MASK 0x1F1F1F1F
+
+#define IPC6_MASK 0x1F1F1F1F
+
+#define IPC7_MASK 0x1F1F1F1F
+
+#define IPC8_MASK 0x1F1F1F1F
+
+#define IPC9_MASK 0x1F1F1F1F
+
+#define IPC10_MASK 0x1F1F1F1F
+
+#define IPC11_MASK 0x00001F1F
+
+
+
+/*********************************************************************/
+/* PMP (parallel master port) definitions */
+
+
+/*********************************************************************/
+/* UART definitions */
+#define USTA_URXDA 0x00000001
+#define USTA_OERR 0x00000002
+#define USTA_FERR 0x00000004
+#define USTA_PERR 0x00000008
+#define USTA_RIDLE 0x00000010
+#define USTA_ADDEN 0x00000020
+#define USTA_URXISEL0 0x00000040
+#define USTA_URXISEL1 0x00000080
+#define USTA_TRMT 0x00000100
+#define USTA_TXBF 0x00000200
+#define USTA_UTXEN 0x00000400
+#define USTA_UTXBRK 0x00000800
+#define USTA_URXEN 0x00001000
+#define USTA_UTXINV 0x00002000
+#define USTA_UTXISEL0 0x00004000
+#define USTA_UTXISEL1 0x00008000
+#define USTA_ADDR 0x00FF0000
+
+#define USTA_URXISEL 0x000000C0
+#define USTA_UTXISEL 0x0000C000
+
+#define UMODE_STSEL 0x00000001
+#define UMODE_PDSEL0 0x00000002
+#define UMODE_PDSEL1 0x00000004
+#define UMODE_BRGH 0x00000008
+#define UMODE_RXINV 0x00000010
+#define UMODE_ABAUD 0x00000020
+#define UMODE_LPBACK 0x00000040
+#define UMODE_WAKE 0x00000080
+#define UMODE_UEN0 0x00000100
+#define UMODE_UEN1 0x00000200
+#define UMODE_ALTIO 0x00000400
+#define UMODE_RTSMD 0x00000800
+#define UMODE_IREN 0x00001000
+#define UMODE_USIDL 0x00002000
+#define UMODE_UFRZ 0x00004000
+#define UMODE_UARTEN 0x00008000
+
+#define UMODE_PDSEL 0x00000006
+#define UMODE_UEN 0x00000300
+
+/* SPI definitions */
+#define SPICON_MSTEN 0x00000020
+#define SPICON_CKP 0x00000040
+#define SPICON_SSEN 0x00000080
+#define SPICON_CKE 0x00000100
+#define SPICON_SMP 0x00000200
+#define SPICON_MODE16 0x00000400
+#define SPICON_MODE32 0x00000800
+#define SPICON_DISSDO 0x00001000
+#define SPICON_SIDL 0x00002000
+#define SPICON_FRZ 0x00004000
+#define SPICON_ON 0x00008000
+#define SPICON_SPIFE 0x00020000
+#define SPICON_FRMPOL 0x20000000
+#define SPICON_FRMSYNC 0x40000000
+#define SPICON_FRMEN 0x80000000
+
+#define SPISTAT_SPIRBF 0x00000001
+#define SPISTAT_SPITBE 0x00000008
+#define SPISTAT_SPIROV 0x00000040
+#define SPISTAT_BUSY 0x00000800
+
+/* SPI1 definitions */
+#ifdef _SPI1
+#define SPI1_CLK_PORT IOPORT_F
+#define SPI1_CLK_BIT BIT_6
+
+#define SPI1_SDO_PORT IOPORT_F
+#define SPI1_SDO_BIT BIT_8
+
+#define SPI1_SDI_PORT IOPORT_F
+#define SPI1_SDI_BIT BIT_7
+
+#define SPI1_SS_PORT IOPORT_B
+#define SPI1_SS_BIT BIT_2
+#endif
+
+/* SPI2 definitions */
+#ifdef _SPI2
+#define SPI2_CLK_PORT IOPORT_G
+#define SPI2_CLK_BIT BIT_6
+
+#define SPI2_SDO_PORT IOPORT_G
+#define SPI2_SDO_BIT BIT_8
+
+#define SPI2_SDI_PORT IOPORT_G
+#define SPI2_SDI_BIT BIT_7
+
+#define SPI2_SS_PORT IOPORT_G
+#define SPI2_SS_BIT BIT_9
+
+#endif
+
+/* FLASH Controller definitions */
+#define NVMCON_NVMOP 0x0000000f
+#define NVMCON_ERASE 0x00000040
+#define NVMCON_WRERR 0x00002000
+#define NVMCON_WREN 0x00004000
+#define NVMCON_WR 0x00008000
+
+#define NVMCON_NVMOP0 0x00000001
+#define NVMCON_NVMOP1 0x00000002
+#define NVMCON_NVMOP2 0x00000004
+#define NVMCON_NVMOP3 0x00000008
+
+#define NVMCON_PROGOP 0x0000000F
+
+#define NVMCON_PROGOP0 0x00000001
+#define NVMCON_PROGOP1 0x00000002
+#define NVMCON_PROGOP2 0x00000004
+#define NVMCON_PROGOP3 0x00000008
+
+
+/* RTCC definitions */
+#define RTCCON_RTCOE 0x00000001
+#define RTCCON_HALFSEC 0x00000002
+#define RTCCON_RTCSYNC 0x00000004
+#define RTCCON_RTCWREN 0x00000008
+#define RTCCON_RTCCLKON 0x00000040
+#define RTCCON_RTSECSEL 0x00000080
+#define RTCCON_FRZ 0x00004000
+#define RTCCON_ON 0x00008000
+#define RTCCON_CAL 0x03ff0000
+
+
+#define RTCALRM_ARPT 0x000000ff
+#define RTCALRM_AMASK 0x00000f00
+#define RTCALRM_ALRMSYNC 0x00001000
+#define RTCALRM_PIV 0x00002000
+#define RTCALRM_CHIME 0x00004000
+#define RTCALRM_ALRMEN 0x00008000
+
+
+#define RTCTIME_SEC01 0x00000f00
+#define RTCTIME_SEC10 0x0000f000
+#define RTCTIME_MIN01 0x000f0000
+#define RTCTIME_MIN10 0x00f00000
+#define RTCTIME_HR01 0x0f000000
+#define RTCTIME_HR10 0xf0000000
+
+
+#define RTCDATE_WDAY01 0x0000000f
+#define RTCDATE_DAY01 0x00000f00
+#define RTCDATE_DAY10 0x0000f000
+#define RTCDATE_MONTH01 0x000f0000
+#define RTCDATE_MONTH10 0x00f00000
+#define RTCDATE_YEAR01 0x0f000000
+#define RTCDATE_YEAR10 0xf0000000
+
+#define ALRMTIME_SEC01 0x00000f00
+#define ALRMTIME_SEC10 0x0000f000
+#define ALRMTIME_MIN01 0x000f0000
+#define ALRMTIME_MIN10 0x00f00000
+#define ALRMTIME_HR01 0x0f000000
+#define ALRMTIME_HR10 0xf0000000
+
+
+#define ALRMDATE_WDAY01 0x0000000f
+#define ALRMDATE_DAY01 0x00000f00
+#define ALRMDATE_DAY10 0x0000f000
+#define ALRMDATE_MONTH01 0x000f0000
+#define ALRMDATE_MONTH10 0x00f00000
+
+
+/* DMAC definitions */
+#define DMACON_SUSPEND 0x00001000
+#define DMACON_SIDL 0x00002000
+#define DMACON_FRZ 0x00004000
+#define DMACON_ON 0x00008000
+
+#define DMASTAT_DMACH 0x00000007
+#define DMASTAT_RDWR 0x00000008
+
+#define DCRCCON_CRCCH 0x00000007
+#define DCRCCON_CRCAPP 0x00000040
+#define DCRCCON_CRCEN 0x00000080
+#define DCRCCON_PLEN 0x00000f00
+
+#define DCHXCON_CHPRI 0x00000003
+#define DCHXCON_CHEDET 0x00000004
+#define DCHXCON_CHXM 0x00000008
+#define DCHXCON_CHAEN 0x00000010
+#define DCHXCON_CHCHN 0x00000020
+#define DCHXCON_CHAED 0x00000040
+#define DCHXCON_CHEN 0x00000080
+#define DCHXCON_CHCHNS 0x00000100
+
+#define DCHXECON_AIRQEN 0x00000008
+#define DCHXECON_SIRQEN 0x00000010
+#define DCHXECON_PATEN 0x00000020
+#define DCHXECON_CABORT 0x00000040
+#define DCHXECON_CFORCE 0x00000080
+#define DCHXECON_CHSIRQ 0x0000ff00
+#define DCHXECON_CHAIRQ 0x00ff0000
+
+#define DCHXINT_CHERIF 0x00000001
+#define DCHXINT_CHTAIF 0x00000002
+#define DCHXINT_CHCCIF 0x00000004
+#define DCHXINT_CHBCIF 0x00000008
+#define DCHXINT_CHDHIF 0x00000010
+#define DCHXINT_CHDDIF 0x00000020
+#define DCHXINT_CHSHIF 0x00000040
+#define DCHXINT_CHSDIF 0x00000080
+#define DCHXINT_CHERIE 0x00010000
+#define DCHXINT_CHTAIE 0x00020000
+#define DCHXINT_CHCCIE 0x00040000
+#define DCHXINT_CHBCIE 0x00080000
+#define DCHXINT_CHDHIE 0x00100000
+#define DCHXINT_CHDDIE 0x00200000
+#define DCHXINT_CHSHIE 0x00400000
+#define DCHXINT_CHSDIE 0x00800000
+
+
+
+/* USB-OTG Definitions */
+#if defined(_USB)
+
+#define UOTGIR_AVBUS_VLD 0x00000001
+#define UOTGIR_BSESS_END 0x00000004
+#define UOTGIR_SESS_VLD 0x00000008
+#define UOTGIR_ACTIVITY 0x00000010
+#define UOTGIR_LSTATE 0x00000020
+#define UOTGIR_1MSEC 0x00000040
+#define UOTGIR_ID 0x00000080
+
+#define UOTGIE_AVBUS_VLD 0x00000001
+#define UOTGIE_BSESS_END 0x00000004
+#define UOTGIE_SESS_VLD 0x00000008
+#define UOTGIE_ACTIVITY 0x00000010
+#define UOTGIE_LSTATE 0x00000020
+#define UOTGIE_T1MSEC 0x00000040
+#define UOTGIE_ID 0x00000080
+
+#define UOTGSTAT_AVBUS_VLD 0x00000001
+#define UOTGSTAT_BSESS_END 0x00000004
+#define UOTGSTAT_SESS_VLD 0x00000008
+#define UOTGSTAT_LSTATE 0x00000020
+#define UOTGSTAT_ID 0x00000080
+
+#define UOTGCTRL_VBUS_DSCHG 0x00000001
+#define UOTGCTRL_VBUS_CHG 0x00000002
+#define UOTGCTRL_OTG_EN 0x00000004
+#define UOTGCTRL_VBUS_ON 0x00000008
+#define UOTGCTRL_DM_LOW 0x00000010
+#define UOTGCTRL_DP_LOW 0x00000020
+#define UOTGCTRL_DM_HIGH 0x00000040
+#define UOTGCTRL_DP_HIGH 0x00000080
+
+#define UIR_USB_RST 0x00000001
+#define UIR_UERR 0x00000002
+#define UIR_SOF_TOK 0x00000004
+#define UIR_TOK_DNE 0x00000008
+#define UIR_UIDLE 0x00000010
+#define UIR_RESUME 0x00000020
+#define UIR_ATTACH 0x00000040
+#define UIR_STALL 0x00000080
+
+#define UIE_USB_RST 0x00000001
+#define UIE_UERR 0x00000002
+#define UIE_SOF_TOK 0x00000004
+#define UIE_TOK_DNE 0x00000008
+#define UIE_UIDLE 0x00000010
+#define UIE_RESUME 0x00000020
+#define UIE_ATTACH 0x00000040
+#define UIE_STALL 0x00000080
+
+#define UEIR_PID_ERR 0x00000001
+#define UEIR_CRC5 0x00000002
+#define UEIR_HOST_EOF 0x00000002
+#define UEIR_CRC16 0x00000004
+#define UEIR_DFN8 0x00000008
+#define UEIR_BTO_ERR 0x00000010
+#define UEIR_DMA_ERR 0x00000020
+#define UEIR_BTS_ERR 0x00000080
+
+#define UEIE_PID_ERR 0x00000001
+#define UEIE_CRC5 0x00000002
+#define UEIE_HOST_EOF 0x00000002
+#define UEIE_CRC16 0x00000004
+#define UEIE_DFN8 0x00000008
+#define UEIE_BTO_ERR 0x00000010
+#define UEIE_DMA_ERR 0x00000020
+#define UEIE_BTS_ERR 0x00000080
+
+#define USTAT_ODD 0x00000004
+#define USTAT_TX 0x00000008
+#define USTAT_ENDPT_MASK 0x000000F0
+
+#define UCTRL_USB_EN 0x00000001
+#define UCTRL_HOST_SOF_EN 0x00000001
+#define UCTRL_ODD_RST 0x00000002
+#define UCTRL_RESUME 0x00000004
+#define UCTRL_HOST_EN 0x00000008
+#define UCTRL_HOST_RESET 0x00000010
+#define UCTRL_TXD_SUSPND 0x00000020
+#define UCTRL_HOST_TOK_BUSY 0x00000020
+#define UCTRL_SE0 0x00000040
+#define UCTRL_HOST_JSTATE 0x00000080
+
+#define UADDR_HOST_LS_EN 0x00000080
+
+#define UBDTP2_BDT_BA_15_9_MASK 0x000000FE
+
+#define UTOK_HOST_TOK_PID_MASK 0x000000F0
+#define UTOK_HOST_TOK_EP_MASK 0x0000000F
+
+#define USOF_THRESHOLD_VALUE_8BYTE_PKT 0x12;
+#define USOF_THRESHOLD_VALUE_16BYTE_PKT 0x1A;
+#define USOF_THRESHOLD_VALUE_32BYTE_PKT 0x2A;
+#define USOF_THRESHOLD_VALUE_64BYTE_PKT 0x4A;
+#define USOF_HOST_CNT_MASK 0x000000FF
+
+#define UBDTP2_BDT_BA_23_16_MASK 0x000000FF
+
+#define UBDTP2_BDT_BA_31_24_MASK 0x000000FF
+
+#define UCNFG1_FSEN 0x00000004
+#define UCNFG1_SUSPND 0x00000008
+#define UCNFG1_PSIDLE 0x00000010
+#define UCNFG1_PFRZ 0x00000020
+#define UCNFG1_UOEMON 0x00000040
+#define UCNFG1_UTEYE 0x00000080
+
+#define UEP0_HSHK 0x00000001
+#define UEP0_STALL 0x00000002
+#define UEP0_EP_TX_EN 0x00000004
+#define UEP0_EP_RX_EN 0x00000008
+#define UEP0_EP_CTL_DIS 0x00000010
+#define UEP0_RETRY_DIS 0x00000040
+#define UEP0_HOST_WOHUB 0x00000080
+
+#define UEPN_HSHK 0x00000001
+#define UEPN_STALL 0x00000002
+#define UEPN_EP_TX_EN 0x00000004
+#define UEPN_EP_RX_EN 0x00000008
+#define UEPN_EP_CTL_DIS 0x00000010
+
+#endif /* _USB */
+
+/****************************************************************
+ * ADC10 Definitions
+*****************************************************************/
+#define ADC_DONE 0x00
+#define ADC_SAMP 0x01
+#define ADC_ASAM 0x02
+#define ADC_CLRASAM 0x08
+#define ADC_SSRC0 0x20
+#define ADC_SSRC1 0x40
+#define ADC_SSRC2 0x80
+#define ADC_FORM0 0x0100
+#define ADC_FORM1 0x0200
+#define ADC_FORM2 0x0400
+#define ADC_SIDL 0x2000
+#define ADC_FRZ 0x4000
+#define ADC_ON 0x8000
+
+#define ADC_ALTS 0x01
+#define ADC_BUFM 0x02
+#define ADC_SMPIO 0x04
+#define ADC_SMPI1 0x08
+#define ADC_SMPI2 0x10
+#define ADC_SMPI3 0x20
+#define ADC_BUFS 0x80
+
+#define ADC_CSCNA 0x0100
+#define ADC_OFFCAL 0x1000
+#define ADC_VCFG0 0x2000
+#define ADC_VCFG1 0x4000
+#define ADC_VCFG2 0x8000
+
+#define ADC_ADCS0 0x01
+#define ADC_ADCS1 0x02
+#define ADC_ADCS2 0x04
+#define ADC_ADCS3 0x08
+#define ADC_ADCS4 0x10
+#define ADC_ADCS5 0x20
+#define ADC_ADCS6 0x40
+#define ADC_ADCS7 0x80
+
+#define ADC_SAMC0 0x0100
+#define ADC_SAMC1 0x0200
+#define ADC_SAMC2 0x0400
+#define ADC_SAMC3 0x0800
+#define ADC_SAMC4 0x1000
+#define ADC_ADRC 0x8000
+
+#define ADC_CH0SA0 0x00010000
+#define ADC_CH0SA1 0x00020000
+#define ADC_CH0SA2 0x00040000
+#define ADC_CH0SA3 0x00080000
+#define ADC_CH0NA 0x00100000
+#define ADC_CH0SB0 0x01000000
+#define ADC_CH0SB1 0x02000000
+#define ADC_CH0SB2 0x04000000
+#define ADC_CH0SB3 0x08000000
+#define ADC_CH0NB 0x80000000
+
+#define ADC_CSSL0 0x01
+#define ADC_CSSL1 0x02
+#define ADC_CSSL2 0x04
+#define ADC_CSSL3 0x08
+#define ADC_CSSL4 0x10
+#define ADC_CSSL5 0x20
+#define ADC_CSSL6 0x40
+#define ADC_CSSL7 0x80
+#define ADC_CSSL8 0x0100
+#define ADC_CSSL9 0x0200
+#define ADC_CSSL10 0x0400
+#define ADC_CSSL11 0x0800
+#define ADC_CSSL12 0x1000
+#define ADC_CSSL13 0x2000
+#define ADC_CSSL14 0x4000
+#define ADC_CSSL15 0x8000
+
+#define ADC_PCFG0 0x01
+#define ADC_PCFG1 0x02
+#define ADC_PCFG2 0x04
+#define ADC_PCFG3 0x08
+#define ADC_PCFG4 0x10
+#define ADC_PCFG5 0x20
+#define ADC_PCFG6 0x40
+#define ADC_PCFG7 0x80
+#define ADC_PCFG8 0x0100
+#define ADC_PCFG9 0x0200
+#define ADC_PCFG10 0x0400
+#define ADC_PCFG11 0x0800
+#define ADC_PCFG12 0x1000
+#define ADC_PCFG13 0x2000
+#define ADC_PCFG14 0x4000
+#define ADC_PCFG15 0x8000
+
+/* AD1CON1 */
+#define _DONE AD1CON1bits.DONE
+#define _SAMP AD1CON1bits.SAMP
+#define _ASAM AD1CON1bits.ASAM
+#define _SSRC AD1CON1bits.SSRC
+#define _FORM0 AD1CON1bits.FORM0
+#define _FORM1 AD1CON1bits.FORM1
+#define _ADSIDL AD1CON1bits.ADSIDL
+#define _ADON AD1CON1bits.ADON
+#define _SSRC0 AD1CON1bits.SSRC0
+#define _SSRC1 AD1CON1bits.SSRC1
+#define _SSRC2 AD1CON1bits.SSRC2
+#define _FORM AD1CON1bits.FORM
+
+/* AD1CON2 */
+#define _ALTS AD1CON2bits.ALTS
+#define _BUFM AD1CON2bits.BUFM
+#define _SMPI AD1CON2bits.SMPI
+#define _BUFS AD1CON2bits.BUFS
+#define _CSCNA AD1CON2bits.CSCNA
+#define _VCFG AD1CON2bits.VCFG
+#define _SMPI0 AD1CON2bits.SMPI0
+#define _SMPI1 AD1CON2bits.SMPI1
+#define _SMPI2 AD1CON2bits.SMPI2
+#define _SMPI3 AD1CON2bits.SMPI3
+#define _VCFG0 AD1CON2bits.VCFG0
+#define _VCFG1 AD1CON2bits.VCFG1
+#define _VCFG2 AD1CON2bits.VCFG2
+
+/* AD1CON3 */
+#define _ADCS AD1CON3bits.ADCS
+#define _SAMC AD1CON3bits.SAMC
+#define _ADRC AD1CON3bits.ADRC
+#define _ADCS0 AD1CON3bits.ADCS0
+#define _ADCS1 AD1CON3bits.ADCS1
+#define _ADCS2 AD1CON3bits.ADCS2
+#define _ADCS3 AD1CON3bits.ADCS3
+#define _ADCS4 AD1CON3bits.ADCS4
+#define _ADCS5 AD1CON3bits.ADCS5
+#define _ADCS6 AD1CON3bits.ADCS6
+#define _ADCS7 AD1CON3bits.ADCS7
+#define _SAMC0 AD1CON3bits.SAMC0
+#define _SAMC1 AD1CON3bits.SAMC1
+#define _SAMC2 AD1CON3bits.SAMC2
+#define _SAMC3 AD1CON3bits.SAMC3
+#define _SAMC4 AD1CON3bits.SAMC4
+
+/* AD1CHS */
+#define _CH0SA AD1CHSbits.CH0SA
+#define _CH0NA AD1CHSbits.CH0NA
+#define _CH0SB AD1CHSbits.CH0SB
+#define _CH0NB AD1CHSbits.CH0NB
+#define _CH0SA0 AD1CHSbits.CH0SA0
+#define _CH0SA1 AD1CHSbits.CH0SA1
+#define _CH0SA2 AD1CHSbits.CH0SA2
+#define _CH0SA3 AD1CHSbits.CH0SA3
+#define _CH0SB0 AD1CHSbits.CH0SB0
+#define _CH0SB1 AD1CHSbits.CH0SB1
+#define _CH0SB2 AD1CHSbits.CH0SB2
+#define _CH0SB3 AD1CHSbits.CH0SB3
+
+/* AD1PCFG */
+#define _PCFG0 AD1PCFGbits.PCFG0
+#define _PCFG1 AD1PCFGbits.PCFG1
+#define _PCFG2 AD1PCFGbits.PCFG2
+#define _PCFG3 AD1PCFGbits.PCFG3
+#define _PCFG4 AD1PCFGbits.PCFG4
+#define _PCFG5 AD1PCFGbits.PCFG5
+#define _PCFG6 AD1PCFGbits.PCFG6
+#define _PCFG7 AD1PCFGbits.PCFG7
+#define _PCFG8 AD1PCFGbits.PCFG8
+#define _PCFG9 AD1PCFGbits.PCFG9
+#define _PCFG10 AD1PCFGbits.PCFG10
+#define _PCFG11 AD1PCFGbits.PCFG11
+#define _PCFG12 AD1PCFGbits.PCFG12
+#define _PCFG13 AD1PCFGbits.PCFG13
+#define _PCFG14 AD1PCFGbits.PCFG14
+#define _PCFG15 AD1PCFGbits.PCFG15
+
+/* AD1CSSL */
+#define _CSSL0 AD1CSSLbits.CSSL0
+#define _CSSL1 AD1CSSLbits.CSSL1
+#define _CSSL2 AD1CSSLbits.CSSL2
+#define _CSSL3 AD1CSSLbits.CSSL3
+#define _CSSL4 AD1CSSLbits.CSSL4
+#define _CSSL5 AD1CSSLbits.CSSL5
+#define _CSSL6 AD1CSSLbits.CSSL6
+#define _CSSL7 AD1CSSLbits.CSSL7
+#define _CSSL8 AD1CSSLbits.CSSL8
+#define _CSSL9 AD1CSSLbits.CSSL9
+#define _CSSL10 AD1CSSLbits.CSSL10
+#define _CSSL11 AD1CSSLbits.CSSL11
+#define _CSSL12 AD1CSSLbits.CSSL12
+#define _CSSL13 AD1CSSLbits.CSSL13
+#define _CSSL14 AD1CSSLbits.CSSL14
+#define _CSSL15 AD1CSSLbits.CSSL15
+
+/****************************************************************
+ * CVREF Definitions
+*****************************************************************/
+#define CVRCON_CVR0 0x0001
+#define CVRCON_CVR1 0x0002
+#define CVRCON_CVR2 0x0004
+#define CVRCON_CVR3 0x0008
+#define CVRCON_CVRSS 0x0010
+#define CVRCON_CVRR 0x0020
+#define CVRCON_CVROE 0x0040
+#define CVRCON_ON 0x8000
+
+/****************************************************************
+ * CMP Definitions
+*****************************************************************/
+/* common CMxCON defines */
+#define CMCON_CCH0 0x0001
+#define CMCON_CCH1 0x0002
+#define CMCON_CREF 0x0010
+#define CMCON_EVPOL0 0x0040
+#define CMCON_EVPOL1 0x0080
+#define CMCON_COUT 0x0100
+#define CMCON_CPOL 0x2000
+#define CMCON_COE 0x4000
+#define CMCON_FRZ 0x4000
+
+/* CMSTAT defines */
+#define CMCON_ON 0x8000
+#define CMCON_SIDL 0x2000
+
+/****************************************************************
+ * OCMP Definitions
+*****************************************************************/
+#define OCCON_OCM0 0x0001
+#define OCCON_OCM1 0x0002
+#define OCCON_OCM2 0x0004
+#define OCCON_OCTSEL 0x0008
+#define OCCON_OCFLT 0x0010
+#define OCCON_OCC32 0x0020
+#define OCCON_SIDL 0x2000
+#define OCCON_FRZ 0x4000
+#define OCCON_ON 0x8000
+
+
+/* WDTCON definitions */
+#define WDT_CLR 0x01
+#define WDT_WEN 0x02 /* may have to change from enable to disable */
+#define WDT_WDTPST0 0x04
+#define WDT_WDTPST1 0x08
+#define WDT_WDTPST2 0x10
+#define WDT_WDTPST3 0x20
+#define WDT_WDTPST4 0x40
+#define WDT_FRZ 0x4000
+#define WDT_ON 0x8000
+
+
+/* OSCCON definitions */
+#define OSC_OSWEN 0x01
+#define OSC_SOCEN 0x02
+#define OSC_URFCEN 0x04
+#define OSC_CF 0x08
+#define OSC_SLPEN 0x10
+#define OSC_LOCK 0x20
+#define OSC_ULOCK 0x40
+#define OSC_CLKLOCK 0x80
+
+#define OSC_NOSC0 0x0100
+#define OSC_NOSC1 0x0200
+#define OSC_NOSC2 0x0400
+#define OSC_COSC0 0x1000
+#define OSC_COSC1 0x2000
+#define OSC_COSC2 0x4000
+
+#define OSC_PLLMULT0 0x010000
+#define OSC_PLLMULT1 0x020000
+#define OSC_PLLMULT2 0x040000
+#define OSC_PBDIV0 0x080000
+#define OSC_PBDIV1 0x100000
+
+#define OSC_FRCDIV0 0x01000000
+#define OSC_FRCDIV1 0x02000000
+#define OSC_FRCDIV2 0x04000000
+#define OSC_PLLODIV0 0x08000000
+#define OSC_PLLODIV1 0x10000000
+#define OSC_PLLODIV2 0x20000000
+
+
+/* OSCTUN definitions */
+#define OSC_TUN0 0x01
+#define OSC_TUN1 0x02
+#define OSC_TUN2 0x04
+#define OSC_TUN3 0x08
+#define OSC_TUN4 0x10
+
+
+/* TRISA */
+#define _TRISA0 TRISAbits.TRISA0
+#define _TRISA1 TRISAbits.TRISA1
+#define _TRISA2 TRISAbits.TRISA2
+#define _TRISA3 TRISAbits.TRISA3
+#define _TRISA4 TRISAbits.TRISA4
+#define _TRISA5 TRISAbits.TRISA5
+#define _TRISA6 TRISAbits.TRISA6
+#define _TRISA7 TRISAbits.TRISA7
+#define _TRISA9 TRISAbits.TRISA9
+#define _TRISA10 TRISAbits.TRISA10
+#define _TRISA14 TRISAbits.TRISA14
+#define _TRISA15 TRISAbits.TRISA15
+
+/* PORTA */
+#define _RA0 PORTAbits.RA0
+#define _RA1 PORTAbits.RA1
+#define _RA2 PORTAbits.RA2
+#define _RA3 PORTAbits.RA3
+#define _RA4 PORTAbits.RA4
+#define _RA5 PORTAbits.RA5
+#define _RA6 PORTAbits.RA6
+#define _RA7 PORTAbits.RA7
+#define _RA9 PORTAbits.RA9
+#define _RA10 PORTAbits.RA10
+#define _RA14 PORTAbits.RA14
+#define _RA15 PORTAbits.RA15
+
+/* LATA */
+#define _LATA0 LATAbits.LATA0
+#define _LATA1 LATAbits.LATA1
+#define _LATA2 LATAbits.LATA2
+#define _LATA3 LATAbits.LATA3
+#define _LATA4 LATAbits.LATA4
+#define _LATA5 LATAbits.LATA5
+#define _LATA6 LATAbits.LATA6
+#define _LATA7 LATAbits.LATA7
+#define _LATA9 LATAbits.LATA9
+#define _LATA10 LATAbits.LATA10
+#define _LATA14 LATAbits.LATA14
+#define _LATA15 LATAbits.LATA15
+
+/* TRISB */
+#define _TRISB0 TRISBbits.TRISB0
+#define _TRISB1 TRISBbits.TRISB1
+#define _TRISB2 TRISBbits.TRISB2
+#define _TRISB3 TRISBbits.TRISB3
+#define _TRISB4 TRISBbits.TRISB4
+#define _TRISB5 TRISBbits.TRISB5
+#define _TRISB6 TRISBbits.TRISB6
+#define _TRISB7 TRISBbits.TRISB7
+#define _TRISB8 TRISBbits.TRISB8
+#define _TRISB9 TRISBbits.TRISB9
+#define _TRISB10 TRISBbits.TRISB10
+#define _TRISB11 TRISBbits.TRISB11
+#define _TRISB12 TRISBbits.TRISB12
+#define _TRISB13 TRISBbits.TRISB13
+#define _TRISB14 TRISBbits.TRISB14
+#define _TRISB15 TRISBbits.TRISB15
+
+/* PORTB */
+#define _RB0 PORTBbits.RB0
+#define _RB1 PORTBbits.RB1
+#define _RB2 PORTBbits.RB2
+#define _RB3 PORTBbits.RB3
+#define _RB4 PORTBbits.RB4
+#define _RB5 PORTBbits.RB5
+#define _RB6 PORTBbits.RB6
+#define _RB7 PORTBbits.RB7
+#define _RB8 PORTBbits.RB8
+#define _RB9 PORTBbits.RB9
+#define _RB10 PORTBbits.RB10
+#define _RB11 PORTBbits.RB11
+#define _RB12 PORTBbits.RB12
+#define _RB13 PORTBbits.RB13
+#define _RB14 PORTBbits.RB14
+#define _RB15 PORTBbits.RB15
+
+/* LATB */
+#define _LATB0 LATBbits.LATB0
+#define _LATB1 LATBbits.LATB1
+#define _LATB2 LATBbits.LATB2
+#define _LATB3 LATBbits.LATB3
+#define _LATB4 LATBbits.LATB4
+#define _LATB5 LATBbits.LATB5
+#define _LATB6 LATBbits.LATB6
+#define _LATB7 LATBbits.LATB7
+#define _LATB8 LATBbits.LATB8
+#define _LATB9 LATBbits.LATB9
+#define _LATB10 LATBbits.LATB10
+#define _LATB11 LATBbits.LATB11
+#define _LATB12 LATBbits.LATB12
+#define _LATB13 LATBbits.LATB13
+#define _LATB14 LATBbits.LATB14
+#define _LATB15 LATBbits.LATB15
+
+/* TRISC */
+#define _TRISC1 TRISCbits.TRISC1
+#define _TRISC2 TRISCbits.TRISC2
+#define _TRISC3 TRISCbits.TRISC3
+#define _TRISC4 TRISCbits.TRISC4
+#define _TRISC12 TRISCbits.TRISC12
+#define _TRISC13 TRISCbits.TRISC13
+#define _TRISC14 TRISCbits.TRISC14
+#define _TRISC15 TRISCbits.TRISC15
+
+/* PORTC */
+#define _RC1 PORTCbits.RC1
+#define _RC2 PORTCbits.RC2
+#define _RC3 PORTCbits.RC3
+#define _RC4 PORTCbits.RC4
+#define _RC12 PORTCbits.RC12
+#define _RC13 PORTCbits.RC13
+#define _RC14 PORTCbits.RC14
+#define _RC15 PORTCbits.RC15
+
+/* LATC */
+#define _LATC1 LATCbits.LATC1
+#define _LATC2 LATCbits.LATC2
+#define _LATC3 LATCbits.LATC3
+#define _LATC4 LATCbits.LATC4
+#define _LATC12 LATCbits.LATC12
+#define _LATC13 LATCbits.LATC13
+#define _LATC14 LATCbits.LATC14
+#define _LATC15 LATCbits.LATC15
+
+/* TRISD */
+#define _TRISD0 TRISDbits.TRISD0
+#define _TRISD1 TRISDbits.TRISD1
+#define _TRISD2 TRISDbits.TRISD2
+#define _TRISD3 TRISDbits.TRISD3
+#define _TRISD4 TRISDbits.TRISD4
+#define _TRISD5 TRISDbits.TRISD5
+#define _TRISD6 TRISDbits.TRISD6
+#define _TRISD7 TRISDbits.TRISD7
+#define _TRISD8 TRISDbits.TRISD8
+#define _TRISD9 TRISDbits.TRISD9
+#define _TRISD10 TRISDbits.TRISD10
+#define _TRISD11 TRISDbits.TRISD11
+#define _TRISD12 TRISDbits.TRISD12
+#define _TRISD13 TRISDbits.TRISD13
+#define _TRISD14 TRISDbits.TRISD14
+#define _TRISD15 TRISDbits.TRISD15
+
+/* PORTD */
+#define _RD0 PORTDbits.RD0
+#define _RD1 PORTDbits.RD1
+#define _RD2 PORTDbits.RD2
+#define _RD3 PORTDbits.RD3
+#define _RD4 PORTDbits.RD4
+#define _RD5 PORTDbits.RD5
+#define _RD6 PORTDbits.RD6
+#define _RD7 PORTDbits.RD7
+#define _RD8 PORTDbits.RD8
+#define _RD9 PORTDbits.RD9
+#define _RD10 PORTDbits.RD10
+#define _RD11 PORTDbits.RD11
+#define _RD12 PORTDbits.RD12
+#define _RD13 PORTDbits.RD13
+#define _RD14 PORTDbits.RD14
+#define _RD15 PORTDbits.RD15
+
+/* LATD */
+#define _LATD0 LATDbits.LATD0
+#define _LATD1 LATDbits.LATD1
+#define _LATD2 LATDbits.LATD2
+#define _LATD3 LATDbits.LATD3
+#define _LATD4 LATDbits.LATD4
+#define _LATD5 LATDbits.LATD5
+#define _LATD6 LATDbits.LATD6
+#define _LATD7 LATDbits.LATD7
+#define _LATD8 LATDbits.LATD8
+#define _LATD9 LATDbits.LATD9
+#define _LATD10 LATDbits.LATD10
+#define _LATD11 LATDbits.LATD11
+#define _LATD12 LATDbits.LATD12
+#define _LATD13 LATDbits.LATD13
+#define _LATD14 LATDbits.LATD14
+#define _LATD15 LATDbits.LATD15
+
+/* TRISE */
+#define _TRISE0 TRISEbits.TRISE0
+#define _TRISE1 TRISEbits.TRISE1
+#define _TRISE2 TRISEbits.TRISE2
+#define _TRISE3 TRISEbits.TRISE3
+#define _TRISE4 TRISEbits.TRISE4
+#define _TRISE5 TRISEbits.TRISE5
+#define _TRISE6 TRISEbits.TRISE6
+#define _TRISE7 TRISEbits.TRISE7
+#define _TRISE8 TRISEbits.TRISE8
+#define _TRISE9 TRISEbits.TRISE9
+
+/* PORTE */
+#define _RE0 PORTEbits.RE0
+#define _RE1 PORTEbits.RE1
+#define _RE2 PORTEbits.RE2
+#define _RE3 PORTEbits.RE3
+#define _RE4 PORTEbits.RE4
+#define _RE5 PORTEbits.RE5
+#define _RE6 PORTEbits.RE6
+#define _RE7 PORTEbits.RE7
+#define _RE8 PORTEbits.RE8
+#define _RE9 PORTEbits.RE9
+
+/* LATE */
+#define _LATE0 LATEbits.LATE0
+#define _LATE1 LATEbits.LATE1
+#define _LATE2 LATEbits.LATE2
+#define _LATE3 LATEbits.LATE3
+#define _LATE4 LATEbits.LATE4
+#define _LATE5 LATEbits.LATE5
+#define _LATE6 LATEbits.LATE6
+#define _LATE7 LATEbits.LATE7
+#define _LATE8 LATEbits.LATE8
+#define _LATE9 LATEbits.LATE9
+
+/* TRISF */
+#define _TRISF0 TRISFbits.TRISF0
+#define _TRISF1 TRISFbits.TRISF1
+#define _TRISF2 TRISFbits.TRISF2
+#define _TRISF3 TRISFbits.TRISF3
+#define _TRISF4 TRISFbits.TRISF4
+#define _TRISF5 TRISFbits.TRISF5
+#define _TRISF6 TRISFbits.TRISF6
+#define _TRISF7 TRISFbits.TRISF7
+#define _TRISF8 TRISFbits.TRISF8
+#define _TRISF12 TRISFbits.TRISF12
+#define _TRISF13 TRISFbits.TRISF13
+
+/* PORTF */
+#define _RF0 PORTFbits.RF0
+#define _RF1 PORTFbits.RF1
+#define _RF2 PORTFbits.RF2
+#define _RF3 PORTFbits.RF3
+#define _RF4 PORTFbits.RF4
+#define _RF5 PORTFbits.RF5
+#define _RF6 PORTFbits.RF6
+#define _RF7 PORTFbits.RF7
+#define _RF8 PORTFbits.RF8
+#define _RF12 PORTFbits.RF12
+#define _RF13 PORTFbits.RF13
+
+/* LATF */
+#define _LATF0 LATFbits.LATF0
+#define _LATF1 LATFbits.LATF1
+#define _LATF2 LATFbits.LATF2
+#define _LATF3 LATFbits.LATF3
+#define _LATF4 LATFbits.LATF4
+#define _LATF5 LATFbits.LATF5
+#define _LATF6 LATFbits.LATF6
+#define _LATF7 LATFbits.LATF7
+#define _LATF8 LATFbits.LATF8
+#define _LATF12 LATFbits.LATF12
+#define _LATF13 LATFbits.LATF13
+
+/* TRISG */
+#define _TRISG0 TRISGbits.TRISG0
+#define _TRISG1 TRISGbits.TRISG1
+#define _TRISG2 TRISGbits.TRISG2
+#define _TRISG3 TRISGbits.TRISG3
+#define _TRISG6 TRISGbits.TRISG6
+#define _TRISG7 TRISGbits.TRISG7
+#define _TRISG8 TRISGbits.TRISG8
+#define _TRISG9 TRISGbits.TRISG9
+#define _TRISG12 TRISGbits.TRISG12
+#define _TRISG13 TRISGbits.TRISG13
+#define _TRISG14 TRISGbits.TRISG14
+#define _TRISG15 TRISGbits.TRISG15
+
+/* PORTG */
+#define _RG0 PORTGbits.RG0
+#define _RG1 PORTGbits.RG1
+#define _RG2 PORTGbits.RG2
+#define _RG3 PORTGbits.RG3
+#define _RG6 PORTGbits.RG6
+#define _RG7 PORTGbits.RG7
+#define _RG8 PORTGbits.RG8
+#define _RG9 PORTGbits.RG9
+#define _RG12 PORTGbits.RG12
+#define _RG13 PORTGbits.RG13
+#define _RG14 PORTGbits.RG14
+#define _RG15 PORTGbits.RG15
+
+/* LATG */
+#define _LATG0 LATGbits.LATG0
+#define _LATG1 LATGbits.LATG1
+#define _LATG2 LATGbits.LATG2
+#define _LATG3 LATGbits.LATG3
+#define _LATG6 LATGbits.LATG6
+#define _LATG7 LATGbits.LATG7
+#define _LATG8 LATGbits.LATG8
+#define _LATG9 LATGbits.LATG9
+#define _LATG12 LATGbits.LATG12
+#define _LATG13 LATGbits.LATG13
+#define _LATG14 LATGbits.LATG14
+#define _LATG15 LATGbits.LATG15
+
+/* OSC defines */
+#define OSC_OSWEN 0x01
+#define OSC_SOCEN 0x02
+#define OSC_URFCEN 0x04
+#define OSC_CF 0x08
+#define OSC_SLPEN 0x10
+#define OSC_LOCK 0x20
+#define OSC_ULOCK 0x40
+#define OSC_CLKLOCK 0x80
+
+#define OSC_NOSC0 0x0100
+#define OSC_NOSC1 0x0200
+#define OSC_NOSC2 0x0400
+#define OSC_COSC0 0x1000
+#define OSC_COSC1 0x2000
+#define OSC_COSC2 0x4000
+
+#define OSC_PLLMULT0 0x010000
+#define OSC_PLLMULT1 0x020000
+#define OSC_PLLMULT2 0x040000
+#define OSC_PBDIV0 0x080000
+#define OSC_PBDIV1 0x100000
+
+#define OSC_FRCDIV0 0x01000000
+#define OSC_FRCDIV1 0x02000000
+#define OSC_FRCDIV2 0x04000000
+#define OSC_PLLODIV0 0x08000000
+#define OSC_PLLODIV1 0x10000000
+#define OSC_PLLODIV2 0x20000000
+
+#define OSC_TUN0 0x01
+#define OSC_TUN1 0x02
+#define OSC_TUN2 0x04
+#define OSC_TUN3 0x08
+#define OSC_TUN4 0x10
+
+
+/* System-wide IRQ numbers
+ * Device-specific definitions now appear in processor header
+ * files.
+ */
+#ifndef _CORE_TIMER_IRQ
+#define _CORE_TIMER_IRQ 0
+#define _CORE_SOFTWARE_0_IRQ 1
+#define _CORE_SOFTWARE_1_IRQ 2
+#define _EXTERNAL_0_IRQ 3
+#define _TIMER_1_IRQ 4
+#define _INPUT_CAPTURE_1_IRQ 5
+#define _OUTPUT_COMPARE_1_IRQ 6
+#define _EXTERNAL_1_IRQ 7
+#define _TIMER_2_IRQ 8
+#define _INPUT_CAPTURE_2_IRQ 9
+#define _OUTPUT_COMPARE_2_IRQ 10
+#define _EXTERNAL_2_IRQ 11
+#define _TIMER_3_IRQ 12
+#define _INPUT_CAPTURE_3_IRQ 13
+#define _OUTPUT_COMPARE_3_IRQ 14
+#define _EXTERNAL_3_IRQ 15
+#define _TIMER_4_IRQ 16
+#define _INPUT_CAPTURE_4_IRQ 17
+#define _OUTPUT_COMPARE_4_IRQ 18
+#define _EXTERNAL_4_IRQ 19
+#define _TIMER_5_IRQ 20
+#define _INPUT_CAPTURE_5_IRQ 21
+#define _OUTPUT_COMPARE_5_IRQ 22
+#define _SPI1_ERR_IRQ 23
+#define _SPI1_TX_IRQ 24
+#define _SPI1_RX_IRQ 25
+#define _UART1_ERR_IRQ 26
+#define _UART1_RX_IRQ 27
+#define _UART1_TX_IRQ 28
+#define _I2C1_BUS_IRQ 29
+#define _I2C1_SLAVE_IRQ 30
+#define _I2C1_MASTER_IRQ 31
+#define _CHANGE_NOTICE_IRQ 32
+#define _ADC_IRQ 33
+#define _PMP_IRQ 34
+#define _COMPARATOR_1_IRQ 35
+#define _COMPARATOR_2_IRQ 36
+#define _SPI2_ERR_IRQ 37
+#define _SPI2_TX_IRQ 38
+#define _SPI2_RX_IRQ 39
+#define _UART2_ERR_IRQ 40
+#define _UART2_RX_IRQ 41
+#define _UART2_TX_IRQ 42
+#define _I2C2_BUS_IRQ 43
+#define _I2C2_SLAVE_IRQ 44
+#define _I2C2_MASTER_IRQ 45
+#define _FAIL_SAFE_MONITOR_IRQ 46
+#define _RTCC_IRQ 47
+#define _DMA0_IRQ 48
+#define _DMA1_IRQ 49
+#define _DMA2_IRQ 50
+#define _DMA3_IRQ 51
+#define _FLASH_CONTROL_IRQ 56
+#endif /* _CORE_TIMER_IRQ */
+
+
+#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/pkg.yml b/hw/mcu/microchip/pic32mx470f512h/pkg.yml
new file mode 100644
index 0000000..824984e
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/pkg.yml
@@ -0,0 +1,31 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/mcu/microchip/pic32mx470f512h
+pkg.description: MCU definition for the Microchip PIC32MX470F512H microcontroller.
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+
+pkg.cflags:
+ - -mprocessor=32MX470F512H
+pkg.deps:
+ - hw/hal
+ - compiler/xc32
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/src/hal_os_tick.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/src/hal_os_tick.c b/hw/mcu/microchip/pic32mx470f512h/src/hal_os_tick.c
new file mode 100644
index 0000000..8fc68d6
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/src/hal_os_tick.c
@@ -0,0 +1,36 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/os.h>
+#include <hal/hal_os_tick.h>
+
+/*
+ * XXX implement tickless mode.
+ */
+void
+os_tick_idle(os_time_t ticks)
+{
+ OS_ASSERT_CRITICAL();
+}
+
+void
+os_tick_init(uint32_t os_ticks_per_sec, int prio)
+{
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/src/hal_system.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/src/hal_system.c b/hw/mcu/microchip/pic32mx470f512h/src/hal_system.c
new file mode 100644
index 0000000..ed6e6a3
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/src/hal_system.c
@@ -0,0 +1,35 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_system.h"
+
+#include <stdint.h>
+
+void
+hal_system_reset(void)
+{
+ while (1) {
+ }
+}
+
+int
+hal_debugger_connected(void)
+{
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/src/hal_uart.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/src/hal_uart.c b/hw/mcu/microchip/pic32mx470f512h/src/hal_uart.c
new file mode 100644
index 0000000..93eff5b
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/src/hal_uart.c
@@ -0,0 +1,463 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_uart.h"
+#include "bsp/bsp.h"
+#include "syscfg/syscfg.h"
+#include "mcu/mips_hal.h"
+#include <assert.h>
+#include <stdlib.h>
+
+#include <xc.h>
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC1CLR = _IEC1_U1TXIE_MASK;
+ break;
+ case 1:
+ IEC1CLR = _IEC1_U2TXIE_MASK;
+ break;
+ case 2:
+ IEC2CLR = _IEC2_U3TXIE_MASK;
+ break;
+ case 3:
+ IEC2CLR = _IEC2_U4TXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC1SET = _IEC1_U1TXIE_MASK;
+ break;
+ case 1:
+ IEC1SET = _IEC1_U2TXIE_MASK;
+ break;
+ case 2:
+ IEC2SET = _IEC2_U3TXIE_MASK;
+ break;
+ case 3:
+ IEC2SET = _IEC2_U4TXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC1CLR = _IEC1_U1RXIE_MASK;
+ break;
+ case 1:
+ IEC1CLR = _IEC1_U2RXIE_MASK;
+ break;
+ case 2:
+ IEC1CLR = _IEC1_U3RXIE_MASK;
+ break;
+ case 3:
+ IEC2CLR = _IEC2_U4RXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC1SET = _IEC1_U1RXIE_MASK;
+ break;
+ case 1:
+ IEC1SET = _IEC1_U2RXIE_MASK;
+ break;
+ case 2:
+ IEC1SET = _IEC1_U3RXIE_MASK;
+ break;
+ case 3:
+ IEC2SET = _IEC2_U4RXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_receive_ready(int port)
+{
+ switch (port) {
+ case 0:
+ uarts[port].u_rx_data = U1RXREG;
+ break;
+ case 1:
+ uarts[port].u_rx_data = U2RXREG;
+ break;
+ case 2:
+ uarts[port].u_rx_data = U3RXREG;
+ break;
+ case 3:
+ uarts[port].u_rx_data = U4RXREG;
+ break;
+ }
+
+ int c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c = uarts[port].u_tx_func(uarts[port].u_func_arg);
+ if (c < 0) {
+ uart_disable_tx_int(port);
+
+ /* call tx done cb */
+ if (uarts[port].u_tx_done) {
+ uarts[port].u_tx_done(uarts[port].u_func_arg);
+ }
+ } else {
+ /* write char out */
+ switch (port) {
+ case 0:
+ U1TXREG = (uint32_t)c & 0xff;
+ break;
+ case 1:
+ U2TXREG = (uint32_t)c & 0xff;
+ break;
+ case 2:
+ U3TXREG = (uint32_t)c & 0xff;
+ break;
+ case 3:
+ U4TXREG = (uint32_t)c & 0xff;
+ break;
+ }
+ }
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART_1_VECTOR))) uart_1_isr(void)
+{
+ uint32_t sta = U1STA;
+ if (sta & _U1STA_URXDA_MASK) {
+ uart_receive_ready(0);
+ IFS1CLR = _IFS1_U1RXIF_MASK;
+ }
+ if (sta & _U1STA_TRMT_MASK) {
+ uart_transmit_ready(0);
+ IFS1CLR = _IFS1_U1TXIF_MASK;
+ }
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART_2_VECTOR))) uart_2_isr(void)
+{
+ uint32_t sta = U2STA;
+ if (sta & _U2STA_URXDA_MASK) {
+ uart_receive_ready(1);
+ IFS1CLR = _IFS1_U2RXIF_MASK;
+ }
+ if (sta & _U2STA_TRMT_MASK) {
+ uart_transmit_ready(1);
+ IFS1CLR = _IFS1_U2TXIF_MASK;
+ }
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART_3_VECTOR))) uart_3_isr(void)
+{
+ uint32_t sta = U3STA;
+ if (sta & _U3STA_URXDA_MASK) {
+ uart_receive_ready(2);
+ IFS1CLR = _IFS1_U3RXIF_MASK;
+ }
+ if (sta & _U3STA_TRMT_MASK) {
+ uart_transmit_ready(2);
+ IFS2CLR = _IFS2_U3TXIF_MASK;
+ }
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART_4_VECTOR))) uart_4_isr(void)
+{
+ uint32_t sta = U4STA;
+ if (sta & _U4STA_URXDA_MASK) {
+ uart_receive_ready(3);
+ IFS2CLR = _IFS2_U4RXIF_MASK;
+ }
+ if (sta & _U4STA_TRMT_MASK) {
+ uart_transmit_ready(3);
+ IFS2CLR = _IFS2_U4TXIF_MASK;
+ }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+ if (uarts[port].u_rx_stall) {
+ /* recover saved data */
+ uint32_t sr;
+ __HAL_DISABLE_INTERRUPTS(sr);
+ int c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c >= 0) {
+ uarts[port].u_rx_stall = 0;
+ /* enable RX interrupt */
+ uart_enable_rx_int(port);
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ uart_enable_tx_int(port);
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ switch (port){
+ case 0:
+ /* wait for transmit holding register to be empty */
+ while(!(U1STA & _U1STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U1TXREG = data;
+ break;
+ case 1:
+ /* wait for transmit holding register to be empty */
+ while(!(U2STA & _U2STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U2TXREG = data;
+ break;
+ case 2:
+ /* wait for transmit holding register to be empty */
+ while(!(U3STA & _U3STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U3TXREG = data;
+ break;
+ case 3:
+ /* wait for transmit holding register to be empty */
+ while(!(U4STA & _U4STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U4TXREG = data;
+ break;
+ }
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint32_t peripheral_clk = MYNEWT_VAL(CLOCK_FREQ) / 2;
+
+ // check input
+ if ((databits < 8) || (databits > 9) || (stopbits < 1) || (stopbits > 2)) {
+ return -1;
+ }
+
+ /* XXX: flow control currently unsupported */
+ (void) flow_ctl;
+ uarts[port].u_rx_stall = 0;
+
+ uint16_t mode = _U1MODE_BRGH_MASK | (stopbits >> 1);
+ switch (parity) {
+ case HAL_UART_PARITY_NONE:
+ if (databits == 9) {
+ mode |= _U1MODE_PDSEL_MASK;
+ }
+ break;
+ case HAL_UART_PARITY_ODD:
+ if (databits == 9) { // PIC does not do 9 bit data + parity.
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL1_MASK;
+ break;
+ case HAL_UART_PARITY_EVEN:
+ if (databits == 9) {
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL0_MASK;
+ break;
+ default:
+ return -1;
+ }
+
+ uint16_t divisor = peripheral_clk / (4 * baudrate) - 1;
+
+ switch (port) {
+ case 0:
+ /* disable */
+ U1MODE = 0;
+ __asm__("nop");
+ U1BRG = divisor;
+ U1MODE = mode;
+ U1STA = _U1STA_URXEN_MASK | _U1STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS1CLR = _IFS1_U1RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC1SET = _IEC1_U1RXIE_MASK;
+
+ /* set interrupt priority */
+ IPC7CLR = _IPC7_U1IP_MASK;
+ IPC7SET = (1 << _IPC7_U1IP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC7CLR = _IPC7_U1IS_MASK;
+ IPC7SET = (0 << _IPC7_U1IS_POSITION); // subpriority 0
+ U1MODESET = _U1MODE_ON_MASK;
+ break;
+ case 1:
+ /* disable */
+ U2MODE = 0;
+ __asm__("nop");
+ U2BRG = divisor;
+ U2MODE = mode;
+ U2STA = _U2STA_URXEN_MASK | _U2STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS1CLR = _IFS1_U2RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC1SET = _IEC1_U2RXIE_MASK;
+
+ /* set interrupt priority */
+ IPC9CLR = _IPC9_U2IP_MASK;
+ IPC9SET = (1 << _IPC9_U2IP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC9CLR = _IPC9_U2IS_MASK;
+ IPC9SET = (0 << _IPC9_U2IS_POSITION); // subpriority 0
+ U2MODESET = _U2MODE_ON_MASK;
+ break;
+ case 2:
+ /* disable */
+ U3MODE = 0;
+ __asm__("nop");
+ U3BRG = divisor;
+ U3MODE = mode;
+ U3STA = _U3STA_URXEN_MASK | _U3STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS1CLR = _IFS1_U3RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC1SET = _IEC1_U3RXIE_MASK;
+
+ /* set interrupt priority */
+ IPC9CLR = _IPC9_U3IP_MASK;
+ IPC9SET = (1 << _IPC9_U3IP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC9CLR = _IPC9_U3IS_MASK;
+ IPC9SET = (0 << _IPC9_U3IS_POSITION); // subpriority 0
+ U3MODESET = _U3MODE_ON_MASK;
+ break;
+ case 3:
+ /* disable */
+ U4MODE = 0;
+ __asm__("nop");
+ U4BRG = divisor;
+ U4MODE = mode;
+ U4STA = _U4STA_URXEN_MASK | _U4STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS2CLR = _IFS2_U4RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC2SET = _IEC2_U4RXIE_MASK;
+
+ /* set interrupt priority */
+ IPC9CLR = _IPC9_U4IP_MASK;
+ IPC9SET = (1 << _IPC9_U4IP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC9CLR = _IPC9_U4IS_MASK;
+ IPC9SET = (0 << _IPC9_U4IS_POSITION); // subpriority 0
+ U4MODESET = _U4MODE_ON_MASK;
+ break;
+ }
+ return 0;
+}
+
+int
+hal_uart_close(int port)
+{
+ switch(port) {
+ case 0:
+ /* disable */
+ U1MODE = 0;
+ /* disable RX interrupt */
+ IEC1CLR = _IEC1_U1RXIE_MASK;
+ break;
+ case 1:
+ /* disable */
+ U2MODE = 0;
+ /* disable RX interrupt */
+ IEC1CLR = _IEC1_U2RXIE_MASK;
+ break;
+ case 2:
+ U3MODE = 0;
+ /* disable RX interrupt */
+ IEC1CLR = _IEC1_U3RXIE_MASK;
+ break;
+ case 3:
+ /* disable */
+ U4MODE = 0;
+ /* disable RX interrupt */
+ IEC2CLR = _IEC2_U4RXIE_MASK;
+ break;
+ default:
+ return -1;
+ }
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/src/hal_watchdog.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/src/hal_watchdog.c b/hw/mcu/microchip/pic32mx470f512h/src/hal_watchdog.c
new file mode 100644
index 0000000..392b967
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/src/hal_watchdog.c
@@ -0,0 +1,39 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_watchdog.h"
+
+#include <assert.h>
+
+int
+hal_watchdog_init(uint32_t expire_msecs)
+{
+ return (0);
+}
+
+void
+hal_watchdog_enable(void)
+{
+}
+
+void
+hal_watchdog_tickle(void)
+{
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mcu.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mcu.h b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mcu.h
new file mode 100644
index 0000000..2be36a9
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mcu.h
@@ -0,0 +1,25 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_MCU_H_
+#define __MCU_MCU_H_
+
+#include "p32mz2048efg100.h"
+
+#endif /* __MCU_MCU_H_ */
[2/7] incubator-mynewt-core git commit: Removed include path,
included specific parts of the Microchip SDK, fixed some errant capitalisation
Posted by ma...@apache.org.
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/kernel/os/include/os/arch/pic32/os/cp0defs.h
----------------------------------------------------------------------
diff --git a/kernel/os/include/os/arch/pic32/os/cp0defs.h b/kernel/os/include/os/arch/pic32/os/cp0defs.h
new file mode 100644
index 0000000..66cefed
--- /dev/null
+++ b/kernel/os/include/os/arch/pic32/os/cp0defs.h
@@ -0,0 +1,1215 @@
+/*-------------------------------------------------------------------------
+ *
+ * Copyright (c) 2014, Microchip Technology Inc. and its subsidiaries ("Microchip")
+ * All rights reserved.
+ * This software is developed by Microchip Technology Inc. and its
+ * subsidiaries ("Microchip").
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. Microchip's name may not be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *-------------------------------------------------------------------------*/
+
+#pragma once
+
+#ifndef __CP0DEFS__H__
+#define __CP0DEFS__H__
+/*
+ * Contains register definitions for the CP0 registers and bits and macros
+ * to access the CP0 registers. This file is included in xc.h and
+ * depends on macro definitions found in that file. To use this file
+ * include xc.h
+ */
+
+#ifdef __LANGUAGE_ASSEMBLY__
+/* CP0 Register Defines
+ * #define _CP0_<register_name> <register_number>, <select_number>
+ */
+#define _CP0_INDEX $0, 0
+#define _CP0_INX $0, 0
+#define _CP0_RANDOM $1, 0
+#define _CP0_RAND $1, 0
+#define _CP0_ENTRYLO0 $2, 0
+#define _CP0_TLBLO0 $2, 0
+#define _CP0_ENTRYLO1 $3, 0
+#define _CP0_TLBLO1 $3, 0
+#define _CP0_CONTEXT $4, 0
+#define _CP0_CTXT $4, 0
+#define _CP0_USERLOCAL $4, 2
+#define _CP0_PAGEMASK $5, 0
+#define _CP0_PAGEGRAIN $5, 1
+#define _CP0_WIRED $6, 0
+#define _CP0_HWRENA $7, 0
+#define _CP0_BADVADDR $8, 0
+#define _CP0_COUNT $9, 0
+#define _CP0_ENTRYHI $10, 0
+#define _CP0_COMPARE $11, 0
+#define _CP0_STATUS $12, 0
+#define _CP0_INTCTL $12, 1
+#define _CP0_SRSCTL $12, 2
+#define _CP0_SRSMAP $12, 3
+#define _CP0_VIEW_IPL $12, 4
+#define _CP0_SRSMAP2 $12, 5
+#define _CP0_CAUSE $13, 0
+#define _CP0_VIEW_RIPL $13, 1
+#define _CP0_NESTEDEXC $13, 2
+#define _CP0_EPC $14, 0
+#define _CP0_NESTEDEPC $14, 1
+#define _CP0_PRID $15, 0
+#define _CP0_EBASE $15, 1
+#define _CP0_CDMMBASE $15, 2
+#define _CP0_CONFIG $16, 0
+#define _CP0_CONFIG1 $16, 1
+#define _CP0_CONFIG2 $16, 2
+#define _CP0_CONFIG3 $16, 3
+#define _CP0_CONFIG4 $16, 4
+#define _CP0_CONFIG5 $16, 5
+#define _CP0_CONFIG7 $16, 7
+#define _CP0_LLADDR $17, 0
+#define _CP0_WATCHLO $18, 0
+#define _CP0_WATCHHI $19, 0
+#define _CP0_DEBUG $23, 0
+#define _CP0_TRACECONTROL $23, 1
+#define _CP0_TRACECONTROL2 $23, 2
+#define _CP0_USERTRACEDATA $23, 3
+#define _CP0_TRACEBPC $23, 4
+#define _CP0_DEBUG2 $23, 5
+#define _CP0_DEPC $24, 0
+#define _CP0_USERTRACEDATA2 $24, 1
+#define _CP0_PERFCNT0_CONTROL $25, 0
+#define _CP0_PERFCNT0_COUNT $25, 1
+#define _CP0_PERFCNT1_CONTROL $25, 2
+#define _CP0_PERFCNT1_COUNT $25, 3
+#define _CP0_ERRCTL $26, 0
+#define _CP0_CACHEERR $27, 0
+#define _CP0_TAGLO $28, 0
+#define _CP0_DATALO $28, 1
+#define _CP0_ERROREPC $30, 0
+#define _CP0_DESAVE $31, 0
+
+#else
+#define _CP0_INDEX 0
+#define _CP0_INDEX_SELECT 0
+#define _CP0_INX 0
+#define _CP0_INX_SELECT 0
+#define _CP0_RANDOM 1
+#define _CP0_RANDOM_SELECT 0
+#define _CP0_RAND 1
+#define _CP0_RAND_SELECT 0
+#define _CP0_ENTRYLO0 2
+#define _CP0_ENTRYLO0_SELECT 0
+#define _CP0_TLBLO0 2
+#define _CP0_TLBLO0_SELECT 0
+#define _CP0_ENTRYLO1 3
+#define _CP0_ENTRYLO1_SELECT 0
+#define _CP0_TLBLO1 3
+#define _CP0_TLBLO1_SELECT 0
+#define _CP0_CONTEXT 4
+#define _CP0_CONTEXT_SELECT 0
+#define _CP0_CTXT 4
+#define _CP0_CTXT_SELECT 0
+#define _CP0_USERLOCAL 4
+#define _CP0_USERLOCAL_SELECT 2
+#define _CP0_PAGEMASK 5
+#define _CP0_PAGEMASK_SELECT 0
+#define _CP0_PAGEGRAIN 5
+#define _CP0_PAGEGRAIN_SELECT 1
+#define _CP0_WIRED 6
+#define _CP0_WIRED_SELECT 0
+#define _CP0_HWRENA 7
+#define _CP0_HWRENA_SELECT 0
+#define _CP0_BADVADDR 8
+#define _CP0_BADVADDR_SELECT 0
+#define _CP0_COUNT 9
+#define _CP0_COUNT_SELECT 0
+#define _CP0_ENTRYHI 10
+#define _CP0_ENTRYHI_SELECT 0
+#define _CP0_COMPARE 11
+#define _CP0_COMPARE_SELECT 0
+#define _CP0_STATUS 12
+#define _CP0_STATUS_SELECT 0
+#define _CP0_INTCTL 12
+#define _CP0_INTCTL_SELECT 1
+#define _CP0_SRSCTL 12
+#define _CP0_SRSCTL_SELECT 2
+#define _CP0_SRSMAP 12
+#define _CP0_SRSMAP_SELECT 3
+#define _CP0_VIEW_IPL 12
+#define _CP0_VIEW_IPL_SELECT 4
+#define _CP0_SRSMAP2 12
+#define _CP0_SRSMAP2_SELECT 5
+#define _CP0_CAUSE 13
+#define _CP0_CAUSE_SELECT 0
+#define _CP0_VIEW_RIPL 13
+#define _CP0_VIEW_RIPL_SELECT 1
+#define _CP0_NESTEDEXC 13
+#define _CP0_NESTEDEXC_SELECT 2
+#define _CP0_EPC 14
+#define _CP0_EPC_SELECT 0
+#define _CP0_NESTEDEPC 14
+#define _CP0_NESTEDEPC_SELECT 1
+#define _CP0_PRID 15
+#define _CP0_PRID_SELECT 0
+#define _CP0_EBASE 15
+#define _CP0_EBASE_SELECT 1
+#define _CP0_CDMMBASE 15
+#define _CP0_CDMMBASE_SELECT 2
+#define _CP0_CONFIG 16
+#define _CP0_CONFIG_SELECT 0
+#define _CP0_CONFIG1 16
+#define _CP0_CONFIG1_SELECT 1
+#define _CP0_CONFIG2 16
+#define _CP0_CONFIG2_SELECT 2
+#define _CP0_CONFIG3 16
+#define _CP0_CONFIG3_SELECT 3
+#define _CP0_CONFIG4 16
+#define _CP0_CONFIG4_SELECT 4
+#define _CP0_CONFIG5 16
+#define _CP0_CONFIG5_SELECT 5
+#define _CP0_CONFIG7 16
+#define _CP0_CONFIG7_SELECT 7
+#define _CP0_LLADDR 17
+#define _CP0_LLADDR_SELECT 0
+#define _CP0_WATCHLO 18
+#define _CP0_WATCHLO_SELECT 0
+#define _CP0_WATCHHI 19
+#define _CP0_WATCHHI_SELECT 0
+#define _CP0_DEBUG 23
+#define _CP0_DEBUG_SELECT 0
+#define _CP0_TRACECONTROL 23
+#define _CP0_TRACECONTROL_SELECT 1
+#define _CP0_TRACECONTROL2 23
+#define _CP0_TRACECONTROL2_SELECT 2
+#define _CP0_USERTRACEDATA 23
+#define _CP0_USERTRACEDATA_SELECT 3
+#define _CP0_TRACEBPC 23
+#define _CP0_TRACEBPC_SELECT 4
+#define _CP0_DEBUG2 23
+#define _CP0_DEBUG2_SELEECT 5
+#define _CP0_DEPC 24
+#define _CP0_DEPC_SELECT 0
+#define _CP0_USERTRACEDATA2 24
+#define _CP0_USERTRACEDATA2_SELECT 1
+#define _CP0_PERFCNT 25
+#define _CP0_PERFCNT0_CONTROL 25
+#define _CP0_PERFCNT0_CONTROL_SELECT 0
+#define _CP0_PERFCNT0_COUNT 25
+#define _CP0_PERFCNT0_COUNT_SELECT 1
+#define _CP0_PERFCNT1_CONTROL 25
+#define _CP0_PERFCNT1_CONTROL_SELECT 2
+#define _CP0_PERFCNT1_COUNT 25
+#define _CP0_PERFCNT1_COUNT_SELECT 3
+#define _CP0_ERRCTL 26
+#define _CP0_ERRCTL_SELECT 0
+#define _CP0_CACHEERR 27
+#define _CP0_CACHEERR_SELECT 0
+#define _CP0_TAGLO 28
+#define _CP0_TAGLO_SELECT 0
+#define _CP0_DATALO 28
+#define _CP0_DATALO_SELECT 1
+#define _CP0_ERROREPC 30
+#define _CP0_ERROREPC_SELECT 0
+#define _CP0_DESAVE 31
+#define _CP0_DESAVE_SELECT 0
+
+#define _CP0_GET_INDEX() _mfc0 (_CP0_INDEX, _CP0_INDEX_SELECT)
+#define _CP0_SET_INDEX(val) _mtc0 (_CP0_INDEX, _CP0_INDEX_SELECT, val)
+#define _CP0_XCH_INDEX(val) _mxc0 (_CP0_INDEX, _CP0_INDEX_SELECT, val)
+#define _CP0_BIC_INDEX(clr) _bcc0 (_CP0_INDEX, _CP0_INDEX_SELECT, clr)
+#define _CP0_BIS_INDEX(set) _bsc0 (_CP0_INDEX, _CP0_INDEX_SELECT, set)
+#define _CP0_BCS_INDEX(c,s) _bcsc0(_CP0_INDEX, _CP0_INDEX_SELECT, c, s)
+
+#define _CP0_GET_INX() _mfc0 (_CP0_INX, _CP0_INX_SELECT)
+#define _CP0_SET_INX(val) _mtc0 (_CP0_INX, _CP0_INX_SELECT, val)
+#define _CP0_XCH_INX(val) _mxc0 (_CP0_INX, _CP0_INX_SELECT, val)
+#define _CP0_BIC_INX(clr) _bcc0 (_CP0_INX, _CP0_INX_SELECT, clr)
+#define _CP0_BIS_INX(set) _bsc0 (_CP0_INX, _CP0_INX_SELECT, set)
+#define _CP0_BCS_INX(c,s) _bcsc0(_CP0_INX, _CP0_INX_SELECT, c, s)
+
+#define _CP0_GET_RANDOM() _mfc0 (_CP0_RANDOM, _CP0_RANDOM_SELECT)
+
+#define _CP0_GET_RAND() _mfc0 (_CP0_RAND, _CP0_RAND_SELECT)
+
+#define _CP0_GET_ENTRYLO0() _mfc0 (_CP0_ENTRYLO0, _CP0_ENTRYLO0_SELECT)
+#define _CP0_SET_ENTRYLO0(val) _mtc0 (_CP0_ENTRYLO0, _CP0_ENTRYLO0_SELECT, val)
+#define _CP0_XCH_ENTRYLO0(val) _mxc0 (_CP0_ENTRYLO0, _CP0_ENTRYLO0_SELECT, val)
+#define _CP0_BIC_ENTRYLO0(clr) _bcc0 (_CP0_ENTRYLO0, _CP0_ENTRYLO0_SELECT, clr)
+#define _CP0_BIS_ENTRYLO0(set) _bsc0 (_CP0_ENTRYLO0, _CP0_ENTRYLO0_SELECT, set)
+#define _CP0_BCS_ENTRYLO0(c,s) _bcsc0(_CP0_ENTRYLO0, _CP0_ENTRYLO0_SELECT, c, s)
+
+#define _CP0_GET_TLBLO0() _mfc0 (_CP0_TLBLO0, _CP0_TLBLO0_SELECT)
+#define _CP0_SET_TLBLO0(val) _mtc0 (_CP0_TLBLO0, _CP0_TLBLO0_SELECT, val)
+#define _CP0_XCH_TLBLO0(val) _mxc0 (_CP0_TLBLO0, _CP0_TLBLO0_SELECT, val)
+#define _CP0_BIC_TLBLO0(clr) _bcc0 (_CP0_TLBLO0, _CP0_TLBLO0_SELECT, clr)
+#define _CP0_BIS_TLBLO0(set) _bsc0 (_CP0_TLBLO0, _CP0_TLBLO0_SELECT, set)
+#define _CP0_BCS_TLBLO0(c,s) _bcsc0(_CP0_TLBLO0, _CP0_TLBLO0_SELECT, c, s)
+
+#define _CP0_GET_ENTRYLO1() _mfc0 (_CP0_ENTRYLO1, _CP0_ENTRYLO1_SELECT)
+#define _CP0_SET_ENTRYLO1(val) _mtc0 (_CP0_ENTRYLO1, _CP0_ENTRYLO1_SELECT, val)
+#define _CP0_XCH_ENTRYLO1(val) _mxc0 (_CP0_ENTRYLO1, _CP0_ENTRYLO1_SELECT, val)
+#define _CP0_BIC_ENTRYLO1(clr) _bcc0 (_CP0_ENTRYLO1, _CP0_ENTRYLO1_SELECT, clr)
+#define _CP0_BIS_ENTRYLO1(set) _bsc0 (_CP0_ENTRYLO1, _CP0_ENTRYLO1_SELECT, set)
+#define _CP0_BCS_ENTRYLO1(c,s) _bcsc0(_CP0_ENTRYLO1, _CP0_ENTRYLO1_SELECT, c, s)
+
+#define _CP0_GET_TLBLO1() _mfc0 (_CP0_TLBLO1, _CP0_TLBLO1_SELECT)
+#define _CP0_SET_TLBLO1(val) _mtc0 (_CP0_TLBLO1, _CP0_TLBLO1_SELECT, val)
+#define _CP0_XCH_TLBLO1(val) _mxc0 (_CP0_TLBLO1, _CP0_TLBLO1_SELECT, val)
+#define _CP0_BIC_TLBLO1(clr) _bcc0 (_CP0_TLBLO1, _CP0_TLBLO1_SELECT, clr)
+#define _CP0_BIS_TLBLO1(set) _bsc0 (_CP0_TLBLO1, _CP0_TLBLO1_SELECT, set)
+#define _CP0_BCS_TLBLO1(c,s) _bcsc0(_CP0_TLBLO1, _CP0_TLBLO1_SELECT, c, s)
+
+#define _CP0_GET_CONTEXT() _mfc0 (_CP0_CONTEXT, _CP0_CONTEXT_SELECT)
+#define _CP0_SET_CONTEXT(val) _mtc0 (_CP0_CONTEXT, _CP0_CONTEXT_SELECT, val)
+#define _CP0_XCH_CONTEXT(val) _mxc0 (_CP0_CONTEXT, _CP0_CONTEXT_SELECT, val)
+#define _CP0_BIC_CONTEXT(clr) _bcc0 (_CP0_CONTEXT, _CP0_CONTEXT_SELECT, clr)
+#define _CP0_BIS_CONTEXT(set) _bsc0 (_CP0_CONTEXT, _CP0_CONTEXT_SELECT, set)
+#define _CP0_BCS_CONTEXT(c,s) _bcsc0(_CP0_CONTEXT, _CP0_CONTEXT_SELECT, c, s)
+
+#define _CP0_GET_CTXT() _mfc0 (_CP0_CTXT, _CP0_CTXT_SELECT)
+#define _CP0_SET_CTXT(val) _mtc0 (_CP0_CTXT, _CP0_CTXT_SELECT, val)
+#define _CP0_XCH_CTXT(val) _mxc0 (_CP0_CTXT, _CP0_CTXT_SELECT, val)
+#define _CP0_BIC_CTXT(clr) _bcc0 (_CP0_CTXT, _CP0_CTXT_SELECT, clr)
+#define _CP0_BIS_CTXT(set) _bsc0 (_CP0_CTXT, _CP0_CTXT_SELECT, set)
+#define _CP0_BCS_CTXT(c,s) _bcsc0(_CP0_CTXT, _CP0_CTXT_SELECT, c, s)
+
+#define _CP0_GET_USERLOCAL() _mfc0 (_CP0_USERLOCAL, _CP0_USERLOCAL_SELECT)
+#define _CP0_SET_USERLOCAL(val) _mtc0 (_CP0_USERLOCAL, _CP0_USERLOCAL_SELECT, val)
+
+#define _CP0_GET_PAGEMASK() _mfc0 (_CP0_PAGEMASK, _CP0_PAGEMASK_SELECT)
+#define _CP0_SET_PAGEMASK(val) _mtc0 (_CP0_PAGEMASK, _CP0_PAGEMASK_SELECT, val)
+
+#define _CP0_GET_PAGEGRAIN() _mfc0 (_CP0_PAGEGRAIN, _CP0_PAGEGRAIN_SELECT)
+#define _CP0_SET_PAGEGRAIN(val) _mtc0 (_CP0_PAGEGRAIN, _CP0_PAGEGRAIN_SELECT, val)
+#define _CP0_XCH_PAGEGRAIN(val) _mxc0 (_CP0_PAGEGRAIN, _CP0_PAGEGRAIN_SELECT, val)
+#define _CP0_BIC_PAGEGRAIN(clr) _bcc0 (_CP0_PAGEGRAIN, _CP0_PAGEGRAIN_SELECT, clr)
+#define _CP0_BIS_PAGEGRAIN(set) _bsc0 (_CP0_PAGEGRAIN, _CP0_PAGEGRAIN_SELECT, set)
+#define _CP0_BCS_PAGEGRAIN(c,s) _bcsc0(_CP0_PAGEGRAIN, _CP0_PAGEGRAIN_SELECT, c, s)
+
+#define _CP0_GET_WIRED() _mfc0 (_CP0_WIRED, _CP0_WIRED_SELECT)
+#define _CP0_SET_WIRED(val) _mtc0 (_CP0_WIRED, _CP0_WIRED_SELECT, val)
+
+#define _CP0_GET_HWRENA() _mfc0 (_CP0_HWRENA, _CP0_HWRENA_SELECT)
+#define _CP0_SET_HWRENA(val) _mtc0 (_CP0_HWRENA, _CP0_HWRENA_SELECT, val)
+#define _CP0_XCH_HWRENA(val) _mxc0 (_CP0_HWRENA, _CP0_HWRENA_SELECT, val)
+#define _CP0_BIC_HWRENA(clr) _bcc0 (_CP0_HWRENA, _CP0_HWRENA_SELECT, clr)
+#define _CP0_BIS_HWRENA(set) _bsc0 (_CP0_HWRENA, _CP0_HWRENA_SELECT, set)
+#define _CP0_BCS_HWRENA(c,s) _bcsc0(_CP0_HWRENA, _CP0_HWRENA_SELECT, c, s)
+
+#define _CP0_GET_BADVADDR() _mfc0 (_CP0_BADVADDR, _CP0_BADVADDR_SELECT)
+
+#define _CP0_GET_COUNT() _mfc0 (_CP0_COUNT, _CP0_COUNT_SELECT)
+#define _CP0_SET_COUNT(val) _mtc0 (_CP0_COUNT, _CP0_COUNT_SELECT, val)
+
+#define _CP0_GET_COUNT() _mfc0 (_CP0_COUNT, _CP0_COUNT_SELECT)
+#define _CP0_SET_COUNT(val) _mtc0 (_CP0_COUNT, _CP0_COUNT_SELECT, val)
+
+#define _CP0_GET_ENTRYHI() _mfc0 (_CP0_ENTRYHI, _CP0_ENTRYHI_SELECT)
+#define _CP0_SET_ENTRYHI(val) _mtc0 (_CP0_ENTRYHI, _CP0_ENTRYHI_SELECT, val)
+#define _CP0_XCH_ENTRYHI(val) _mxc0 (_CP0_ENTRYHI, _CP0_ENTRYHI_SELECT, val)
+#define _CP0_BIC_ENTRYHI(clr) _bcc0 (_CP0_ENTRYHI, _CP0_ENTRYHI_SELECT, clr)
+#define _CP0_BIS_ENTRYHI(set) _bsc0 (_CP0_ENTRYHI, _CP0_ENTRYHI_SELECT, set)
+#define _CP0_BCS_ENTRYHI(c,s) _bcsc0(_CP0_ENTRYHI, _CP0_ENTRYHI_SELECT, c, s)
+
+#define _CP0_GET_COMPARE() _mfc0 (_CP0_COMPARE, _CP0_COMPARE_SELECT)
+#define _CP0_SET_COMPARE(val) _mtc0 (_CP0_COMPARE, _CP0_COMPARE_SELECT, val)
+
+#define _CP0_GET_STATUS() _mfc0 (_CP0_STATUS, _CP0_STATUS_SELECT)
+#define _CP0_SET_STATUS(val) _mtc0 (_CP0_STATUS, _CP0_STATUS_SELECT, val)
+#define _CP0_XCH_STATUS(val) _mxc0 (_CP0_STATUS, _CP0_STATUS_SELECT, val)
+#define _CP0_BIC_STATUS(clr) _bcc0 (_CP0_STATUS, _CP0_STATUS_SELECT, clr)
+#define _CP0_BIS_STATUS(set) _bsc0 (_CP0_STATUS, _CP0_STATUS_SELECT, set)
+#define _CP0_BCS_STATUS(c,s) _bcsc0(_CP0_STATUS, _CP0_STATUS_SELECT, c, s)
+
+#define _CP0_GET_INTCTL() _mfc0 (_CP0_INTCTL, _CP0_INTCTL_SELECT)
+#define _CP0_SET_INTCTL(val) _mtc0 (_CP0_INTCTL, _CP0_INTCTL_SELECT, val)
+#define _CP0_XCH_INTCTL(val) _mxc0 (_CP0_INTCTL, _CP0_INTCTL_SELECT, val)
+
+#define _CP0_GET_SRSCTL() _mfc0 (_CP0_SRSCTL, _CP0_SRSCTL_SELECT)
+#define _CP0_SET_SRSCTL(val) _mtc0 (_CP0_SRSCTL, _CP0_SRSCTL_SELECT, val)
+#define _CP0_XCH_SRSCTL(val) _mxc0 (_CP0_SRSCTL, _CP0_SRSCTL_SELECT, val)
+
+#define _CP0_GET_SRSMAP() _mfc0 (_CP0_SRSMAP, _CP0_SRSMAP_SELECT)
+#define _CP0_SET_SRSMAP(val) _mtc0 (_CP0_SRSMAP, _CP0_SRSMAP_SELECT, val)
+#define _CP0_XCH_SRSMAP(val) _mxc0 (_CP0_SRSMAP, _CP0_SRSMAP_SELECT, val)
+
+#define _CP0_GET_VIEW_IPL() _mfc0 (_CP0_VIEW_IPL, _CP0_VIEW_IPL_SELECT)
+#define _CP0_SET_VIEW_IPL(val) _mtc0 (_CP0_VIEW_IPL, _CP0_VIEW_IPL_SELECT, val)
+#define _CP0_XCH_VIEW_IPL(val) _mxc0 (_CP0_VIEW_IPL, _CP0_VIEW_IPL_SELECT, val)
+#define _CP0_BIC_VIEW_IPL(clr) _bcc0 (_CP0_VIEW_IPL, _CP0_VIEW_IPL_SELECT, clr)
+#define _CP0_BIS_VIEW_IPL(set) _bsc0 (_CP0_VIEW_IPL, _CP0_VIEW_IPL_SELECT, set)
+#define _CP0_BCS_VIEW_IPL(c,s) _bcsc0(_CP0_VIEW_IPL, _CP0_VIEW_IPL_SELECT, c, s)
+
+#define _CP0_GET_SRSMAP2() _mfc0 (_CP0_SRSMAP2, _CP0_SRSMAP2_SELECT)
+#define _CP0_SET_SRSMAP2(val) _mtc0 (_CP0_SRSMAP2, _CP0_SRSMAP2_SELECT, val)
+#define _CP0_XCH_SRSMAP2(val) _mxc0 (_CP0_SRSMAP2, _CP0_SRSMAP2_SELECT, val)
+
+#define _CP0_GET_CAUSE() _mfc0 (_CP0_CAUSE, _CP0_CAUSE_SELECT)
+#define _CP0_SET_CAUSE(val) _mtc0 (_CP0_CAUSE, _CP0_CAUSE_SELECT, val)
+#define _CP0_XCH_CAUSE(val) _mxc0 (_CP0_CAUSE, _CP0_CAUSE_SELECT, val)
+#define _CP0_BIC_CAUSE(clr) _bcc0 (_CP0_CAUSE, _CP0_CAUSE_SELECT, clr)
+#define _CP0_BIS_CAUSE(set) _bsc0 (_CP0_CAUSE, _CP0_CAUSE_SELECT, set)
+#define _CP0_BCS_CAUSE(c,s) _bcsc0(_CP0_CAUSE, _CP0_CAUSE_SELECT, c, s)
+
+#define _CP0_GET_VIEW_RIPL() _mfc0 (_CP0_VIEW_RIPL, _CP0_VIEW_RIPL_SELECT)
+#define _CP0_SET_VIEW_RIPL(val) _mtc0 (_CP0_VIEW_RIPL, _CP0_VIEW_RIPL_SELECT, val)
+#define _CP0_XCH_VIEW_RIPL(val) _mxc0 (_CP0_VIEW_RIPL, _CP0_VIEW_RIPL_SELECT, val)
+#define _CP0_BIC_VIEW_RIPL(clr) _bcc0 (_CP0_VIEW_RIPL, _CP0_VIEW_RIPL_SELECT, clr)
+#define _CP0_BIS_VIEW_RIPL(set) _bsc0 (_CP0_VIEW_RIPL, _CP0_VIEW_RIPL_SELECT, set)
+#define _CP0_BCS_VIEW_RIPL(c,s) _bcsc0(_CP0_VIEW_RIPL, _CP0_VIEW_RIPL_SELECT, c, s)
+
+#define _CP0_GET_NESTEDEXC() _mfc0 (_CP0_NESTEDEXC, _CP0_NESTEDEXC_SELECT)
+#define _CP0_SET_NESTEDEXC(val) _mtc0 (_CP0_NESTEDEXC, _CP0_NESTEDEXC_SELECT, val)
+#define _CP0_XCH_NESTEDEXC(val) _mxc0 (_CP0_NESTEDEXC, _CP0_NESTEDEXC_SELECT, val)
+#define _CP0_BIC_NESTEDEXC(clr) _bcc0 (_CP0_NESTEDEXC, _CP0_NESTEDEXC_SELECT, clr)
+#define _CP0_BIS_NESTEDEXC(set) _bsc0 (_CP0_NESTEDEXC, _CP0_NESTEDEXC_SELECT, set)
+#define _CP0_BCS_NESTEDEXC(c,s) _bcsc0(_CP0_NESTEDEXC, _CP0_NESTEDEXC_SELECT, c, s)
+
+#define _CP0_GET_EPC() _mfc0 (_CP0_EPC, _CP0_EPC_SELECT)
+#define _CP0_SET_EPC(val) _mtc0 (_CP0_EPC, _CP0_EPC_SELECT, val)
+
+#define _CP0_GET_NESTEDEPC() _mfc0 (_CP0_NESTEDEPC, _CP0_NESTEDEPC_SELECT)
+#define _CP0_SET_NESTEDEPC(val) _mtc0 (_CP0_NESTEDEPC, _CP0_NESTEDEPC_SELECT, val)
+
+#define _CP0_GET_PRID() _mfc0 (_CP0_PRID, _CP0_PRID_SELECT)
+
+#define _CP0_GET_EBASE() _mfc0 (_CP0_EBASE, _CP0_EBASE_SELECT)
+#define _CP0_SET_EBASE(val) _mtc0 (_CP0_EBASE, _CP0_EBASE_SELECT, val)
+#define _CP0_XCH_EBASE(val) _mxc0 (_CP0_EBASE, _CP0_EBASE_SELECT, val)
+
+#define _CP0_GET_CDMMBASE() _mfc0 (_CP0_CDMMBASE, _CP0_CDMMBASE_SELECT)
+#define _CP0_SET_CDMMBASE(val) _mtc0 (_CP0_CDMMBASE, _CP0_CDMMBASE_SELECT, val)
+#define _CP0_XCH_CDMMBASE(val) _mxc0 (_CP0_CDMMBASE, _CP0_CDMMBASE_SELECT, val)
+#define _CP0_BIC_CDMMBASE(clr) _bcc0 (_CP0_CDMMBASE, _CP0_CDMMBASE_SELECT, clr)
+#define _CP0_BIS_CDMMBASE(set) _bsc0 (_CP0_CDMMBASE, _CP0_CDMMBASE_SELECT, set)
+#define _CP0_BCS_CDMMBASE(c,s) _bcsc0(_CP0_CDMMBASE, _CP0_CDMMBASE_SELECT, c, s)
+
+#define _CP0_GET_CONFIG() _mfc0 (_CP0_CONFIG, _CP0_CONFIG_SELECT)
+#define _CP0_GET_CONFIG1() _mfc0 (_CP0_CONFIG1, _CP0_CONFIG1_SELECT)
+#define _CP0_GET_CONFIG2() _mfc0 (_CP0_CONFIG2, _CP0_CONFIG2_SELECT)
+#define _CP0_GET_CONFIG3() _mfc0 (_CP0_CONFIG3, _CP0_CONFIG3_SELECT)
+#define _CP0_GET_CONFIG4() _mfc0 (_CP0_CONFIG4, _CP0_CONFIG4_SELECT)
+#define _CP0_GET_CONFIG5() _mfc0 (_CP0_CONFIG5, _CP0_CONFIG5_SELECT)
+#define _CP0_GET_CONFIG7() _mfc0 (_CP0_CONFIG7, _CP0_CONFIG7_SELECT)
+
+#define _CP0_GET_LLADDR() _mfc0 (_CP0_LLADDR, _CP0_LLADDR_SELECT)
+
+#define _CP0_GET_WATCHLO() _mfc0 (_CP0_WATCHLO, _CP0_WATCHLO_SELECT)
+#define _CP0_SET_WATCHLO(val) _mtc0 (_CP0_WATCHLO, _CP0_WATCHLO_SELECT, val)
+#define _CP0_XCH_WATCHLO(val) _mxc0 (_CP0_WATCHLO, _CP0_WATCHLO_SELECT, val)
+#define _CP0_BIC_WATCHLO(clr) _bcc0 (_CP0_WATCHLO, _CP0_WATCHLO_SELECT, clr)
+#define _CP0_BIS_WATCHLO(set) _bsc0 (_CP0_WATCHLO, _CP0_WATCHLO_SELECT, set)
+#define _CP0_BCS_WATCHLO(c,s) _bcsc0(_CP0_WATCHLO, _CP0_WATCHLO_SELECT, c, s)
+
+#define _CP0_GET_WATCHHI() _mfc0 (_CP0_WATCHHI, _CP0_WATCHHI_SELECT)
+#define _CP0_SET_WATCHHI(val) _mtc0 (_CP0_WATCHHI, _CP0_WATCHHI_SELECT, val)
+#define _CP0_XCH_WATCHHI(val) _mxc0 (_CP0_WATCHHI, _CP0_WATCHHI_SELECT, val)
+#define _CP0_BIC_WATCHHI(clr) _bcc0 (_CP0_WATCHHI, _CP0_WATCHHI_SELECT, clr)
+#define _CP0_BIS_WATCHHI(set) _bsc0 (_CP0_WATCHHI, _CP0_WATCHHI_SELECT, set)
+#define _CP0_BCS_WATCHHI(c,s) _bcsc0(_CP0_WATCHHI, _CP0_WATCHHI_SELECT, c, s)
+
+#define _CP0_GET_DEBUG() _mfc0 (_CP0_DEBUG, _CP0_DEBUG_SELECT)
+#define _CP0_SET_DEBUG(val) _mtc0 (_CP0_DEBUG, _CP0_DEBUG_SELECT, val)
+#define _CP0_XCH_DEBUG(val) _mxc0 (_CP0_DEBUG, _CP0_DEBUG_SELECT, val)
+#define _CP0_BIC_DEBUG(clr) _bcc0 (_CP0_DEBUG, _CP0_DEBUG_SELECT, clr)
+#define _CP0_BIS_DEBUG(set) _bsc0 (_CP0_DEBUG, _CP0_DEBUG_SELECT, set)
+#define _CP0_BCS_DEBUG(c,s) _bcsc0(_CP0_DEBUG, _CP0_DEBUG_SELECT, c, s)
+
+#define _CP0_GET_TRACECONTROL() \
+ _mfc0 (_CP0_TRACECONTROL, _CP0_TRACECONTROL_SELECT)
+#define _CP0_SET_TRACECONTROL(val) \
+ _mtc0 (_CP0_TRACECONTROL, _CP0_TRACECONTROL_SELECT, val)
+#define _CP0_XCH_TRACECONTROL(val) \
+ _mxc0 (_CP0_TRACECONTROL, _CP0_TRACECONTROL_SELECT, val)
+#define _CP0_BIC_TRACECONTROL(clr) \
+ _bcc0 (_CP0_TRACECONTROL, _CP0_TRACECONTROL_SELECT, clr)
+#define _CP0_BIS_TRACECONTROL(set) \
+ _bsc0 (_CP0_TRACECONTROL, _CP0_TRACECONTROL_SELECT, set)
+#define _CP0_BCS_TRACECONTROL(c,s) \
+ _bcsc0(_CP0_TRACECONTROL, _CP0_TRACECONTROL_SELECT, c, s)
+
+#define _CP0_GET_TRACECONTROL2() \
+ _mfc0 (_CP0_TRACECONTROL2, _CP0_TRACECONTROL2_SELECT)
+
+#define _CP0_GET_USERTRACEDATA() \
+ _mfc0 (_CP0_USERTRACEDATA, _CP0_USERTRACEDATA_SELECT)
+#define _CP0_SET_USERTRACEDATA(val) \
+ _mtc0 (_CP0_USERTRACEDATA, _CP0_USERTRACEDATA_SELECT, val)
+#define _CP0_XCH_USERTRACEDATA(val) \
+ _mxc0 (_CP0_USERTRACEDATA, _CP0_USERTRACEDATA_SELECT, val)
+
+#define _CP0_GET_USERTRACEDATA2() \
+ _mfc0 (_CP0_USERTRACEDATA2, _CP0_USERTRACEDATA2_SELECT)
+#define _CP0_SET_USERTRACEDATA2(val) \
+ _mtc0 (_CP0_USERTRACEDATA2, _CP0_USERTRACEDATA2_SELECT, val)
+#define _CP0_XCH_USERTRACEDATA2(val) \
+ _mxc0 (_CP0_USERTRACEDATA2, _CP0_USERTRACEDATA2_SELECT, val)
+
+#define _CP0_GET_TRACEBPC() _mfc0 (_CP0_TRACEBPC, _CP0_TRACEBPC_SELECT)
+#define _CP0_SET_TRACEBPC(val) _mtc0 (_CP0_TRACEBPC, _CP0_TRACEBPC_SELECT, val)
+#define _CP0_XCH_TRACEBPC(val) _mxc0 (_CP0_TRACEBPC, _CP0_TRACEBPC_SELECT, val)
+#define _CP0_BIC_TRACEBPC(clr) _bcc0 (_CP0_TRACEBPC, _CP0_TRACEBPC_SELECT, clr)
+#define _CP0_BIS_TRACEBPC(set) _bsc0 (_CP0_TRACEBPC, _CP0_TRACEBPC_SELECT, set)
+#define _CP0_BCS_TRACEBPC(c,s) _bcsc0(_CP0_TRACEBPC, _CP0_TRACEBPC_SELECT, c, s)
+
+#define _CP0_GET_DEBUG2() _mfc0 (_CP0_DEBUG2, _CP0_DEBUG2_SELECT)
+
+#define _CP0_GET_DEPC() _mfc0 (_CP0_DEPC, _CP0_DEPC_SELECT)
+#define _CP0_SET_DEPC(val) _mtc0 (_CP0_DEPC, _CP0_DEPC_SELECT, val)
+#define _CP0_XCH_DEPC(val) _mxc0 (_CP0_DEPC, _CP0_DEPC_SELECT, val)
+
+#define _CP0_GET_PERFCNT0_CONTROL() _mfc0 (_CP0_PERFCNT0_CONTROL, _CP0_PERFCNT0_CONTROL_SELECT)
+#define _CP0_SET_PERFCNT0_CONTROL(val) _mtc0 (_CP0_PERFCNT0_CONTROL, _CP0_PERFCNT0_CONTROL_SELECT, val)
+#define _CP0_XCH_PERFCNT0_CONTROL(val) _mxc0 (_CP0_PERFCNT0_CONTROL, _CP0_PERFCNT0_CONTROL_SELECT, val)
+#define _CP0_BIC_PERFCNT0_CONTROL(clr) _bcc0 (_CP0_PERFCNT0_CONTROL, _CP0_PERFCNT0_CONTROL_SELECT, clr)
+#define _CP0_BIS_PERFCNT0_CONTROL(set) _bsc0 (_CP0_PERFCNT0_CONTROL, _CP0_PERFCNT0_CONTROL_SELECT, set)
+#define _CP0_BCS_PERFCNT0_CONTROL(c,s) _bcsc0(_CP0_PERFCNT0_CONTROL, _CP0_PERFCNT0_CONTROL_SELECT, c, s)
+
+#define _CP0_GET_PERFCNT0_COUNT() _mfc0 (_CP0_PERFCNT0_COUNT, _CP0_PERFCNT0_COUNT_SELECT)
+#define _CP0_SET_PERFCNT0_COUNT(val) _mtc0 (_CP0_PERFCNT0_COUNT, _CP0_PERFCNT0_COUNT_SELECT, val)
+
+#define _CP0_GET_PERFCNT1_CONTROL() _mfc0 (_CP0_PERFCNT1_CONTROL, _CP0_PERFCNT1_CONTROL_SELECT)
+#define _CP0_SET_PERFCNT1_CONTROL(val) _mtc0 (_CP0_PERFCNT1_CONTROL, _CP0_PERFCNT1_CONTROL_SELECT, val)
+#define _CP0_XCH_PERFCNT1_CONTROL(val) _mxc0 (_CP0_PERFCNT1_CONTROL, _CP0_PERFCNT1_CONTROL_SELECT, val)
+#define _CP0_BIC_PERFCNT1_CONTROL(clr) _bcc0 (_CP0_PERFCNT1_CONTROL, _CP0_PERFCNT1_CONTROL_SELECT, clr)
+#define _CP0_BIS_PERFCNT1_CONTROL(set) _bsc0 (_CP0_PERFCNT1_CONTROL, _CP0_PERFCNT1_CONTROL_SELECT, set)
+#define _CP0_BCS_PERFCNT1_CONTROL(c,s) _bcsc0(_CP0_PERFCNT1_CONTROL, _CP0_PERFCNT1_CONTROL_SELECT, c, s)
+
+#define _CP0_GET_PERFCNT1_COUNT() _mfc0 (_CP0_PERFCNT1_COUNT, _CP0_PERFCNT1_COUNT_SELECT)
+#define _CP0_SET_PERFCNT1_COUNT(val) _mtc0 (_CP0_PERFCNT1_COUNT, _CP0_PERFCNT1_COUNT_SELECT, val)
+
+#define _CP0_GET_CACHEERR() _mfc0 (_CP0_CACHEERR, _CP0_CACHEERR_SELECT)
+
+#define _CP0_GET_TAGLO() _mfc0 (_CP0_TAGLO, _CP0_TAGLO_SELECT)
+#define _CP0_SET_TAGLO(val) _mtc0 (_CP0_TAGLO, _CP0_TAGLO_SELECT, val)
+#define _CP0_XCH_TAGLO(val) _mxc0 (_CP0_TAGLO, _CP0_TAGLO_SELECT, val)
+#define _CP0_BIC_TAGLO(clr) _bcc0 (_CP0_TAGLO, _CP0_TAGLO_SELECT, clr)
+#define _CP0_BIS_TAGLO(set) _bsc0 (_CP0_TAGLO, _CP0_TAGLO_SELECT, set)
+#define _CP0_BCS_TAGLO(c,s) _bcsc0(_CP0_TAGLO, _CP0_TAGLO_SELECT, c, s)
+
+#define _CP0_GET_DATALO() _mfc0 (_CP0_DATALO, _CP0_DATALO_SELECT)
+#define _CP0_SET_DATALO(val) _mtc0 (_CP0_DATALO, _CP0_DATALO_SELECT, val)
+
+#define _CP0_GET_ERROREPC() _mfc0 (_CP0_ERROREPC, _CP0_ERROREPC_SELECT)
+#define _CP0_SET_ERROREPC(val) _mtc0 (_CP0_ERROREPC, _CP0_ERROREPC_SELECT, val)
+#define _CP0_XCH_ERROREPC(val) _mxc0 (_CP0_ERROREPC, _CP0_ERROREPC_SELECT, val)
+
+#define _CP0_GET_DESAVE() _mfc0 (_CP0_DESAVE, _CP0_DESAVE_SELECT)
+#define _CP0_SET_DESAVE(val) _mtc0 (_CP0_DESAVE, _CP0_DESAVE_SELECT, val)
+#define _CP0_XCH_DESAVE(val) _mxc0 (_CP0_DESAVE, _CP0_DESAVE_SELECT, val)
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _CP0_HWRENA_MASK_POSITION 0x00000000
+#define _CP0_HWRENA_MASK_MASK 0x0000000F
+#define _CP0_HWRENA_MASK_LENGTH 0x00000004
+
+#define _CP0_BADVADDR_ALL_POSITION 0x00000000
+#define _CP0_BADVADDR_ALL_MASK 0xFFFFFFFF
+#define _CP0_BADVADDR_ALL_LENGTH 0x00000020
+
+#define _CP0_COUNT_ALL_POSITION 0x00000000
+#define _CP0_COUNT_ALL_MASK 0xFFFFFFFF
+#define _CP0_COUNT_ALL_LENGTH 0x00000020
+
+#define _CP0_COMPARE_ALL_POSITION 0x00000000
+#define _CP0_COMPARE_ALL_MASK 0xFFFFFFFF
+#define _CP0_COMPARE_ALL_LENGTH 0x00000020
+
+#define _CP0_STATUS_IE_POSITION 0x00000000
+#define _CP0_STATUS_IE_MASK 0x00000001
+#define _CP0_STATUS_IE_LENGTH 0x00000001
+
+#define _CP0_STATUS_EXL_POSITION 0x00000001
+#define _CP0_STATUS_EXL_MASK 0x00000002
+#define _CP0_STATUS_EXL_LENGTH 0x00000001
+
+#define _CP0_STATUS_ERL_POSITION 0x00000002
+#define _CP0_STATUS_ERL_MASK 0x00000004
+#define _CP0_STATUS_ERL_LENGTH 0x00000001
+
+#define _CP0_STATUS_UM_POSITION 0x00000004
+#define _CP0_STATUS_UM_MASK 0x00000010
+#define _CP0_STATUS_UM_LENGTH 0x00000001
+
+#define _CP0_STATUS_IM0_POSITION 0x00000008
+#define _CP0_STATUS_IM0_MASK 0x00000100
+#define _CP0_STATUS_IM0_LENGTH 0x00000001
+
+#define _CP0_STATUS_IM1_POSITION 0x00000009
+#define _CP0_STATUS_IM1_MASK 0x00000200
+#define _CP0_STATUS_IM1_LENGTH 0x00000001
+
+#define _CP0_STATUS_IPL_POSITION 0x0000000A
+#define _CP0_STATUS_IPL_MASK 0x0000FC00
+#define _CP0_STATUS_IPL_LENGTH 0x00000006
+
+#define _CP0_STATUS_IM2_POSITION 0x0000000A
+#define _CP0_STATUS_IM2_MASK 0x00000400
+#define _CP0_STATUS_IM2_LENGTH 0x00000001
+
+#define _CP0_STATUS_IM3_POSITION 0x0000000B
+#define _CP0_STATUS_IM3_MASK 0x00000800
+#define _CP0_STATUS_IM3_LENGTH 0x00000001
+
+#define _CP0_STATUS_IM4_POSITION 0x0000000C
+#define _CP0_STATUS_IM4_MASK 0x00001000
+#define _CP0_STATUS_IM4_LENGTH 0x00000001
+
+#define _CP0_STATUS_IM5_POSITION 0x0000000D
+#define _CP0_STATUS_IM5_MASK 0x00002000
+#define _CP0_STATUS_IM5_LENGTH 0x00000001
+
+#define _CP0_STATUS_IM6_POSITION 0x0000000E
+#define _CP0_STATUS_IM6_MASK 0x00004000
+#define _CP0_STATUS_IM6_LENGTH 0x00000001
+
+#define _CP0_STATUS_IM7_POSITION 0x0000000F
+#define _CP0_STATUS_IM7_MASK 0x00008000
+#define _CP0_STATUS_IM7_LENGTH 0x00000001
+
+#define _CP0_STATUS_CEE_POSITION 0x00000011
+#define _CP0_STATUS_CEE_MASK 0x00020000
+#define _CP0_STATUS_CEE_LENGTH 0x00000001
+
+#define _CP0_STATUS_NMI_POSITION 0x00000013
+#define _CP0_STATUS_NMI_MASK 0x00080000
+#define _CP0_STATUS_NMI_LENGTH 0x00000001
+
+#define _CPO_STATUS_SR_POSITION 0x00000014
+#define _CP0_STATUS_SR_MASK 0x00100000
+#define _CP0_STATUS_SR_LENGTH 0x00000001
+
+/* TLB Shutdown */
+#define _CP0_STATUS_TS_POSITION 0x00000015
+#define _CP0_STATUS_TS_MASK 0x00200000
+#define _CP0_STATUS_TS_LENGTH 0x00000001
+
+#define _CP0_STATUS_BEV_POSITION 0x00000016
+#define _CP0_STATUS_BEV_MASK 0x00400000
+#define _CP0_STATUS_BEV_LENGTH 0x00000001
+
+/* enable MDMX/DSP ASE */
+#define _CP0_STATUS_MX_POSITION 0x00000018
+#define _CP0_STATUS_MX_MASK 0x01000000
+#define _CP0_STATUS_MX_LENGTH 0x00000001
+
+#define _CP0_STATUS_RE_POSITION 0x00000019
+#define _CP0_STATUS_RE_MASK 0x02000000
+#define _CP0_STATUS_RE_LENGTH 0x00000001
+
+#define _CP0_STATUS_FR_POSITION 0x0000001A
+#define _CP0_STATUS_FR_MASK 0x04000000
+#define _CP0_STATUS_FR_LENGTH 0x00000001
+
+#define _CP0_STATUS_RP_POSITION 0x0000001B
+#define _CP0_STATUS_RP_MASK 0x08000000
+#define _CP0_STATUS_RP_LENGTH 0x00000001
+
+#define _CP0_STATUS_CU0_POSITION 0x0000001C
+#define _CP0_STATUS_CU0_MASK 0x10000000
+#define _CP0_STATUS_CU0_LENGTH 0x00000001
+
+#define _CP0_STATUS_CU1_POSITION 0x0000001D
+#define _CP0_STATUS_CU1_MASK 0x20000000
+#define _CP0_STATUS_CU1_LENGTH 0x00000001
+
+#define _CP0_STATUS_CU2_POSITION 0x0000001E
+#define _CP0_STATUS_CU2_MASK 0x40000000
+#define _CP0_STATUS_CU2_LENGTH 0x00000001
+
+#define _CP0_STATUS_CU3_POSITION 0x0000001F
+#define _CP0_STATUS_CU3_MASK 0x80000000
+#define _CP0_STATUS_CU3_LENGTH 0x00000001
+
+#define _CP0_INTCTL_VS_POSITION 0x00000005
+#define _CP0_INTCTL_VS_MASK 0x000003E0
+#define _CP0_INTCTL_VS_LENGTH 0x00000005
+
+#define _CP0_INTCTL_IPPCI_POSITION 0x0000001A
+#define _CP0_INTCTL_IPPCI_MASK 0x1C000000
+#define _CP0_INTCTL_IPPCI_LENGTH 0x00000003
+
+#define _CP0_INTCTL_IPTI_POSITION 0x0000001D
+#define _CP0_INTCTL_IPTI_MASK 0xE0000000
+#define _CP0_INTCTL_IPTI_LENGTH 0x00000003
+
+#define _CP0_SRSCTL_CSS_POSITION 0x00000000
+#define _CP0_SRSCTL_CSS_MASK 0x0000000F
+#define _CP0_SRSCTL_CSS_LENGTH 0x00000004
+
+#define _CP0_SRSCTL_PSS_POSITION 0x00000006
+#define _CP0_SRSCTL_PSS_MASK 0x000003C0
+#define _CP0_SRSCTL_PSS_LENGTH 0x00000004
+
+#define _CP0_SRSCTL_ESS_POSITION 0x0000000C
+#define _CP0_SRSCTL_ESS_MASK 0x0000F000
+#define _CP0_SRSCTL_ESS_LENGTH 0x00000004
+
+#define _CP0_SRSCTL_EICSS_POSITION 0x00000012
+#define _CP0_SRSCTL_EICSS_MASK 0x003C0000
+#define _CP0_SRSCTL_EICSS_LENGTH 0x00000004
+
+#define _CP0_SRSCTL_HSS_POSITION 0x0000001A
+#define _CP0_SRSCTL_HSS_MASK 0x3C000000
+#define _CP0_SRSCTL_HSS_LENGTH 0x00000004
+
+#define _CP0_SRSMAP_SSV0_POSITION 0x00000000
+#define _CP0_SRSMAP_SSV0_MASK 0x0000000F
+#define _CP0_SRSMAP_SSV0_LENGTH 0x00000004
+
+#define _CP0_SRSMAP_SSV1_POSITION 0x00000004
+#define _CP0_SRSMAP_SSV1_MASK 0x000000F0
+#define _CP0_SRSMAP_SSV1_LENGTH 0x00000004
+
+#define _CP0_SRSMAP_SSV2_POSITION 0x00000008
+#define _CP0_SRSMAP_SSV2_MASK 0x00000F00
+#define _CP0_SRSMAP_SSV2_LENGTH 0x00000004
+
+#define _CP0_SRSMAP_SSV3_POSITION 0x0000000C
+#define _CP0_SRSMAP_SSV3_MASK 0x0000F000
+#define _CP0_SRSMAP_SSV3_LENGTH 0x00000004
+
+#define _CP0_SRSMAP_SSV4_POSITION 0x00000010
+#define _CP0_SRSMAP_SSV4_MASK 0x000F0000
+#define _CP0_SRSMAP_SSV4_LENGTH 0x00000004
+
+#define _CP0_SRSMAP_SSV5_POSITION 0x00000014
+#define _CP0_SRSMAP_SSV5_MASK 0x00F00000
+#define _CP0_SRSMAP_SSV5_LENGTH 0x00000004
+
+#define _CP0_SRSMAP_SSV6_POSITION 0x00000018
+#define _CP0_SRSMAP_SSV6_MASK 0x0F000000
+#define _CP0_SRSMAP_SSV6_LENGTH 0x00000004
+
+#define _CP0_SRSMAP_SSV7_POSITION 0x0000001C
+#define _CP0_SRSMAP_SSV7_MASK 0xF0000000
+#define _CP0_SRSMAP_SSV7_LENGTH 0x00000004
+
+#define _CP0_CAUSE_EXCCODE_POSITION 0x00000002
+#define _CP0_CAUSE_EXCCODE_MASK 0x0000007C
+#define _CP0_CAUSE_EXCCODE_LENGTH 0x00000005
+
+#define _CP0_CAUSE_IP0_POSITION 0x00000008
+#define _CP0_CAUSE_IP0_MASK 0x00000100
+#define _CP0_CAUSE_IP0_LENGTH 0x00000001
+
+#define _CP0_CAUSE_IP1_POSITION 0x00000009
+#define _CP0_CAUSE_IP1_MASK 0x00000200
+#define _CP0_CAUSE_IP1_LENGTH 0x00000001
+
+#define _CP0_CAUSE_RIPL_POSITION 0x0000000A
+#define _CP0_CAUSE_RIPL_MASK 0x0000FC00
+#define _CP0_CAUSE_RIPL_LENGTH 0x00000006
+
+#define _CP0_CAUSE_IP2_POSITION 0x0000000A
+#define _CP0_CAUSE_IP2_MASK 0x00000400
+#define _CP0_CAUSE_IP2_LENGTH 0x00000001
+
+#define _CP0_CAUSE_IP3_POSITION 0x0000000B
+#define _CP0_CAUSE_IP3_MASK 0x00000800
+#define _CP0_CAUSE_IP3_LENGTH 0x00000001
+
+#define _CP0_CAUSE_IP4_POSITION 0x0000000C
+#define _CP0_CAUSE_IP4_MASK 0x00001000
+#define _CP0_CAUSE_IP4_LENGTH 0x00000001
+
+#define _CP0_CAUSE_IP5_POSITION 0x0000000D
+#define _CP0_CAUSE_IP5_MASK 0x00002000
+#define _CP0_CAUSE_IP5_LENGTH 0x00000001
+
+#define _CP0_CAUSE_IP6_POSITION 0x0000000E
+#define _CP0_CAUSE_IP6_MASK 0x00004000
+#define _CP0_CAUSE_IP6_LENGTH 0x00000001
+
+#define _CP0_CAUSE_IP7_POSITION 0x0000000F
+#define _CP0_CAUSE_IP7_MASK 0x00008000
+#define _CP0_CAUSE_IP7_LENGTH 0x00000001
+
+#define _CP0_CAUSE_WP_POSITION 0x00000016
+#define _CP0_CAUSE_WP_MASK 0x00400000
+#define _CP0_CAUSE_WP_LENGTH 0x00000001
+
+#define _CP0_CAUSE_IV_POSITION 0x00000017
+#define _CP0_CAUSE_IV_MASK 0x00800000
+#define _CP0_CAUSE_IV_LENGTH 0x00000001
+
+#define _CP0_CAUSE_PCI_POSITION 0x0000001A
+#define _CP0_CAUSE_PCI_MASK 0x04000000
+#define _CP0_CAUSE_PCI_LENGTH 0x00000001
+
+#define _CP0_CAUSE_DC_POSITION 0x0000001B
+#define _CP0_CAUSE_DC_MASK 0x08000000
+#define _CP0_CAUSE_DC_LENGTH 0x00000001
+
+#define _CP0_CAUSE_CE_POSITION 0x0000001C
+#define _CP0_CAUSE_CE_MASK 0x30000000
+#define _CP0_CAUSE_CE_LENGTH 0x00000002
+
+#define _CP0_CAUSE_TI_POSITION 0x0000001E
+#define _CP0_CAUSE_TI_MASK 0x40000000
+#define _CP0_CAUSE_TI_LENGTH 0x00000001
+
+#define _CP0_CAUSE_BD_POSITION 0x0000001F
+#define _CP0_CAUSE_BD_MASK 0x80000000
+#define _CP0_CAUSE_BD_LENGTH 0x00000001
+
+#define _EXCCODE_INT 0x00
+#define _EXCCODE_MOD 0x01 /* tlb modification */
+#define _EXCCODE_TLBL 0x02 /* tlb miss (load/i-fetch) */
+#define _EXCCODE_TLBS 0x03 /* tlb miss (store) */
+#define _EXCCODE_ADEL 0x04
+#define _EXCCODE_ADES 0x05
+#define _EXCCODE_IBE 0x06
+#define _EXCCODE_DBE 0x07
+#define _EXCCODE_SYS 0x08
+#define _EXCCODE_BP 0x09
+#define _EXCCODE_RI 0x0A
+#define _EXCCODE_CPU 0x0B
+#define _EXCCODE_OV 0x0C
+#define _EXCCODE_TR 0x0D
+#define _EXCCODE_IS1 0x10
+#define _EXCCODE_CEU 0x11
+#define _EXCCODE_C2E 0x12
+#define _EXCCODE_DSPU 0x1A /* dsp unusable */
+
+#define _CP0_EPC_ALL_POSITION 0x00000000
+#define _CP0_EPC_ALL_MASK 0xFFFFFFFF
+#define _CP0_EPC_ALL_LENGTH 0x00000020
+
+#define _CP0_PRID_REVISION_POSITION 0x00000000
+#define _CP0_PRID_REVISION_MASK 0x000000FF
+#define _CP0_PRID_REVISION_LENGTH 0x00000020
+
+#define _CP0_PRID_PATCHREV_POSITION 0x00000000
+#define _CP0_PRID_PATCHREV_MASK 0x00000003
+#define _CP0_PRID_PATCHREV_LENGTH 0x00000002
+
+#define _CP0_PRID_MINORREV_POSITION 0x00000002
+#define _CP0_PRID_MINORREV_MASK 0x0000001C
+#define _CP0_PRID_MINORREV_LENGTH 0x00000003
+
+#define _CP0_PRID_MAJORREV_POSITION 0x00000005
+#define _CP0_PRID_MAJORREV_MASK 0x000000E0
+#define _CP0_PRID_MAJORREV_LENGTH 0x00000003
+
+#define _CP0_PRID_PROCESSORID_POSITION 0x00000008
+#define _CP0_PRID_PROCESSORID_MASK 0x0000FF00
+#define _CP0_PRID_PROCESSORID_LENGTH 0x00000008
+
+#define _CP0_PRID_COMPANYID_POSITION 0x00000010
+#define _CP0_PRID_COMPANYID_MASK 0x00FF0000
+#define _CP0_PRID_COMPANYID_LENGTH 0x00000008
+
+#define _CP0_EBASE_CPUNUM_POSITION 0x00000000
+#define _CP0_EBASE_CPUNUM_MASK 0x000003FF
+#define _CP0_EBASE_CPUNUM_LENGTH 0x0000000A
+
+#define _CP0_EBASE_EBASE_POSITION 0x0000000C
+#define _CP0_EBASE_EBASE_MASK 0x3FFFF000
+#define _CP0_EBASE_EBASE_LENGTH 0x0000000E
+
+/* Kseg0 coherency algorithm */
+#define _CP0_CONFIG_K0_POSITION 0x00000000
+#define _CP0_CONFIG_K0_MASK 0x00000007
+#define _CP0_CONFIG_K0_LENGTH 0x00000003
+
+/* MMU Type */
+#define _CP0_CONFIG_MT_POSITION 0x00000007
+#define _CP0_CONFIG_MT_MASK 0x00000380
+#define _CP0_CONFIG_MT_LENGTH 0x00000003
+#define _CP0_CONFIG_MT_NONE (0<<7)
+#define _CP0_CONFIG_MT_TLB (1<<7)
+#define _CP0_CONFIG_MT_BAT (2<<7)
+#define _CP0_CONFIG_MT_NONSTD (3<<7)
+
+#define _CP0_CONFIG_AR_POSITION 0x0000000A
+#define _CP0_CONFIG_AR_MASK 0x00001C00
+#define _CP0_CONFIG_AR_LENGTH 0x00000003
+
+#define _CP0_CONFIG_AT_POSITION 0x0000000D
+#define _CP0_CONFIG_AT_MASK 0x00006000
+#define _CP0_CONFIG_AT_LENGTH 0x00000002
+
+#define _CP0_CONFIG_BE_POSITION 0x0000000F
+#define _CP0_CONFIG_BE_MASK 0x00008000
+#define _CP0_CONFIG_BE_LENGTH 0x00000001
+
+#define _CP0_CONFIG_DS_POSITION 0x00000010
+#define _CP0_CONFIG_DS_MASK 0x00010000
+#define _CP0_CONFIG_DS_LENGTH 0x00000001
+
+#define _CP0_CONFIG_MDU_POSITION 0x00000014
+#define _CP0_CONFIG_MDU_MASK 0x00100000
+#define _CP0_CONFIG_MDU_LENGTH 0x00000001
+
+#define _CP0_CONFIG_SB_POSITION 0x00000015
+#define _CP0_CONFIG_SB_MASK 0x00200000
+#define _CP0_CONFIG_SB_LENGTH 0x00000001
+
+#define _CP0_CONFIG_UDI_POSITION 0x00000016
+#define _CP0_CONFIG_UDI_MASK 0x00400000
+#define _CP0_CONFIG_UDI_LENGTH 0x00000001
+
+#define _CP0_CONFIG_KU_POSITION 0x00000019
+#define _CP0_CONFIG_KU_MASK 0x70000000
+#define _CP0_CONFIG_KU_LENGTH 0x00000003
+
+#define _CP0_CONFIG_M_POSITION 0x0000001F
+#define _CP0_CONFIG_M_MASK 0x80000000
+#define _CP0_CONFIG_M_LENGTH 0x00000001
+
+#define _CP0_CONFIG1_FP_POSITION 0x00000000
+#define _CP0_CONFIG1_FP_MASK 0x00000001
+#define _CP0_CONFIG1_FP_LENGTH 0x00000001
+
+#define _CP0_CONFIG1_EP_POSITION 0x00000001
+#define _CP0_CONFIG1_EP_MASK 0x00000002
+#define _CP0_CONFIG1_EP_LENGTH 0x00000001
+
+#define _CP0_CONFIG1_CA_POSITION 0x00000002
+#define _CP0_CONFIG1_CA_MASK 0x00000004
+#define _CP0_CONFIG1_CA_LENGTH 0x00000001
+
+#define _CP0_CONFIG1_WR_POSITION 0x00000003
+#define _CP0_CONFIG1_WR_MASK 0x00000008
+#define _CP0_CONFIG1_WR_LENGTH 0x00000001
+
+#define _CP0_CONFIG1_PC_POSITION 0x00000004
+#define _CP0_CONFIG1_PC_MASK 0x00000010
+#define _CP0_CONFIG1_PC_LENGTH 0x00000001
+
+#define _CP0_CONFIG1_MD_POSITION 0x00000005
+#define _CP0_CONFIG1_MD_MASK 0x00000020
+#define _CP0_CONFIG1_MD_LENGTH 0x00000001
+
+#define _CP0_CONFIG1_C2_POSITION 0x00000006
+#define _CP0_CONFIG1_C2_MASK 0x00000040
+#define _CP0_CONFIG1_C2_LENGTH 0x00000001
+
+#define _CP0_CONFIG1_DA_POSITION 0x00000007
+#define _CP0_CONFIG1_DA_MASK 0x00000380
+#define _CP0_CONFIG1_DA_LENGTH 0x00000003
+
+#define _CP0_CONFIG1_DL_POSITION 0x0000000A
+#define _CP0_CONFIG1_DL_MASK 0x00001C00
+#define _CP0_CONFIG1_DL_LENGTH 0x00000003
+
+#define _CP0_CONFIG1_DS_POSITION 0x0000000D
+#define _CP0_CONFIG1_DS_MASK 0x0000E000
+#define _CP0_CONFIG1_DS_LENGTH 0x00000003
+
+#define _CP0_CONFIG1_IA_POSITION 0x00000010
+#define _CP0_CONFIG1_IA_MASK 0x00070000
+#define _CP0_CONFIG1_IA_LENGTH 0x00000003
+
+#define _CP0_CONFIG1_IL_POSITION 0x00000013
+#define _CP0_CONFIG1_IL_MASK 0x00380000
+#define _CP0_CONFIG1_IL_LENGTH 0x00000003
+
+#define _CP0_CONFIG1_IS_POSITION 0x00000016
+#define _CP0_CONFIG1_IS_MASK 0x01C00000
+#define _CP0_CONFIG1_IS_LENGTH 0x00000003
+
+#define _CP0_CONFIG1_MMUSIZE_POSITION 0x00000019
+#define _CP0_CONFIG1_MMUSIZE_MASK 0x7E000000
+#define _CP0_CONFIG1_MMUSIZE_LENGTH 0x00000006
+
+#define _CP0_CONFIG1_M_POSITION 0x0000001F
+#define _CP0_CONFIG1_M_MASK 0x80000000
+#define _CP0_CONFIG1_M_LENGTH 0x00000001
+
+#define _CP0_CONFIG2_M_POSITION 0x0000001F
+#define _CP0_CONFIG2_M_MASK 0x80000000
+#define _CP0_CONFIG2_M_LENGTH 0x00000001
+
+#define _CP0_CONFIG3_TL_POSITION 0x00000000
+#define _CP0_CONFIG3_TL_MASK 0x00000001
+#define _CP0_CONFIG3_TL_LENGTH 0x00000001
+
+#define _CP0_CONFIG3_SM_POSITION 0x00000001
+#define _CP0_CONFIG3_SM_MASK 0x00000002
+#define _CP0_CONFIG3_SM_LENGTH 0x00000001
+
+#define _CP0_CONFIG3_SP_POSITION 0x00000004
+#define _CP0_CONFIG3_SP_MASK 0x00000010
+#define _CP0_CONFIG3_SP_LENGTH 0x00000001
+
+#define _CP0_CONFIG3_VINT_POSITION 0x00000005
+#define _CP0_CONFIG3_VINT_MASK 0x00000020
+#define _CP0_CONFIG3_VINT_LENGTH 0x00000001
+
+#define _CP0_CONFIG3_VEIC_POSITION 0x00000006
+#define _CP0_CONFIG3_VEIC_MASK 0x00000040
+#define _CP0_CONFIG3_VEIC_LENGTH 0x00000001
+
+#define _CP0_CONFIG3_ITL_POSITION 0x00000008
+#define _CP0_CONFIG3_ITL_MASK 0x00000100
+#define _CP0_CONFIG3_ITL_LENGTH 0x00000001
+
+/* DSP ASE present */
+#define _CP0_CONFIG3_DSPP_POSITION 0x0000000A
+#define _CP0_CONFIG3_DSPP_MASK 0x00000400
+#define _CP0_CONFIG3_DSPP_LENGTH 0x00000001
+
+#define _CP0_CONFIG3_DSP2P_POSITION 0x0000000B
+#define _CP0_CONFIG3_DSP2P_MASK 0x00000800
+#define _CP0_CONFIG3_DSP2P_LENGTH 0x00000001
+
+#define _CP0_CONFIG3_M_POSITION 0x0000001F
+#define _CP0_CONFIG3_M_MASK 0x80000000
+#define _CP0_CONFIG3_M_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DSS_POSITION 0x00000000
+#define _CP0_DEBUG_DSS_MASK 0x00000001
+#define _CP0_DEBUG_DSS_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DBP_POSITION 0x00000001
+#define _CP0_DEBUG_DBP_MASK 0x00000002
+#define _CP0_DEBUG_DBP_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DDBL_POSITION 0x00000002
+#define _CP0_DEBUG_DDBL_MASK 0x00000004
+#define _CP0_DEBUG_DDBL_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DDBS_POSITION 0x00000003
+#define _CP0_DEBUG_DDBS_MASK 0x00000008
+#define _CP0_DEBUG_DDBS_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DIB_POSITION 0x00000004
+#define _CP0_DEBUG_DIB_MASK 0x00000010
+#define _CP0_DEBUG_DIB_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DINT_POSITION 0x00000005
+#define _CP0_DEBUG_DINT_MASK 0x00000020
+#define _CP0_DEBUG_DINT_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DIBIMPR_POSITION 0x00000006
+#define _CP0_DEBUG_DIBIMPR_MASK 0x00000040
+#define _CP0_DEBUG_DIBIMPR_LENGTH 0x00000001
+
+#define _CP0_DEBUG_R_POSITION 0x00000007
+#define _CP0_DEBUG_R_MASK 0x00000080
+#define _CP0_DEBUG_R_LENGTH 0x00000001
+
+#define _CP0_DEBUG_SST_POSITION 0x00000008
+#define _CP0_DEBUG_SST_MASK 0x00000100
+#define _CP0_DEBUG_SST_LENGTH 0x00000001
+
+#define _CP0_DEBUG_NOSST_POSITION 0x00000009
+#define _CP0_DEBUG_NOSST_MASK 0x00000200
+#define _CP0_DEBUG_NOSST_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DEXCCODE_POSITION 0x0000000A
+#define _CP0_DEBUG_DEXCCODE_MASK 0x00007C00
+#define _CP0_DEBUG_DEXCCODE_LENGTH 0x00000005
+
+#define _CP0_DEBUG_VER_POSITION 0x0000000F
+#define _CP0_DEBUG_VER_MASK 0x00038000
+#define _CP0_DEBUG_VER_LENGTH 0x00000003
+
+#define _CP0_DEBUG_DDBLIMPR_POSITION 0x00000012
+#define _CP0_DEBUG_DDBLIMPR_MASK 0x00040000
+#define _CP0_DEBUG_DDBLIMPR_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DDBSIMPR_POSITION 0x00000013
+#define _CP0_DEBUG_DDBSIMPR_MASK 0x00080000
+#define _CP0_DEBUG_DDBSIMPR_LENGTH 0x00000001
+
+#define _CP0_DEBUG_IEXI_POSITION 0x00000014
+#define _CP0_DEBUG_IEXI_MASK 0x00100000
+#define _CP0_DEBUG_IEXI_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DBUSEP_POSITION 0x00000015
+#define _CP0_DEBUG_DBUSEP_MASK 0x00200000
+#define _CP0_DEBUG_DBUSEP_LENGTH 0x00000001
+
+#define _CP0_DEBUG_CACHEEP_POSITION 0x00000016
+#define _CP0_DEBUG_CACHEEP_MASK 0x00400000
+#define _CP0_DEBUG_CACHEEP_LENGTH 0x00000001
+
+#define _CP0_DEBUG_MCHECKP_POSITION 0x00000017
+#define _CP0_DEBUG_MCHECKP_MASK 0x00800000
+#define _CP0_DEBUG_MCHECKP_LENGTH 0x00000001
+
+#define _CP0_DEBUG_IBUSEP_POSITION 0x00000018
+#define _CP0_DEBUG_IBUSEP_MASK 0x01000000
+#define _CP0_DEBUG_IBUSEP_LENGTH 0x00000001
+
+#define _CP0_DEBUG_COUNTDM_POSITION 0x00000019
+#define _CP0_DEBUG_COUNTDM_MASK 0x02000000
+#define _CP0_DEBUG_COUNTDM_LENGTH 0x00000001
+
+#define _CP0_DEBUG_HALT_POSITION 0x0000001A
+#define _CP0_DEBUG_HALT_MASK 0x04000000
+#define _CP0_DEBUG_HALT_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DOZE_POSITION 0x0000001B
+#define _CP0_DEBUG_DOZE_MASK 0x08000000
+#define _CP0_DEBUG_DOZE_LENGTH 0x00000001
+
+#define _CP0_DEBUG_LSNM_POSITION 0x0000001C
+#define _CP0_DEBUG_LSNM_MASK 0x10000000
+#define _CP0_DEBUG_LSNM_LENGTH 0x00000001
+
+#define _CP0_DEBUG_NODCR_POSITION 0x0000001D
+#define _CP0_DEBUG_NODCR_MASK 0x20000000
+#define _CP0_DEBUG_NODCR_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DM_POSITION 0x0000001E
+#define _CP0_DEBUG_DM_MASK 0x40000000
+#define _CP0_DEBUG_DM_LENGTH 0x00000001
+
+#define _CP0_DEBUG_DBD_POSITION 0x0000001F
+#define _CP0_DEBUG_DBD_MASK 0x80000000
+#define _CP0_DEBUG_DBD_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_ON_POSITION 0x00000000
+#define _CP0_TRACECONTROL_ON_MASK 0x00000001
+#define _CP0_TRACECONTROL_ON_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_MODE_POSITION 0x00000001
+#define _CP0_TRACECONTROL_MODE_MASK 0x0000000E
+#define _CP0_TRACECONTROL_MODE_LENGTH 0x00000003
+
+#define _CP0_TRACECONTROL_G_POSITION 0x00000004
+#define _CP0_TRACECONTROL_G_MASK 0x00000010
+#define _CP0_TRACECONTROL_G_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_ASID_POSITION 0x00000005
+#define _CP0_TRACECONTROL_ASID_MASK 0x00001FE0
+#define _CP0_TRACECONTROL_ASID_LENGTH 0x00000008
+
+#define _CP0_TRACECONTROL_ASID_M_POSITION 0x0000000D
+#define _CP0_TRACECONTROL_ASID_M_MASK 0x001FE000
+#define _CP0_TRACECONTROL_ASID_M_LENGTH 0x00000008
+
+#define _CP0_TRACECONTROL_U_POSITION 0x00000015
+#define _CP0_TRACECONTROL_U_MASK 0x00200000
+#define _CP0_TRACECONTROL_U_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_0_POSITION 0x00000016
+#define _CP0_TRACECONTROL_0_MASK 0x00400000
+#define _CP0_TRACECONTROL_0_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_K_POSITION 0x00000017
+#define _CP0_TRACECONTROL_K_MASK 0x00800000
+#define _CP0_TRACECONTROL_K_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_E_POSITION 0x00000018
+#define _CP0_TRACECONTROL_E_MASK 0x01000000
+#define _CP0_TRACECONTROL_E_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_D_POSITION 0x00000019
+#define _CP0_TRACECONTROL_D_MASK 0x02000000
+#define _CP0_TRACECONTROL_D_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_IO_POSITION 0x0000001A
+#define _CP0_TRACECONTROL_IO_MASK 0x04000000
+#define _CP0_TRACECONTROL_IO_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_TB_POSITION 0x0000001B
+#define _CP0_TRACECONTROL_TB_MASK 0x08000000
+#define _CP0_TRACECONTROL_TB_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_UT_POSITION 0x0000001E
+#define _CP0_TRACECONTROL_UT_MASK 0x40000000
+#define _CP0_TRACECONTROL_UT_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL_TS_POSITION 0x0000001F
+#define _CP0_TRACECONTROL_TS_MASK 0x80000000
+#define _CP0_TRACECONTROL_TS_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL2_SYP_POSITION 0x00000000
+#define _CP0_TRACECONTROL2_SYP_MASK 0x00000007
+#define _CP0_TRACECONTROL2_SYP_LENGTH 0x00000003
+
+#define _CP0_TRACECONTROL2_TBU_POSITION 0x00000003
+#define _CP0_TRACECONTROL2_TBU_MASK 0x00000008
+#define _CP0_TRACECONTROL2_TBU_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL2_TBI_POSITION 0x00000004
+#define _CP0_TRACECONTROL2_TBI_MASK 0x00000010
+#define _CP0_TRACECONTROL2_TBI_LENGTH 0x00000001
+
+#define _CP0_TRACECONTROL2_VALIDMODES_POSITION 0x00000005
+#define _CP0_TRACECONTROL2_VALIDMODES_MASK 0x00000060
+#define _CP0_TRACECONTROL2_VALIDMODES_LENGTH 0x00000002
+
+#define _CP0_USERTRACEDATA_DATA_POSITION 0x00000000
+#define _CP0_USERTRACEDATA_DATA_MASK 0xFFFFFFFF
+#define _CP0_USERTRACEDATA_DATA_LENGTH 0x00000020
+
+#define _CP0_TRACEBPC_IBPON_POSITION 0x00000000
+#define _CP0_TRACEBPC_IBPON_MASK 0x0000003F
+#define _CP0_TRACEBPC_IBPON_LENGTH 0x00000006
+
+#define _CP0_TRACEBPC_IE_POSITION 0x0000000F
+#define _CP0_TRACEBPC_IE_MASK 0x00008000
+#define _CP0_TRACEBPC_IE_LENGTH 0x00000001
+
+#define _CP0_TRACEBPC_DBPON_POSITION 0x00000010
+#define _CP0_TRACEBPC_DBPON_MASK 0x00030000
+#define _CP0_TRACEBPC_DBPON_LENGTH 0x00000002
+
+#define _CP0_TRACEBPC_DE_POSITION 0x0000001F
+#define _CP0_TRACEBPC_DE_MASK 0x80000000
+#define _CP0_TRACEBPC_DE_LENGTH 0x00000001
+
+#define _CP0_DEBUG2_PACO_POSITION 0x00000000
+#define _CP0_DEBUG2_PACO_MASK 0x00000001
+#define _CP0_DEBUG2_PACO_LENGTH 0x00000001
+
+#define _CP0_DEBUG2_TUP_POSITION 0x00000001
+#define _CP0_DEBUG2_TUP_MASK 0x00000002
+#define _CP0_DEBUG2_TUP_LENGTH 0x00000001
+
+#define _CP0_DEBUG2_DQ_POSITION 0x00000002
+#define _CP0_DEBUG2_DQ_MASK 0x00000004
+#define _CP0_DEBUG2_DQ_LENGTH 0x00000001
+
+#define _CP0_DEBUG2_PRM_POSITION 0x00000003
+#define _CP0_DEBUG2_PRM_MASK 0x00000008
+#define _CP0_DEBUG2_PRM_LENGTH 0x00000001
+
+#define _CP0_DEPC_ALL_POSITION 0x00000000
+#define _CP0_DEPC_ALL_MASK 0xFFFFFFFF
+#define _CP0_DEPC_ALL_LENGTH 0x00000020
+
+#define _CP0_ERROREPC_ALL_POSITION 0x00000000
+#define _CP0_ERROREPC_ALL_MASK 0xFFFFFFFF
+#define _CP0_ERROREPC_ALL_LENGTH 0x00000020
+
+#define _CP0_DESAVE_ALL_POSITION 0x00000000
+#define _CP0_DESAVE_ALL_MASK 0xFFFFFFFF
+#define _CP0_DESAVE_ALL_LENGTH 0x00000020
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/kernel/os/include/os/arch/pic32/os/os_arch_defs.h
----------------------------------------------------------------------
diff --git a/kernel/os/include/os/arch/pic32/os/os_arch_defs.h b/kernel/os/include/os/arch/pic32/os/os_arch_defs.h
new file mode 100644
index 0000000..d4fee3b
--- /dev/null
+++ b/kernel/os/include/os/arch/pic32/os/os_arch_defs.h
@@ -0,0 +1,60 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef _OS_ARCH_DEFS_H
+#define _OS_ARCH_DEFS_H
+
+#include "cp0defs.h"
+
+#ifdef __LANGUAGE_ASSEMBLY__
+
+#define v0 $2
+#define v1 $3
+#define a0 $4
+#define a1 $5
+#define a2 $6
+#define a3 $7
+#define t0 $8
+#define t1 $9
+#define t2 $10
+#define t3 $11
+#define t4 $12
+#define t5 $13
+#define t6 $14
+#define t7 $15
+#define t8 $24
+#define t9 $25
+#define s0 $16
+#define s1 $17
+#define s2 $18
+#define s3 $19
+#define s4 $20
+#define s5 $21
+#define s6 $22
+#define s7 $23
+#define s8 $30
+#define fp $30
+#define k0 $26
+#define k1 $27
+#define gp $28
+#define sp $29
+#define ra $31
+
+#endif /* __LANGUAGE_ASSEMBLY__ */
+
+#endif /* _OS_ARCH_DEFS_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/kernel/os/src/arch/pic32/asm/ctx.S
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32/asm/ctx.S b/kernel/os/src/arch/pic32/asm/ctx.S
index 1985f81..4c5ad94 100644
--- a/kernel/os/src/arch/pic32/asm/ctx.S
+++ b/kernel/os/src/arch/pic32/asm/ctx.S
@@ -17,7 +17,8 @@
* under the License.
*/
-#include <xc.h>
+#include "mcu/mcu.h"
+#include "os/os_arch_defs.h"
#include "syscfg/syscfg.h"
#define OS_STACK_ALIGNMENT (8)
[5/7] incubator-mynewt-core git commit: Removed include path,
included specific parts of the Microchip SDK, fixed some errant capitalisation
Posted by ma...@apache.org.
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mx470f512h/include/mcu/p32mx470f512h.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470f512h/include/mcu/p32mx470f512h.h b/hw/mcu/microchip/pic32mx470f512h/include/mcu/p32mx470f512h.h
new file mode 100644
index 0000000..f66255f
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470f512h/include/mcu/p32mx470f512h.h
@@ -0,0 +1,17933 @@
+/*-------------------------------------------------------------------------
+ * PIC32MX470F512H processor header
+ * Build date : Feb 18 2016
+ *
+ * Copyright (c) 2016, Microchip Technology Inc. and its subsidiaries ("Microchip")
+ * All rights reserved.
+ *
+ * This software is developed by Microchip Technology Inc. and its
+ * subsidiaries ("Microchip").
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. Microchip's name may not be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#pragma once
+#ifndef __32MX470F512H_H
+#define __32MX470F512H_H
+
+#if defined (__LANGUAGE_C__) || defined (__LANGUAGE_C_PLUS_PLUS)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define WDTCON WDTCON
+extern volatile unsigned int WDTCON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned WDTCLR:1;
+ unsigned WDTWINEN:1;
+ unsigned SWDTPS:5;
+ unsigned :8;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :2;
+ unsigned SWDTPS0:1;
+ unsigned SWDTPS1:1;
+ unsigned SWDTPS2:1;
+ unsigned SWDTPS3:1;
+ unsigned SWDTPS4:1;
+ };
+ struct {
+ unsigned :2;
+ unsigned WDTPSTA:5;
+ };
+ struct {
+ unsigned :2;
+ unsigned WDTPS:5;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __WDTCONbits_t;
+extern volatile __WDTCONbits_t WDTCONbits __asm__ ("WDTCON") __attribute__((section("sfrs")));
+extern volatile unsigned int WDTCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int WDTCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int WDTCONINV __attribute__((section("sfrs")));
+#define RTCCON RTCCON
+extern volatile unsigned int RTCCON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned RTCOE:1;
+ unsigned HALFSEC:1;
+ unsigned RTCSYNC:1;
+ unsigned RTCWREN:1;
+ unsigned :2;
+ unsigned RTCCLKON:1;
+ unsigned RTSECSEL:1;
+ unsigned :5;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ unsigned CAL:10;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __RTCCONbits_t;
+extern volatile __RTCCONbits_t RTCCONbits __asm__ ("RTCCON") __attribute__((section("sfrs")));
+extern volatile unsigned int RTCCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int RTCCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int RTCCONINV __attribute__((section("sfrs")));
+#define RTCALRM RTCALRM
+extern volatile unsigned int RTCALRM __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ARPT:8;
+ unsigned AMASK:4;
+ unsigned ALRMSYNC:1;
+ unsigned PIV:1;
+ unsigned CHIME:1;
+ unsigned ALRMEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __RTCALRMbits_t;
+extern volatile __RTCALRMbits_t RTCALRMbits __asm__ ("RTCALRM") __attribute__((section("sfrs")));
+extern volatile unsigned int RTCALRMCLR __attribute__((section("sfrs")));
+extern volatile unsigned int RTCALRMSET __attribute__((section("sfrs")));
+extern volatile unsigned int RTCALRMINV __attribute__((section("sfrs")));
+#define RTCTIME RTCTIME
+extern volatile unsigned int RTCTIME __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :8;
+ unsigned SEC01:4;
+ unsigned SEC10:4;
+ unsigned MIN01:4;
+ unsigned MIN10:4;
+ unsigned HR01:4;
+ unsigned HR10:4;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __RTCTIMEbits_t;
+extern volatile __RTCTIMEbits_t RTCTIMEbits __asm__ ("RTCTIME") __attribute__((section("sfrs")));
+extern volatile unsigned int RTCTIMECLR __attribute__((section("sfrs")));
+extern volatile unsigned int RTCTIMESET __attribute__((section("sfrs")));
+extern volatile unsigned int RTCTIMEINV __attribute__((section("sfrs")));
+#define RTCDATE RTCDATE
+extern volatile unsigned int RTCDATE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned WDAY01:4;
+ unsigned :4;
+ unsigned DAY01:4;
+ unsigned DAY10:4;
+ unsigned MONTH01:4;
+ unsigned MONTH10:4;
+ unsigned YEAR01:4;
+ unsigned YEAR10:4;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __RTCDATEbits_t;
+extern volatile __RTCDATEbits_t RTCDATEbits __asm__ ("RTCDATE") __attribute__((section("sfrs")));
+extern volatile unsigned int RTCDATECLR __attribute__((section("sfrs")));
+extern volatile unsigned int RTCDATESET __attribute__((section("sfrs")));
+extern volatile unsigned int RTCDATEINV __attribute__((section("sfrs")));
+#define ALRMTIME ALRMTIME
+extern volatile unsigned int ALRMTIME __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :8;
+ unsigned SEC01:4;
+ unsigned SEC10:4;
+ unsigned MIN01:4;
+ unsigned MIN10:4;
+ unsigned HR01:4;
+ unsigned HR10:4;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __ALRMTIMEbits_t;
+extern volatile __ALRMTIMEbits_t ALRMTIMEbits __asm__ ("ALRMTIME") __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMTIMECLR __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMTIMESET __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMTIMEINV __attribute__((section("sfrs")));
+#define ALRMDATE ALRMDATE
+extern volatile unsigned int ALRMDATE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned WDAY01:4;
+ unsigned :4;
+ unsigned DAY01:4;
+ unsigned DAY10:4;
+ unsigned MONTH01:4;
+ unsigned MONTH10:4;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __ALRMDATEbits_t;
+extern volatile __ALRMDATEbits_t ALRMDATEbits __asm__ ("ALRMDATE") __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMDATECLR __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMDATESET __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMDATEINV __attribute__((section("sfrs")));
+#define T1CON T1CON
+extern volatile unsigned int T1CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :1;
+ unsigned TCS:1;
+ unsigned TSYNC:1;
+ unsigned :1;
+ unsigned TCKPS:2;
+ unsigned :1;
+ unsigned TGATE:1;
+ unsigned :3;
+ unsigned TWIP:1;
+ unsigned TWDIS:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :4;
+ unsigned TCKPS0:1;
+ unsigned TCKPS1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned TSIDL:1;
+ unsigned :1;
+ unsigned TON:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __T1CONbits_t;
+extern volatile __T1CONbits_t T1CONbits __asm__ ("T1CON") __attribute__((section("sfrs")));
+extern volatile unsigned int T1CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int T1CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int T1CONINV __attribute__((section("sfrs")));
+#define TMR1 TMR1
+extern volatile unsigned int TMR1 __attribute__((section("sfrs")));
+extern volatile unsigned int TMR1CLR __attribute__((section("sfrs")));
+extern volatile unsigned int TMR1SET __attribute__((section("sfrs")));
+extern volatile unsigned int TMR1INV __attribute__((section("sfrs")));
+#define PR1 PR1
+extern volatile unsigned int PR1 __attribute__((section("sfrs")));
+extern volatile unsigned int PR1CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PR1SET __attribute__((section("sfrs")));
+extern volatile unsigned int PR1INV __attribute__((section("sfrs")));
+#define T2CON T2CON
+extern volatile unsigned int T2CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :1;
+ unsigned TCS:1;
+ unsigned :1;
+ unsigned T32:1;
+ unsigned TCKPS:3;
+ unsigned TGATE:1;
+ unsigned :5;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :4;
+ unsigned TCKPS0:1;
+ unsigned TCKPS1:1;
+ unsigned TCKPS2:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned TSIDL:1;
+ unsigned :1;
+ unsigned TON:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __T2CONbits_t;
+extern volatile __T2CONbits_t T2CONbits __asm__ ("T2CON") __attribute__((section("sfrs")));
+extern volatile unsigned int T2CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int T2CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int T2CONINV __attribute__((section("sfrs")));
+#define TMR2 TMR2
+extern volatile unsigned int TMR2 __attribute__((section("sfrs")));
+extern volatile unsigned int TMR2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int TMR2SET __attribute__((section("sfrs")));
+extern volatile unsigned int TMR2INV __attribute__((section("sfrs")));
+#define PR2 PR2
+extern volatile unsigned int PR2 __attribute__((section("sfrs")));
+extern volatile unsigned int PR2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PR2SET __attribute__((section("sfrs")));
+extern volatile unsigned int PR2INV __attribute__((section("sfrs")));
+#define T3CON T3CON
+extern volatile unsigned int T3CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :1;
+ unsigned TCS:1;
+ unsigned :2;
+ unsigned TCKPS:3;
+ unsigned TGATE:1;
+ unsigned :5;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :4;
+ unsigned TCKPS0:1;
+ unsigned TCKPS1:1;
+ unsigned TCKPS2:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned TSIDL:1;
+ unsigned :1;
+ unsigned TON:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __T3CONbits_t;
+extern volatile __T3CONbits_t T3CONbits __asm__ ("T3CON") __attribute__((section("sfrs")));
+extern volatile unsigned int T3CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int T3CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int T3CONINV __attribute__((section("sfrs")));
+#define TMR3 TMR3
+extern volatile unsigned int TMR3 __attribute__((section("sfrs")));
+extern volatile unsigned int TMR3CLR __attribute__((section("sfrs")));
+extern volatile unsigned int TMR3SET __attribute__((section("sfrs")));
+extern volatile unsigned int TMR3INV __attribute__((section("sfrs")));
+#define PR3 PR3
+extern volatile unsigned int PR3 __attribute__((section("sfrs")));
+extern volatile unsigned int PR3CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PR3SET __attribute__((section("sfrs")));
+extern volatile unsigned int PR3INV __attribute__((section("sfrs")));
+#define T4CON T4CON
+extern volatile unsigned int T4CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :1;
+ unsigned TCS:1;
+ unsigned :1;
+ unsigned T32:1;
+ unsigned TCKPS:3;
+ unsigned TGATE:1;
+ unsigned :5;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :4;
+ unsigned TCKPS0:1;
+ unsigned TCKPS1:1;
+ unsigned TCKPS2:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned TSIDL:1;
+ unsigned :1;
+ unsigned TON:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __T4CONbits_t;
+extern volatile __T4CONbits_t T4CONbits __asm__ ("T4CON") __attribute__((section("sfrs")));
+extern volatile unsigned int T4CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int T4CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int T4CONINV __attribute__((section("sfrs")));
+#define TMR4 TMR4
+extern volatile unsigned int TMR4 __attribute__((section("sfrs")));
+extern volatile unsigned int TMR4CLR __attribute__((section("sfrs")));
+extern volatile unsigned int TMR4SET __attribute__((section("sfrs")));
+extern volatile unsigned int TMR4INV __attribute__((section("sfrs")));
+#define PR4 PR4
+extern volatile unsigned int PR4 __attribute__((section("sfrs")));
+extern volatile unsigned int PR4CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PR4SET __attribute__((section("sfrs")));
+extern volatile unsigned int PR4INV __attribute__((section("sfrs")));
+#define T5CON T5CON
+extern volatile unsigned int T5CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :1;
+ unsigned TCS:1;
+ unsigned :2;
+ unsigned TCKPS:3;
+ unsigned TGATE:1;
+ unsigned :5;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :4;
+ unsigned TCKPS0:1;
+ unsigned TCKPS1:1;
+ unsigned TCKPS2:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned TSIDL:1;
+ unsigned :1;
+ unsigned TON:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __T5CONbits_t;
+extern volatile __T5CONbits_t T5CONbits __asm__ ("T5CON") __attribute__((section("sfrs")));
+extern volatile unsigned int T5CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int T5CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int T5CONINV __attribute__((section("sfrs")));
+#define TMR5 TMR5
+extern volatile unsigned int TMR5 __attribute__((section("sfrs")));
+extern volatile unsigned int TMR5CLR __attribute__((section("sfrs")));
+extern volatile unsigned int TMR5SET __attribute__((section("sfrs")));
+extern volatile unsigned int TMR5INV __attribute__((section("sfrs")));
+#define PR5 PR5
+extern volatile unsigned int PR5 __attribute__((section("sfrs")));
+extern volatile unsigned int PR5CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PR5SET __attribute__((section("sfrs")));
+extern volatile unsigned int PR5INV __attribute__((section("sfrs")));
+#define IC1CON IC1CON
+extern volatile unsigned int IC1CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ICM:3;
+ unsigned ICBNE:1;
+ unsigned ICOV:1;
+ unsigned ICI:2;
+ unsigned ICTMR:1;
+ unsigned C32:1;
+ unsigned FEDGE:1;
+ unsigned :3;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned ICM0:1;
+ unsigned ICM1:1;
+ unsigned ICM2:1;
+ unsigned :2;
+ unsigned ICI0:1;
+ unsigned ICI1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned ICSIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IC1CONbits_t;
+extern volatile __IC1CONbits_t IC1CONbits __asm__ ("IC1CON") __attribute__((section("sfrs")));
+extern volatile unsigned int IC1CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int IC1CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int IC1CONINV __attribute__((section("sfrs")));
+#define IC1BUF IC1BUF
+extern volatile unsigned int IC1BUF __attribute__((section("sfrs")));
+#define IC2CON IC2CON
+extern volatile unsigned int IC2CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ICM:3;
+ unsigned ICBNE:1;
+ unsigned ICOV:1;
+ unsigned ICI:2;
+ unsigned ICTMR:1;
+ unsigned C32:1;
+ unsigned FEDGE:1;
+ unsigned :3;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned ICM0:1;
+ unsigned ICM1:1;
+ unsigned ICM2:1;
+ unsigned :2;
+ unsigned ICI0:1;
+ unsigned ICI1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned ICSIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IC2CONbits_t;
+extern volatile __IC2CONbits_t IC2CONbits __asm__ ("IC2CON") __attribute__((section("sfrs")));
+extern volatile unsigned int IC2CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int IC2CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int IC2CONINV __attribute__((section("sfrs")));
+#define IC2BUF IC2BUF
+extern volatile unsigned int IC2BUF __attribute__((section("sfrs")));
+#define IC3CON IC3CON
+extern volatile unsigned int IC3CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ICM:3;
+ unsigned ICBNE:1;
+ unsigned ICOV:1;
+ unsigned ICI:2;
+ unsigned ICTMR:1;
+ unsigned C32:1;
+ unsigned FEDGE:1;
+ unsigned :3;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned ICM0:1;
+ unsigned ICM1:1;
+ unsigned ICM2:1;
+ unsigned :2;
+ unsigned ICI0:1;
+ unsigned ICI1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned ICSIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IC3CONbits_t;
+extern volatile __IC3CONbits_t IC3CONbits __asm__ ("IC3CON") __attribute__((section("sfrs")));
+extern volatile unsigned int IC3CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int IC3CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int IC3CONINV __attribute__((section("sfrs")));
+#define IC3BUF IC3BUF
+extern volatile unsigned int IC3BUF __attribute__((section("sfrs")));
+#define IC4CON IC4CON
+extern volatile unsigned int IC4CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ICM:3;
+ unsigned ICBNE:1;
+ unsigned ICOV:1;
+ unsigned ICI:2;
+ unsigned ICTMR:1;
+ unsigned C32:1;
+ unsigned FEDGE:1;
+ unsigned :3;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned ICM0:1;
+ unsigned ICM1:1;
+ unsigned ICM2:1;
+ unsigned :2;
+ unsigned ICI0:1;
+ unsigned ICI1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned ICSIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IC4CONbits_t;
+extern volatile __IC4CONbits_t IC4CONbits __asm__ ("IC4CON") __attribute__((section("sfrs")));
+extern volatile unsigned int IC4CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int IC4CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int IC4CONINV __attribute__((section("sfrs")));
+#define IC4BUF IC4BUF
+extern volatile unsigned int IC4BUF __attribute__((section("sfrs")));
+#define IC5CON IC5CON
+extern volatile unsigned int IC5CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ICM:3;
+ unsigned ICBNE:1;
+ unsigned ICOV:1;
+ unsigned ICI:2;
+ unsigned ICTMR:1;
+ unsigned C32:1;
+ unsigned FEDGE:1;
+ unsigned :3;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned ICM0:1;
+ unsigned ICM1:1;
+ unsigned ICM2:1;
+ unsigned :2;
+ unsigned ICI0:1;
+ unsigned ICI1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned ICSIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IC5CONbits_t;
+extern volatile __IC5CONbits_t IC5CONbits __asm__ ("IC5CON") __attribute__((section("sfrs")));
+extern volatile unsigned int IC5CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int IC5CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int IC5CONINV __attribute__((section("sfrs")));
+#define IC5BUF IC5BUF
+extern volatile unsigned int IC5BUF __attribute__((section("sfrs")));
+#define OC1CON OC1CON
+extern volatile unsigned int OC1CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned OCM:3;
+ unsigned OCTSEL:1;
+ unsigned OCFLT:1;
+ unsigned OC32:1;
+ unsigned :7;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned OCM0:1;
+ unsigned OCM1:1;
+ unsigned OCM2:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned OCSIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __OC1CONbits_t;
+extern volatile __OC1CONbits_t OC1CONbits __asm__ ("OC1CON") __attribute__((section("sfrs")));
+extern volatile unsigned int OC1CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC1CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC1CONINV __attribute__((section("sfrs")));
+#define OC1R OC1R
+extern volatile unsigned int OC1R __attribute__((section("sfrs")));
+extern volatile unsigned int OC1RCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC1RSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC1RINV __attribute__((section("sfrs")));
+#define OC1RS OC1RS
+extern volatile unsigned int OC1RS __attribute__((section("sfrs")));
+extern volatile unsigned int OC1RSCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC1RSSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC1RSINV __attribute__((section("sfrs")));
+#define OC2CON OC2CON
+extern volatile unsigned int OC2CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned OCM:3;
+ unsigned OCTSEL:1;
+ unsigned OCFLT:1;
+ unsigned OC32:1;
+ unsigned :7;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned OCM0:1;
+ unsigned OCM1:1;
+ unsigned OCM2:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned OCSIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __OC2CONbits_t;
+extern volatile __OC2CONbits_t OC2CONbits __asm__ ("OC2CON") __attribute__((section("sfrs")));
+extern volatile unsigned int OC2CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC2CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC2CONINV __attribute__((section("sfrs")));
+#define OC2R OC2R
+extern volatile unsigned int OC2R __attribute__((section("sfrs")));
+extern volatile unsigned int OC2RCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC2RSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC2RINV __attribute__((section("sfrs")));
+#define OC2RS OC2RS
+extern volatile unsigned int OC2RS __attribute__((section("sfrs")));
+extern volatile unsigned int OC2RSCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC2RSSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC2RSINV __attribute__((section("sfrs")));
+#define OC3CON OC3CON
+extern volatile unsigned int OC3CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned OCM:3;
+ unsigned OCTSEL:1;
+ unsigned OCFLT:1;
+ unsigned OC32:1;
+ unsigned :7;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned OCM0:1;
+ unsigned OCM1:1;
+ unsigned OCM2:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned OCSIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __OC3CONbits_t;
+extern volatile __OC3CONbits_t OC3CONbits __asm__ ("OC3CON") __attribute__((section("sfrs")));
+extern volatile unsigned int OC3CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC3CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC3CONINV __attribute__((section("sfrs")));
+#define OC3R OC3R
+extern volatile unsigned int OC3R __attribute__((section("sfrs")));
+extern volatile unsigned int OC3RCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC3RSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC3RINV __attribute__((section("sfrs")));
+#define OC3RS OC3RS
+extern volatile unsigned int OC3RS __attribute__((section("sfrs")));
+extern volatile unsigned int OC3RSCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC3RSSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC3RSINV __attribute__((section("sfrs")));
+#define OC4CON OC4CON
+extern volatile unsigned int OC4CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned OCM:3;
+ unsigned OCTSEL:1;
+ unsigned OCFLT:1;
+ unsigned OC32:1;
+ unsigned :7;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned OCM0:1;
+ unsigned OCM1:1;
+ unsigned OCM2:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned OCSIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __OC4CONbits_t;
+extern volatile __OC4CONbits_t OC4CONbits __asm__ ("OC4CON") __attribute__((section("sfrs")));
+extern volatile unsigned int OC4CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC4CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC4CONINV __attribute__((section("sfrs")));
+#define OC4R OC4R
+extern volatile unsigned int OC4R __attribute__((section("sfrs")));
+extern volatile unsigned int OC4RCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC4RSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC4RINV __attribute__((section("sfrs")));
+#define OC4RS OC4RS
+extern volatile unsigned int OC4RS __attribute__((section("sfrs")));
+extern volatile unsigned int OC4RSCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC4RSSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC4RSINV __attribute__((section("sfrs")));
+#define OC5CON OC5CON
+extern volatile unsigned int OC5CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned OCM:3;
+ unsigned OCTSEL:1;
+ unsigned OCFLT:1;
+ unsigned OC32:1;
+ unsigned :7;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned OCM0:1;
+ unsigned OCM1:1;
+ unsigned OCM2:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned OCSIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __OC5CONbits_t;
+extern volatile __OC5CONbits_t OC5CONbits __asm__ ("OC5CON") __attribute__((section("sfrs")));
+extern volatile unsigned int OC5CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC5CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC5CONINV __attribute__((section("sfrs")));
+#define OC5R OC5R
+extern volatile unsigned int OC5R __attribute__((section("sfrs")));
+extern volatile unsigned int OC5RCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC5RSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC5RINV __attribute__((section("sfrs")));
+#define OC5RS OC5RS
+extern volatile unsigned int OC5RS __attribute__((section("sfrs")));
+extern volatile unsigned int OC5RSCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OC5RSSET __attribute__((section("sfrs")));
+extern volatile unsigned int OC5RSINV __attribute__((section("sfrs")));
+#define I2C1111CON I2C1111CON
+extern volatile unsigned int I2C1111CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned SEN:1;
+ unsigned RSEN:1;
+ unsigned PEN:1;
+ unsigned RCEN:1;
+ unsigned ACKEN:1;
+ unsigned ACKDT:1;
+ unsigned STREN:1;
+ unsigned GCEN:1;
+ unsigned SMEN:1;
+ unsigned DISSLW:1;
+ unsigned A10M:1;
+ unsigned STRICT:1;
+ unsigned SCLREL:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :11;
+ unsigned IPMIEN:1;
+ unsigned :1;
+ unsigned I2CSIDL:1;
+ unsigned :1;
+ unsigned I2CEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __I2C1111CONbits_t;
+extern volatile __I2C1111CONbits_t I2C1111CONbits __asm__ ("I2C1111CON") __attribute__((section("sfrs")));
+#define I2C1CON I2C1CON
+extern volatile unsigned int I2C1CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned SEN:1;
+ unsigned RSEN:1;
+ unsigned PEN:1;
+ unsigned RCEN:1;
+ unsigned ACKEN:1;
+ unsigned ACKDT:1;
+ unsigned STREN:1;
+ unsigned GCEN:1;
+ unsigned SMEN:1;
+ unsigned DISSLW:1;
+ unsigned A10M:1;
+ unsigned STRICT:1;
+ unsigned SCLREL:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :11;
+ unsigned IPMIEN:1;
+ unsigned :1;
+ unsigned I2CSIDL:1;
+ unsigned :1;
+ unsigned I2CEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __I2C1CONbits_t;
+extern volatile __I2C1CONbits_t I2C1CONbits __asm__ ("I2C1CON") __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111CONINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1CONINV __attribute__((section("sfrs")));
+#define I2C1111STAT I2C1111STAT
+extern volatile unsigned int I2C1111STAT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned TBF:1;
+ unsigned RBF:1;
+ unsigned R_W:1;
+ unsigned S:1;
+ unsigned P:1;
+ unsigned D_A:1;
+ unsigned I2COV:1;
+ unsigned IWCOL:1;
+ unsigned ADD10:1;
+ unsigned GCSTAT:1;
+ unsigned BCL:1;
+ unsigned :3;
+ unsigned TRSTAT:1;
+ unsigned ACKSTAT:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned I2CPOV:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __I2C1111STATbits_t;
+extern volatile __I2C1111STATbits_t I2C1111STATbits __asm__ ("I2C1111STAT") __attribute__((section("sfrs")));
+#define I2C1STAT I2C1STAT
+extern volatile unsigned int I2C1STAT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned TBF:1;
+ unsigned RBF:1;
+ unsigned R_W:1;
+ unsigned S:1;
+ unsigned P:1;
+ unsigned D_A:1;
+ unsigned I2COV:1;
+ unsigned IWCOL:1;
+ unsigned ADD10:1;
+ unsigned GCSTAT:1;
+ unsigned BCL:1;
+ unsigned :3;
+ unsigned TRSTAT:1;
+ unsigned ACKSTAT:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned I2CPOV:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __I2C1STATbits_t;
+extern volatile __I2C1STATbits_t I2C1STATbits __asm__ ("I2C1STAT") __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111STATCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1STATCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111STATSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1STATSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111STATINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1STATINV __attribute__((section("sfrs")));
+#define I2C1111ADD I2C1111ADD
+extern volatile unsigned int I2C1111ADD __attribute__((section("sfrs")));
+#define I2C1ADD I2C1ADD
+extern volatile unsigned int I2C1ADD __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111ADDCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1ADDCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111ADDSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1ADDSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111ADDINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1ADDINV __attribute__((section("sfrs")));
+#define I2C1111MSK I2C1111MSK
+extern volatile unsigned int I2C1111MSK __attribute__((section("sfrs")));
+#define I2C1MSK I2C1MSK
+extern volatile unsigned int I2C1MSK __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111MSKCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1MSKCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111MSKSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1MSKSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111MSKINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1MSKINV __attribute__((section("sfrs")));
+#define I2C1111BRG I2C1111BRG
+extern volatile unsigned int I2C1111BRG __attribute__((section("sfrs")));
+#define I2C1BRG I2C1BRG
+extern volatile unsigned int I2C1BRG __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111BRGINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1BRGINV __attribute__((section("sfrs")));
+#define I2C1111TRN I2C1111TRN
+extern volatile unsigned int I2C1111TRN __attribute__((section("sfrs")));
+#define I2C1TRN I2C1TRN
+extern volatile unsigned int I2C1TRN __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111TRNCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1TRNCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111TRNSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1TRNSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1111TRNINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2C1TRNINV __attribute__((section("sfrs")));
+#define I2C1111RCV I2C1111RCV
+extern volatile unsigned int I2C1111RCV __attribute__((section("sfrs")));
+#define I2C1RCV I2C1RCV
+extern volatile unsigned int I2C1RCV __attribute__((section("sfrs")));
+#define I2C2CON I2C2CON
+extern volatile unsigned int I2C2CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned SEN:1;
+ unsigned RSEN:1;
+ unsigned PEN:1;
+ unsigned RCEN:1;
+ unsigned ACKEN:1;
+ unsigned ACKDT:1;
+ unsigned STREN:1;
+ unsigned GCEN:1;
+ unsigned SMEN:1;
+ unsigned DISSLW:1;
+ unsigned A10M:1;
+ unsigned STRICT:1;
+ unsigned SCLREL:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :11;
+ unsigned IPMIEN:1;
+ unsigned :1;
+ unsigned I2CSIDL:1;
+ unsigned :1;
+ unsigned I2CEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __I2C2CONbits_t;
+extern volatile __I2C2CONbits_t I2C2CONbits __asm__ ("I2C2CON") __attribute__((section("sfrs")));
+#define I2CABCON I2CABCON
+extern volatile unsigned int I2CABCON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned SEN:1;
+ unsigned RSEN:1;
+ unsigned PEN:1;
+ unsigned RCEN:1;
+ unsigned ACKEN:1;
+ unsigned ACKDT:1;
+ unsigned STREN:1;
+ unsigned GCEN:1;
+ unsigned SMEN:1;
+ unsigned DISSLW:1;
+ unsigned A10M:1;
+ unsigned STRICT:1;
+ unsigned SCLREL:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :11;
+ unsigned IPMIEN:1;
+ unsigned :1;
+ unsigned I2CSIDL:1;
+ unsigned :1;
+ unsigned I2CEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __I2CABCONbits_t;
+extern volatile __I2CABCONbits_t I2CABCONbits __asm__ ("I2CABCON") __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2CONINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABCONINV __attribute__((section("sfrs")));
+#define I2C2STAT I2C2STAT
+extern volatile unsigned int I2C2STAT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned TBF:1;
+ unsigned RBF:1;
+ unsigned R_W:1;
+ unsigned S:1;
+ unsigned P:1;
+ unsigned D_A:1;
+ unsigned I2COV:1;
+ unsigned IWCOL:1;
+ unsigned ADD10:1;
+ unsigned GCSTAT:1;
+ unsigned BCL:1;
+ unsigned :3;
+ unsigned TRSTAT:1;
+ unsigned ACKSTAT:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned I2CPOV:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __I2C2STATbits_t;
+extern volatile __I2C2STATbits_t I2C2STATbits __asm__ ("I2C2STAT") __attribute__((section("sfrs")));
+#define I2CABSTAT I2CABSTAT
+extern volatile unsigned int I2CABSTAT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned TBF:1;
+ unsigned RBF:1;
+ unsigned R_W:1;
+ unsigned S:1;
+ unsigned P:1;
+ unsigned D_A:1;
+ unsigned I2COV:1;
+ unsigned IWCOL:1;
+ unsigned ADD10:1;
+ unsigned GCSTAT:1;
+ unsigned BCL:1;
+ unsigned :3;
+ unsigned TRSTAT:1;
+ unsigned ACKSTAT:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned I2CPOV:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __I2CABSTATbits_t;
+extern volatile __I2CABSTATbits_t I2CABSTATbits __asm__ ("I2CABSTAT") __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2STATCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABSTATCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2STATSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABSTATSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2STATINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABSTATINV __attribute__((section("sfrs")));
+#define I2C2ADD I2C2ADD
+extern volatile unsigned int I2C2ADD __attribute__((section("sfrs")));
+#define I2CABADD I2CABADD
+extern volatile unsigned int I2CABADD __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2ADDCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABADDCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2ADDSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABADDSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2ADDINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABADDINV __attribute__((section("sfrs")));
+#define I2C2MSK I2C2MSK
+extern volatile unsigned int I2C2MSK __attribute__((section("sfrs")));
+#define I2CABMSK I2CABMSK
+extern volatile unsigned int I2CABMSK __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2MSKCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABMSKCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2MSKSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABMSKSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2MSKINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABMSKINV __attribute__((section("sfrs")));
+#define I2C2BRG I2C2BRG
+extern volatile unsigned int I2C2BRG __attribute__((section("sfrs")));
+#define I2CABBRG I2CABBRG
+extern volatile unsigned int I2CABBRG __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABBRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABBRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2BRGINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABBRGINV __attribute__((section("sfrs")));
+#define I2C2TRN I2C2TRN
+extern volatile unsigned int I2C2TRN __attribute__((section("sfrs")));
+#define I2CABTRN I2CABTRN
+extern volatile unsigned int I2CABTRN __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2TRNCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABTRNCLR __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2TRNSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABTRNSET __attribute__((section("sfrs")));
+extern volatile unsigned int I2C2TRNINV __attribute__((section("sfrs")));
+extern volatile unsigned int I2CABTRNINV __attribute__((section("sfrs")));
+#define I2C2RCV I2C2RCV
+extern volatile unsigned int I2C2RCV __attribute__((section("sfrs")));
+#define I2CABRCV I2CABRCV
+extern volatile unsigned int I2CABRCV __attribute__((section("sfrs")));
+#define SPI1CON SPI1CON
+extern volatile unsigned int SPI1CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned SRXISEL:2;
+ unsigned STXISEL:2;
+ unsigned DISSDI:1;
+ unsigned MSTEN:1;
+ unsigned CKP:1;
+ unsigned SSEN:1;
+ unsigned CKE:1;
+ unsigned SMP:1;
+ unsigned MODE16:1;
+ unsigned MODE32:1;
+ unsigned DISSDO:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ unsigned ENHBUF:1;
+ unsigned SPIFE:1;
+ unsigned :5;
+ unsigned MCLKSEL:1;
+ unsigned FRMCNT:3;
+ unsigned FRMSYPW:1;
+ unsigned MSSEN:1;
+ unsigned FRMPOL:1;
+ unsigned FRMSYNC:1;
+ unsigned FRMEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __SPI1CONbits_t;
+extern volatile __SPI1CONbits_t SPI1CONbits __asm__ ("SPI1CON") __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1CONINV __attribute__((section("sfrs")));
+#define SPI1STAT SPI1STAT
+extern volatile unsigned int SPI1STAT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned SPIRBF:1;
+ unsigned SPITBF:1;
+ unsigned :1;
+ unsigned SPITBE:1;
+ unsigned :1;
+ unsigned SPIRBE:1;
+ unsigned SPIROV:1;
+ unsigned SRMT:1;
+ unsigned SPITUR:1;
+ unsigned :2;
+ unsigned SPIBUSY:1;
+ unsigned FRMERR:1;
+ unsigned :3;
+ unsigned TXBUFELM:5;
+ unsigned :3;
+ unsigned RXBUFELM:5;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __SPI1STATbits_t;
+extern volatile __SPI1STATbits_t SPI1STATbits __asm__ ("SPI1STAT") __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1STATCLR __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1STATSET __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1STATINV __attribute__((section("sfrs")));
+#define SPI1BUF SPI1BUF
+extern volatile unsigned int SPI1BUF __attribute__((section("sfrs")));
+#define SPI1BRG SPI1BRG
+extern volatile unsigned int SPI1BRG __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1BRGINV __attribute__((section("sfrs")));
+#define SPI1CON2 SPI1CON2
+extern volatile unsigned int SPI1CON2 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned AUDMOD:2;
+ unsigned :1;
+ unsigned AUDMONO:1;
+ unsigned :3;
+ unsigned AUDEN:1;
+ unsigned IGNTUR:1;
+ unsigned IGNROV:1;
+ unsigned SPITUREN:1;
+ unsigned SPIROVEN:1;
+ unsigned FRMERREN:1;
+ unsigned :2;
+ unsigned SPISGNEXT:1;
+ };
+ struct {
+ unsigned AUDMOD0:1;
+ unsigned AUDMOD1:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __SPI1CON2bits_t;
+extern volatile __SPI1CON2bits_t SPI1CON2bits __asm__ ("SPI1CON2") __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1CON2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1CON2SET __attribute__((section("sfrs")));
+extern volatile unsigned int SPI1CON2INV __attribute__((section("sfrs")));
+#define SPI2CON SPI2CON
+extern volatile unsigned int SPI2CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned SRXISEL:2;
+ unsigned STXISEL:2;
+ unsigned DISSDI:1;
+ unsigned MSTEN:1;
+ unsigned CKP:1;
+ unsigned SSEN:1;
+ unsigned CKE:1;
+ unsigned SMP:1;
+ unsigned MODE16:1;
+ unsigned MODE32:1;
+ unsigned DISSDO:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ unsigned ENHBUF:1;
+ unsigned SPIFE:1;
+ unsigned :5;
+ unsigned MCLKSEL:1;
+ unsigned FRMCNT:3;
+ unsigned FRMSYPW:1;
+ unsigned MSSEN:1;
+ unsigned FRMPOL:1;
+ unsigned FRMSYNC:1;
+ unsigned FRMEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __SPI2CONbits_t;
+extern volatile __SPI2CONbits_t SPI2CONbits __asm__ ("SPI2CON") __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2CONINV __attribute__((section("sfrs")));
+#define SPI2STAT SPI2STAT
+extern volatile unsigned int SPI2STAT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned SPIRBF:1;
+ unsigned SPITBF:1;
+ unsigned :1;
+ unsigned SPITBE:1;
+ unsigned :1;
+ unsigned SPIRBE:1;
+ unsigned SPIROV:1;
+ unsigned SRMT:1;
+ unsigned SPITUR:1;
+ unsigned :2;
+ unsigned SPIBUSY:1;
+ unsigned FRMERR:1;
+ unsigned :3;
+ unsigned TXBUFELM:5;
+ unsigned :3;
+ unsigned RXBUFELM:5;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __SPI2STATbits_t;
+extern volatile __SPI2STATbits_t SPI2STATbits __asm__ ("SPI2STAT") __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2STATCLR __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2STATSET __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2STATINV __attribute__((section("sfrs")));
+#define SPI2BUF SPI2BUF
+extern volatile unsigned int SPI2BUF __attribute__((section("sfrs")));
+#define SPI2BRG SPI2BRG
+extern volatile unsigned int SPI2BRG __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2BRGINV __attribute__((section("sfrs")));
+#define SPI2CON2 SPI2CON2
+extern volatile unsigned int SPI2CON2 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned AUDMOD:2;
+ unsigned :1;
+ unsigned AUDMONO:1;
+ unsigned :3;
+ unsigned AUDEN:1;
+ unsigned IGNTUR:1;
+ unsigned IGNROV:1;
+ unsigned SPITUREN:1;
+ unsigned SPIROVEN:1;
+ unsigned FRMERREN:1;
+ unsigned :2;
+ unsigned SPISGNEXT:1;
+ };
+ struct {
+ unsigned AUDMOD0:1;
+ unsigned AUDMOD1:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __SPI2CON2bits_t;
+extern volatile __SPI2CON2bits_t SPI2CON2bits __asm__ ("SPI2CON2") __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2CON2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2CON2SET __attribute__((section("sfrs")));
+extern volatile unsigned int SPI2CON2INV __attribute__((section("sfrs")));
+#define U1MODE U1MODE
+extern volatile unsigned int U1MODE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned STSEL:1;
+ unsigned PDSEL:2;
+ unsigned BRGH:1;
+ unsigned RXINV:1;
+ unsigned ABAUD:1;
+ unsigned LPBACK:1;
+ unsigned WAKE:1;
+ unsigned UEN:2;
+ unsigned :1;
+ unsigned RTSMD:1;
+ unsigned IREN:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :1;
+ unsigned PDSEL0:1;
+ unsigned PDSEL1:1;
+ unsigned :5;
+ unsigned UEN0:1;
+ unsigned UEN1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned USIDL:1;
+ unsigned :1;
+ unsigned UARTEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U1MODEbits_t;
+extern volatile __U1MODEbits_t U1MODEbits __asm__ ("U1MODE") __attribute__((section("sfrs")));
+#define UDCMODE UDCMODE
+extern volatile unsigned int UDCMODE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned STSEL:1;
+ unsigned PDSEL:2;
+ unsigned BRGH:1;
+ unsigned RXINV:1;
+ unsigned ABAUD:1;
+ unsigned LPBACK:1;
+ unsigned WAKE:1;
+ unsigned UEN:2;
+ unsigned :1;
+ unsigned RTSMD:1;
+ unsigned IREN:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :1;
+ unsigned PDSEL0:1;
+ unsigned PDSEL1:1;
+ unsigned :5;
+ unsigned UEN0:1;
+ unsigned UEN1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned USIDL:1;
+ unsigned :1;
+ unsigned UARTEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __UDCMODEbits_t;
+extern volatile __UDCMODEbits_t UDCMODEbits __asm__ ("UDCMODE") __attribute__((section("sfrs")));
+extern volatile unsigned int U1MODECLR __attribute__((section("sfrs")));
+extern volatile unsigned int UDCMODECLR __attribute__((section("sfrs")));
+extern volatile unsigned int U1MODESET __attribute__((section("sfrs")));
+extern volatile unsigned int UDCMODESET __attribute__((section("sfrs")));
+extern volatile unsigned int U1MODEINV __attribute__((section("sfrs")));
+extern volatile unsigned int UDCMODEINV __attribute__((section("sfrs")));
+#define U1STA U1STA
+extern volatile unsigned int U1STA __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned URXDA:1;
+ unsigned OERR:1;
+ unsigned FERR:1;
+ unsigned PERR:1;
+ unsigned RIDLE:1;
+ unsigned ADDEN:1;
+ unsigned URXISEL:2;
+ unsigned TRMT:1;
+ unsigned UTXBF:1;
+ unsigned UTXEN:1;
+ unsigned UTXBRK:1;
+ unsigned URXEN:1;
+ unsigned UTXINV:1;
+ unsigned UTXISEL:2;
+ unsigned ADDR:8;
+ unsigned ADM_EN:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned URXISEL0:1;
+ unsigned URXISEL1:1;
+ unsigned :6;
+ unsigned UTXISEL0:1;
+ unsigned UTXISEL1:1;
+ };
+ struct {
+ unsigned :14;
+ unsigned UTXSEL:2;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U1STAbits_t;
+extern volatile __U1STAbits_t U1STAbits __asm__ ("U1STA") __attribute__((section("sfrs")));
+#define UDCSTA UDCSTA
+extern volatile unsigned int UDCSTA __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned URXDA:1;
+ unsigned OERR:1;
+ unsigned FERR:1;
+ unsigned PERR:1;
+ unsigned RIDLE:1;
+ unsigned ADDEN:1;
+ unsigned URXISEL:2;
+ unsigned TRMT:1;
+ unsigned UTXBF:1;
+ unsigned UTXEN:1;
+ unsigned UTXBRK:1;
+ unsigned URXEN:1;
+ unsigned UTXINV:1;
+ unsigned UTXISEL:2;
+ unsigned ADDR:8;
+ unsigned ADM_EN:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned URXISEL0:1;
+ unsigned URXISEL1:1;
+ unsigned :6;
+ unsigned UTXISEL0:1;
+ unsigned UTXISEL1:1;
+ };
+ struct {
+ unsigned :14;
+ unsigned UTXSEL:2;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __UDCSTAbits_t;
+extern volatile __UDCSTAbits_t UDCSTAbits __asm__ ("UDCSTA") __attribute__((section("sfrs")));
+extern volatile unsigned int U1STACLR __attribute__((section("sfrs")));
+extern volatile unsigned int UDCSTACLR __attribute__((section("sfrs")));
+extern volatile unsigned int U1STASET __attribute__((section("sfrs")));
+extern volatile unsigned int UDCSTASET __attribute__((section("sfrs")));
+extern volatile unsigned int U1STAINV __attribute__((section("sfrs")));
+extern volatile unsigned int UDCSTAINV __attribute__((section("sfrs")));
+#define U1TXREG U1TXREG
+extern volatile unsigned int U1TXREG __attribute__((section("sfrs")));
+#define UDCTXREG UDCTXREG
+extern volatile unsigned int UDCTXREG __attribute__((section("sfrs")));
+#define U1RXREG U1RXREG
+extern volatile unsigned int U1RXREG __attribute__((section("sfrs")));
+#define UDCRXREG UDCRXREG
+extern volatile unsigned int UDCRXREG __attribute__((section("sfrs")));
+#define U1BRG U1BRG
+extern volatile unsigned int U1BRG __attribute__((section("sfrs")));
+#define UDCBRG UDCBRG
+extern volatile unsigned int UDCBRG __attribute__((section("sfrs")));
+extern volatile unsigned int U1BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int UDCBRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int U1BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int UDCBRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int U1BRGINV __attribute__((section("sfrs")));
+extern volatile unsigned int UDCBRGINV __attribute__((section("sfrs")));
+#define U2MODE U2MODE
+extern volatile unsigned int U2MODE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned STSEL:1;
+ unsigned PDSEL:2;
+ unsigned BRGH:1;
+ unsigned RXINV:1;
+ unsigned ABAUD:1;
+ unsigned LPBACK:1;
+ unsigned WAKE:1;
+ unsigned UEN:2;
+ unsigned :1;
+ unsigned RTSMD:1;
+ unsigned IREN:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :1;
+ unsigned PDSEL0:1;
+ unsigned PDSEL1:1;
+ unsigned :5;
+ unsigned UEN0:1;
+ unsigned UEN1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned USIDL:1;
+ unsigned :1;
+ unsigned UARTEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U2MODEbits_t;
+extern volatile __U2MODEbits_t U2MODEbits __asm__ ("U2MODE") __attribute__((section("sfrs")));
+#define U8932MODE U8932MODE
+extern volatile unsigned int U8932MODE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned STSEL:1;
+ unsigned PDSEL:2;
+ unsigned BRGH:1;
+ unsigned RXINV:1;
+ unsigned ABAUD:1;
+ unsigned LPBACK:1;
+ unsigned WAKE:1;
+ unsigned UEN:2;
+ unsigned :1;
+ unsigned RTSMD:1;
+ unsigned IREN:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :1;
+ unsigned PDSEL0:1;
+ unsigned PDSEL1:1;
+ unsigned :5;
+ unsigned UEN0:1;
+ unsigned UEN1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned USIDL:1;
+ unsigned :1;
+ unsigned UARTEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U8932MODEbits_t;
+extern volatile __U8932MODEbits_t U8932MODEbits __asm__ ("U8932MODE") __attribute__((section("sfrs")));
+extern volatile unsigned int U2MODECLR __attribute__((section("sfrs")));
+extern volatile unsigned int U8932MODECLR __attribute__((section("sfrs")));
+extern volatile unsigned int U2MODESET __attribute__((section("sfrs")));
+extern volatile unsigned int U8932MODESET __attribute__((section("sfrs")));
+extern volatile unsigned int U2MODEINV __attribute__((section("sfrs")));
+extern volatile unsigned int U8932MODEINV __attribute__((section("sfrs")));
+#define U2STA U2STA
+extern volatile unsigned int U2STA __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned URXDA:1;
+ unsigned OERR:1;
+ unsigned FERR:1;
+ unsigned PERR:1;
+ unsigned RIDLE:1;
+ unsigned ADDEN:1;
+ unsigned URXISEL:2;
+ unsigned TRMT:1;
+ unsigned UTXBF:1;
+ unsigned UTXEN:1;
+ unsigned UTXBRK:1;
+ unsigned URXEN:1;
+ unsigned UTXINV:1;
+ unsigned UTXISEL:2;
+ unsigned ADDR:8;
+ unsigned ADM_EN:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned URXISEL0:1;
+ unsigned URXISEL1:1;
+ unsigned :6;
+ unsigned UTXISEL0:1;
+ unsigned UTXISEL1:1;
+ };
+ struct {
+ unsigned :14;
+ unsigned UTXSEL:2;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U2STAbits_t;
+extern volatile __U2STAbits_t U2STAbits __asm__ ("U2STA") __attribute__((section("sfrs")));
+#define U8932STA U8932STA
+extern volatile unsigned int U8932STA __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned URXDA:1;
+ unsigned OERR:1;
+ unsigned FERR:1;
+ unsigned PERR:1;
+ unsigned RIDLE:1;
+ unsigned ADDEN:1;
+ unsigned URXISEL:2;
+ unsigned TRMT:1;
+ unsigned UTXBF:1;
+ unsigned UTXEN:1;
+ unsigned UTXBRK:1;
+ unsigned URXEN:1;
+ unsigned UTXINV:1;
+ unsigned UTXISEL:2;
+ unsigned ADDR:8;
+ unsigned ADM_EN:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned URXISEL0:1;
+ unsigned URXISEL1:1;
+ unsigned :6;
+ unsigned UTXISEL0:1;
+ unsigned UTXISEL1:1;
+ };
+ struct {
+ unsigned :14;
+ unsigned UTXSEL:2;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U8932STAbits_t;
+extern volatile __U8932STAbits_t U8932STAbits __asm__ ("U8932STA") __attribute__((section("sfrs")));
+extern volatile unsigned int U2STACLR __attribute__((section("sfrs")));
+extern volatile unsigned int U8932STACLR __attribute__((section("sfrs")));
+extern volatile unsigned int U2STASET __attribute__((section("sfrs")));
+extern volatile unsigned int U8932STASET __attribute__((section("sfrs")));
+extern volatile unsigned int U2STAINV __attribute__((section("sfrs")));
+extern volatile unsigned int U8932STAINV __attribute__((section("sfrs")));
+#define U2TXREG U2TXREG
+extern volatile unsigned int U2TXREG __attribute__((section("sfrs")));
+#define U8932TXREG U8932TXREG
+extern volatile unsigned int U8932TXREG __attribute__((section("sfrs")));
+#define U2RXREG U2RXREG
+extern volatile unsigned int U2RXREG __attribute__((section("sfrs")));
+#define U8932RXREG U8932RXREG
+extern volatile unsigned int U8932RXREG __attribute__((section("sfrs")));
+#define U2BRG U2BRG
+extern volatile unsigned int U2BRG __attribute__((section("sfrs")));
+#define U8932BRG U8932BRG
+extern volatile unsigned int U8932BRG __attribute__((section("sfrs")));
+extern volatile unsigned int U2BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int U8932BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int U2BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int U8932BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int U2BRGINV __attribute__((section("sfrs")));
+extern volatile unsigned int U8932BRGINV __attribute__((section("sfrs")));
+#define U39MODE U39MODE
+extern volatile unsigned int U39MODE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned STSEL:1;
+ unsigned PDSEL:2;
+ unsigned BRGH:1;
+ unsigned RXINV:1;
+ unsigned ABAUD:1;
+ unsigned LPBACK:1;
+ unsigned WAKE:1;
+ unsigned UEN:2;
+ unsigned :1;
+ unsigned RTSMD:1;
+ unsigned IREN:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :1;
+ unsigned PDSEL0:1;
+ unsigned PDSEL1:1;
+ unsigned :5;
+ unsigned UEN0:1;
+ unsigned UEN1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned USIDL:1;
+ unsigned :1;
+ unsigned UARTEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U39MODEbits_t;
+extern volatile __U39MODEbits_t U39MODEbits __asm__ ("U39MODE") __attribute__((section("sfrs")));
+#define U3MODE U3MODE
+extern volatile unsigned int U3MODE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned STSEL:1;
+ unsigned PDSEL:2;
+ unsigned BRGH:1;
+ unsigned RXINV:1;
+ unsigned ABAUD:1;
+ unsigned LPBACK:1;
+ unsigned WAKE:1;
+ unsigned UEN:2;
+ unsigned :1;
+ unsigned RTSMD:1;
+ unsigned IREN:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :1;
+ unsigned PDSEL0:1;
+ unsigned PDSEL1:1;
+ unsigned :5;
+ unsigned UEN0:1;
+ unsigned UEN1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned USIDL:1;
+ unsigned :1;
+ unsigned UARTEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U3MODEbits_t;
+extern volatile __U3MODEbits_t U3MODEbits __asm__ ("U3MODE") __attribute__((section("sfrs")));
+extern volatile unsigned int U39MODECLR __attribute__((section("sfrs")));
+extern volatile unsigned int U3MODECLR __attribute__((section("sfrs")));
+extern volatile unsigned int U39MODESET __attribute__((section("sfrs")));
+extern volatile unsigned int U3MODESET __attribute__((section("sfrs")));
+extern volatile unsigned int U39MODEINV __attribute__((section("sfrs")));
+extern volatile unsigned int U3MODEINV __attribute__((section("sfrs")));
+#define U39STA U39STA
+extern volatile unsigned int U39STA __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned URXDA:1;
+ unsigned OERR:1;
+ unsigned FERR:1;
+ unsigned PERR:1;
+ unsigned RIDLE:1;
+ unsigned ADDEN:1;
+ unsigned URXISEL:2;
+ unsigned TRMT:1;
+ unsigned UTXBF:1;
+ unsigned UTXEN:1;
+ unsigned UTXBRK:1;
+ unsigned URXEN:1;
+ unsigned UTXINV:1;
+ unsigned UTXISEL:2;
+ unsigned ADDR:8;
+ unsigned ADM_EN:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned URXISEL0:1;
+ unsigned URXISEL1:1;
+ unsigned :6;
+ unsigned UTXISEL0:1;
+ unsigned UTXISEL1:1;
+ };
+ struct {
+ unsigned :14;
+ unsigned UTXSEL:2;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U39STAbits_t;
+extern volatile __U39STAbits_t U39STAbits __asm__ ("U39STA") __attribute__((section("sfrs")));
+#define U3STA U3STA
+extern volatile unsigned int U3STA __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned URXDA:1;
+ unsigned OERR:1;
+ unsigned FERR:1;
+ unsigned PERR:1;
+ unsigned RIDLE:1;
+ unsigned ADDEN:1;
+ unsigned URXISEL:2;
+ unsigned TRMT:1;
+ unsigned UTXBF:1;
+ unsigned UTXEN:1;
+ unsigned UTXBRK:1;
+ unsigned URXEN:1;
+ unsigned UTXINV:1;
+ unsigned UTXISEL:2;
+ unsigned ADDR:8;
+ unsigned ADM_EN:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned URXISEL0:1;
+ unsigned URXISEL1:1;
+ unsigned :6;
+ unsigned UTXISEL0:1;
+ unsigned UTXISEL1:1;
+ };
+ struct {
+ unsigned :14;
+ unsigned UTXSEL:2;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U3STAbits_t;
+extern volatile __U3STAbits_t U3STAbits __asm__ ("U3STA") __attribute__((section("sfrs")));
+extern volatile unsigned int U39STACLR __attribute__((section("sfrs")));
+extern volatile unsigned int U3STACLR __attribute__((section("sfrs")));
+extern volatile unsigned int U39STASET __attribute__((section("sfrs")));
+extern volatile unsigned int U3STASET __attribute__((section("sfrs")));
+extern volatile unsigned int U39STAINV __attribute__((section("sfrs")));
+extern volatile unsigned int U3STAINV __attribute__((section("sfrs")));
+#define U39TXREG U39TXREG
+extern volatile unsigned int U39TXREG __attribute__((section("sfrs")));
+#define U3TXREG U3TXREG
+extern volatile unsigned int U3TXREG __attribute__((section("sfrs")));
+#define U39RXREG U39RXREG
+extern volatile unsigned int U39RXREG __attribute__((section("sfrs")));
+#define U3RXREG U3RXREG
+extern volatile unsigned int U3RXREG __attribute__((section("sfrs")));
+#define U39BRG U39BRG
+extern volatile unsigned int U39BRG __attribute__((section("sfrs")));
+#define U3BRG U3BRG
+extern volatile unsigned int U3BRG __attribute__((section("sfrs")));
+extern volatile unsigned int U39BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int U3BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int U39BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int U3BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int U39BRGINV __attribute__((section("sfrs")));
+extern volatile unsigned int U3BRGINV __attribute__((section("sfrs")));
+#define U4MODE U4MODE
+extern volatile unsigned int U4MODE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned STSEL:1;
+ unsigned PDSEL:2;
+ unsigned BRGH:1;
+ unsigned RXINV:1;
+ unsigned ABAUD:1;
+ unsigned LPBACK:1;
+ unsigned WAKE:1;
+ unsigned UEN:2;
+ unsigned :1;
+ unsigned RTSMD:1;
+ unsigned IREN:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :1;
+ unsigned PDSEL0:1;
+ unsigned PDSEL1:1;
+ unsigned :5;
+ unsigned UEN0:1;
+ unsigned UEN1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned USIDL:1;
+ unsigned :1;
+ unsigned UARTEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U4MODEbits_t;
+extern volatile __U4MODEbits_t U4MODEbits __asm__ ("U4MODE") __attribute__((section("sfrs")));
+#define UodMODE UodMODE
+extern volatile unsigned int UodMODE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned STSEL:1;
+ unsigned PDSEL:2;
+ unsigned BRGH:1;
+ unsigned RXINV:1;
+ unsigned ABAUD:1;
+ unsigned LPBACK:1;
+ unsigned WAKE:1;
+ unsigned UEN:2;
+ unsigned :1;
+ unsigned RTSMD:1;
+ unsigned IREN:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :1;
+ unsigned PDSEL0:1;
+ unsigned PDSEL1:1;
+ unsigned :5;
+ unsigned UEN0:1;
+ unsigned UEN1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned USIDL:1;
+ unsigned :1;
+ unsigned UARTEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __UodMODEbits_t;
+extern volatile __UodMODEbits_t UodMODEbits __asm__ ("UodMODE") __attribute__((section("sfrs")));
+extern volatile unsigned int U4MODECLR __attribute__((section("sfrs")));
+extern volatile unsigned int UodMODECLR __attribute__((section("sfrs")));
+extern volatile unsigned int U4MODESET __attribute__((section("sfrs")));
+extern volatile unsigned int UodMODESET __attribute__((section("sfrs")));
+extern volatile unsigned int U4MODEINV __attribute__((section("sfrs")));
+extern volatile unsigned int UodMODEINV __attribute__((section("sfrs")));
+#define U4STA U4STA
+extern volatile unsigned int U4STA __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned URXDA:1;
+ unsigned OERR:1;
+ unsigned FERR:1;
+ unsigned PERR:1;
+ unsigned RIDLE:1;
+ unsigned ADDEN:1;
+ unsigned URXISEL:2;
+ unsigned TRMT:1;
+ unsigned UTXBF:1;
+ unsigned UTXEN:1;
+ unsigned UTXBRK:1;
+ unsigned URXEN:1;
+ unsigned UTXINV:1;
+ unsigned UTXISEL:2;
+ unsigned ADDR:8;
+ unsigned ADM_EN:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned URXISEL0:1;
+ unsigned URXISEL1:1;
+ unsigned :6;
+ unsigned UTXISEL0:1;
+ unsigned UTXISEL1:1;
+ };
+ struct {
+ unsigned :14;
+ unsigned UTXSEL:2;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __U4STAbits_t;
+extern volatile __U4STAbits_t U4STAbits __asm__ ("U4STA") __attribute__((section("sfrs")));
+#define UodSTA UodSTA
+extern volatile unsigned int UodSTA __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned URXDA:1;
+ unsigned OERR:1;
+ unsigned FERR:1;
+ unsigned PERR:1;
+ unsigned RIDLE:1;
+ unsigned ADDEN:1;
+ unsigned URXISEL:2;
+ unsigned TRMT:1;
+ unsigned UTXBF:1;
+ unsigned UTXEN:1;
+ unsigned UTXBRK:1;
+ unsigned URXEN:1;
+ unsigned UTXINV:1;
+ unsigned UTXISEL:2;
+ unsigned ADDR:8;
+ unsigned ADM_EN:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned URXISEL0:1;
+ unsigned URXISEL1:1;
+ unsigned :6;
+ unsigned UTXISEL0:1;
+ unsigned UTXISEL1:1;
+ };
+ struct {
+ unsigned :14;
+ unsigned UTXSEL:2;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __UodSTAbits_t;
+extern volatile __UodSTAbits_t UodSTAbits __asm__ ("UodSTA") __attribute__((section("sfrs")));
+extern volatile unsigned int U4STACLR __attribute__((section("sfrs")));
+extern volatile unsigned int UodSTACLR __attribute__((section("sfrs")));
+extern volatile unsigned int U4STASET __attribute__((section("sfrs")));
+extern volatile unsigned int UodSTASET __attribute__((section("sfrs")));
+extern volatile unsigned int U4STAINV __attribute__((section("sfrs")));
+extern volatile unsigned int UodSTAINV __attribute__((section("sfrs")));
+#define U4TXREG U4TXREG
+extern volatile unsigned int U4TXREG __attribute__((section("sfrs")));
+#define UodTXREG UodTXREG
+extern volatile unsigned int UodTXREG __attribute__((section("sfrs")));
+#define U4RXREG U4RXREG
+extern volatile unsigned int U4RXREG __attribute__((section("sfrs")));
+#define UodRXREG UodRXREG
+extern volatile unsigned int UodRXREG __attribute__((section("sfrs")));
+#define U4BRG U4BRG
+extern volatile unsigned int U4BRG __attribute__((section("sfrs")));
+#define UodBRG UodBRG
+extern volatile unsigned int UodBRG __attribute__((section("sfrs")));
+extern volatile unsigned int U4BRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int UodBRGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int U4BRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int UodBRGSET __attribute__((section("sfrs")));
+extern volatile unsigned int U4BRGINV __attribute__((section("sfrs")));
+extern volatile unsigned int UodBRGINV __attribute__((section("sfrs")));
+#define PMCON PMCON
+extern volatile unsigned int PMCON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned RDSP:1;
+ unsigned WRSP:1;
+ unsigned :1;
+ unsigned CS1P:1;
+ unsigned CS2P:1;
+ unsigned ALP:1;
+ unsigned CSF:2;
+ unsigned PTRDEN:1;
+ unsigned PTWREN:1;
+ unsigned PMPTTL:1;
+ unsigned ADRMUX:2;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :6;
+ unsigned CSF0:1;
+ unsigned CSF1:1;
+ unsigned :3;
+ unsigned ADRMUX0:1;
+ unsigned ADRMUX1:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned PSIDL:1;
+ unsigned :1;
+ unsigned PMPEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __PMCONbits_t;
+extern volatile __PMCONbits_t PMCONbits __asm__ ("PMCON") __attribute__((section("sfrs")));
+extern volatile unsigned int PMCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int PMCONINV __attribute__((section("sfrs")));
+#define PMMODE PMMODE
+extern volatile unsigned int PMMODE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned WAITE:2;
+ unsigned WAITM:4;
+ unsigned WAITB:2;
+ unsigned MODE:2;
+ unsigned MODE16:1;
+ unsigned INCM:2;
+ unsigned IRQM:2;
+ unsigned BUSY:1;
+ };
+ struct {
+ unsigned WAITE0:1;
+ unsigned WAITE1:1;
+ unsigned WAITM0:1;
+ unsigned WAITM1:1;
+ unsigned WAITM2:1;
+ unsigned WAITM3:1;
+ unsigned WAITB0:1;
+ unsigned WAITB1:1;
+ unsigned MODE0:1;
+ unsigned MODE1:1;
+ unsigned :1;
+ unsigned INCM0:1;
+ unsigned INCM1:1;
+ unsigned IRQM0:1;
+ unsigned IRQM1:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __PMMODEbits_t;
+extern volatile __PMMODEbits_t PMMODEbits __asm__ ("PMMODE") __attribute__((section("sfrs")));
+extern volatile unsigned int PMMODECLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMMODESET __attribute__((section("sfrs")));
+extern volatile unsigned int PMMODEINV __attribute__((section("sfrs")));
+#define PMADDR PMADDR
+extern volatile unsigned int PMADDR __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ADDR:14;
+ unsigned CS:2;
+ };
+ struct {
+ unsigned PADDR:14;
+ };
+ struct {
+ unsigned :14;
+ unsigned CS1:1;
+ unsigned CS2:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __PMADDRbits_t;
+extern volatile __PMADDRbits_t PMADDRbits __asm__ ("PMADDR") __attribute__((section("sfrs")));
+extern volatile unsigned int PMADDRCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMADDRSET __attribute__((section("sfrs")));
+extern volatile unsigned int PMADDRINV __attribute__((section("sfrs")));
+#define PMDOUT PMDOUT
+extern volatile unsigned int PMDOUT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned DATAOUT:32;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __PMDOUTbits_t;
+extern volatile __PMDOUTbits_t PMDOUTbits __asm__ ("PMDOUT") __attribute__((section("sfrs")));
+extern volatile unsigned int PMDOUTCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMDOUTSET __attribute__((section("sfrs")));
+extern volatile unsigned int PMDOUTINV __attribute__((section("sfrs")));
+#define PMDIN PMDIN
+extern volatile unsigned int PMDIN __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned DATAIN:32;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __PMDINbits_t;
+extern volatile __PMDINbits_t PMDINbits __asm__ ("PMDIN") __attribute__((section("sfrs")));
+extern volatile unsigned int PMDINCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMDINSET __attribute__((section("sfrs")));
+extern volatile unsigned int PMDININV __attribute__((section("sfrs")));
+#define PMAEN PMAEN
+extern volatile unsigned int PMAEN __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned PTEN:16;
+ };
+ struct {
+ unsigned PTEN0:1;
+ unsigned PTEN1:1;
+ unsigned PTEN2:1;
+ unsigned PTEN3:1;
+ unsigned PTEN4:1;
+ unsigned PTEN5:1;
+ unsigned PTEN6:1;
+ unsigned PTEN7:1;
+ unsigned PTEN8:1;
+ unsigned PTEN9:1;
+ unsigned PTEN10:1;
+ unsigned PTEN11:1;
+ unsigned PTEN12:1;
+ unsigned PTEN13:1;
+ unsigned PTEN14:1;
+ unsigned PTEN15:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __PMAENbits_t;
+extern volatile __PMAENbits_t PMAENbits __asm__ ("PMAEN") __attribute__((section("sfrs")));
+extern volatile unsigned int PMAENCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMAENSET __attribute__((section("sfrs")));
+extern volatile unsigned int PMAENINV __attribute__((section("sfrs")));
+#define PMSTAT PMSTAT
+extern volatile unsigned int PMSTAT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned OB0E:1;
+ unsigned OB1E:1;
+ unsigned OB2E:1;
+ unsigned OB3E:1;
+ unsigned :2;
+ unsigned OBUF:1;
+ unsigned OBE:1;
+ unsigned IB0F:1;
+ unsigned IB1F:1;
+ unsigned IB2F:1;
+ unsigned IB3F:1;
+ unsigned :2;
+ unsigned IBOV:1;
+ unsigned IBF:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __PMSTATbits_t;
+extern volatile __PMSTATbits_t PMSTATbits __asm__ ("PMSTAT") __attribute__((section("sfrs")));
+extern volatile unsigned int PMSTATCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMSTATSET __attribute__((section("sfrs")));
+extern volatile unsigned int PMSTATINV __attribute__((section("sfrs")));
+#define AD1CON1 AD1CON1
+extern volatile unsigned int AD1CON1 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned DONE:1;
+ unsigned SAMP:1;
+ unsigned ASAM:1;
+ unsigned :1;
+ unsigned CLRASAM:1;
+ unsigned SSRC:3;
+ unsigned FORM:3;
+ unsigned :2;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned :5;
+ unsigned SSRC0:1;
+ unsigned SSRC1:1;
+ unsigned SSRC2:1;
+ unsigned FORM0:1;
+ unsigned FORM1:1;
+ unsigned FORM2:1;
+ };
+ struct {
+ unsigned :13;
+ unsigned ADSIDL:1;
+ unsigned :1;
+ unsigned ADON:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __AD1CON1bits_t;
+extern volatile __AD1CON1bits_t AD1CON1bits __asm__ ("AD1CON1") __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CON1CLR __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CON1SET __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CON1INV __attribute__((section("sfrs")));
+#define AD1CON2 AD1CON2
+extern volatile unsigned int AD1CON2 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ALTS:1;
+ unsigned BUFM:1;
+ unsigned SMPI:4;
+ unsigned :1;
+ unsigned BUFS:1;
+ unsigned :2;
+ unsigned CSCNA:1;
+ unsigned :1;
+ unsigned OFFCAL:1;
+ unsigned VCFG:3;
+ };
+ struct {
+ unsigned :2;
+ unsigned SMPI0:1;
+ unsigned SMPI1:1;
+ unsigned SMPI2:1;
+ unsigned SMPI3:1;
+ unsigned :7;
+ unsigned VCFG0:1;
+ unsigned VCFG1:1;
+ unsigned VCFG2:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __AD1CON2bits_t;
+extern volatile __AD1CON2bits_t AD1CON2bits __asm__ ("AD1CON2") __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CON2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CON2SET __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CON2INV __attribute__((section("sfrs")));
+#define AD1CON3 AD1CON3
+extern volatile unsigned int AD1CON3 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ADCS:8;
+ unsigned SAMC:5;
+ unsigned :2;
+ unsigned ADRC:1;
+ };
+ struct {
+ unsigned ADCS0:1;
+ unsigned ADCS1:1;
+ unsigned ADCS2:1;
+ unsigned ADCS3:1;
+ unsigned ADCS4:1;
+ unsigned ADCS5:1;
+ unsigned ADCS6:1;
+ unsigned ADCS7:1;
+ unsigned SAMC0:1;
+ unsigned SAMC1:1;
+ unsigned SAMC2:1;
+ unsigned SAMC3:1;
+ unsigned SAMC4:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __AD1CON3bits_t;
+extern volatile __AD1CON3bits_t AD1CON3bits __asm__ ("AD1CON3") __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CON3CLR __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CON3SET __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CON3INV __attribute__((section("sfrs")));
+#define AD1CHS AD1CHS
+extern volatile unsigned int AD1CHS __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :16;
+ unsigned CH0SA:5;
+ unsigned :2;
+ unsigned CH0NA:1;
+ unsigned CH0SB:5;
+ unsigned :2;
+ unsigned CH0NB:1;
+ };
+ struct {
+ unsigned :16;
+ unsigned CH0SA0:1;
+ unsigned CH0SA1:1;
+ unsigned CH0SA2:1;
+ unsigned CH0SA3:1;
+ unsigned CH0SA4:1;
+ unsigned :3;
+ unsigned CH0SB0:1;
+ unsigned CH0SB1:1;
+ unsigned CH0SB2:1;
+ unsigned CH0SB3:1;
+ unsigned CH0SB4:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __AD1CHSbits_t;
+extern volatile __AD1CHSbits_t AD1CHSbits __asm__ ("AD1CHS") __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CHSCLR __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CHSSET __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CHSINV __attribute__((section("sfrs")));
+#define AD1CSSL AD1CSSL
+extern volatile unsigned int AD1CSSL __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned CSSL:31;
+ };
+ struct {
+ unsigned CSSL0:1;
+ unsigned CSSL1:1;
+ unsigned CSSL2:1;
+ unsigned CSSL3:1;
+ unsigned CSSL4:1;
+ unsigned CSSL5:1;
+ unsigned CSSL6:1;
+ unsigned CSSL7:1;
+ unsigned CSSL8:1;
+ unsigned CSSL9:1;
+ unsigned CSSL10:1;
+ unsigned CSSL11:1;
+ unsigned CSSL12:1;
+ unsigned CSSL13:1;
+ unsigned CSSL14:1;
+ unsigned CSSL15:1;
+ unsigned CSSL16:1;
+ unsigned CSSL17:1;
+ unsigned CSSL18:1;
+ unsigned CSSL19:1;
+ unsigned CSSL20:1;
+ unsigned CSSL21:1;
+ unsigned CSSL22:1;
+ unsigned CSSL23:1;
+ unsigned CSSL24:1;
+ unsigned CSSL25:1;
+ unsigned CSSL26:1;
+ unsigned CSSL27:1;
+ unsigned CSSL28:1;
+ unsigned CSSL29:1;
+ unsigned CSSL30:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __AD1CSSLbits_t;
+extern volatile __AD1CSSLbits_t AD1CSSLbits __asm__ ("AD1CSSL") __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CSSLCLR __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CSSLSET __attribute__((section("sfrs")));
+extern volatile unsigned int AD1CSSLINV __attribute__((section("sfrs")));
+#define ADC1BUF0 ADC1BUF0
+extern volatile unsigned int ADC1BUF0 __attribute__((section("sfrs")));
+#define ADC1BUF1 ADC1BUF1
+extern volatile unsigned int ADC1BUF1 __attribute__((section("sfrs")));
+#define ADC1BUF2 ADC1BUF2
+extern volatile unsigned int ADC1BUF2 __attribute__((section("sfrs")));
+#define ADC1BUF3 ADC1BUF3
+extern volatile unsigned int ADC1BUF3 __attribute__((section("sfrs")));
+#define ADC1BUF4 ADC1BUF4
+extern volatile unsigned int ADC1BUF4 __attribute__((section("sfrs")));
+#define ADC1BUF5 ADC1BUF5
+extern volatile unsigned int ADC1BUF5 __attribute__((section("sfrs")));
+#define ADC1BUF6 ADC1BUF6
+extern volatile unsigned int ADC1BUF6 __attribute__((section("sfrs")));
+#define ADC1BUF7 ADC1BUF7
+extern volatile unsigned int ADC1BUF7 __attribute__((section("sfrs")));
+#define ADC1BUF8 ADC1BUF8
+extern volatile unsigned int ADC1BUF8 __attribute__((section("sfrs")));
+#define ADC1BUF9 ADC1BUF9
+extern volatile unsigned int ADC1BUF9 __attribute__((section("sfrs")));
+#define ADC1BUFA ADC1BUFA
+extern volatile unsigned int ADC1BUFA __attribute__((section("sfrs")));
+#define ADC1BUFB ADC1BUFB
+extern volatile unsigned int ADC1BUFB __attribute__((section("sfrs")));
+#define ADC1BUFC ADC1BUFC
+extern volatile unsigned int ADC1BUFC __attribute__((section("sfrs")));
+#define ADC1BUFD ADC1BUFD
+extern volatile unsigned int ADC1BUFD __attribute__((section("sfrs")));
+#define ADC1BUFE ADC1BUFE
+extern volatile unsigned int ADC1BUFE __attribute__((section("sfrs")));
+#define ADC1BUFF ADC1BUFF
+extern volatile unsigned int ADC1BUFF __attribute__((section("sfrs")));
+#define CVRCON CVRCON
+extern volatile unsigned int CVRCON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned CVR:4;
+ unsigned CVRSS:1;
+ unsigned CVRR:1;
+ unsigned CVROE:1;
+ unsigned :8;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned CVR0:1;
+ unsigned CVR1:1;
+ unsigned CVR2:1;
+ unsigned CVR3:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __CVRCONbits_t;
+extern volatile __CVRCONbits_t CVRCONbits __asm__ ("CVRCON") __attribute__((section("sfrs")));
+extern volatile unsigned int CVRCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int CVRCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int CVRCONINV __attribute__((section("sfrs")));
+#define CM1CON CM1CON
+extern volatile unsigned int CM1CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned CCH:2;
+ unsigned :2;
+ unsigned CREF:1;
+ unsigned :1;
+ unsigned EVPOL:2;
+ unsigned COUT:1;
+ unsigned :4;
+ unsigned CPOL:1;
+ unsigned COE:1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned CCH0:1;
+ unsigned CCH1:1;
+ unsigned :4;
+ unsigned EVPOL0:1;
+ unsigned EVPOL1:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __CM1CONbits_t;
+extern volatile __CM1CONbits_t CM1CONbits __asm__ ("CM1CON") __attribute__((section("sfrs")));
+extern volatile unsigned int CM1CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int CM1CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int CM1CONINV __attribute__((section("sfrs")));
+#define CM2CON CM2CON
+extern volatile unsigned int CM2CON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned CCH:2;
+ unsigned :2;
+ unsigned CREF:1;
+ unsigned :1;
+ unsigned EVPOL:2;
+ unsigned COUT:1;
+ unsigned :4;
+ unsigned CPOL:1;
+ unsigned COE:1;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned CCH0:1;
+ unsigned CCH1:1;
+ unsigned :4;
+ unsigned EVPOL0:1;
+ unsigned EVPOL1:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __CM2CONbits_t;
+extern volatile __CM2CONbits_t CM2CONbits __asm__ ("CM2CON") __attribute__((section("sfrs")));
+extern volatile unsigned int CM2CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int CM2CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int CM2CONINV __attribute__((section("sfrs")));
+#define CMSTAT CMSTAT
+extern volatile unsigned int CMSTAT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned C1OUT:1;
+ unsigned C2OUT:1;
+ unsigned :11;
+ unsigned SIDL:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __CMSTATbits_t;
+extern volatile __CMSTATbits_t CMSTATbits __asm__ ("CMSTAT") __attribute__((section("sfrs")));
+extern volatile unsigned int CMSTATCLR __attribute__((section("sfrs")));
+extern volatile unsigned int CMSTATSET __attribute__((section("sfrs")));
+extern volatile unsigned int CMSTATINV __attribute__((section("sfrs")));
+#define CTMUCON CTMUCON
+extern volatile unsigned int CTMUCON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned IRNG:2;
+ unsigned ITRIM:6;
+ unsigned CTTRIG:1;
+ unsigned IDISSEN:1;
+ unsigned EDGSEQEN:1;
+ unsigned EDGEN:1;
+ unsigned TGEN:1;
+ unsigned CTMUSIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ unsigned :2;
+ unsigned EDG2SEL:4;
+ unsigned EDG2POL:1;
+ unsigned EDG2MOD:1;
+ unsigned EDG1STAT:1;
+ unsigned EDG2STAT:1;
+ unsigned EDG1SEL:4;
+ unsigned EDG1POL:1;
+ unsigned EDG1MOD:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __CTMUCONbits_t;
+extern volatile __CTMUCONbits_t CTMUCONbits __asm__ ("CTMUCON") __attribute__((section("sfrs")));
+extern volatile unsigned int CTMUCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int CTMUCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int CTMUCONINV __attribute__((section("sfrs")));
+#define OSCCON OSCCON
+extern volatile unsigned int OSCCON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned OSWEN:1;
+ unsigned SOSCEN:1;
+ unsigned UFRCEN:1;
+ unsigned CF:1;
+ unsigned SLPEN:1;
+ unsigned SLOCK:1;
+ unsigned ULOCK:1;
+ unsigned CLKLOCK:1;
+ unsigned NOSC:3;
+ unsigned :1;
+ unsigned COSC:3;
+ unsigned :1;
+ unsigned PLLMULT:3;
+ unsigned PBDIV:2;
+ unsigned PBDIVRDY:1;
+ unsigned SOSCRDY:1;
+ unsigned :1;
+ unsigned FRCDIV:3;
+ unsigned PLLODIV:3;
+ };
+ struct {
+ unsigned :8;
+ unsigned NOSC0:1;
+ unsigned NOSC1:1;
+ unsigned NOSC2:1;
+ unsigned :1;
+ unsigned COSC0:1;
+ unsigned COSC1:1;
+ unsigned COSC2:1;
+ unsigned :1;
+ unsigned PLLMULT0:1;
+ unsigned PLLMULT1:1;
+ unsigned PLLMULT2:1;
+ unsigned PBDIV0:1;
+ unsigned PBDIV1:1;
+ unsigned :3;
+ unsigned FRCDIV0:1;
+ unsigned FRCDIV1:1;
+ unsigned FRCDIV2:1;
+ unsigned PLLODIV0:1;
+ unsigned PLLODIV1:1;
+ unsigned PLLODIV2:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __OSCCONbits_t;
+extern volatile __OSCCONbits_t OSCCONbits __asm__ ("OSCCON") __attribute__((section("sfrs")));
+extern volatile unsigned int OSCCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OSCCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int OSCCONINV __attribute__((section("sfrs")));
+#define OSCTUN OSCTUN
+extern volatile unsigned int OSCTUN __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned TUN:6;
+ };
+ struct {
+ unsigned TUN0:1;
+ unsigned TUN1:1;
+ unsigned TUN2:1;
+ unsigned TUN3:1;
+ unsigned TUN4:1;
+ unsigned TUN5:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __OSCTUNbits_t;
+extern volatile __OSCTUNbits_t OSCTUNbits __asm__ ("OSCTUN") __attribute__((section("sfrs")));
+extern volatile unsigned int OSCTUNCLR __attribute__((section("sfrs")));
+extern volatile un
<TRUNCATED>
[3/7] incubator-mynewt-core git commit: Removed include path,
included specific parts of the Microchip SDK, fixed some errant capitalisation
Posted by ma...@apache.org.
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2e8de777/hw/mcu/microchip/pic32mz2048efg100/include/mcu/p32mz2048efg100.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/include/mcu/p32mz2048efg100.h b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/p32mz2048efg100.h
new file mode 100644
index 0000000..a4c9a64
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/p32mz2048efg100.h
@@ -0,0 +1,51671 @@
+/*-------------------------------------------------------------------------
+ * PIC32MZ2048EFG100 processor header
+ * Build date : Feb 18 2016
+ *
+ * Copyright (c) 2016, Microchip Technology Inc. and its subsidiaries ("Microchip")
+ * All rights reserved.
+ *
+ * This software is developed by Microchip Technology Inc. and its
+ * subsidiaries ("Microchip").
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. Microchip's name may not be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#pragma once
+#ifndef __32MZ2048EFG100_H
+#define __32MZ2048EFG100_H
+
+#if defined (__LANGUAGE_C__) || defined (__LANGUAGE_C_PLUS_PLUS)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CFGCON CFGCON
+extern volatile unsigned int CFGCON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned TDOEN:1;
+ unsigned :1;
+ unsigned TROEN:1;
+ unsigned JTAGEN:1;
+ unsigned ECCCON:2;
+ unsigned :1;
+ unsigned IOANCPN:1;
+ unsigned USBSSEN:1;
+ unsigned :2;
+ unsigned PGLOCK:1;
+ unsigned PMDLOCK:1;
+ unsigned IOLOCK:1;
+ unsigned :2;
+ unsigned OCACLK:1;
+ unsigned ICACLK:1;
+ unsigned :6;
+ unsigned CPUPRI:1;
+ unsigned DMAPRI:1;
+} __CFGCONbits_t;
+extern volatile __CFGCONbits_t CFGCONbits __asm__ ("CFGCON") __attribute__((section("sfrs")));
+#define DEVID DEVID
+extern volatile unsigned int DEVID __attribute__((section("sfrs")));
+typedef struct {
+ unsigned DEVID:28;
+ unsigned VER:4;
+} __DEVIDbits_t;
+extern volatile __DEVIDbits_t DEVIDbits __asm__ ("DEVID") __attribute__((section("sfrs")));
+#define SYSKEY SYSKEY
+extern volatile unsigned int SYSKEY __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SYSKEY:32;
+} __SYSKEYbits_t;
+extern volatile __SYSKEYbits_t SYSKEYbits __asm__ ("SYSKEY") __attribute__((section("sfrs")));
+#define PMD1 PMD1
+extern volatile unsigned int PMD1 __attribute__((section("sfrs")));
+typedef struct {
+ unsigned ADCMD:1;
+ unsigned :11;
+ unsigned CVRMD:1;
+} __PMD1bits_t;
+extern volatile __PMD1bits_t PMD1bits __asm__ ("PMD1") __attribute__((section("sfrs")));
+extern volatile unsigned int PMD1CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMD1SET __attribute__((section("sfrs")));
+extern volatile unsigned int PMD1INV __attribute__((section("sfrs")));
+#define PMD2 PMD2
+extern volatile unsigned int PMD2 __attribute__((section("sfrs")));
+typedef struct {
+ unsigned CMP1MD:1;
+ unsigned CMP2MD:1;
+} __PMD2bits_t;
+extern volatile __PMD2bits_t PMD2bits __asm__ ("PMD2") __attribute__((section("sfrs")));
+extern volatile unsigned int PMD2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMD2SET __attribute__((section("sfrs")));
+extern volatile unsigned int PMD2INV __attribute__((section("sfrs")));
+#define PMD3 PMD3
+extern volatile unsigned int PMD3 __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IC1MD:1;
+ unsigned IC2MD:1;
+ unsigned IC3MD:1;
+ unsigned IC4MD:1;
+ unsigned IC5MD:1;
+ unsigned IC6MD:1;
+ unsigned IC7MD:1;
+ unsigned IC8MD:1;
+ unsigned IC9MD:1;
+ unsigned :7;
+ unsigned OC1MD:1;
+ unsigned OC2MD:1;
+ unsigned OC3MD:1;
+ unsigned OC4MD:1;
+ unsigned OC5MD:1;
+ unsigned OC6MD:1;
+ unsigned OC7MD:1;
+ unsigned OC8MD:1;
+ unsigned OC9MD:1;
+} __PMD3bits_t;
+extern volatile __PMD3bits_t PMD3bits __asm__ ("PMD3") __attribute__((section("sfrs")));
+extern volatile unsigned int PMD3CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMD3SET __attribute__((section("sfrs")));
+extern volatile unsigned int PMD3INV __attribute__((section("sfrs")));
+#define PMD4 PMD4
+extern volatile unsigned int PMD4 __attribute__((section("sfrs")));
+typedef struct {
+ unsigned T1MD:1;
+ unsigned T2MD:1;
+ unsigned T3MD:1;
+ unsigned T4MD:1;
+ unsigned T5MD:1;
+ unsigned T6MD:1;
+ unsigned T7MD:1;
+ unsigned T8MD:1;
+ unsigned T9MD:1;
+} __PMD4bits_t;
+extern volatile __PMD4bits_t PMD4bits __asm__ ("PMD4") __attribute__((section("sfrs")));
+extern volatile unsigned int PMD4CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMD4SET __attribute__((section("sfrs")));
+extern volatile unsigned int PMD4INV __attribute__((section("sfrs")));
+#define PMD5 PMD5
+extern volatile unsigned int PMD5 __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U1MD:1;
+ unsigned U2MD:1;
+ unsigned U3MD:1;
+ unsigned U4MD:1;
+ unsigned U5MD:1;
+ unsigned U6MD:1;
+ unsigned :2;
+ unsigned SPI1MD:1;
+ unsigned SPI2MD:1;
+ unsigned SPI3MD:1;
+ unsigned SPI4MD:1;
+ unsigned SPI5MD:1;
+ unsigned SPI6MD:1;
+ unsigned :2;
+ unsigned I2C1MD:1;
+ unsigned I2C2MD:1;
+ unsigned I2C3MD:1;
+ unsigned I2C4MD:1;
+ unsigned I2C5MD:1;
+ unsigned :3;
+ unsigned USBMD:1;
+} __PMD5bits_t;
+extern volatile __PMD5bits_t PMD5bits __asm__ ("PMD5") __attribute__((section("sfrs")));
+extern volatile unsigned int PMD5CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMD5SET __attribute__((section("sfrs")));
+extern volatile unsigned int PMD5INV __attribute__((section("sfrs")));
+#define PMD6 PMD6
+extern volatile unsigned int PMD6 __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RTCCMD:1;
+ unsigned :7;
+ unsigned REFO1MD:1;
+ unsigned REFO2MD:1;
+ unsigned REFO3MD:1;
+ unsigned REFO4MD:1;
+ unsigned :4;
+ unsigned PMPMD:1;
+ unsigned EBIMD:1;
+ unsigned :5;
+ unsigned SQI1MD:1;
+ unsigned :4;
+ unsigned ETHMD:1;
+} __PMD6bits_t;
+extern volatile __PMD6bits_t PMD6bits __asm__ ("PMD6") __attribute__((section("sfrs")));
+extern volatile unsigned int PMD6CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMD6SET __attribute__((section("sfrs")));
+extern volatile unsigned int PMD6INV __attribute__((section("sfrs")));
+#define PMD7 PMD7
+extern volatile unsigned int PMD7 __attribute__((section("sfrs")));
+typedef struct {
+ unsigned :4;
+ unsigned DMAMD:1;
+ unsigned :15;
+ unsigned RNGMD:1;
+} __PMD7bits_t;
+extern volatile __PMD7bits_t PMD7bits __asm__ ("PMD7") __attribute__((section("sfrs")));
+extern volatile unsigned int PMD7CLR __attribute__((section("sfrs")));
+extern volatile unsigned int PMD7SET __attribute__((section("sfrs")));
+extern volatile unsigned int PMD7INV __attribute__((section("sfrs")));
+#define CFGEBIA CFGEBIA
+extern volatile unsigned int CFGEBIA __attribute__((section("sfrs")));
+typedef struct {
+ unsigned EBIA0EN:1;
+ unsigned EBIA1EN:1;
+ unsigned EBIA2EN:1;
+ unsigned EBIA3EN:1;
+ unsigned EBIA4EN:1;
+ unsigned EBIA5EN:1;
+ unsigned EBIA6EN:1;
+ unsigned EBIA7EN:1;
+ unsigned EBIA8EN:1;
+ unsigned EBIA9EN:1;
+ unsigned EBIA10EN:1;
+ unsigned EBIA11EN:1;
+ unsigned EBIA12EN:1;
+ unsigned EBIA13EN:1;
+ unsigned EBIA14EN:1;
+ unsigned EBIA15EN:1;
+ unsigned EBIA16EN:1;
+ unsigned EBIA17EN:1;
+ unsigned EBIA18EN:1;
+ unsigned EBIA19EN:1;
+ unsigned EBIA20EN:1;
+ unsigned EBIA21EN:1;
+ unsigned EBIA22EN:1;
+ unsigned EBIA23EN:1;
+ unsigned :7;
+ unsigned EBIPINEN:1;
+} __CFGEBIAbits_t;
+extern volatile __CFGEBIAbits_t CFGEBIAbits __asm__ ("CFGEBIA") __attribute__((section("sfrs")));
+extern volatile unsigned int CFGEBIACLR __attribute__((section("sfrs")));
+extern volatile unsigned int CFGEBIASET __attribute__((section("sfrs")));
+extern volatile unsigned int CFGEBIAINV __attribute__((section("sfrs")));
+#define CFGEBIC CFGEBIC
+extern volatile unsigned int CFGEBIC __attribute__((section("sfrs")));
+typedef struct {
+ unsigned EBIDEN0:1;
+ unsigned EBIDEN1:1;
+ unsigned :2;
+ unsigned EBICSEN0:1;
+ unsigned EBICSEN1:1;
+ unsigned EBICSEN2:1;
+ unsigned EBICSEN3:1;
+ unsigned EBIBSEN0:1;
+ unsigned EBIBSEN1:1;
+ unsigned :2;
+ unsigned EBIOEEN:1;
+ unsigned EBIWEEN:1;
+ unsigned :2;
+ unsigned EBIRPEN:1;
+ unsigned EBIRDYLVL:1;
+ unsigned :7;
+ unsigned EBIRDYEN1:1;
+ unsigned EBIRDYEN2:1;
+ unsigned EBIRDYEN3:1;
+ unsigned :1;
+ unsigned EBIRDYINV1:1;
+ unsigned EBIRDYINV2:1;
+ unsigned EBIRDYINV3:1;
+} __CFGEBICbits_t;
+extern volatile __CFGEBICbits_t CFGEBICbits __asm__ ("CFGEBIC") __attribute__((section("sfrs")));
+extern volatile unsigned int CFGEBICCLR __attribute__((section("sfrs")));
+extern volatile unsigned int CFGEBICSET __attribute__((section("sfrs")));
+extern volatile unsigned int CFGEBICINV __attribute__((section("sfrs")));
+#define CFGPG CFGPG
+extern volatile unsigned int CFGPG __attribute__((section("sfrs")));
+typedef struct {
+ unsigned CPUPG:2;
+ unsigned :2;
+ unsigned DMAPG:2;
+ unsigned :2;
+ unsigned USBPG:2;
+ unsigned :6;
+ unsigned ETHPG:2;
+ unsigned :2;
+ unsigned SQI1PG:2;
+ unsigned FCPG:2;
+ unsigned :6;
+ unsigned ICD1PG:2;
+} __CFGPGbits_t;
+extern volatile __CFGPGbits_t CFGPGbits __asm__ ("CFGPG") __attribute__((section("sfrs")));
+extern volatile unsigned int CFGPGCLR __attribute__((section("sfrs")));
+extern volatile unsigned int CFGPGSET __attribute__((section("sfrs")));
+extern volatile unsigned int CFGPGINV __attribute__((section("sfrs")));
+#define NVMCON NVMCON
+extern volatile unsigned int NVMCON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned NVMOP:4;
+ unsigned :2;
+ unsigned BFSWAP:1;
+ unsigned PFSWAP:1;
+ unsigned :4;
+ unsigned LVDERR:1;
+ unsigned WRERR:1;
+ unsigned WREN:1;
+ unsigned WR:1;
+ };
+ struct {
+ unsigned NVMOP0:1;
+ unsigned NVMOP1:1;
+ unsigned NVMOP2:1;
+ unsigned NVMOP3:1;
+ unsigned :3;
+ unsigned SWAP:1;
+ };
+ struct {
+ unsigned PROGOP:4;
+ };
+ struct {
+ unsigned PROGOP0:1;
+ unsigned PROGOP1:1;
+ unsigned PROGOP2:1;
+ unsigned PROGOP3:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __NVMCONbits_t;
+extern volatile __NVMCONbits_t NVMCONbits __asm__ ("NVMCON") __attribute__((section("sfrs")));
+extern volatile unsigned int NVMCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int NVMCONINV __attribute__((section("sfrs")));
+#define NVMKEY NVMKEY
+extern volatile unsigned int NVMKEY __attribute__((section("sfrs")));
+#define NVMADDR NVMADDR
+extern volatile unsigned int NVMADDR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMADDRCLR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMADDRSET __attribute__((section("sfrs")));
+extern volatile unsigned int NVMADDRINV __attribute__((section("sfrs")));
+#define NVMDATA0 NVMDATA0
+extern volatile unsigned int NVMDATA0 __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA0CLR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA0SET __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA0INV __attribute__((section("sfrs")));
+#define NVMDATA1 NVMDATA1
+extern volatile unsigned int NVMDATA1 __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA1CLR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA1SET __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA1INV __attribute__((section("sfrs")));
+#define NVMDATA2 NVMDATA2
+extern volatile unsigned int NVMDATA2 __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA2SET __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA2INV __attribute__((section("sfrs")));
+#define NVMDATA3 NVMDATA3
+extern volatile unsigned int NVMDATA3 __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA3CLR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA3SET __attribute__((section("sfrs")));
+extern volatile unsigned int NVMDATA3INV __attribute__((section("sfrs")));
+#define NVMSRCADDR NVMSRCADDR
+extern volatile unsigned int NVMSRCADDR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMSRCADDRCLR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMSRCADDRSET __attribute__((section("sfrs")));
+extern volatile unsigned int NVMSRCADDRINV __attribute__((section("sfrs")));
+#define NVMPWP NVMPWP
+extern volatile unsigned int NVMPWP __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PWP:24;
+ unsigned :7;
+ unsigned PWPULOCK:1;
+} __NVMPWPbits_t;
+extern volatile __NVMPWPbits_t NVMPWPbits __asm__ ("NVMPWP") __attribute__((section("sfrs")));
+extern volatile unsigned int NVMPWPCLR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMPWPSET __attribute__((section("sfrs")));
+extern volatile unsigned int NVMPWPINV __attribute__((section("sfrs")));
+#define NVMBWP NVMBWP
+extern volatile unsigned int NVMBWP __attribute__((section("sfrs")));
+typedef struct {
+ unsigned UBWP0:1;
+ unsigned UBWP1:1;
+ unsigned UBWP2:1;
+ unsigned UBWP3:1;
+ unsigned UBWP4:1;
+ unsigned :2;
+ unsigned UBWPULOCK:1;
+ unsigned LBWP0:1;
+ unsigned LBWP1:1;
+ unsigned LBWP2:1;
+ unsigned LBWP3:1;
+ unsigned LBWP4:1;
+ unsigned :2;
+ unsigned LBWPULOCK:1;
+} __NVMBWPbits_t;
+extern volatile __NVMBWPbits_t NVMBWPbits __asm__ ("NVMBWP") __attribute__((section("sfrs")));
+extern volatile unsigned int NVMBWPCLR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMBWPSET __attribute__((section("sfrs")));
+extern volatile unsigned int NVMBWPINV __attribute__((section("sfrs")));
+#define NVMCON2 NVMCON2
+extern volatile unsigned int NVMCON2 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :6;
+ unsigned SWAPLOCK:2;
+ };
+ struct {
+ unsigned :8;
+ unsigned ERETRY:2;
+ unsigned :2;
+ unsigned VREAD1:1;
+ unsigned CREAD1:1;
+ unsigned :1;
+ unsigned LPRD:1;
+ unsigned LPRDWS:5;
+ unsigned :7;
+ unsigned ERSCNT:4;
+ };
+} __NVMCON2bits_t;
+extern volatile __NVMCON2bits_t NVMCON2bits __asm__ ("NVMCON2") __attribute__((section("sfrs")));
+extern volatile unsigned int NVMCON2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int NVMCON2SET __attribute__((section("sfrs")));
+extern volatile unsigned int NVMCON2INV __attribute__((section("sfrs")));
+#define WDTCON WDTCON
+extern volatile unsigned int WDTCON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned WDTWINEN:1;
+ unsigned :7;
+ unsigned RUNDIV:5;
+ unsigned :2;
+ unsigned ON:1;
+ unsigned WDTCLRKEY:16;
+} __WDTCONbits_t;
+extern volatile __WDTCONbits_t WDTCONbits __asm__ ("WDTCON") __attribute__((section("sfrs")));
+extern volatile unsigned int WDTCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int WDTCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int WDTCONINV __attribute__((section("sfrs")));
+#define DMTCON DMTCON
+extern volatile unsigned int DMTCON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned :15;
+ unsigned ON:1;
+} __DMTCONbits_t;
+extern volatile __DMTCONbits_t DMTCONbits __asm__ ("DMTCON") __attribute__((section("sfrs")));
+#define DMTPRECLR DMTPRECLR
+extern volatile unsigned int DMTPRECLR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned :8;
+ unsigned STEP1:8;
+} __DMTPRECLRbits_t;
+extern volatile __DMTPRECLRbits_t DMTPRECLRbits __asm__ ("DMTPRECLR") __attribute__((section("sfrs")));
+#define DMTCLR DMTCLR
+extern volatile unsigned int DMTCLR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned STEP2:8;
+} __DMTCLRbits_t;
+extern volatile __DMTCLRbits_t DMTCLRbits __asm__ ("DMTCLR") __attribute__((section("sfrs")));
+#define DMTSTAT DMTSTAT
+extern volatile unsigned int DMTSTAT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned WINOPN:1;
+ unsigned :4;
+ unsigned DMTEVENT:1;
+ unsigned BAD:2;
+ };
+ struct {
+ unsigned :6;
+ unsigned BAD2:1;
+ unsigned BAD1:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __DMTSTATbits_t;
+extern volatile __DMTSTATbits_t DMTSTATbits __asm__ ("DMTSTAT") __attribute__((section("sfrs")));
+#define DMTCNT DMTCNT
+extern volatile unsigned int DMTCNT __attribute__((section("sfrs")));
+typedef struct {
+ unsigned COUNTER:32;
+} __DMTCNTbits_t;
+extern volatile __DMTCNTbits_t DMTCNTbits __asm__ ("DMTCNT") __attribute__((section("sfrs")));
+#define DMTPSCNT DMTPSCNT
+extern volatile unsigned int DMTPSCNT __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PSCNT:32;
+} __DMTPSCNTbits_t;
+extern volatile __DMTPSCNTbits_t DMTPSCNTbits __asm__ ("DMTPSCNT") __attribute__((section("sfrs")));
+#define DMTPSINTV DMTPSINTV
+extern volatile unsigned int DMTPSINTV __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PSINTV:32;
+} __DMTPSINTVbits_t;
+extern volatile __DMTPSINTVbits_t DMTPSINTVbits __asm__ ("DMTPSINTV") __attribute__((section("sfrs")));
+#define RTCCON RTCCON
+extern volatile unsigned int RTCCON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned RTCOE:1;
+ unsigned HALFSEC:1;
+ unsigned RTCSYNC:1;
+ unsigned RTCWREN:1;
+ unsigned :2;
+ unsigned RTCCLKON:1;
+ unsigned RTCOUTSEL:2;
+ unsigned RTCCLKSEL:2;
+ unsigned :2;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ unsigned CAL:10;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __RTCCONbits_t;
+extern volatile __RTCCONbits_t RTCCONbits __asm__ ("RTCCON") __attribute__((section("sfrs")));
+extern volatile unsigned int RTCCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int RTCCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int RTCCONINV __attribute__((section("sfrs")));
+#define RTCALRM RTCALRM
+extern volatile unsigned int RTCALRM __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ARPT:8;
+ unsigned AMASK:4;
+ unsigned ALRMSYNC:1;
+ unsigned PIV:1;
+ unsigned CHIME:1;
+ unsigned ALRMEN:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __RTCALRMbits_t;
+extern volatile __RTCALRMbits_t RTCALRMbits __asm__ ("RTCALRM") __attribute__((section("sfrs")));
+extern volatile unsigned int RTCALRMCLR __attribute__((section("sfrs")));
+extern volatile unsigned int RTCALRMSET __attribute__((section("sfrs")));
+extern volatile unsigned int RTCALRMINV __attribute__((section("sfrs")));
+#define RTCTIME RTCTIME
+extern volatile unsigned int RTCTIME __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :8;
+ unsigned SEC01:4;
+ unsigned SEC10:4;
+ unsigned MIN01:4;
+ unsigned MIN10:4;
+ unsigned HR01:4;
+ unsigned HR10:4;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __RTCTIMEbits_t;
+extern volatile __RTCTIMEbits_t RTCTIMEbits __asm__ ("RTCTIME") __attribute__((section("sfrs")));
+extern volatile unsigned int RTCTIMECLR __attribute__((section("sfrs")));
+extern volatile unsigned int RTCTIMESET __attribute__((section("sfrs")));
+extern volatile unsigned int RTCTIMEINV __attribute__((section("sfrs")));
+#define RTCDATE RTCDATE
+extern volatile unsigned int RTCDATE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned WDAY01:4;
+ unsigned :4;
+ unsigned DAY01:4;
+ unsigned DAY10:4;
+ unsigned MONTH01:4;
+ unsigned MONTH10:4;
+ unsigned YEAR01:4;
+ unsigned YEAR10:4;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __RTCDATEbits_t;
+extern volatile __RTCDATEbits_t RTCDATEbits __asm__ ("RTCDATE") __attribute__((section("sfrs")));
+extern volatile unsigned int RTCDATECLR __attribute__((section("sfrs")));
+extern volatile unsigned int RTCDATESET __attribute__((section("sfrs")));
+extern volatile unsigned int RTCDATEINV __attribute__((section("sfrs")));
+#define ALRMTIME ALRMTIME
+extern volatile unsigned int ALRMTIME __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :8;
+ unsigned SEC01:4;
+ unsigned SEC10:4;
+ unsigned MIN01:4;
+ unsigned MIN10:4;
+ unsigned HR01:4;
+ unsigned HR10:4;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __ALRMTIMEbits_t;
+extern volatile __ALRMTIMEbits_t ALRMTIMEbits __asm__ ("ALRMTIME") __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMTIMECLR __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMTIMESET __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMTIMEINV __attribute__((section("sfrs")));
+#define ALRMDATE ALRMDATE
+extern volatile unsigned int ALRMDATE __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned WDAY01:4;
+ unsigned :4;
+ unsigned DAY01:4;
+ unsigned DAY10:4;
+ unsigned MONTH01:4;
+ unsigned MONTH10:4;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __ALRMDATEbits_t;
+extern volatile __ALRMDATEbits_t ALRMDATEbits __asm__ ("ALRMDATE") __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMDATECLR __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMDATESET __attribute__((section("sfrs")));
+extern volatile unsigned int ALRMDATEINV __attribute__((section("sfrs")));
+#define CVRCON CVRCON
+extern volatile unsigned int CVRCON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned CVR:4;
+ unsigned CVRSS:1;
+ unsigned CVRR:1;
+ unsigned CVROE:1;
+ unsigned :8;
+ unsigned ON:1;
+ };
+ struct {
+ unsigned CVR0:1;
+ unsigned CVR1:1;
+ unsigned CVR2:1;
+ unsigned CVR3:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __CVRCONbits_t;
+extern volatile __CVRCONbits_t CVRCONbits __asm__ ("CVRCON") __attribute__((section("sfrs")));
+extern volatile unsigned int CVRCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int CVRCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int CVRCONINV __attribute__((section("sfrs")));
+#define _ICDCON _ICDCON
+extern volatile unsigned int _ICDCON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned CKSWBKEN:1;
+ unsigned SLPBKEN:1;
+ unsigned WDTBKEN:1;
+ unsigned WDTEN:1;
+ unsigned RSTBUG:1;
+ unsigned DMTBKEN:1;
+ unsigned DMTEN:1;
+ unsigned :7;
+ unsigned FRZ:1;
+} ___ICDCONbits_t;
+extern volatile ___ICDCONbits_t _ICDCONbits __asm__ ("_ICDCON") __attribute__((section("sfrs")));
+#define _ICDSTAT _ICDSTAT
+extern volatile unsigned int _ICDSTAT __attribute__((section("sfrs")));
+typedef struct {
+ unsigned CKSWBF:1;
+ unsigned SLPBF:1;
+ unsigned WDTBF:1;
+ unsigned DMTBF:1;
+} ___ICDSTATbits_t;
+extern volatile ___ICDSTATbits_t _ICDSTATbits __asm__ ("_ICDSTAT") __attribute__((section("sfrs")));
+#define OSCCON OSCCON
+extern volatile unsigned int OSCCON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned OSWEN:1;
+ unsigned SOSCEN:1;
+ unsigned :1;
+ unsigned CF:1;
+ unsigned SLPEN:1;
+ unsigned :2;
+ unsigned CLKLOCK:1;
+ unsigned NOSC:3;
+ unsigned :1;
+ unsigned COSC:3;
+ unsigned :6;
+ unsigned SLP2SPD:1;
+ unsigned :1;
+ unsigned DRMEN:1;
+ unsigned FRCDIV:3;
+} __OSCCONbits_t;
+extern volatile __OSCCONbits_t OSCCONbits __asm__ ("OSCCON") __attribute__((section("sfrs")));
+extern volatile unsigned int OSCCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OSCCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int OSCCONINV __attribute__((section("sfrs")));
+#define OSCTUN OSCTUN
+extern volatile unsigned int OSCTUN __attribute__((section("sfrs")));
+typedef struct {
+ unsigned TUN:6;
+} __OSCTUNbits_t;
+extern volatile __OSCTUNbits_t OSCTUNbits __asm__ ("OSCTUN") __attribute__((section("sfrs")));
+extern volatile unsigned int OSCTUNCLR __attribute__((section("sfrs")));
+extern volatile unsigned int OSCTUNSET __attribute__((section("sfrs")));
+extern volatile unsigned int OSCTUNINV __attribute__((section("sfrs")));
+#define SPLLCON SPLLCON
+extern volatile unsigned int SPLLCON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PLLRANGE:3;
+ unsigned :4;
+ unsigned PLLICLK:1;
+ unsigned PLLIDIV:3;
+ unsigned :5;
+ unsigned PLLMULT:7;
+ unsigned :1;
+ unsigned PLLODIV:3;
+} __SPLLCONbits_t;
+extern volatile __SPLLCONbits_t SPLLCONbits __asm__ ("SPLLCON") __attribute__((section("sfrs")));
+extern volatile unsigned int SPLLCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int SPLLCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int SPLLCONINV __attribute__((section("sfrs")));
+#define RCON RCON
+extern volatile unsigned int RCON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned POR:1;
+ unsigned BOR:1;
+ unsigned IDLE:1;
+ unsigned SLEEP:1;
+ unsigned WDTO:1;
+ unsigned DMTO:1;
+ unsigned SWR:1;
+ unsigned EXTR:1;
+ unsigned :1;
+ unsigned CMR:1;
+ unsigned :16;
+ unsigned BCFGFAIL:1;
+ unsigned BCFGERR:1;
+} __RCONbits_t;
+extern volatile __RCONbits_t RCONbits __asm__ ("RCON") __attribute__((section("sfrs")));
+extern volatile unsigned int RCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int RCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int RCONINV __attribute__((section("sfrs")));
+#define RSWRST RSWRST
+extern volatile unsigned int RSWRST __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SWRST:1;
+} __RSWRSTbits_t;
+extern volatile __RSWRSTbits_t RSWRSTbits __asm__ ("RSWRST") __attribute__((section("sfrs")));
+extern volatile unsigned int RSWRSTCLR __attribute__((section("sfrs")));
+extern volatile unsigned int RSWRSTSET __attribute__((section("sfrs")));
+extern volatile unsigned int RSWRSTINV __attribute__((section("sfrs")));
+#define RNMICON RNMICON
+extern volatile unsigned int RNMICON __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned NMICNT:16;
+ unsigned WDTS:1;
+ unsigned CF:1;
+ unsigned :1;
+ unsigned GNMI:1;
+ unsigned :3;
+ unsigned SWNMI:1;
+ unsigned WDTO:1;
+ unsigned DMTO:1;
+ };
+ struct {
+ unsigned :24;
+ unsigned WDTR:1;
+ };
+} __RNMICONbits_t;
+extern volatile __RNMICONbits_t RNMICONbits __asm__ ("RNMICON") __attribute__((section("sfrs")));
+extern volatile unsigned int RNMICONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int RNMICONSET __attribute__((section("sfrs")));
+extern volatile unsigned int RNMICONINV __attribute__((section("sfrs")));
+#define PWRCON PWRCON
+extern volatile unsigned int PWRCON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned VREGS:1;
+} __PWRCONbits_t;
+extern volatile __PWRCONbits_t PWRCONbits __asm__ ("PWRCON") __attribute__((section("sfrs")));
+extern volatile unsigned int PWRCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PWRCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int PWRCONINV __attribute__((section("sfrs")));
+#define REFO1CON REFO1CON
+extern volatile unsigned int REFO1CON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned ROSEL:4;
+ unsigned :4;
+ unsigned ACTIVE:1;
+ unsigned DIVSWEN:1;
+ unsigned :1;
+ unsigned RSLP:1;
+ unsigned OE:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ unsigned RODIV:15;
+} __REFO1CONbits_t;
+extern volatile __REFO1CONbits_t REFO1CONbits __asm__ ("REFO1CON") __attribute__((section("sfrs")));
+extern volatile unsigned int REFO1CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int REFO1CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int REFO1CONINV __attribute__((section("sfrs")));
+#define REFO1TRIM REFO1TRIM
+extern volatile unsigned int REFO1TRIM __attribute__((section("sfrs")));
+typedef struct {
+ unsigned :23;
+ unsigned ROTRIM:9;
+} __REFO1TRIMbits_t;
+extern volatile __REFO1TRIMbits_t REFO1TRIMbits __asm__ ("REFO1TRIM") __attribute__((section("sfrs")));
+extern volatile unsigned int REFO1TRIMCLR __attribute__((section("sfrs")));
+extern volatile unsigned int REFO1TRIMSET __attribute__((section("sfrs")));
+extern volatile unsigned int REFO1TRIMINV __attribute__((section("sfrs")));
+#define REFO2CON REFO2CON
+extern volatile unsigned int REFO2CON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned ROSEL:4;
+ unsigned :4;
+ unsigned ACTIVE:1;
+ unsigned DIVSWEN:1;
+ unsigned :1;
+ unsigned RSLP:1;
+ unsigned OE:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ unsigned RODIV:15;
+} __REFO2CONbits_t;
+extern volatile __REFO2CONbits_t REFO2CONbits __asm__ ("REFO2CON") __attribute__((section("sfrs")));
+extern volatile unsigned int REFO2CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int REFO2CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int REFO2CONINV __attribute__((section("sfrs")));
+#define REFO2TRIM REFO2TRIM
+extern volatile unsigned int REFO2TRIM __attribute__((section("sfrs")));
+typedef struct {
+ unsigned :23;
+ unsigned ROTRIM:9;
+} __REFO2TRIMbits_t;
+extern volatile __REFO2TRIMbits_t REFO2TRIMbits __asm__ ("REFO2TRIM") __attribute__((section("sfrs")));
+extern volatile unsigned int REFO2TRIMCLR __attribute__((section("sfrs")));
+extern volatile unsigned int REFO2TRIMSET __attribute__((section("sfrs")));
+extern volatile unsigned int REFO2TRIMINV __attribute__((section("sfrs")));
+#define REFO3CON REFO3CON
+extern volatile unsigned int REFO3CON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned ROSEL:4;
+ unsigned :4;
+ unsigned ACTIVE:1;
+ unsigned DIVSWEN:1;
+ unsigned :1;
+ unsigned RSLP:1;
+ unsigned OE:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ unsigned RODIV:15;
+} __REFO3CONbits_t;
+extern volatile __REFO3CONbits_t REFO3CONbits __asm__ ("REFO3CON") __attribute__((section("sfrs")));
+extern volatile unsigned int REFO3CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int REFO3CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int REFO3CONINV __attribute__((section("sfrs")));
+#define REFO3TRIM REFO3TRIM
+extern volatile unsigned int REFO3TRIM __attribute__((section("sfrs")));
+typedef struct {
+ unsigned :23;
+ unsigned ROTRIM:9;
+} __REFO3TRIMbits_t;
+extern volatile __REFO3TRIMbits_t REFO3TRIMbits __asm__ ("REFO3TRIM") __attribute__((section("sfrs")));
+extern volatile unsigned int REFO3TRIMCLR __attribute__((section("sfrs")));
+extern volatile unsigned int REFO3TRIMSET __attribute__((section("sfrs")));
+extern volatile unsigned int REFO3TRIMINV __attribute__((section("sfrs")));
+#define REFO4CON REFO4CON
+extern volatile unsigned int REFO4CON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned ROSEL:4;
+ unsigned :4;
+ unsigned ACTIVE:1;
+ unsigned DIVSWEN:1;
+ unsigned :1;
+ unsigned RSLP:1;
+ unsigned OE:1;
+ unsigned SIDL:1;
+ unsigned :1;
+ unsigned ON:1;
+ unsigned RODIV:15;
+} __REFO4CONbits_t;
+extern volatile __REFO4CONbits_t REFO4CONbits __asm__ ("REFO4CON") __attribute__((section("sfrs")));
+extern volatile unsigned int REFO4CONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int REFO4CONSET __attribute__((section("sfrs")));
+extern volatile unsigned int REFO4CONINV __attribute__((section("sfrs")));
+#define REFO4TRIM REFO4TRIM
+extern volatile unsigned int REFO4TRIM __attribute__((section("sfrs")));
+typedef struct {
+ unsigned :23;
+ unsigned ROTRIM:9;
+} __REFO4TRIMbits_t;
+extern volatile __REFO4TRIMbits_t REFO4TRIMbits __asm__ ("REFO4TRIM") __attribute__((section("sfrs")));
+extern volatile unsigned int REFO4TRIMCLR __attribute__((section("sfrs")));
+extern volatile unsigned int REFO4TRIMSET __attribute__((section("sfrs")));
+extern volatile unsigned int REFO4TRIMINV __attribute__((section("sfrs")));
+#define PB1DIV PB1DIV
+extern volatile unsigned int PB1DIV __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PBDIV:7;
+ unsigned :4;
+ unsigned PBDIVRDY:1;
+} __PB1DIVbits_t;
+extern volatile __PB1DIVbits_t PB1DIVbits __asm__ ("PB1DIV") __attribute__((section("sfrs")));
+extern volatile unsigned int PB1DIVCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PB1DIVSET __attribute__((section("sfrs")));
+extern volatile unsigned int PB1DIVINV __attribute__((section("sfrs")));
+#define PB2DIV PB2DIV
+extern volatile unsigned int PB2DIV __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PBDIV:7;
+ unsigned :4;
+ unsigned PBDIVRDY:1;
+ unsigned :3;
+ unsigned ON:1;
+} __PB2DIVbits_t;
+extern volatile __PB2DIVbits_t PB2DIVbits __asm__ ("PB2DIV") __attribute__((section("sfrs")));
+extern volatile unsigned int PB2DIVCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PB2DIVSET __attribute__((section("sfrs")));
+extern volatile unsigned int PB2DIVINV __attribute__((section("sfrs")));
+#define PB3DIV PB3DIV
+extern volatile unsigned int PB3DIV __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PBDIV:7;
+ unsigned :4;
+ unsigned PBDIVRDY:1;
+ unsigned :3;
+ unsigned ON:1;
+} __PB3DIVbits_t;
+extern volatile __PB3DIVbits_t PB3DIVbits __asm__ ("PB3DIV") __attribute__((section("sfrs")));
+extern volatile unsigned int PB3DIVCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PB3DIVSET __attribute__((section("sfrs")));
+extern volatile unsigned int PB3DIVINV __attribute__((section("sfrs")));
+#define PB4DIV PB4DIV
+extern volatile unsigned int PB4DIV __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PBDIV:7;
+ unsigned :4;
+ unsigned PBDIVRDY:1;
+ unsigned :3;
+ unsigned ON:1;
+} __PB4DIVbits_t;
+extern volatile __PB4DIVbits_t PB4DIVbits __asm__ ("PB4DIV") __attribute__((section("sfrs")));
+extern volatile unsigned int PB4DIVCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PB4DIVSET __attribute__((section("sfrs")));
+extern volatile unsigned int PB4DIVINV __attribute__((section("sfrs")));
+#define PB5DIV PB5DIV
+extern volatile unsigned int PB5DIV __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PBDIV:7;
+ unsigned :4;
+ unsigned PBDIVRDY:1;
+ unsigned :3;
+ unsigned ON:1;
+} __PB5DIVbits_t;
+extern volatile __PB5DIVbits_t PB5DIVbits __asm__ ("PB5DIV") __attribute__((section("sfrs")));
+extern volatile unsigned int PB5DIVCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PB5DIVSET __attribute__((section("sfrs")));
+extern volatile unsigned int PB5DIVINV __attribute__((section("sfrs")));
+#define PB7DIV PB7DIV
+extern volatile unsigned int PB7DIV __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PBDIV:7;
+ unsigned :4;
+ unsigned PBDIVRDY:1;
+ unsigned :3;
+ unsigned ON:1;
+} __PB7DIVbits_t;
+extern volatile __PB7DIVbits_t PB7DIVbits __asm__ ("PB7DIV") __attribute__((section("sfrs")));
+extern volatile unsigned int PB7DIVCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PB7DIVSET __attribute__((section("sfrs")));
+extern volatile unsigned int PB7DIVINV __attribute__((section("sfrs")));
+#define PB8DIV PB8DIV
+extern volatile unsigned int PB8DIV __attribute__((section("sfrs")));
+typedef struct {
+ unsigned PBDIV:7;
+ unsigned :4;
+ unsigned PBDIVRDY:1;
+ unsigned :3;
+ unsigned ON:1;
+} __PB8DIVbits_t;
+extern volatile __PB8DIVbits_t PB8DIVbits __asm__ ("PB8DIV") __attribute__((section("sfrs")));
+extern volatile unsigned int PB8DIVCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PB8DIVSET __attribute__((section("sfrs")));
+extern volatile unsigned int PB8DIVINV __attribute__((section("sfrs")));
+#define SLEWCON SLEWCON
+extern volatile unsigned int SLEWCON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned BUSY:1;
+ unsigned DNEN:1;
+ unsigned UPEN:1;
+ unsigned :5;
+ unsigned SLWDIV:3;
+ unsigned :5;
+ unsigned SYSDIV:4;
+} __SLEWCONbits_t;
+extern volatile __SLEWCONbits_t SLEWCONbits __asm__ ("SLEWCON") __attribute__((section("sfrs")));
+extern volatile unsigned int SLEWCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int SLEWCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int SLEWCONINV __attribute__((section("sfrs")));
+#define CLKSTAT CLKSTAT
+extern volatile unsigned int CLKSTAT __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned FRCRDY:1;
+ unsigned SPDIVRDY:1;
+ unsigned POSCRDY:1;
+ unsigned :1;
+ unsigned SOSCRDY:1;
+ unsigned LPRCRDY:1;
+ };
+ struct {
+ unsigned :1;
+ unsigned DIVSPLLRDY:1;
+ };
+} __CLKSTATbits_t;
+extern volatile __CLKSTATbits_t CLKSTATbits __asm__ ("CLKSTAT") __attribute__((section("sfrs")));
+extern volatile unsigned int CLKSTATCLR __attribute__((section("sfrs")));
+extern volatile unsigned int CLKSTATSET __attribute__((section("sfrs")));
+extern volatile unsigned int CLKSTATINV __attribute__((section("sfrs")));
+#define INT1R INT1R
+extern volatile unsigned int INT1R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned INT1R:4;
+} __INT1Rbits_t;
+extern volatile __INT1Rbits_t INT1Rbits __asm__ ("INT1R") __attribute__((section("sfrs")));
+#define INT2R INT2R
+extern volatile unsigned int INT2R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned INT2R:4;
+} __INT2Rbits_t;
+extern volatile __INT2Rbits_t INT2Rbits __asm__ ("INT2R") __attribute__((section("sfrs")));
+#define INT3R INT3R
+extern volatile unsigned int INT3R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned INT3R:4;
+} __INT3Rbits_t;
+extern volatile __INT3Rbits_t INT3Rbits __asm__ ("INT3R") __attribute__((section("sfrs")));
+#define INT4R INT4R
+extern volatile unsigned int INT4R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned INT4R:4;
+} __INT4Rbits_t;
+extern volatile __INT4Rbits_t INT4Rbits __asm__ ("INT4R") __attribute__((section("sfrs")));
+#define T2CKR T2CKR
+extern volatile unsigned int T2CKR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned T2CKR:4;
+} __T2CKRbits_t;
+extern volatile __T2CKRbits_t T2CKRbits __asm__ ("T2CKR") __attribute__((section("sfrs")));
+#define T3CKR T3CKR
+extern volatile unsigned int T3CKR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned T3CKR:4;
+} __T3CKRbits_t;
+extern volatile __T3CKRbits_t T3CKRbits __asm__ ("T3CKR") __attribute__((section("sfrs")));
+#define T4CKR T4CKR
+extern volatile unsigned int T4CKR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned T4CKR:4;
+} __T4CKRbits_t;
+extern volatile __T4CKRbits_t T4CKRbits __asm__ ("T4CKR") __attribute__((section("sfrs")));
+#define T5CKR T5CKR
+extern volatile unsigned int T5CKR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned T5CKR:4;
+} __T5CKRbits_t;
+extern volatile __T5CKRbits_t T5CKRbits __asm__ ("T5CKR") __attribute__((section("sfrs")));
+#define T6CKR T6CKR
+extern volatile unsigned int T6CKR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned T6CKR:4;
+} __T6CKRbits_t;
+extern volatile __T6CKRbits_t T6CKRbits __asm__ ("T6CKR") __attribute__((section("sfrs")));
+#define T7CKR T7CKR
+extern volatile unsigned int T7CKR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned T7CKR:4;
+} __T7CKRbits_t;
+extern volatile __T7CKRbits_t T7CKRbits __asm__ ("T7CKR") __attribute__((section("sfrs")));
+#define T8CKR T8CKR
+extern volatile unsigned int T8CKR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned T8CKR:4;
+} __T8CKRbits_t;
+extern volatile __T8CKRbits_t T8CKRbits __asm__ ("T8CKR") __attribute__((section("sfrs")));
+#define T9CKR T9CKR
+extern volatile unsigned int T9CKR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned T9CKR:4;
+} __T9CKRbits_t;
+extern volatile __T9CKRbits_t T9CKRbits __asm__ ("T9CKR") __attribute__((section("sfrs")));
+#define IC1R IC1R
+extern volatile unsigned int IC1R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IC1R:4;
+} __IC1Rbits_t;
+extern volatile __IC1Rbits_t IC1Rbits __asm__ ("IC1R") __attribute__((section("sfrs")));
+#define IC2R IC2R
+extern volatile unsigned int IC2R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IC2R:4;
+} __IC2Rbits_t;
+extern volatile __IC2Rbits_t IC2Rbits __asm__ ("IC2R") __attribute__((section("sfrs")));
+#define IC3R IC3R
+extern volatile unsigned int IC3R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IC3R:4;
+} __IC3Rbits_t;
+extern volatile __IC3Rbits_t IC3Rbits __asm__ ("IC3R") __attribute__((section("sfrs")));
+#define IC4R IC4R
+extern volatile unsigned int IC4R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IC4R:4;
+} __IC4Rbits_t;
+extern volatile __IC4Rbits_t IC4Rbits __asm__ ("IC4R") __attribute__((section("sfrs")));
+#define IC5R IC5R
+extern volatile unsigned int IC5R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IC5R:4;
+} __IC5Rbits_t;
+extern volatile __IC5Rbits_t IC5Rbits __asm__ ("IC5R") __attribute__((section("sfrs")));
+#define IC6R IC6R
+extern volatile unsigned int IC6R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IC6R:4;
+} __IC6Rbits_t;
+extern volatile __IC6Rbits_t IC6Rbits __asm__ ("IC6R") __attribute__((section("sfrs")));
+#define IC7R IC7R
+extern volatile unsigned int IC7R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IC7R:4;
+} __IC7Rbits_t;
+extern volatile __IC7Rbits_t IC7Rbits __asm__ ("IC7R") __attribute__((section("sfrs")));
+#define IC8R IC8R
+extern volatile unsigned int IC8R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IC8R:4;
+} __IC8Rbits_t;
+extern volatile __IC8Rbits_t IC8Rbits __asm__ ("IC8R") __attribute__((section("sfrs")));
+#define IC9R IC9R
+extern volatile unsigned int IC9R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IC9R:4;
+} __IC9Rbits_t;
+extern volatile __IC9Rbits_t IC9Rbits __asm__ ("IC9R") __attribute__((section("sfrs")));
+#define OCFAR OCFAR
+extern volatile unsigned int OCFAR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned OCFAR:4;
+} __OCFARbits_t;
+extern volatile __OCFARbits_t OCFARbits __asm__ ("OCFAR") __attribute__((section("sfrs")));
+#define U1RXR U1RXR
+extern volatile unsigned int U1RXR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U1RXR:4;
+} __U1RXRbits_t;
+extern volatile __U1RXRbits_t U1RXRbits __asm__ ("U1RXR") __attribute__((section("sfrs")));
+#define U1CTSR U1CTSR
+extern volatile unsigned int U1CTSR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U1CTSR:4;
+} __U1CTSRbits_t;
+extern volatile __U1CTSRbits_t U1CTSRbits __asm__ ("U1CTSR") __attribute__((section("sfrs")));
+#define U2RXR U2RXR
+extern volatile unsigned int U2RXR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U2RXR:4;
+} __U2RXRbits_t;
+extern volatile __U2RXRbits_t U2RXRbits __asm__ ("U2RXR") __attribute__((section("sfrs")));
+#define U2CTSR U2CTSR
+extern volatile unsigned int U2CTSR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U2CTSR:4;
+} __U2CTSRbits_t;
+extern volatile __U2CTSRbits_t U2CTSRbits __asm__ ("U2CTSR") __attribute__((section("sfrs")));
+#define U3RXR U3RXR
+extern volatile unsigned int U3RXR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U3RXR:4;
+} __U3RXRbits_t;
+extern volatile __U3RXRbits_t U3RXRbits __asm__ ("U3RXR") __attribute__((section("sfrs")));
+#define U3CTSR U3CTSR
+extern volatile unsigned int U3CTSR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U3CTSR:4;
+} __U3CTSRbits_t;
+extern volatile __U3CTSRbits_t U3CTSRbits __asm__ ("U3CTSR") __attribute__((section("sfrs")));
+#define U4RXR U4RXR
+extern volatile unsigned int U4RXR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U4RXR:4;
+} __U4RXRbits_t;
+extern volatile __U4RXRbits_t U4RXRbits __asm__ ("U4RXR") __attribute__((section("sfrs")));
+#define U4CTSR U4CTSR
+extern volatile unsigned int U4CTSR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U4CTSR:4;
+} __U4CTSRbits_t;
+extern volatile __U4CTSRbits_t U4CTSRbits __asm__ ("U4CTSR") __attribute__((section("sfrs")));
+#define U5RXR U5RXR
+extern volatile unsigned int U5RXR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U5RXR:4;
+} __U5RXRbits_t;
+extern volatile __U5RXRbits_t U5RXRbits __asm__ ("U5RXR") __attribute__((section("sfrs")));
+#define U5CTSR U5CTSR
+extern volatile unsigned int U5CTSR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U5CTSR:4;
+} __U5CTSRbits_t;
+extern volatile __U5CTSRbits_t U5CTSRbits __asm__ ("U5CTSR") __attribute__((section("sfrs")));
+#define U6RXR U6RXR
+extern volatile unsigned int U6RXR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U6RXR:4;
+} __U6RXRbits_t;
+extern volatile __U6RXRbits_t U6RXRbits __asm__ ("U6RXR") __attribute__((section("sfrs")));
+#define U6CTSR U6CTSR
+extern volatile unsigned int U6CTSR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned U6CTSR:4;
+} __U6CTSRbits_t;
+extern volatile __U6CTSRbits_t U6CTSRbits __asm__ ("U6CTSR") __attribute__((section("sfrs")));
+#define SDI1R SDI1R
+extern volatile unsigned int SDI1R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SDI1R:4;
+} __SDI1Rbits_t;
+extern volatile __SDI1Rbits_t SDI1Rbits __asm__ ("SDI1R") __attribute__((section("sfrs")));
+#define SS1R SS1R
+extern volatile unsigned int SS1R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SS1R:4;
+} __SS1Rbits_t;
+extern volatile __SS1Rbits_t SS1Rbits __asm__ ("SS1R") __attribute__((section("sfrs")));
+#define SDI2R SDI2R
+extern volatile unsigned int SDI2R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SDI2R:4;
+} __SDI2Rbits_t;
+extern volatile __SDI2Rbits_t SDI2Rbits __asm__ ("SDI2R") __attribute__((section("sfrs")));
+#define SS2R SS2R
+extern volatile unsigned int SS2R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SS2R:4;
+} __SS2Rbits_t;
+extern volatile __SS2Rbits_t SS2Rbits __asm__ ("SS2R") __attribute__((section("sfrs")));
+#define SDI3R SDI3R
+extern volatile unsigned int SDI3R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SDI3R:4;
+} __SDI3Rbits_t;
+extern volatile __SDI3Rbits_t SDI3Rbits __asm__ ("SDI3R") __attribute__((section("sfrs")));
+#define SS3R SS3R
+extern volatile unsigned int SS3R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SS3R:4;
+} __SS3Rbits_t;
+extern volatile __SS3Rbits_t SS3Rbits __asm__ ("SS3R") __attribute__((section("sfrs")));
+#define SDI4R SDI4R
+extern volatile unsigned int SDI4R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SDI4R:4;
+} __SDI4Rbits_t;
+extern volatile __SDI4Rbits_t SDI4Rbits __asm__ ("SDI4R") __attribute__((section("sfrs")));
+#define SS4R SS4R
+extern volatile unsigned int SS4R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SS4R:4;
+} __SS4Rbits_t;
+extern volatile __SS4Rbits_t SS4Rbits __asm__ ("SS4R") __attribute__((section("sfrs")));
+#define SDI5R SDI5R
+extern volatile unsigned int SDI5R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SDI5R:4;
+} __SDI5Rbits_t;
+extern volatile __SDI5Rbits_t SDI5Rbits __asm__ ("SDI5R") __attribute__((section("sfrs")));
+#define SS5R SS5R
+extern volatile unsigned int SS5R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SS5R:4;
+} __SS5Rbits_t;
+extern volatile __SS5Rbits_t SS5Rbits __asm__ ("SS5R") __attribute__((section("sfrs")));
+#define SDI6R SDI6R
+extern volatile unsigned int SDI6R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SDI6R:4;
+} __SDI6Rbits_t;
+extern volatile __SDI6Rbits_t SDI6Rbits __asm__ ("SDI6R") __attribute__((section("sfrs")));
+#define SS6R SS6R
+extern volatile unsigned int SS6R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SS6R:4;
+} __SS6Rbits_t;
+extern volatile __SS6Rbits_t SS6Rbits __asm__ ("SS6R") __attribute__((section("sfrs")));
+#define REFCLKI1R REFCLKI1R
+extern volatile unsigned int REFCLKI1R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned REFCLKI1R:4;
+} __REFCLKI1Rbits_t;
+extern volatile __REFCLKI1Rbits_t REFCLKI1Rbits __asm__ ("REFCLKI1R") __attribute__((section("sfrs")));
+#define REFCLKI3R REFCLKI3R
+extern volatile unsigned int REFCLKI3R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned REFCLKI3R:4;
+} __REFCLKI3Rbits_t;
+extern volatile __REFCLKI3Rbits_t REFCLKI3Rbits __asm__ ("REFCLKI3R") __attribute__((section("sfrs")));
+#define REFCLKI4R REFCLKI4R
+extern volatile unsigned int REFCLKI4R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned REFCLKI4R:4;
+} __REFCLKI4Rbits_t;
+extern volatile __REFCLKI4Rbits_t REFCLKI4Rbits __asm__ ("REFCLKI4R") __attribute__((section("sfrs")));
+#define RPA14R RPA14R
+extern volatile unsigned int RPA14R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPA14R:4;
+} __RPA14Rbits_t;
+extern volatile __RPA14Rbits_t RPA14Rbits __asm__ ("RPA14R") __attribute__((section("sfrs")));
+#define RPA15R RPA15R
+extern volatile unsigned int RPA15R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPA15R:4;
+} __RPA15Rbits_t;
+extern volatile __RPA15Rbits_t RPA15Rbits __asm__ ("RPA15R") __attribute__((section("sfrs")));
+#define RPB0R RPB0R
+extern volatile unsigned int RPB0R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB0R:4;
+} __RPB0Rbits_t;
+extern volatile __RPB0Rbits_t RPB0Rbits __asm__ ("RPB0R") __attribute__((section("sfrs")));
+#define RPB1R RPB1R
+extern volatile unsigned int RPB1R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB1R:4;
+} __RPB1Rbits_t;
+extern volatile __RPB1Rbits_t RPB1Rbits __asm__ ("RPB1R") __attribute__((section("sfrs")));
+#define RPB2R RPB2R
+extern volatile unsigned int RPB2R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB2R:4;
+} __RPB2Rbits_t;
+extern volatile __RPB2Rbits_t RPB2Rbits __asm__ ("RPB2R") __attribute__((section("sfrs")));
+#define RPB3R RPB3R
+extern volatile unsigned int RPB3R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB3R:4;
+} __RPB3Rbits_t;
+extern volatile __RPB3Rbits_t RPB3Rbits __asm__ ("RPB3R") __attribute__((section("sfrs")));
+#define RPB5R RPB5R
+extern volatile unsigned int RPB5R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB5R:4;
+} __RPB5Rbits_t;
+extern volatile __RPB5Rbits_t RPB5Rbits __asm__ ("RPB5R") __attribute__((section("sfrs")));
+#define RPB6R RPB6R
+extern volatile unsigned int RPB6R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB6R:4;
+} __RPB6Rbits_t;
+extern volatile __RPB6Rbits_t RPB6Rbits __asm__ ("RPB6R") __attribute__((section("sfrs")));
+#define RPB7R RPB7R
+extern volatile unsigned int RPB7R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB7R:4;
+} __RPB7Rbits_t;
+extern volatile __RPB7Rbits_t RPB7Rbits __asm__ ("RPB7R") __attribute__((section("sfrs")));
+#define RPB8R RPB8R
+extern volatile unsigned int RPB8R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB8R:4;
+} __RPB8Rbits_t;
+extern volatile __RPB8Rbits_t RPB8Rbits __asm__ ("RPB8R") __attribute__((section("sfrs")));
+#define RPB9R RPB9R
+extern volatile unsigned int RPB9R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB9R:4;
+} __RPB9Rbits_t;
+extern volatile __RPB9Rbits_t RPB9Rbits __asm__ ("RPB9R") __attribute__((section("sfrs")));
+#define RPB10R RPB10R
+extern volatile unsigned int RPB10R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB10R:4;
+} __RPB10Rbits_t;
+extern volatile __RPB10Rbits_t RPB10Rbits __asm__ ("RPB10R") __attribute__((section("sfrs")));
+#define RPB14R RPB14R
+extern volatile unsigned int RPB14R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB14R:4;
+} __RPB14Rbits_t;
+extern volatile __RPB14Rbits_t RPB14Rbits __asm__ ("RPB14R") __attribute__((section("sfrs")));
+#define RPB15R RPB15R
+extern volatile unsigned int RPB15R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPB15R:4;
+} __RPB15Rbits_t;
+extern volatile __RPB15Rbits_t RPB15Rbits __asm__ ("RPB15R") __attribute__((section("sfrs")));
+#define RPC1R RPC1R
+extern volatile unsigned int RPC1R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPC1R:4;
+} __RPC1Rbits_t;
+extern volatile __RPC1Rbits_t RPC1Rbits __asm__ ("RPC1R") __attribute__((section("sfrs")));
+#define RPC2R RPC2R
+extern volatile unsigned int RPC2R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPC2R:4;
+} __RPC2Rbits_t;
+extern volatile __RPC2Rbits_t RPC2Rbits __asm__ ("RPC2R") __attribute__((section("sfrs")));
+#define RPC3R RPC3R
+extern volatile unsigned int RPC3R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPC3R:4;
+} __RPC3Rbits_t;
+extern volatile __RPC3Rbits_t RPC3Rbits __asm__ ("RPC3R") __attribute__((section("sfrs")));
+#define RPC4R RPC4R
+extern volatile unsigned int RPC4R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPC4R:4;
+} __RPC4Rbits_t;
+extern volatile __RPC4Rbits_t RPC4Rbits __asm__ ("RPC4R") __attribute__((section("sfrs")));
+#define RPC13R RPC13R
+extern volatile unsigned int RPC13R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPC13R:4;
+} __RPC13Rbits_t;
+extern volatile __RPC13Rbits_t RPC13Rbits __asm__ ("RPC13R") __attribute__((section("sfrs")));
+#define RPC14R RPC14R
+extern volatile unsigned int RPC14R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPC14R:4;
+} __RPC14Rbits_t;
+extern volatile __RPC14Rbits_t RPC14Rbits __asm__ ("RPC14R") __attribute__((section("sfrs")));
+#define RPD0R RPD0R
+extern volatile unsigned int RPD0R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD0R:4;
+} __RPD0Rbits_t;
+extern volatile __RPD0Rbits_t RPD0Rbits __asm__ ("RPD0R") __attribute__((section("sfrs")));
+#define RPD1R RPD1R
+extern volatile unsigned int RPD1R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD1R:4;
+} __RPD1Rbits_t;
+extern volatile __RPD1Rbits_t RPD1Rbits __asm__ ("RPD1R") __attribute__((section("sfrs")));
+#define RPD2R RPD2R
+extern volatile unsigned int RPD2R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD2R:4;
+} __RPD2Rbits_t;
+extern volatile __RPD2Rbits_t RPD2Rbits __asm__ ("RPD2R") __attribute__((section("sfrs")));
+#define RPD3R RPD3R
+extern volatile unsigned int RPD3R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD3R:4;
+} __RPD3Rbits_t;
+extern volatile __RPD3Rbits_t RPD3Rbits __asm__ ("RPD3R") __attribute__((section("sfrs")));
+#define RPD4R RPD4R
+extern volatile unsigned int RPD4R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD4R:4;
+} __RPD4Rbits_t;
+extern volatile __RPD4Rbits_t RPD4Rbits __asm__ ("RPD4R") __attribute__((section("sfrs")));
+#define RPD5R RPD5R
+extern volatile unsigned int RPD5R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD5R:4;
+} __RPD5Rbits_t;
+extern volatile __RPD5Rbits_t RPD5Rbits __asm__ ("RPD5R") __attribute__((section("sfrs")));
+#define RPD9R RPD9R
+extern volatile unsigned int RPD9R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD9R:4;
+} __RPD9Rbits_t;
+extern volatile __RPD9Rbits_t RPD9Rbits __asm__ ("RPD9R") __attribute__((section("sfrs")));
+#define RPD10R RPD10R
+extern volatile unsigned int RPD10R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD10R:4;
+} __RPD10Rbits_t;
+extern volatile __RPD10Rbits_t RPD10Rbits __asm__ ("RPD10R") __attribute__((section("sfrs")));
+#define RPD11R RPD11R
+extern volatile unsigned int RPD11R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD11R:4;
+} __RPD11Rbits_t;
+extern volatile __RPD11Rbits_t RPD11Rbits __asm__ ("RPD11R") __attribute__((section("sfrs")));
+#define RPD12R RPD12R
+extern volatile unsigned int RPD12R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD12R:4;
+} __RPD12Rbits_t;
+extern volatile __RPD12Rbits_t RPD12Rbits __asm__ ("RPD12R") __attribute__((section("sfrs")));
+#define RPD14R RPD14R
+extern volatile unsigned int RPD14R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD14R:4;
+} __RPD14Rbits_t;
+extern volatile __RPD14Rbits_t RPD14Rbits __asm__ ("RPD14R") __attribute__((section("sfrs")));
+#define RPD15R RPD15R
+extern volatile unsigned int RPD15R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPD15R:4;
+} __RPD15Rbits_t;
+extern volatile __RPD15Rbits_t RPD15Rbits __asm__ ("RPD15R") __attribute__((section("sfrs")));
+#define RPE3R RPE3R
+extern volatile unsigned int RPE3R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPE3R:4;
+} __RPE3Rbits_t;
+extern volatile __RPE3Rbits_t RPE3Rbits __asm__ ("RPE3R") __attribute__((section("sfrs")));
+#define RPE5R RPE5R
+extern volatile unsigned int RPE5R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPE5R:4;
+} __RPE5Rbits_t;
+extern volatile __RPE5Rbits_t RPE5Rbits __asm__ ("RPE5R") __attribute__((section("sfrs")));
+#define RPE8R RPE8R
+extern volatile unsigned int RPE8R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPE8R:4;
+} __RPE8Rbits_t;
+extern volatile __RPE8Rbits_t RPE8Rbits __asm__ ("RPE8R") __attribute__((section("sfrs")));
+#define RPE9R RPE9R
+extern volatile unsigned int RPE9R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPE9R:4;
+} __RPE9Rbits_t;
+extern volatile __RPE9Rbits_t RPE9Rbits __asm__ ("RPE9R") __attribute__((section("sfrs")));
+#define RPF0R RPF0R
+extern volatile unsigned int RPF0R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPF0R:4;
+} __RPF0Rbits_t;
+extern volatile __RPF0Rbits_t RPF0Rbits __asm__ ("RPF0R") __attribute__((section("sfrs")));
+#define RPF1R RPF1R
+extern volatile unsigned int RPF1R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPF1R:4;
+} __RPF1Rbits_t;
+extern volatile __RPF1Rbits_t RPF1Rbits __asm__ ("RPF1R") __attribute__((section("sfrs")));
+#define RPF2R RPF2R
+extern volatile unsigned int RPF2R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPF2R:4;
+} __RPF2Rbits_t;
+extern volatile __RPF2Rbits_t RPF2Rbits __asm__ ("RPF2R") __attribute__((section("sfrs")));
+#define RPF3R RPF3R
+extern volatile unsigned int RPF3R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPF3R:4;
+} __RPF3Rbits_t;
+extern volatile __RPF3Rbits_t RPF3Rbits __asm__ ("RPF3R") __attribute__((section("sfrs")));
+#define RPF4R RPF4R
+extern volatile unsigned int RPF4R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPF4R:4;
+} __RPF4Rbits_t;
+extern volatile __RPF4Rbits_t RPF4Rbits __asm__ ("RPF4R") __attribute__((section("sfrs")));
+#define RPF5R RPF5R
+extern volatile unsigned int RPF5R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPF5R:4;
+} __RPF5Rbits_t;
+extern volatile __RPF5Rbits_t RPF5Rbits __asm__ ("RPF5R") __attribute__((section("sfrs")));
+#define RPF8R RPF8R
+extern volatile unsigned int RPF8R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPF8R:4;
+} __RPF8Rbits_t;
+extern volatile __RPF8Rbits_t RPF8Rbits __asm__ ("RPF8R") __attribute__((section("sfrs")));
+#define RPF12R RPF12R
+extern volatile unsigned int RPF12R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPF12R:4;
+} __RPF12Rbits_t;
+extern volatile __RPF12Rbits_t RPF12Rbits __asm__ ("RPF12R") __attribute__((section("sfrs")));
+#define RPF13R RPF13R
+extern volatile unsigned int RPF13R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPF13R:4;
+} __RPF13Rbits_t;
+extern volatile __RPF13Rbits_t RPF13Rbits __asm__ ("RPF13R") __attribute__((section("sfrs")));
+#define RPG0R RPG0R
+extern volatile unsigned int RPG0R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPG0R:4;
+} __RPG0Rbits_t;
+extern volatile __RPG0Rbits_t RPG0Rbits __asm__ ("RPG0R") __attribute__((section("sfrs")));
+#define RPG1R RPG1R
+extern volatile unsigned int RPG1R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPG1R:4;
+} __RPG1Rbits_t;
+extern volatile __RPG1Rbits_t RPG1Rbits __asm__ ("RPG1R") __attribute__((section("sfrs")));
+#define RPG6R RPG6R
+extern volatile unsigned int RPG6R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPG6R:4;
+} __RPG6Rbits_t;
+extern volatile __RPG6Rbits_t RPG6Rbits __asm__ ("RPG6R") __attribute__((section("sfrs")));
+#define RPG7R RPG7R
+extern volatile unsigned int RPG7R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPG7R:4;
+} __RPG7Rbits_t;
+extern volatile __RPG7Rbits_t RPG7Rbits __asm__ ("RPG7R") __attribute__((section("sfrs")));
+#define RPG8R RPG8R
+extern volatile unsigned int RPG8R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPG8R:4;
+} __RPG8Rbits_t;
+extern volatile __RPG8Rbits_t RPG8Rbits __asm__ ("RPG8R") __attribute__((section("sfrs")));
+#define RPG9R RPG9R
+extern volatile unsigned int RPG9R __attribute__((section("sfrs")));
+typedef struct {
+ unsigned RPG9R:4;
+} __RPG9Rbits_t;
+extern volatile __RPG9Rbits_t RPG9Rbits __asm__ ("RPG9R") __attribute__((section("sfrs")));
+#define INTCON INTCON
+extern volatile unsigned int INTCON __attribute__((section("sfrs")));
+typedef struct {
+ unsigned INT0EP:1;
+ unsigned INT1EP:1;
+ unsigned INT2EP:1;
+ unsigned INT3EP:1;
+ unsigned INT4EP:1;
+ unsigned :3;
+ unsigned TPC:3;
+ unsigned :1;
+ unsigned MVEC:1;
+ unsigned :11;
+ unsigned NMIKEY:8;
+} __INTCONbits_t;
+extern volatile __INTCONbits_t INTCONbits __asm__ ("INTCON") __attribute__((section("sfrs")));
+extern volatile unsigned int INTCONCLR __attribute__((section("sfrs")));
+extern volatile unsigned int INTCONSET __attribute__((section("sfrs")));
+extern volatile unsigned int INTCONINV __attribute__((section("sfrs")));
+#define PRISS PRISS
+extern volatile unsigned int PRISS __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SS0:1;
+ unsigned :3;
+ unsigned PRI1SS:4;
+ unsigned PRI2SS:4;
+ unsigned PRI3SS:4;
+ unsigned PRI4SS:4;
+ unsigned PRI5SS:4;
+ unsigned PRI6SS:4;
+ unsigned PRI7SS:4;
+} __PRISSbits_t;
+extern volatile __PRISSbits_t PRISSbits __asm__ ("PRISS") __attribute__((section("sfrs")));
+extern volatile unsigned int PRISSCLR __attribute__((section("sfrs")));
+extern volatile unsigned int PRISSSET __attribute__((section("sfrs")));
+extern volatile unsigned int PRISSINV __attribute__((section("sfrs")));
+#define INTSTAT INTSTAT
+extern volatile unsigned int INTSTAT __attribute__((section("sfrs")));
+typedef struct {
+ unsigned SIRQ:8;
+ unsigned SRIPL:3;
+} __INTSTATbits_t;
+extern volatile __INTSTATbits_t INTSTATbits __asm__ ("INTSTAT") __attribute__((section("sfrs")));
+extern volatile unsigned int INTSTATCLR __attribute__((section("sfrs")));
+extern volatile unsigned int INTSTATSET __attribute__((section("sfrs")));
+extern volatile unsigned int INTSTATINV __attribute__((section("sfrs")));
+#define IPTMR IPTMR
+extern volatile unsigned int IPTMR __attribute__((section("sfrs")));
+typedef struct {
+ unsigned IPTMR:32;
+} __IPTMRbits_t;
+extern volatile __IPTMRbits_t IPTMRbits __asm__ ("IPTMR") __attribute__((section("sfrs")));
+extern volatile unsigned int IPTMRCLR __attribute__((section("sfrs")));
+extern volatile unsigned int IPTMRSET __attribute__((section("sfrs")));
+extern volatile unsigned int IPTMRINV __attribute__((section("sfrs")));
+#define IFS0 IFS0
+extern volatile unsigned int IFS0 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned CTIF:1;
+ unsigned CS0IF:1;
+ unsigned CS1IF:1;
+ unsigned INT0IF:1;
+ unsigned T1IF:1;
+ unsigned IC1EIF:1;
+ unsigned IC1IF:1;
+ unsigned OC1IF:1;
+ unsigned INT1IF:1;
+ unsigned T2IF:1;
+ unsigned IC2EIF:1;
+ unsigned IC2IF:1;
+ unsigned OC2IF:1;
+ unsigned INT2IF:1;
+ unsigned T3IF:1;
+ unsigned IC3EIF:1;
+ unsigned IC3IF:1;
+ unsigned OC3IF:1;
+ unsigned INT3IF:1;
+ unsigned T4IF:1;
+ unsigned IC4EIF:1;
+ unsigned IC4IF:1;
+ unsigned OC4IF:1;
+ unsigned INT4IF:1;
+ unsigned T5IF:1;
+ unsigned IC5EIF:1;
+ unsigned IC5IF:1;
+ unsigned OC5IF:1;
+ unsigned T6IF:1;
+ unsigned IC6EIF:1;
+ unsigned IC6IF:1;
+ unsigned OC6IF:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IFS0bits_t;
+extern volatile __IFS0bits_t IFS0bits __asm__ ("IFS0") __attribute__((section("sfrs")));
+extern volatile unsigned int IFS0CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IFS0SET __attribute__((section("sfrs")));
+extern volatile unsigned int IFS0INV __attribute__((section("sfrs")));
+#define IFS1 IFS1
+extern volatile unsigned int IFS1 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned T7IF:1;
+ unsigned IC7EIF:1;
+ unsigned IC7IF:1;
+ unsigned OC7IF:1;
+ unsigned T8IF:1;
+ unsigned IC8EIF:1;
+ unsigned IC8IF:1;
+ unsigned OC8IF:1;
+ unsigned T9IF:1;
+ unsigned IC9EIF:1;
+ unsigned IC9IF:1;
+ unsigned OC9IF:1;
+ unsigned ADCIF:1;
+ unsigned ADCFIFOIF:1;
+ unsigned ADCDC1IF:1;
+ unsigned ADCDC2IF:1;
+ unsigned ADCDC3IF:1;
+ unsigned ADCDC4IF:1;
+ unsigned ADCDC5IF:1;
+ unsigned ADCDC6IF:1;
+ unsigned ADCDF1IF:1;
+ unsigned ADCDF2IF:1;
+ unsigned ADCDF3IF:1;
+ unsigned ADCDF4IF:1;
+ unsigned ADCDF5IF:1;
+ unsigned ADCDF6IF:1;
+ unsigned ADCFLTIF:1;
+ unsigned ADCD0IF:1;
+ unsigned ADCD1IF:1;
+ unsigned ADCD2IF:1;
+ unsigned ADCD3IF:1;
+ unsigned ADCD4IF:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IFS1bits_t;
+extern volatile __IFS1bits_t IFS1bits __asm__ ("IFS1") __attribute__((section("sfrs")));
+extern volatile unsigned int IFS1CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IFS1SET __attribute__((section("sfrs")));
+extern volatile unsigned int IFS1INV __attribute__((section("sfrs")));
+#define IFS2 IFS2
+extern volatile unsigned int IFS2 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ADCD5IF:1;
+ unsigned ADCD6IF:1;
+ unsigned ADCD7IF:1;
+ unsigned ADCD8IF:1;
+ unsigned ADCD9IF:1;
+ unsigned ADCD10IF:1;
+ unsigned ADCD11IF:1;
+ unsigned ADCD12IF:1;
+ unsigned ADCD13IF:1;
+ unsigned ADCD14IF:1;
+ unsigned ADCD15IF:1;
+ unsigned ADCD16IF:1;
+ unsigned ADCD17IF:1;
+ unsigned ADCD18IF:1;
+ unsigned ADCD19IF:1;
+ unsigned ADCD20IF:1;
+ unsigned ADCD21IF:1;
+ unsigned ADCD22IF:1;
+ unsigned ADCD23IF:1;
+ unsigned ADCD24IF:1;
+ unsigned ADCD25IF:1;
+ unsigned ADCD26IF:1;
+ unsigned ADCD27IF:1;
+ unsigned ADCD28IF:1;
+ unsigned ADCD29IF:1;
+ unsigned ADCD30IF:1;
+ unsigned ADCD31IF:1;
+ unsigned ADCD32IF:1;
+ unsigned ADCD33IF:1;
+ unsigned ADCD34IF:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IFS2bits_t;
+extern volatile __IFS2bits_t IFS2bits __asm__ ("IFS2") __attribute__((section("sfrs")));
+extern volatile unsigned int IFS2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IFS2SET __attribute__((section("sfrs")));
+extern volatile unsigned int IFS2INV __attribute__((section("sfrs")));
+#define IFS3 IFS3
+extern volatile unsigned int IFS3 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :6;
+ unsigned ADCD43IF:1;
+ unsigned ADCD44IF:1;
+ unsigned CPCIF:1;
+ unsigned CFDCIF:1;
+ unsigned SBIF:1;
+ unsigned :2;
+ unsigned SPI1EIF:1;
+ unsigned SPI1RXIF:1;
+ unsigned SPI1TXIF:1;
+ unsigned U1EIF:1;
+ unsigned U1RXIF:1;
+ unsigned U1TXIF:1;
+ unsigned I2C1BIF:1;
+ unsigned I2C1SIF:1;
+ unsigned I2C1MIF:1;
+ unsigned CNAIF:1;
+ unsigned CNBIF:1;
+ unsigned CNCIF:1;
+ unsigned CNDIF:1;
+ unsigned CNEIF:1;
+ unsigned CNFIF:1;
+ unsigned CNGIF:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IFS3bits_t;
+extern volatile __IFS3bits_t IFS3bits __asm__ ("IFS3") __attribute__((section("sfrs")));
+extern volatile unsigned int IFS3CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IFS3SET __attribute__((section("sfrs")));
+extern volatile unsigned int IFS3INV __attribute__((section("sfrs")));
+#define IFS4 IFS4
+extern volatile unsigned int IFS4 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned PMPIF:1;
+ unsigned PMPEIF:1;
+ unsigned CMP1IF:1;
+ unsigned CMP2IF:1;
+ unsigned USBIF:1;
+ unsigned USBDMAIF:1;
+ unsigned DMA0IF:1;
+ unsigned DMA1IF:1;
+ unsigned DMA2IF:1;
+ unsigned DMA3IF:1;
+ unsigned DMA4IF:1;
+ unsigned DMA5IF:1;
+ unsigned DMA6IF:1;
+ unsigned DMA7IF:1;
+ unsigned SPI2EIF:1;
+ unsigned SPI2RXIF:1;
+ unsigned SPI2TXIF:1;
+ unsigned U2EIF:1;
+ unsigned U2RXIF:1;
+ unsigned U2TXIF:1;
+ unsigned I2C2BIF:1;
+ unsigned I2C2SIF:1;
+ unsigned I2C2MIF:1;
+ unsigned :2;
+ unsigned ETHIF:1;
+ unsigned SPI3EIF:1;
+ unsigned SPI3RXIF:1;
+ unsigned SPI3TXIF:1;
+ unsigned U3EIF:1;
+ unsigned U3RXIF:1;
+ unsigned U3TXIF:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IFS4bits_t;
+extern volatile __IFS4bits_t IFS4bits __asm__ ("IFS4") __attribute__((section("sfrs")));
+extern volatile unsigned int IFS4CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IFS4SET __attribute__((section("sfrs")));
+extern volatile unsigned int IFS4INV __attribute__((section("sfrs")));
+#define IFS5 IFS5
+extern volatile unsigned int IFS5 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned I2C3BIF:1;
+ unsigned I2C3SIF:1;
+ unsigned I2C3MIF:1;
+ unsigned SPI4EIF:1;
+ unsigned SPI4RXIF:1;
+ unsigned SPI4TXIF:1;
+ unsigned RTCCIF:1;
+ unsigned FCEIF:1;
+ unsigned PREIF:1;
+ unsigned SQI1IF:1;
+ unsigned U4EIF:1;
+ unsigned U4RXIF:1;
+ unsigned U4TXIF:1;
+ unsigned I2C4BIF:1;
+ unsigned I2C4SIF:1;
+ unsigned I2C4MIF:1;
+ unsigned SPI5EIF:1;
+ unsigned SPI5RXIF:1;
+ unsigned SPI5TXIF:1;
+ unsigned U5EIF:1;
+ unsigned U5RXIF:1;
+ unsigned U5TXIF:1;
+ unsigned I2C5BIF:1;
+ unsigned I2C5SIF:1;
+ unsigned I2C5MIF:1;
+ unsigned SPI6IF:1;
+ unsigned SPI6RXIF:1;
+ unsigned SPI6TX:1;
+ unsigned U6EIF:1;
+ unsigned U6RXIF:1;
+ unsigned U6TXIF:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IFS5bits_t;
+extern volatile __IFS5bits_t IFS5bits __asm__ ("IFS5") __attribute__((section("sfrs")));
+extern volatile unsigned int IFS5CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IFS5SET __attribute__((section("sfrs")));
+extern volatile unsigned int IFS5INV __attribute__((section("sfrs")));
+#define IFS6 IFS6
+extern volatile unsigned int IFS6 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ADCEOSIF:1;
+ unsigned ADCARDYIF:1;
+ unsigned ADCURDYIF:1;
+ unsigned :1;
+ unsigned ADCGRPIF:1;
+ unsigned :1;
+ unsigned ADC0EIF:1;
+ unsigned ADC1EIF:1;
+ unsigned ADC2EIF:1;
+ unsigned ADC3EIF:1;
+ unsigned ADC4EIF:1;
+ unsigned :2;
+ unsigned ADC7EIF:1;
+ unsigned ADC0WIF:1;
+ unsigned ADC1WIF:1;
+ unsigned ADC2WIF:1;
+ unsigned ADC3WIF:1;
+ unsigned ADC4WIF:1;
+ unsigned :2;
+ unsigned ADC7WIF:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IFS6bits_t;
+extern volatile __IFS6bits_t IFS6bits __asm__ ("IFS6") __attribute__((section("sfrs")));
+extern volatile unsigned int IFS6CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IFS6SET __attribute__((section("sfrs")));
+extern volatile unsigned int IFS6INV __attribute__((section("sfrs")));
+#define IEC0 IEC0
+extern volatile unsigned int IEC0 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned CTIE:1;
+ unsigned CS0IE:1;
+ unsigned CS1IE:1;
+ unsigned INT0IE:1;
+ unsigned T1IE:1;
+ unsigned IC1EIE:1;
+ unsigned IC1IE:1;
+ unsigned OC1IE:1;
+ unsigned INT1IE:1;
+ unsigned T2IE:1;
+ unsigned IC2EIE:1;
+ unsigned IC2IE:1;
+ unsigned OC2IE:1;
+ unsigned INT2IE:1;
+ unsigned T3IE:1;
+ unsigned IC3EIE:1;
+ unsigned IC3IE:1;
+ unsigned OC3IE:1;
+ unsigned INT3IE:1;
+ unsigned T4IE:1;
+ unsigned IC4EIE:1;
+ unsigned IC4IE:1;
+ unsigned OC4IE:1;
+ unsigned INT4IE:1;
+ unsigned T5IE:1;
+ unsigned IC5EIE:1;
+ unsigned IC5IE:1;
+ unsigned OC5IE:1;
+ unsigned T6IE:1;
+ unsigned IC6EIE:1;
+ unsigned IC6IE:1;
+ unsigned OC6IE:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IEC0bits_t;
+extern volatile __IEC0bits_t IEC0bits __asm__ ("IEC0") __attribute__((section("sfrs")));
+extern volatile unsigned int IEC0CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IEC0SET __attribute__((section("sfrs")));
+extern volatile unsigned int IEC0INV __attribute__((section("sfrs")));
+#define IEC1 IEC1
+extern volatile unsigned int IEC1 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned T7IE:1;
+ unsigned IC7EIE:1;
+ unsigned IC7IE:1;
+ unsigned OC7IE:1;
+ unsigned T8IE:1;
+ unsigned IC8EIE:1;
+ unsigned IC8IE:1;
+ unsigned OC8IE:1;
+ unsigned T9IE:1;
+ unsigned IC9EIE:1;
+ unsigned IC9IE:1;
+ unsigned OC9IE:1;
+ unsigned ADCIE:1;
+ unsigned ADCFIFOIE:1;
+ unsigned ADCDC1IE:1;
+ unsigned ADCDC2IE:1;
+ unsigned ADCDC3IE:1;
+ unsigned ADCDC4IE:1;
+ unsigned ADCDC5IE:1;
+ unsigned ADCDC6IE:1;
+ unsigned ADCDF1IE:1;
+ unsigned ADCDF2IE:1;
+ unsigned ADCDF3IE:1;
+ unsigned ADCDF4IE:1;
+ unsigned ADCDF5IE:1;
+ unsigned ADCDF6IE:1;
+ unsigned ADCFLTIE:1;
+ unsigned ADCD0IE:1;
+ unsigned ADCD1IE:1;
+ unsigned ADCD2IE:1;
+ unsigned ADCD3IE:1;
+ unsigned ADCD4IE:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IEC1bits_t;
+extern volatile __IEC1bits_t IEC1bits __asm__ ("IEC1") __attribute__((section("sfrs")));
+extern volatile unsigned int IEC1CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IEC1SET __attribute__((section("sfrs")));
+extern volatile unsigned int IEC1INV __attribute__((section("sfrs")));
+#define IEC2 IEC2
+extern volatile unsigned int IEC2 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ADCD5IE:1;
+ unsigned ADCD6IE:1;
+ unsigned ADCD7IE:1;
+ unsigned ADCD8IE:1;
+ unsigned ADCD9IE:1;
+ unsigned ADCD10IE:1;
+ unsigned ADCD11IE:1;
+ unsigned ADCD12IE:1;
+ unsigned ADCD13IE:1;
+ unsigned ADCD14IE:1;
+ unsigned ADCD15IE:1;
+ unsigned ADCD16IE:1;
+ unsigned ADCD17IE:1;
+ unsigned ADCD18IE:1;
+ unsigned ADCD19IE:1;
+ unsigned ADCD20IE:1;
+ unsigned ADCD21IE:1;
+ unsigned ADCD22IE:1;
+ unsigned ADCD23IE:1;
+ unsigned ADCD24IE:1;
+ unsigned ADCD25IE:1;
+ unsigned ADCD26IE:1;
+ unsigned ADCD27IE:1;
+ unsigned ADCD28IE:1;
+ unsigned ADCD29IE:1;
+ unsigned ADCD30IE:1;
+ unsigned ADCD31IE:1;
+ unsigned ADCD32IE:1;
+ unsigned ADCD33IE:1;
+ unsigned ADCD34IE:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IEC2bits_t;
+extern volatile __IEC2bits_t IEC2bits __asm__ ("IEC2") __attribute__((section("sfrs")));
+extern volatile unsigned int IEC2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IEC2SET __attribute__((section("sfrs")));
+extern volatile unsigned int IEC2INV __attribute__((section("sfrs")));
+#define IEC3 IEC3
+extern volatile unsigned int IEC3 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned :6;
+ unsigned ADCD43IE:1;
+ unsigned ADCD44IE:1;
+ unsigned CPCIE:1;
+ unsigned CFDCIE:1;
+ unsigned SBIE:1;
+ unsigned :2;
+ unsigned SPI1EIE:1;
+ unsigned SPI1RXIE:1;
+ unsigned SPI1TXIE:1;
+ unsigned U1EIE:1;
+ unsigned U1RXIE:1;
+ unsigned U1TXIE:1;
+ unsigned I2C1BIE:1;
+ unsigned I2C1SIE:1;
+ unsigned I2C1MIE:1;
+ unsigned CNAIE:1;
+ unsigned CNBIE:1;
+ unsigned CNCIE:1;
+ unsigned CNDIE:1;
+ unsigned CNEIE:1;
+ unsigned CNFIE:1;
+ unsigned CNGIE:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IEC3bits_t;
+extern volatile __IEC3bits_t IEC3bits __asm__ ("IEC3") __attribute__((section("sfrs")));
+extern volatile unsigned int IEC3CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IEC3SET __attribute__((section("sfrs")));
+extern volatile unsigned int IEC3INV __attribute__((section("sfrs")));
+#define IEC4 IEC4
+extern volatile unsigned int IEC4 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned PMPIE:1;
+ unsigned PMPEIE:1;
+ unsigned CMP1IE:1;
+ unsigned CMP2IE:1;
+ unsigned USBIE:1;
+ unsigned USBDMAIE:1;
+ unsigned DMA0IE:1;
+ unsigned DMA1IE:1;
+ unsigned DMA2IE:1;
+ unsigned DMA3IE:1;
+ unsigned DMA4IE:1;
+ unsigned DMA5IE:1;
+ unsigned DMA6IE:1;
+ unsigned DMA7IE:1;
+ unsigned SPI2EIE:1;
+ unsigned SPI2RXIE:1;
+ unsigned SPI2TXIE:1;
+ unsigned U2EIE:1;
+ unsigned U2RXIE:1;
+ unsigned U2TXIE:1;
+ unsigned I2C2BIE:1;
+ unsigned I2C2SIE:1;
+ unsigned I2C2MIE:1;
+ unsigned :2;
+ unsigned ETHIE:1;
+ unsigned SPI3EIE:1;
+ unsigned SPI3RXIE:1;
+ unsigned SPI3TXIE:1;
+ unsigned U3EIE:1;
+ unsigned U3RXIE:1;
+ unsigned U3TXIE:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IEC4bits_t;
+extern volatile __IEC4bits_t IEC4bits __asm__ ("IEC4") __attribute__((section("sfrs")));
+extern volatile unsigned int IEC4CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IEC4SET __attribute__((section("sfrs")));
+extern volatile unsigned int IEC4INV __attribute__((section("sfrs")));
+#define IEC5 IEC5
+extern volatile unsigned int IEC5 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned I2C3BIE:1;
+ unsigned I2C3SIE:1;
+ unsigned I2C3MIE:1;
+ unsigned SPI4EIE:1;
+ unsigned SPI4RXIE:1;
+ unsigned SPI4TXIE:1;
+ unsigned RTCCIE:1;
+ unsigned FCEIE:1;
+ unsigned PREIE:1;
+ unsigned SQI1IE:1;
+ unsigned U4EIE:1;
+ unsigned U4RXIE:1;
+ unsigned U4TXIE:1;
+ unsigned I2C4BIE:1;
+ unsigned I2C4SIE:1;
+ unsigned I2C4MIE:1;
+ unsigned SPI5EIE:1;
+ unsigned SPI5RXIE:1;
+ unsigned SPI5TXIE:1;
+ unsigned U5EIE:1;
+ unsigned U5RXIE:1;
+ unsigned U5TXIE:1;
+ unsigned I2C5BIE:1;
+ unsigned I2C5SIE:1;
+ unsigned I2C5MIE:1;
+ unsigned SPI6IE:1;
+ unsigned SPI6RXIE:1;
+ unsigned SPI6TXIE:1;
+ unsigned U6EIE:1;
+ unsigned U6RXIE:1;
+ unsigned U6TXIE:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IEC5bits_t;
+extern volatile __IEC5bits_t IEC5bits __asm__ ("IEC5") __attribute__((section("sfrs")));
+extern volatile unsigned int IEC5CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IEC5SET __attribute__((section("sfrs")));
+extern volatile unsigned int IEC5INV __attribute__((section("sfrs")));
+#define IEC6 IEC6
+extern volatile unsigned int IEC6 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned ADCEOSIE:1;
+ unsigned ADCARDYIE:1;
+ unsigned ADCURDYIE:1;
+ unsigned :1;
+ unsigned ADCGRPIE:1;
+ unsigned :1;
+ unsigned ADC0EIE:1;
+ unsigned ADC1EIE:1;
+ unsigned ADC2EIE:1;
+ unsigned ADC3EIE:1;
+ unsigned ADC4EIE:1;
+ unsigned :2;
+ unsigned ADC7EIE:1;
+ unsigned ADC0WIE:1;
+ unsigned ADC1WIE:1;
+ unsigned ADC2WIE:1;
+ unsigned ADC3WIE:1;
+ unsigned ADC4WIE:1;
+ unsigned :2;
+ unsigned ADC7WIE:1;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IEC6bits_t;
+extern volatile __IEC6bits_t IEC6bits __asm__ ("IEC6") __attribute__((section("sfrs")));
+extern volatile unsigned int IEC6CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IEC6SET __attribute__((section("sfrs")));
+extern volatile unsigned int IEC6INV __attribute__((section("sfrs")));
+#define IPC0 IPC0
+extern volatile unsigned int IPC0 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned CTIS:2;
+ unsigned CTIP:3;
+ unsigned :3;
+ unsigned CS0IS:2;
+ unsigned CS0IP:3;
+ unsigned :3;
+ unsigned CS1IS:2;
+ unsigned CS1IP:3;
+ unsigned :3;
+ unsigned INT0IS:2;
+ unsigned INT0IP:3;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IPC0bits_t;
+extern volatile __IPC0bits_t IPC0bits __asm__ ("IPC0") __attribute__((section("sfrs")));
+extern volatile unsigned int IPC0CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IPC0SET __attribute__((section("sfrs")));
+extern volatile unsigned int IPC0INV __attribute__((section("sfrs")));
+#define IPC1 IPC1
+extern volatile unsigned int IPC1 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned T1IS:2;
+ unsigned T1IP:3;
+ unsigned :3;
+ unsigned IC1EIS:2;
+ unsigned IC1EIP:3;
+ unsigned :3;
+ unsigned IC1IS:2;
+ unsigned IC1IP:3;
+ unsigned :3;
+ unsigned OC1IS:2;
+ unsigned OC1IP:3;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IPC1bits_t;
+extern volatile __IPC1bits_t IPC1bits __asm__ ("IPC1") __attribute__((section("sfrs")));
+extern volatile unsigned int IPC1CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IPC1SET __attribute__((section("sfrs")));
+extern volatile unsigned int IPC1INV __attribute__((section("sfrs")));
+#define IPC2 IPC2
+extern volatile unsigned int IPC2 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned INT1IS:2;
+ unsigned INT1IP:3;
+ unsigned :3;
+ unsigned T2IS:2;
+ unsigned T2IP:3;
+ unsigned :3;
+ unsigned IC2EIS:2;
+ unsigned IC2EIP:3;
+ unsigned :3;
+ unsigned IC2IS:2;
+ unsigned IC2IP:3;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IPC2bits_t;
+extern volatile __IPC2bits_t IPC2bits __asm__ ("IPC2") __attribute__((section("sfrs")));
+extern volatile unsigned int IPC2CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IPC2SET __attribute__((section("sfrs")));
+extern volatile unsigned int IPC2INV __attribute__((section("sfrs")));
+#define IPC3 IPC3
+extern volatile unsigned int IPC3 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned OC2IS:2;
+ unsigned OC2IP:3;
+ unsigned :3;
+ unsigned INT2IS:2;
+ unsigned INT2IP:3;
+ unsigned :3;
+ unsigned T3IS:2;
+ unsigned T3IP:3;
+ unsigned :3;
+ unsigned IC3EIS:2;
+ unsigned IC3EIP:3;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IPC3bits_t;
+extern volatile __IPC3bits_t IPC3bits __asm__ ("IPC3") __attribute__((section("sfrs")));
+extern volatile unsigned int IPC3CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IPC3SET __attribute__((section("sfrs")));
+extern volatile unsigned int IPC3INV __attribute__((section("sfrs")));
+#define IPC4 IPC4
+extern volatile unsigned int IPC4 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned IC3IS:2;
+ unsigned IC3IP:3;
+ unsigned :3;
+ unsigned OC3IS:2;
+ unsigned OC3IP:3;
+ unsigned :3;
+ unsigned INT3IS:2;
+ unsigned INT3IP:3;
+ unsigned :3;
+ unsigned T4IS:2;
+ unsigned T4IP:3;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IPC4bits_t;
+extern volatile __IPC4bits_t IPC4bits __asm__ ("IPC4") __attribute__((section("sfrs")));
+extern volatile unsigned int IPC4CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IPC4SET __attribute__((section("sfrs")));
+extern volatile unsigned int IPC4INV __attribute__((section("sfrs")));
+#define IPC5 IPC5
+extern volatile unsigned int IPC5 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned IC4EIS:2;
+ unsigned IC4EIP:3;
+ unsigned :3;
+ unsigned IC4IS:2;
+ unsigned IC4IP:3;
+ unsigned :3;
+ unsigned OC4IS:2;
+ unsigned OC4IP:3;
+ unsigned :3;
+ unsigned INT4IS:2;
+ unsigned INT4IP:3;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IPC5bits_t;
+extern volatile __IPC5bits_t IPC5bits __asm__ ("IPC5") __attribute__((section("sfrs")));
+extern volatile unsigned int IPC5CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IPC5SET __attribute__((section("sfrs")));
+extern volatile unsigned int IPC5INV __attribute__((section("sfrs")));
+#define IPC6 IPC6
+extern volatile unsigned int IPC6 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned T5IS:2;
+ unsigned T5IP:3;
+ unsigned :3;
+ unsigned IC5EIS:2;
+ unsigned IC5EIP:3;
+ unsigned :3;
+ unsigned IC5IS:2;
+ unsigned IC5IP:3;
+ unsigned :3;
+ unsigned OC5IS:2;
+ unsigned OC5IP:3;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IPC6bits_t;
+extern volatile __IPC6bits_t IPC6bits __asm__ ("IPC6") __attribute__((section("sfrs")));
+extern volatile unsigned int IPC6CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IPC6SET __attribute__((section("sfrs")));
+extern volatile unsigned int IPC6INV __attribute__((section("sfrs")));
+#define IPC7 IPC7
+extern volatile unsigned int IPC7 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned T6IS:2;
+ unsigned T6IP:3;
+ unsigned :3;
+ unsigned IC6EIS:2;
+ unsigned IC6EIP:3;
+ unsigned :3;
+ unsigned IC6IS:2;
+ unsigned IC6IP:3;
+ unsigned :3;
+ unsigned OC6IS:2;
+ unsigned OC6IP:3;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IPC7bits_t;
+extern volatile __IPC7bits_t IPC7bits __asm__ ("IPC7") __attribute__((section("sfrs")));
+extern volatile unsigned int IPC7CLR __attribute__((section("sfrs")));
+extern volatile unsigned int IPC7SET __attribute__((section("sfrs")));
+extern volatile unsigned int IPC7INV __attribute__((section("sfrs")));
+#define IPC8 IPC8
+extern volatile unsigned int IPC8 __attribute__((section("sfrs")));
+typedef union {
+ struct {
+ unsigned T7IS:2;
+ unsigned T7IP:3;
+ unsigned :3;
+ unsigned IC7EIS:2;
+ unsigned IC7EIP:3;
+ unsigned :3;
+ unsigned IC7IS:2;
+ unsigned IC7IP:3;
+ unsigned :3;
+ unsigned OC7IS:2;
+ unsigned OC7IP:3;
+ };
+ struct {
+ unsigned w:32;
+ };
+} __IPC8bits_t;
+extern volatile __IPC8bits_t IPC8bits __asm__ ("IPC8") __attribute__((section("sfrs")));
+extern volatile unsigned int IPC8CLR __attribute__((section
<TRUNCATED>
[7/7] incubator-mynewt-core git commit: This closes #231.
Posted by ma...@apache.org.
This closes #231.
Merge branch 'pic32' of https://github.com/IMGJulian/incubator-mynewt-core
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/11981880
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/11981880
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/11981880
Branch: refs/heads/master
Commit: 1198188006d18a6b6c23e7acb36e4644e349f091
Parents: c527b86 2e8de77
Author: Marko Kiiskila <ma...@runtime.io>
Authored: Thu Apr 13 10:35:39 2017 -0700
Committer: Marko Kiiskila <ma...@runtime.io>
Committed: Thu Apr 13 10:35:39 2017 -0700
----------------------------------------------------------------------
compiler/xc32/compiler.yml | 2 +-
hw/bsp/pic32mx470_6LP_clicker/bsp.yml | 53 -
hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h | 52 -
.../include/bsp/bsp_sysid.h | 36 -
hw/bsp/pic32mx470_6LP_clicker/pkg.yml | 46 -
hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c | 27 -
hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c | 85 -
hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c | 51 -
hw/bsp/pic32mx470_6LP_clicker/syscfg.yml | 41 -
hw/bsp/pic32mx470_6lp_clicker/bsp.yml | 53 +
hw/bsp/pic32mx470_6lp_clicker/include/bsp/bsp.h | 52 +
.../include/bsp/bsp_sysid.h | 36 +
hw/bsp/pic32mx470_6lp_clicker/pkg.yml | 46 +
hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c | 27 +
hw/bsp/pic32mx470_6lp_clicker/src/os_bsp.c | 85 +
hw/bsp/pic32mx470_6lp_clicker/src/sbrk.c | 51 +
hw/bsp/pic32mx470_6lp_clicker/syscfg.yml | 41 +
hw/bsp/pic32mz2048_wi-fire/bsp.yml | 2 +-
hw/bsp/pic32mz2048_wi-fire/syscfg.yml | 2 +-
.../pic32mx470F512H/include/mcu/mips_bsp.h | 24 -
.../pic32mx470F512H/include/mcu/mips_hal.h | 39 -
.../pic32mx470F512H/include/mcu/pic32mx470.h | 25 -
hw/mcu/microchip/pic32mx470F512H/pkg.yml | 31 -
.../microchip/pic32mx470F512H/src/hal_os_tick.c | 36 -
.../microchip/pic32mx470F512H/src/hal_system.c | 35 -
hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c | 463 -
.../pic32mx470F512H/src/hal_watchdog.c | 39 -
.../microchip/pic32mx470f512h/include/mcu/mcu.h | 25 +
.../pic32mx470f512h/include/mcu/mips_bsp.h | 24 +
.../pic32mx470f512h/include/mcu/mips_hal.h | 39 +
.../pic32mx470f512h/include/mcu/p32mx470f512h.h | 17933 ++++++
.../pic32mx470f512h/include/mcu/pic32.h | 25 +
.../pic32mx470f512h/include/mcu/ppic32mx.h | 1280 +
hw/mcu/microchip/pic32mx470f512h/pkg.yml | 31 +
.../microchip/pic32mx470f512h/src/hal_os_tick.c | 36 +
.../microchip/pic32mx470f512h/src/hal_system.c | 35 +
hw/mcu/microchip/pic32mx470f512h/src/hal_uart.c | 463 +
.../pic32mx470f512h/src/hal_watchdog.c | 39 +
.../pic32mz2048efg100/include/mcu/mcu.h | 25 +
.../include/mcu/p32mz2048efg100.h | 51671 +++++++++++++++++
.../pic32mz2048efg100/include/mcu/pic32.h | 25 +
.../pic32mz2048efg100/include/mcu/pic32mz2048.h | 25 -
kernel/os/include/os/arch/pic32/os/cp0defs.h | 1215 +
kernel/os/include/os/arch/pic32/os/os_arch.h | 83 +
.../os/include/os/arch/pic32/os/os_arch_defs.h | 60 +
kernel/os/include/os/arch/pic32mx/os/os_arch.h | 84 -
kernel/os/include/os/arch/pic32mz/os/os_arch.h | 84 -
kernel/os/src/arch/mips/asm/ctx.S | 16 +-
kernel/os/src/arch/mips/os_arch_mips.c | 2 +-
kernel/os/src/arch/pic32/asm/ctx.S | 190 +
kernel/os/src/arch/pic32/os_arch_pic32.c | 221 +
kernel/os/src/arch/pic32/os_fault.c | 122 +
kernel/os/src/arch/pic32mx/asm/ctx.S | 163 -
kernel/os/src/arch/pic32mx/os_arch_pic32mx.c | 213 -
kernel/os/src/arch/pic32mx/os_fault.c | 122 -
kernel/os/src/arch/pic32mz/asm/ctx.S | 163 -
kernel/os/src/arch/pic32mz/os_arch_pic32mz.c | 213 -
kernel/os/src/arch/pic32mz/os_fault.c | 122 -
58 files changed, 73949 insertions(+), 2280 deletions(-)
----------------------------------------------------------------------