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Posted to commits@nuttx.apache.org by gn...@apache.org on 2020/03/06 00:24:42 UTC
[incubator-nuttx] branch master updated: SAMA5D27 peripheral
support - USB Host working (#444)
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 730133d SAMA5D27 peripheral support - USB Host working (#444)
730133d is described below
commit 730133d84a62b77ced3f54478ca2f470c0364c0d
Author: patacongo <sp...@yahoo.com>
AuthorDate: Thu Mar 5 18:11:32 2020 -0600
SAMA5D27 peripheral support - USB Host working (#444)
* SAMA5D27 peripheral support - USB Host working
- updated nsh defconfig with vfat for testing USB Host
- sama5d2_xult: USB Host worked.
- ported sam_bringup.c code from sama5d3-xplained
- USB 2.0 HS now working
- other perpherals may work, but haven't been tested
* update license headers to approve NuttX Apache-2.0
---
arch/arm/include/sama5/sama5d2_irq.h | 14 +-
arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h | 17 +-
arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h | 22 +-
arch/arm/src/sama5/sam_clockconfig.c | 25 +-
arch/arm/src/sama5/sam_pioirq.c | 32 +-
arch/arm/src/sama5/sama5d2x_periphclks.h | 7 +-
boards/arm/sama5/sama5d2-xult/Kconfig | 11 +
boards/arm/sama5/sama5d2-xult/README.txt | 5 +
.../sama5/sama5d2-xult/configs/netnsh/defconfig | 122 ++++
.../arm/sama5/sama5d2-xult/include/board_498mhz.h | 202 +++++++
boards/arm/sama5/sama5d2-xult/src/Makefile | 90 ++-
boards/arm/sama5/sama5d2-xult/src/sam_adc.c | 86 +++
boards/arm/sama5/sama5d2-xult/src/sam_ajoystick.c | 437 +++++++++++++++
boards/arm/sama5/sama5d2-xult/src/sam_appinit.c | 41 +-
boards/arm/sama5/sama5d2-xult/src/sam_at25.c | 128 +++++
boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c | 41 +-
boards/arm/sama5/sama5d2-xult/src/sam_boot.c | 54 +-
boards/arm/sama5/sama5d2-xult/src/sam_bringup.c | 338 ++++++++++-
boards/arm/sama5/sama5d2-xult/src/sam_buttons.c | 41 +-
boards/arm/sama5/sama5d2-xult/src/sam_can.c | 100 ++++
boards/arm/sama5/sama5d2-xult/src/sam_ethernet.c | 328 +++++++++++
boards/arm/sama5/sama5d2-xult/src/sam_hsmci.c | 329 +++++++++++
boards/arm/sama5/sama5d2-xult/src/sam_i2schar.c | 111 ++++
boards/arm/sama5/sama5d2-xult/src/sam_nandflash.c | 212 +++++++
boards/arm/sama5/sama5d2-xult/src/sam_ostest.c | 99 ++++
boards/arm/sama5/sama5d2-xult/src/sam_pwm.c | 147 +++++
boards/arm/sama5/sama5d2-xult/src/sam_sdram.c | 615 +++++++++++++++++++++
boards/arm/sama5/sama5d2-xult/src/sam_spi.c | 179 ++++++
boards/arm/sama5/sama5d2-xult/src/sam_usb.c | 527 ++++++++++++++++++
boards/arm/sama5/sama5d2-xult/src/sam_usbmsc.c | 91 +++
boards/arm/sama5/sama5d2-xult/src/sam_userleds.c | 41 +-
boards/arm/sama5/sama5d2-xult/src/sama5d2-xult.h | 375 +++++++++++--
.../sama5/sama5d3-xplained/src/sama5d3-xplained.h | 23 +-
33 files changed, 4623 insertions(+), 267 deletions(-)
diff --git a/arch/arm/include/sama5/sama5d2_irq.h b/arch/arm/include/sama5/sama5d2_irq.h
index 0776ae0..d2f750f 100644
--- a/arch/arm/include/sama5/sama5d2_irq.h
+++ b/arch/arm/include/sama5/sama5d2_irq.h
@@ -48,10 +48,10 @@
* Pre-processor Definitions
****************************************************************************************/
-/* SAMA5D3 Peripheral Identifiers */
+/* SAMA5D2 Peripheral Identifiers */
#define SAM_PID_FIQ (0) /* Advanced Interrupt Controller FIQ */
- /* 2 Reserved */
+ /* 1 Reserved */
#define SAM_PID_ARM (2) /* Performance Monitor Unit */
#define SAM_PID_PIT (3) /* Periodic Interval Timer Interrupt */
#define SAM_PID_WDT (4) /* Watchdog timer Interrupt */
@@ -69,7 +69,7 @@
#define SAM_PID_MATRIX0 (15) /* H64MX, 64-bit AHB Matrix */
#define SAM_PID_SECUMOD (16) /* Secure Module */
#define SAM_PID_HSMC (17) /* Multi-bit ECC Interrupt */
-#define SAM_PID_PIO (18) /* Parallel I/O Controller */
+#define SAM_PID_PIOA (18) /* Parallel I/O Controller */
#define SAM_PID_FLEXCOM0 (19) /* FLEXCOM 0 */
#define SAM_PID_FLEXCOM1 (20) /* FLEXCOM 1 */
@@ -131,6 +131,7 @@
#define SAM_PID_SDMMC0T (71) /* Secure Data Memory Card Controller 0 */
#define SAM_PID_SDMMC1T (72) /* Secure Data Memory Card Controller 1 */
/* 73 Reserved */
+
#define SAM_PID_SYS (74) /* System Controller Interrupt PMC, RTC, RSTC */
#define SAM_PID_ACC (75) /* Analog Comparator */
#define SAM_PID_RXLP (76) /* UART Low-Power */
@@ -159,7 +160,7 @@
#define SAM_IRQ_MATRIX0 SAM_PID_MATRIX0 /* H64MX, 64-bit AHB Matrix */
#define SAM_IRQ_SECUMOD SAM_PID_SECUMOD /* Secure Module */
#define SAM_IRQ_HSMC SAM_PID_HSMC /* Multi-bit ECC Interrupt */
-#define SAM_IRQ_PIO SAM_PID_PIO /* Parallel I/O Controller */
+#define SAM_IRQ_PIOA SAM_PID_PIOA /* Parallel I/O Controller */
#define SAM_IRQ_FLEXCOM0 SAM_PID_FLEXCOM0 /* FLEXCOM 0 */
#define SAM_IRQ_FLEXCOM1 SAM_PID_FLEXCOM1 /* FLEXCOM 1 */
@@ -204,8 +205,11 @@
#define SAM_IRQ_CLASSD SAM_PID_CLASSD /* Audio Class D Amplifier */
/* Special Function Register (no interrupt) */
+
/* Secured Advanced Interrupt Controller (no interrupt) */
+
/* Advanced Interrupt Controller (no interrupt) */
+
#define SAM_IRQ_L2CC SAM_PID_L2CC /* L2 Cache Controller */
#define SAM_IRQ_MCAN01 SAM_PID_MCAN01 /* MCAN controller 0, Interrupt 1 */
#define SAM_IRQ_MCAN11 SAM_PID_MCAN11 /* MCAN controller 1, Interrupt 1 */
@@ -220,7 +224,9 @@
#define SAM_IRQ_SYS SAM_PID_SYS /* System Controller Interrupt PMC, RTC, RSTC */
#define SAM_IRQ_ACC SAM_PID_ACC /* Analog Comparator */
#define SAM_IRQ_RXLP SAM_PID_RXLP /* UART Low-Power */
+
/* Special Function Register BackUp (no interrupt) */
+
/* Chip ID (no interrupt) */
#define SAM_IRQ_NINT (SAM_PID_RXLP + 1)
diff --git a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
index 36486f2..17052bd 100644
--- a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
+++ b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
@@ -124,7 +124,6 @@
# define SAM_SHA_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: SHA */
# define SAM_AES_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: AES */
/* 0x00030000-0xf7ffffff: Reserved */
-
#define SAM_PERIPHB_PSECTION 0xf8000000 /* 0xf8000000-0xfbffffff: Internal Peripherals B */
# define SAM_SPI0_OFFSET 0x00000000 /* 0x00000000-0x00003fff: SPI0 */
# define SAM_SSC0_OFFSET 0x00004000 /* 0x00004000-0x00007fff: SSC0 */
@@ -157,6 +156,8 @@
# define SAM_SFC_OFFSET 0x0004c000 /* 0x0004c000-0x0004ffff: SFC */
# define SAM_I2SC0_OFFSET 0x00050000 /* 0x00050000-0x00053fff: I2SC0 */
# define SAM_CAN0_OFFSET 0x00054000 /* 0x00054000-0x00057fff: CAN0 */
+# define SAM_SYSC_PSECTION 0xf8048000 /* 0xf8048000-0xf8048fff: System Controller */
+# define SAM_SYSC_PADDR 0xf8048000 /* 0xf8048000-0xf8048fff: System Controller */
#define SAM_PERIPHC_PSECTION 0xfc000000 /* 0xfc000000-0xffffffff: Internal Peripherals C */
# define SAM_SPI1_OFFSET 0x00000000 /* 0x00000000-0x00003fff: SPI1 */
@@ -193,6 +194,7 @@
* region. The implemented sizes of the EBI CS0-3 and DDRCS regions
* are not known apriori and must be specified with configuration settings.
*/
+
/* 0x00000000-0x0fffffff: Internal Memories */
#define SAM_ROM_SIZE (256*1024) /* 0x00000000-0x0003ffff: ROM */
#ifdef CONFIG_ARMV7A_L2CC_PL310
@@ -218,6 +220,7 @@
#define SAM_PERIPHA_SIZE (192*1024) /* 0xf0000000-0xf002ffff: Internal Peripherals A */
#define SAM_PERIPHB_SIZE (352*1024) /* 0xf8000000-0xf8057fff: Internal Peripherals B */
#define SAM_PERIPHC_SIZE (431*1024) /* 0xfc000000-0xfc06bfff: Internal Peripherals C */
+#define SAM_SYSC_SIZE (1*1024*1024) /* 0xf8048000-0xf8048fff: Internal Peripherals */
/* Force configured sizes that might exceed 2GB to be unsigned long */
@@ -444,11 +447,15 @@
# define SAM_PERIPHA_VSECTION 0xf0000000 /* 0xf0000000-0xf7ffffff: Internal Peripherals A */
# define SAM_PERIPHB_VSECTION 0xf8000000 /* 0xf8000000-0xfbffffff: Internal Peripherals B */
# define SAM_PERIPHC_VSECTION 0xfc000000 /* 0xfc000000-0xffffffff: Internal Peripherals C */
+# define SAM_SYSC_VSECTION 0xfff00000 /* 0xfff00000-0xffffbfff: System Controller */
+# define SAM_SYSC_VADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */
#else
#define SAM_PERIPH_VSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
# define SAM_PERIPHA_VSECTION 0xf0000000 /* 0xf0000000-0xf00fffff: Internal Peripherals A */
# define SAM_PERIPHB_VSECTION 0xf1000000 /* 0xf1000000-0xf10fffff: Internal Peripherals B */
# define SAM_PERIPHC_VSECTION 0xf2000000 /* 0xf2000000-0xf20fffff: Internal Peripherals C */
+# define SAM_SYSC_VSECTION 0xf2000000 /* 0xf2000000-0xf20fffff: System Controller */
+# define SAM_SYSC_VADDR 0xf20fc000 /* 0xf20fc000-0xf20fffff: System Controller */
#endif
#endif
@@ -521,6 +528,10 @@
#define SAM_SFRBU_VBASE (SAM_PERIPHC_VSECTION+SAM_SFRBU_OFFSET)
#define SAM_CHIPID_VBASE (SAM_PERIPHC_VSECTION+SAM_CHIPID_OFFSET)
+#define SAM_PIOA_VBASE (SAM_PERIPHA_VSECTION+SAM_PIO_OFFSET)
+#define SAM_PIOB_VBASE (SAM_PERIPHB_VSECTION+SAM_PIO_OFFSET)
+#define SAM_PIOC_VBASE (SAM_PERIPHC_VSECTION+SAM_PIO_OFFSET)
+
/* NuttX virtual base address
*
* The boot logic will create a temporarily mapping based on where NuttX is
@@ -880,8 +891,4 @@
* Public Data
************************************************************************************/
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_MEMORYMAP_H */
diff --git a/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h
index 7770a95..d4a9349 100644
--- a/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h
+++ b/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h
@@ -46,6 +46,7 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
+
/* Decimal configuration values may exceed 2Gb and, hence, overflow to negative
* values unless we force them to unsigned long:
*/
@@ -97,6 +98,7 @@
#define SAM_AXIMX_PSECTION 0x00800000 /* 0x00800000-0x008fffff: AXI Matr */
#define SAM_DAP_PSECTION 0x00900000 /* 0x00900000-0x009fffff: DAP */
/* 0x00a00000-0x0fffffff: Undefined */
+
/* SAMA5 Internal Peripheral Offsets */
#define SAM_PERIPHA_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
@@ -116,8 +118,6 @@
# define SAM_ISI_OFFSET 0x00034000 /* 0x00034000-0x00037fff: ISI */
# define SAM_SFR_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: SFR */
/* 0x0003c000-0x07ffffff: Reserved */
-
-#define SAM_PERIPHB_PSECTION 0xf8000000 /* 0xf8000000-0xffffbfff: Internal Peripherals B */
# define SAM_HSMCI1_OFFSET 0x00000000 /* 0x00000000-0x00000fff: HSMCI1 */
# define SAM_HSMCI2_OFFSET 0x00004000 /* 0x00004000-0x00007fff: HSMCI2 */
# define SAM_SPI1_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SPI1 */
@@ -136,8 +136,7 @@
# define SAM_TDES_OFFSET 0x0003c000 /* 0x0003c000-0x0003ffff: TDES */
# define SAM_TRNG_OFFSET 0x00040000 /* 0x00040000-0x00043fff: TRNG */
/* 0x00044000-0x00ffbfff: Reserved */
-#define SAM_SYSC_PSECTION 0xfff00000 /* 0xfff00000-0xffffffff: System Controller */
-#define SAM_SYSC_PADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */
+# define SAM_SYSC_PADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */
# define SAM_SYSC_OFFSET 0x00000000 /* 0x0fffc000-0x0fffffff: System Controller */
/* System Controller Peripheral Offsets. All relative to the beginning of the
@@ -146,7 +145,6 @@
#define SAM_HSMC_OFFSET 0x00000000 /* 0x00000000-0x00000fff: HSMC */
/* 0x00001000-0x000023ff: Reserved */
-#define SAM_FUSE_OFFSET 0x00002400 /* 0x00002400-0x000025ff: FUSE */
#define SAM_DMAC0_OFFSET 0x00002600 /* 0x00002600-0x000027ff: DMAC0 */
#define SAM_DMAC1_OFFSET 0x00002800 /* 0x00002800-0x000029ff: DMAC1 */
#define SAM_MPDDRC_OFFSET 0x00002a00 /* 0x00002a00-0x00002bff: MPDDRC */
@@ -163,13 +161,11 @@
#define SAM_RSTC_OFFSET 0x00003e00 /* 0x00003e00-0x00003e0f: RSTC */
#define SAM_SHDC_OFFSET 0x00003e10 /* 0x00003e10-0x00003e1f: SHDC */
/* 0x00003e20-0x00003e2f: Reserved */
-#define SAM_PITC_OFFSET 0x00003e30 /* 0x00003e30-0x00003e3f: PITC */
#define SAM_WDT_OFFSET 0x00003e40 /* 0x00003e40-0x00003e4f: WDT */
#define SAM_SCKCR_OFFSET 0x00003e50 /* 0x00003e50-0x00003e53: SCKCR */
#define SAM_BSC_OFFSET 0x00003e54 /* 0x00003e54-0x00003e5f: BSC */
#define SAM_GPBR_OFFSET 0x00003e60 /* 0x00003e60-0x00003e6f: GPBR */
/* 0x00003e70-0x00003eaf: Reserved */
-#define SAM_RTCC_OFFSET 0x00003eb0 /* 0x00003eb0-0x00003edf: RTCC */
/* 0x00003ee0-0x00003fff: Reserved */
/* Sizes of memory regions in bytes.
@@ -178,11 +174,12 @@
* region. The implemented sizes of the EBI CS0-3 and DDRCS regions
* are not known apriori and must be specified with configuration settings.
*/
+
/* 0x00000000-0x0fffffff: Internal Memories */
-#define SAM_BOOTMEM_SIZE (1*1024*1024) /* 0x00000000-0x000fffff: Boot memory */
#define SAM_ROM_SIZE (1*1024*1024) /* 0x00100000-0x001fffff: ROM */
#define SAM_NFCSRAM_SIZE (1*1024*1024) /* 0x00200000-0x002fffff: NFC SRAM */
/* 0x00300000-0x003fffff: SRAM0 and SRAM1 */
+
#define SAM_ISRAM_SIZE (64*1024 + SAM_ISRAM1_SIZE)
#define SAM_SMD_SIZE (1*1024*1024) /* 0x00400000-0x004fffff: SMD */
#define SAM_UDPHSRAM_SIZE (1*1024*1024) /* 0x00500000-0x005fffff: UDPH SRAM */
@@ -192,7 +189,6 @@
#define SAM_DAP_SIZE (1*1024*1024) /* 0x00900000-0x009fffff: DAP */
#define SAM_NFCCR_SIZE (256*1024*1024) /* 0x70000000-0x7fffffff: NFC Command Registers */
/* 0xf0000000-0xffffffff: Internal Peripherals */
-#define SAM_PERIPHA_SIZE (240*1024) /* 0xf0000000-0xf003bfff: Internal Peripherals */
#define SAM_PERIPHB_SIZE (272*1024) /* 0xf8000000-0xf8043fff: Internal Peripherals */
#define SAM_SYSC_SIZE (1*1024*1024) /* 0xfff00000-0x0ffffedf: Internal Peripherals */
@@ -374,8 +370,8 @@
#define SAM_PERIPH_VSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
# define SAM_PERIPHA_VSECTION 0xf0000000 /* 0xf0000000-0xf7ffffff: Internal Peripherals A */
# define SAM_PERIPHB_VSECTION 0xf8000000 /* 0xf8000000-0xffefffff: Internal Peripherals B */
-# define SAM_SYSC_VSECTION 0xfff00000 /* 0xfff00000-0xffffbfff: System Controller */
-# define SAM_SYSC_VADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */
+# define SAM_SYSC_VSECTION 0xf8048000 /* 0xf8048000-0xf8048fff: System Controller */
+# define SAM_SYSC_VADDR 0xf80fc000 /* 0xf8048000-0xf8048fff: System Controller */
#else
#define SAM_PERIPH_VSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */
# define SAM_PERIPHA_VSECTION 0xf0000000 /* 0xf0000000-0xf00fffff: Internal Peripherals A */
@@ -804,8 +800,4 @@
* Public Data
************************************************************************************/
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_MEMORYMAP_H */
diff --git a/arch/arm/src/sama5/sam_clockconfig.c b/arch/arm/src/sama5/sam_clockconfig.c
index 6a209d7..92b5bcb 100644
--- a/arch/arm/src/sama5/sam_clockconfig.c
+++ b/arch/arm/src/sama5/sam_clockconfig.c
@@ -72,7 +72,7 @@
#if !defined(CONFIG_SAMA5_EHCI) && !defined(CONFIG_SAMA5_OHCI) && \
!defined(CONFIG_SAMA5_UDPHS)
- /* No... ignore the board setup */
+/* No... ignore the board setup */
# undef BOARD_USE_UPLL
#endif
@@ -438,9 +438,9 @@ static inline void sam_usbclockconfig(void)
/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the
* embedded High-speed transceivers. UPLLCK is the output of the 480 MHz
- * UTMI PLL (UPLL). The source clock of the UTMI PLL is the Main OSC output:
- * Either the 12MHz internal oscillator on a 12MHz crystal. The Main OSC
- * must be 12MHz because the UPLL has a built-in 40x multiplier.
+ * UTMI PLL (UPLL). The source clock of the UTMI PLL is the Main OSC
+ * output: either the 12MHz internal oscillator or a 12MHz crystal. The
+ * Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier.
*
* For High-speed operations, the user has to perform the following:
*
@@ -500,7 +500,7 @@ static inline void sam_usbclockconfig(void)
* No idea why? Let the board.h file decide which to use.
*/
- regval |= PMC_USB_USBDIV(BOARD_UPLL_OHCI_DIV-1);
+ regval |= PMC_USB_USBDIV(BOARD_UPLL_OHCI_DIV - 1);
putreg32(regval, SAM_PMC_USB);
#else /* BOARD_USE_UPLL */
@@ -537,10 +537,10 @@ static inline void sam_usbclockconfig(void)
* Description:
* Called to initialize the SAM3/4. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
- * clocking using the settings in board.h. (After power-on reset, the SAMA5
- * is initially running on a 12MHz internal RC clock). This function also
- * performs other low-level chip initialization of the chip including master
- * clock, IRQ & watchdog configuration.
+ * clocking using the settings in board.h. (After power-on reset, the SAMA5
+ * is initially running on a 12MHz internal RC clock). This function also
+ * performs other low-level chip initialization of the chip including
+ * master clock, IRQ & watchdog configuration.
*
* Boot Sequence
*
@@ -627,8 +627,8 @@ void __ramfunc__ sam_clockconfig(void)
* frequency:
*
* - Enable the 32768 Hz oscillator if best accuracy is needed
- * - Reprogram the SMC setup, cycle, hold, mode timing registers for EBI
- * CS0, to adapt them to the new clock.
+ * - Reprogram the SMC setup, cycle, hold, mode timing registers for
+ * EBI CS0, to adapt them to the new clock.
*
* Then below:
*
@@ -638,6 +638,7 @@ void __ramfunc__ sam_clockconfig(void)
*/
/* Enable the 32768 Hz oscillator */
+
/* REVISIT! */
/* Reprogram the SMC setup, cycle, hold, mode timing registers for EBI
@@ -705,7 +706,7 @@ void __ramfunc__ sam_clockconfig(void)
#ifdef ATSAMA5D2
/* Enable clocking to the PIO module */
- sam_pio_enableclk();
+ sam_pioa_enableclk();
#endif
/* Setup USB clocking */
diff --git a/arch/arm/src/sama5/sam_pioirq.c b/arch/arm/src/sama5/sam_pioirq.c
index 9bc2888..b653db7 100644
--- a/arch/arm/src/sama5/sam_pioirq.c
+++ b/arch/arm/src/sama5/sam_pioirq.c
@@ -124,6 +124,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin)
return OK;
}
#endif
+
#ifdef CONFIG_SAMA5_PIOB_IRQ
if (irq <= SAM_IRQ_PB31)
{
@@ -132,6 +133,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin)
return OK;
}
#endif
+
#ifdef CONFIG_SAMA5_PIOC_IRQ
if (irq <= SAM_IRQ_PC31)
{
@@ -140,6 +142,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin)
return OK;
}
#endif
+
#ifdef CONFIG_SAMA5_PIOD_IRQ
if (irq <= SAM_IRQ_PD31)
{
@@ -148,6 +151,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin)
return OK;
}
#endif
+
#ifdef CONFIG_SAMA5_PIOE_IRQ
if (irq <= SAM_IRQ_PE31)
{
@@ -156,6 +160,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin)
return OK;
}
#endif
+
#ifdef CONFIG_SAMA5_PIOF_IRQ
if (irq <= SAM_IRQ_PF31)
{
@@ -183,7 +188,8 @@ static int sam_piointerrupt(uint32_t base, int irq0, void *context)
uint32_t bit;
int irq;
- pending = getreg32(base + SAM_PIO_ISR_OFFSET) & getreg32(base + SAM_PIO_IMR_OFFSET);
+ pending = getreg32(base + SAM_PIO_ISR_OFFSET) & getreg32(base +
+ SAM_PIO_IMR_OFFSET);
for (bit = 1, irq = irq0; pending != 0; bit <<= 1, irq++)
{
if ((pending & bit) != 0)
@@ -367,13 +373,13 @@ void sam_pioirqinitialize(void)
#endif
}
-/************************************************************************************
+/****************************************************************************
* Name: sam_pioirq
*
* Description:
* Configure an interrupt for the specified PIO pin.
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_pioirq(pio_pinset_t pinset)
{
@@ -423,6 +429,7 @@ void sam_pioirq(pio_pinset_t pinset)
/* Are any additional interrupt modes selected? */
+#ifdef _PIO_INT_AIM
if ((pinset & _PIO_INT_AIM) != 0)
{
/* Yes.. Enable additional interrupt mode */
@@ -444,11 +451,15 @@ void sam_pioirq(pio_pinset_t pinset)
if ((pinset & _PIO_INT_RH) != 0)
{
- putreg32(pin, base + SAM_PIO_REHLSR_OFFSET); /* High level/Rising edge */
+ /* High level/Rising edge */
+
+ putreg32(pin, base + SAM_PIO_REHLSR_OFFSET);
}
else
{
- putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */
+ /* Low level/Falling edge */
+
+ putreg32(pin, base + SAM_PIO_FELLSR_OFFSET);
}
}
else
@@ -457,6 +468,7 @@ void sam_pioirq(pio_pinset_t pinset)
putreg32(pin, base + SAM_PIO_AIMDR_OFFSET);
}
+#endif
#if defined(SAM_PIO_ISLR_OFFSET)
/* Disable writing to PIO registers */
@@ -465,13 +477,13 @@ void sam_pioirq(pio_pinset_t pinset)
#endif
}
-/************************************************************************************
+/****************************************************************************
* Name: sam_pioirqenable
*
* Description:
* Enable the interrupt for specified PIO IRQ
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_pioirqenable(int irq)
{
@@ -482,18 +494,18 @@ void sam_pioirqenable(int irq)
{
/* Clear (all) pending interrupts and enable this pin interrupt */
- //(void)getreg32(base + SAM_PIO_ISR_OFFSET);
+ (void)getreg32(base + SAM_PIO_ISR_OFFSET);
putreg32((1 << pin), base + SAM_PIO_IER_OFFSET);
}
}
-/************************************************************************************
+/****************************************************************************
* Name: sam_pioirqdisable
*
* Description:
* Disable the interrupt for specified PIO IRQ
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_pioirqdisable(int irq)
{
diff --git a/arch/arm/src/sama5/sama5d2x_periphclks.h b/arch/arm/src/sama5/sama5d2x_periphclks.h
index 2867e5d..010e160 100644
--- a/arch/arm/src/sama5/sama5d2x_periphclks.h
+++ b/arch/arm/src/sama5/sama5d2x_periphclks.h
@@ -48,6 +48,7 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
+
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
@@ -74,7 +75,7 @@
#define sam_matrix0_enableclk() sam_enableperiph0(SAM_PID_MATRIX0)
#define sam_secumod_enableclk() sam_enableperiph0(SAM_PID_SECUMOD)
#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
-#define sam_pio_enableclk() sam_enableperiph0(SAM_PID_PIO)
+#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
#define sam_flexcom0_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM2)
@@ -144,7 +145,7 @@
#define sam_matrix0_disableclk() sam_disableperiph0(SAM_PID_MATRIX0)
#define sam_secumod_disableclk() sam_disableperiph0(SAM_PID_SECUMOD)
#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
-#define sam_pio_disableclk() sam_disableperiph0(SAM_PID_PIO)
+#define sam_pio_disableclk() sam_disableperiph0(SAM_PID_PIOA)
#define sam_flexcom0_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM2)
@@ -214,7 +215,7 @@
#define sam_matrix0_isenabled() sam_isenabled0(SAM_PID_MATRIX0)
#define sam_secumod_isenabled() sam_isenabled0(SAM_PID_SECUMOD)
#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
-#define sam_pio_isenabled() sam_isenabled0(SAM_PID_PIO)
+#define sam_pio_isenabled() sam_isenabled0(SAM_PID_PIOA)
#define sam_flexcom0_isenabled() sam_isenabled0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_isenabled() sam_isenabled0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_isenabled() sam_isenabled0(SAM_PID_FLEXCOM2)
diff --git a/boards/arm/sama5/sama5d2-xult/Kconfig b/boards/arm/sama5/sama5d2-xult/Kconfig
index bb486ca..1a079e4 100644
--- a/boards/arm/sama5/sama5d2-xult/Kconfig
+++ b/boards/arm/sama5/sama5d2-xult/Kconfig
@@ -23,4 +23,15 @@ config SAMA5D2XULT_528MHZ
endchoice # CPU Frequency
+config SAMA5D2XULT_USBHOST_STACKSIZE
+ int "USB host waiter stack size"
+ default 1536 if USBHOST_HUB
+ default 1024 if !USBHOST_HUB
+ depends on USBHOST
+
+config SAMA5D2XULT_USBHOST_PRIO
+ int "USB host waiter task priority"
+ default 100
+ depends on USBHOST
+
endif # ARCH_BOARD_SAMA5D2_XULT
diff --git a/boards/arm/sama5/sama5d2-xult/README.txt b/boards/arm/sama5/sama5d2-xult/README.txt
index a171291..0b4de63 100644
--- a/boards/arm/sama5/sama5d2-xult/README.txt
+++ b/boards/arm/sama5/sama5d2-xult/README.txt
@@ -795,6 +795,11 @@ Configurations
Now for the gory details:
+ netnsh:
+
+ This is a network enabled configuration based on the NuttShell (NSH)
+ REVISIT: More to be provided.
+
nsh:
This configuration directory provide the NuttShell (NSH). This is a
diff --git a/boards/arm/sama5/sama5d2-xult/configs/netnsh/defconfig b/boards/arm/sama5/sama5d2-xult/configs/netnsh/defconfig
new file mode 100644
index 0000000..1cea24f
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/configs/netnsh/defconfig
@@ -0,0 +1,122 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_AUDIO_FORMAT_MP3 is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_SAMA5_UART0 is not set
+# CONFIG_SAMA5_UHPHS_RHPORT3 is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="sama5d2-xult"
+CONFIG_ARCH_BOARD_SAMA5D2_XULT=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP="sama5"
+CONFIG_ARCH_CHIP_ATSAMA5D27=y
+CONFIG_ARCH_CHIP_SAMA5=y
+CONFIG_ARCH_CHIP_SAMA5D2=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_IRQBUTTONS=y
+CONFIG_ARCH_LOWVECTORS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_AUDIO=y
+CONFIG_AUDIO_NUM_BUFFERS=8
+CONFIG_BOARD_LOOPSPERMSEC=65775
+CONFIG_BOOT_RUNFROMSDRAM=y
+CONFIG_BUILTIN=y
+CONFIG_CDCACM=y
+CONFIG_DEV_ZERO=y
+CONFIG_EXAMPLES_TCPBLASTER=y
+CONFIG_EXAMPLES_TCPECHO=y
+CONFIG_EXAMPLES_UDPBLASTER=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FAT_LFN=y
+CONFIG_FS_BINFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FATTIME=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_FS_TMPFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_HIDKBD_POLLUSEC=80000
+CONFIG_I2S=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_IOB_NBUFFERS=24
+CONFIG_IOB_THROTTLE=0
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NET_ARP_SEND=y
+CONFIG_NET_CDCECM=y
+CONFIG_NET_ETH_PKTSIZE=1500
+CONFIG_NET_ICMP=y
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_LOOPBACK=y
+CONFIG_NET_SENDFILE=y
+CONFIG_NET_SOCKOPTS=y
+CONFIG_NET_SOLINGER=y
+CONFIG_NET_TCP=y
+CONFIG_NET_TCPBACKLOG=y
+CONFIG_NET_TCP_DELAYED_ACK=y
+CONFIG_NET_TCP_KEEPALIVE=y
+CONFIG_NET_TCP_WRITE_BUFFERS=y
+CONFIG_NET_UDP=y
+CONFIG_NET_UDP_WRITE_BUFFERS=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAMLOG=y
+CONFIG_RAMLOG_BUFSIZE=16384
+CONFIG_RAMLOG_SYSLOG=y
+CONFIG_RAM_SIZE=268435456
+CONFIG_RAM_START=0x20000000
+CONFIG_RAM_VSTART=0x20000000
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SAMA5D2XULT_498MHZ=y
+CONFIG_SAMA5_BOOT_SDRAM=y
+CONFIG_SAMA5_DDRCS_HEAP_END=0x2fa00000
+CONFIG_SAMA5_DDRCS_RESERVE=y
+CONFIG_SAMA5_EHCI=y
+CONFIG_SAMA5_OHCI=y
+CONFIG_SAMA5_PIO_IRQ=y
+CONFIG_SAMA5_RTC=y
+CONFIG_SAMA5_TRNG=y
+CONFIG_SAMA5_UART1=y
+CONFIG_SAMA5_UDPHS=y
+CONFIG_SAMA5_UHPHS=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_HPWORKPRIORITY=192
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SERIAL_TERMIOS=y
+CONFIG_SIG_DEFAULT=y
+CONFIG_SIG_EVTHREAD=y
+CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_SYSLOG_TIMESTAMP=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
+CONFIG_SYSTEM_PING=y
+CONFIG_TTY_SIGINT=y
+CONFIG_TTY_SIGSTP=y
+CONFIG_UART1_SERIAL_CONSOLE=y
+CONFIG_UBOOT_UIMAGE=y
+CONFIG_UIMAGE_ENTRY_POINT=0x20008040
+CONFIG_UIMAGE_LOAD_ADDRESS=0x20008000
+CONFIG_USBDEV=y
+CONFIG_USBDEV_DUALSPEED=y
+CONFIG_USBHOST_CDCACM=y
+CONFIG_USBHOST_COMPOSITE=y
+CONFIG_USBHOST_HIDKBD=y
+CONFIG_USBHOST_HUB=y
+CONFIG_USBHOST_MSC=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
diff --git a/boards/arm/sama5/sama5d2-xult/include/board_498mhz.h b/boards/arm/sama5/sama5d2-xult/include/board_498mhz.h
new file mode 100644
index 0000000..010687b
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/include/board_498mhz.h
@@ -0,0 +1,202 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/include/board_498mhz.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_SAMA5_SAMA5D2_XULT_INCLUDE_BOARD_498MHZ_H
+#define __BOARDS_ARM_SAMA5_SAMA5D2_XULT_INCLUDE_BOARD_498MHZ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking *****************************************************************/
+
+/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC.
+ * These definitions will configure operational clocking.
+ *
+ * This is the configuration results in a CPU clock of 498MHz:
+ *
+ * MAINOSC: Frequency = 12MHz (crystal)
+ * PLLA: PLL Multiplier = 43+1 to generate PLLACK = 498MHz
+ * Master Clock (MCK): Source = PLLACK/1, Prescalar = 1, MDIV = 4 to generate
+ * MCK = 166MHz
+ * CPU clock = 498MHz
+ */
+
+/* Main oscillator register settings.
+ *
+ * The start up time should be should be:
+ * Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
+ */
+
+#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
+
+/* PLLA configuration.
+ *
+ * Multipler = 43+1: PLLACK = 44 * 12MHz = 498MHz
+ */
+
+#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
+#define BOARD_CKGR_PLLAR_OUT (0)
+#define BOARD_CKGR_PLLAR_MUL (43 << PMC_CKGR_PLLAR_MUL_SHIFT)
+
+/* PMC master clock register settings.
+ *
+ * Master/Processor Clock Source Selection = PLLA
+ * Master/Processor Clock Prescaler = 1
+ * PLLA Divider = 1
+ * Master Clock Division (MDIV) = 4
+ *
+ * NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3.
+ *
+ * Prescaler input = 498MHz / 1 = 498MHz
+ * Prescaler output = 498MHz / 1 = 498MHz
+ * Processor Clock (PCK) = 498MHz
+ * Master clock (MCK) = 498MHz / 4 = 132MHz
+ */
+
+#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
+#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
+#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV1
+#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV4
+
+/* ADC Configuration
+ *
+ * ADCClock = MCK / ((PRESCAL+1) * 2)
+ *
+ * Given:
+ * MCK = 132MHz
+ * ADCClock = 8MHz
+ * Then:
+ * PRESCAL = 7.25
+ *
+ * PRESCAL=7 and MCK=132MHz yields ADC clock of 8.25MHz
+ */
+
+#define BOARD_ADC_PRESCAL (7)
+#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
+
+/* Resulting frequencies */
+
+#define BOARD_MAINCK_FREQUENCY BOARD_MAINOSC_FREQUENCY
+#define BOARD_PLLA_FREQUENCY (996000000) /* PLLACK: 83 * 12Mhz / 1 */
+#define BOARD_PCK_FREQUENCY (498000000) /* CPU: PLLACK / 2 / 1 */
+#define BOARD_MCK_FREQUENCY (166000000) /* MCK: PLLACK / 1 / 1 / 3 */
+#define BOARD_ADCCLK_FREQUENCY (83000000) /* ADCCLK: MCK / ((7+1)*2) */
+
+/* Clocking to certain peripherals may be MCK/2.
+ *
+ * REVISIT: I am not sure why this is. Perhaps because of H32MXDIV?
+ */
+
+#define BOARD_PIT_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
+#define BOARD_USART_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
+#define BOARD_FLEXCOM_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
+
+#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
+ defined(CONFIG_SAMA5_UDPHS)
+
+/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
+ * High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
+ * (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
+ * the 12MHz internal RC oscillator on a an external 12MHz crystal. The
+ * Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier.
+ *
+ * For High-speed operations, the user has to perform the following:
+ *
+ * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
+ * PMC_PCER register.
+ * 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
+ * 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
+ * 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
+ * 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
+ * 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
+ * register.
+ * 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
+ * PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
+ * selected.
+ * 8) Enable OHCI clocks, UHP bit in PMC_SCER register.
+ *
+ * Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI
+ * driver is initialized.
+ */
+
+# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
+# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
+# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
+#endif
+
+/* HSMCI clocking
+ *
+ * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
+ * divided by (2*(CLKDIV) + CLOCKODD + 2).
+ *
+ * MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2)
+ *
+ * Where CLKDIV has a range of 0-255.
+ */
+
+/* MCK = 132MHz, CLKDIV = 164, MCI_SPEED = 132MHz / (2*164 + 0 + 2) = 400 KHz */
+
+#define HSMCI_INIT_CLKDIV (164 << HSMCI_MR_CLKDIV_SHIFT)
+
+/* MCK = 132MHz, CLKDIV = 2 w/CLOCKODD, MCI_SPEED = 132MHz /(2*2 + 1 + 2) = 18.9 MHz */
+
+#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD)
+
+/* MCK = 132MHz, CLKDIV = 2, MCI_SPEED = 132MHz /(2*2 + 0 + 2) = 22 MHz */
+
+#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
+#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* !__ASSEMBLY__ */
+#endif /* __BOARDS_ARM_SAMA5_SAMA5D2_XULT_INCLUDE_BOARD_498MHZ_H */
diff --git a/boards/arm/sama5/sama5d2-xult/src/Makefile b/boards/arm/sama5/sama5d2-xult/src/Makefile
index 0c20cab..045347f 100644
--- a/boards/arm/sama5/sama5d2-xult/src/Makefile
+++ b/boards/arm/sama5/sama5d2-xult/src/Makefile
@@ -1,7 +1,7 @@
############################################################################
-# boards/arm/sama5/sama5d2-xult/src/Makefile
+# boards/arm/sama5/sama5d3-xplained/src/Makefile
#
-# Copyright (C) 2015 Gregory Nutt. All rights reserved.
+# Copyright (C) 2020 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gn...@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
@@ -36,18 +36,96 @@
-include $(TOPDIR)/Make.defs
ASRCS =
-CSRCS = sam_boot.c sam_userleds.c
+CSRCS = sam_boot.c
-ifeq ($(CONFIG_LIB_BOARDCTL),y)
-CSRCS += sam_appinit.c sam_bringup.c
+ifeq ($(CONFIG_SAMA5_SPI0),y)
+CSRCS += sam_spi.c
+else
+ifeq ($(CONFIG_SAMA5_SPI1),y)
+CSRCS += sam_spi.c
+endif
+endif
+
+ifeq ($(CONFIG_SAMA5_DDRCS),y)
+CSRCS += sam_sdram.c
+endif
+
+ifeq ($(CONFIG_SAMA5_EBICS3_NAND),y)
+CSRCS += sam_nandflash.c
+endif
+
+ifeq ($(CONFIG_MTD_AT25),y)
+ifeq ($(CONFIG_SAMA5_SPI0),y)
+CSRCS += sam_at25.c
+endif
+endif
+
+ifeq ($(CONFIG_SAMA5_HSMCI0),y)
+CSRCS += sam_hsmci.c
+else
+ifeq ($(CONFIG_SAMA5_HSMCI1),y)
+CSRCS += sam_hsmci.c
+endif
+endif
+
+ifeq ($(CONFIG_SAMA5_UHPHS),y)
+CSRCS += sam_usb.c
+else
+ifeq ($(CONFIG_SAMA5_UDPHS),y)
+CSRCS += sam_usb.c
+endif
+endif
+
+ifeq ($(CONFIG_SAMA5_EMACA),y)
+CSRCS += sam_ethernet.c
else
-ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y)
+ifeq ($(CONFIG_SAMA5_GMAC),y)
+CSRCS += sam_ethernet.c
+endif
+endif
+
+ifeq ($(CONFIG_LIB_BOARDCTL),y)
+CSRCS += sam_appinit.c
CSRCS += sam_bringup.c
endif
+
+ifeq ($(CONFIG_ADC),y)
+CSRCS += sam_adc.c
+ifeq ($(CONFIG_AJOYSTICK),y)
+CSRCS += sam_ajoystick.c
+endif
+endif
+
+ifeq ($(CONFIG_PWM),y)
+CSRCS += sam_pwm.c
+endif
+
+ifeq ($(CONFIG_CAN),y)
+CSRCS += sam_can.c
+endif
+
+ifeq ($(CONFIG_AUDIO_I2SCHAR),y)
+ifeq ($(CONFIG_SAMA5_SSC0),y)
+CSRCS += sam_i2schar.c
+else
+ifeq ($(CONFIG_SAMA5_SSC1),y)
+CSRCS += sam_i2schar.c
+endif
+endif
+endif
+
+ifeq ($(CONFIG_USBMSC),y)
+CSRCS += sam_usbmsc.c
+endif
+
+ifeq ($(CONFIG_ARCH_FPU),y)
+CSRCS += sam_ostest.c
endif
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += sam_autoleds.c
+else
+CSRCS += sam_userleds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_adc.c b/boards/arm/sama5/sama5d2-xult/src/sam_adc.c
new file mode 100644
index 0000000..9264b9c
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_adc.c
@@ -0,0 +1,86 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_adc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <nuttx/analog/adc.h>
+
+#include "sam_adc.h"
+#include "sama5d2-xult.h"
+
+#ifdef CONFIG_SAMA5_ADC
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_adc_setup
+ *
+ * Description:
+ * Initialize ADC and register the ADC driver.
+ *
+ ****************************************************************************/
+
+int sam_adc_setup(void)
+{
+ static bool initialized = false;
+ struct adc_dev_s *adc;
+ int ret;
+
+ /* Check if we have already initialized */
+
+ if (!initialized)
+ {
+ /* Call stm32_adcinitialize() to get an instance of the ADC interface */
+
+ adc = sam_adc_initialize();
+ if (adc == NULL)
+ {
+ aerr("ERROR: Failed to get ADC interface\n");
+ return -ENODEV;
+ }
+
+ /* Register the ADC driver at "/dev/adc0" */
+
+ ret = adc_register("/dev/adc0", adc);
+ if (ret < 0)
+ {
+ aerr("ERROR: adc_register failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Now we are initialized */
+
+ initialized = true;
+ }
+
+ return OK;
+}
+
+#endif /* CONFIG_ADC */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_ajoystick.c b/boards/arm/sama5/sama5d2-xult/src/sam_ajoystick.c
new file mode 100644
index 0000000..78f4eee
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_ajoystick.c
@@ -0,0 +1,437 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_ajoystick.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/input/ajoystick.h>
+
+#include "sam_pio.h"
+#include "sam_adc.h"
+#include "hardware/sam_adc.h"
+#include "sama5d2-xult.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Check for pre-requisites and pin conflicts */
+
+#ifdef CONFIG_AJOYSTICK
+# if !defined(CONFIG_ADC)
+# error CONFIG_ADC is required for the Itead joystick
+# undef CONFIG_AJOYSTICK
+# elif !defined(CONFIG_SAMA5_ADC_CHAN0) || !defined(CONFIG_SAMA5_ADC_CHAN1)
+# error CONFIG_SAMA5_ADC_CHAN0 and 1 are required for Itead joystick
+# elif !defined(CONFIG_SAMA5_PIOC_IRQ)
+# error CONFIG_SAMA5_PIOC_IRQ is required for the Itead joystick
+# undef CONFIG_AJOYSTICK
+# elif defined(CONFIG_SAMA5_EMACA)
+# error EMAC conflicts with the Itead PIO usage
+# undef CONFIG_AJOYSTICK
+# elif defined(CONFIG_SAMA5_SSC0)
+# error SSC0 conflicts with the Itead PIO usage
+# undef CONFIG_AJOYSTICK
+# elif defined(CONFIG_SAMA5_SPI1)
+# warning SPI1 may conflict with the Itead PIO usage
+# elif defined(CONFIG_SAMA5_ISI)
+# warning ISI may conflict with the Itead PIO usage
+# endif
+#endif /* CONFIG_AJOYSTICK */
+
+#ifdef CONFIG_AJOYSTICK
+
+/* Number of Joystick buttons */
+
+#define AJOY_NGPIOS 7
+
+/* Bitset of supported Joystick buttons */
+
+#define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \
+ AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \
+ AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \
+ AJOY_BUTTON_7_BIT )
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static ajoy_buttonset_t ajoy_supported(FAR const struct ajoy_lowerhalf_s
+ *lower);
+static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower,
+ FAR struct ajoy_sample_s *sample);
+static ajoy_buttonset_t ajoy_buttons(FAR const struct ajoy_lowerhalf_s
+ *lower);
+static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower,
+ ajoy_buttonset_t press, ajoy_buttonset_t release,
+ ajoy_handler_t handler, FAR void *arg);
+
+static void ajoy_disable(void);
+static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Pin configuration for each Itead joystick button. Index using AJOY_*
+ * button definitions in include/nuttx/input/ajoystick.h.
+ */
+
+static const pio_pinset_t g_joypio[AJOY_NGPIOS] =
+{
+ PIO_BUTTON_1, PIO_BUTTON_2, PIO_BUTTON_3, PIO_BUTTON_4,
+ PIO_BUTTON_5, PIO_BUTTON_6, PIO_BUTTON_6
+};
+
+static const uint8_t g_joyirq[AJOY_NGPIOS] =
+{
+ IRQ_BUTTON_1, IRQ_BUTTON_2, IRQ_BUTTON_3, IRQ_BUTTON_4,
+ IRQ_BUTTON_5, IRQ_BUTTON_6, IRQ_BUTTON_6
+};
+
+/* This is the button joystick lower half driver interface */
+
+static const struct ajoy_lowerhalf_s g_ajoylower =
+{
+ .al_supported = ajoy_supported,
+ .al_sample = ajoy_sample,
+ .al_buttons = ajoy_buttons,
+ .al_enable = ajoy_enable,
+};
+
+/* Thread-independent file structure for the open ADC driver */
+
+static struct file g_adcfile;
+
+/* Current interrupt handler and argument */
+
+static ajoy_handler_t g_ajoyhandler;
+static FAR void *g_ajoyarg;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ajoy_supported
+ *
+ * Description:
+ * Return the set of buttons supported on the button joystick device
+ *
+ ****************************************************************************/
+
+static ajoy_buttonset_t ajoy_supported(FAR const struct ajoy_lowerhalf_s
+ *lower)
+{
+ iinfo("Supported: %02x\n", AJOY_SUPPORTED);
+ return (ajoy_buttonset_t)AJOY_SUPPORTED;
+}
+
+/****************************************************************************
+ * Name: ajoy_sample
+ *
+ * Description:
+ * Return the current state of all button joystick buttons
+ *
+ ****************************************************************************/
+
+static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower,
+ FAR struct ajoy_sample_s *sample)
+{
+ struct adc_msg_s adcmsg[SAM_ADC_NCHANNELS];
+ FAR struct adc_msg_s *ptr;
+ ssize_t nread;
+ ssize_t offset;
+ int have;
+ int i;
+
+ /* Read all of the available samples (handling the case where additional
+ * channels are enabled).
+ */
+
+ nread = file_read(&g_adcfile, adcmsg,
+ MAX_ADC_CHANNELS * sizeof(struct adc_msg_s));
+ if (nread < 0)
+ {
+ if (nread != EINTR)
+ {
+ ierr("ERROR: read failed: %d\n", (int)nread);
+ }
+
+ return nread;
+ }
+ else if (nread < 2 * sizeof(struct adc_msg_s))
+ {
+ ierr("ERROR: read too small: %ld\n", (long)nread);
+ return -EIO;
+ }
+
+ /* Sample and the raw analog inputs */
+
+ for (i = 0, offset = 0, have = 0;
+ i < SAM_ADC_NCHANNELS && offset < nread && have != 3;
+ i++, offset += sizeof(struct adc_msg_s))
+ {
+ ptr = &adcmsg[i];
+
+ /* Is this one of the channels that we need? */
+
+ if ((have & 1) == 0 && ptr->am_channel == 0)
+ {
+ int32_t tmp = ptr->am_data;
+ sample->as_x = (int16_t)tmp;
+ have |= 1;
+
+ iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x);
+ }
+
+ if ((have & 2) == 0 && ptr->am_channel == 1)
+ {
+ int32_t tmp = ptr->am_data;
+ sample->as_y = (int16_t)tmp;
+ have |= 2;
+
+ iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y);
+ }
+ }
+
+ if (have != 3)
+ {
+ ierr("ERROR: Could not find joystack channels\n");
+ return -EIO;
+ }
+
+ /* Sample the discrete button inputs */
+
+ sample->as_buttons = ajoy_buttons(lower);
+ iinfo("Returning: %02x\n", AJOY_SUPPORTED);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: ajoy_buttons
+ *
+ * Description:
+ * Return the current state of button data (only)
+ *
+ ****************************************************************************/
+
+static ajoy_buttonset_t ajoy_buttons(FAR const struct ajoy_lowerhalf_s
+ *lower)
+{
+ ajoy_buttonset_t ret = 0;
+ int i;
+
+ /* Read each joystick GPIO value */
+
+ for (i = 0; i < AJOY_NGPIOS; i++)
+ {
+ /* Button outputs are pulled high. So a sensed low level means that the
+ * button is pressed.
+ */
+
+ if (!sam_pioread(g_joypio[i]))
+ {
+ ret |= (1 << i);
+ }
+ }
+
+ iinfo("Returning: %02x\n", ret);
+ return ret;
+}
+
+/****************************************************************************
+ * Name: ajoy_enable
+ *
+ * Description:
+ * Enable interrupts on the selected set of joystick buttons. And empty
+ * set will disable all interrupts.
+ *
+ ****************************************************************************/
+
+static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower,
+ ajoy_buttonset_t press, ajoy_buttonset_t release,
+ ajoy_handler_t handler, FAR void *arg)
+{
+ irqstate_t flags;
+ ajoy_buttonset_t either = press | release;
+ ajoy_buttonset_t bit;
+ int i;
+
+ /* Start with all interrupts disabled */
+
+ flags = enter_critical_section();
+ ajoy_disable();
+
+ iinfo("press: %02x release: %02x handler: %p arg: %p\n",
+ press, release, handler, arg);
+
+ /* If no events are indicated or if no handler is provided, then this
+ * must really be a request to disable interrupts.
+ */
+
+ if (either && handler)
+ {
+ /* Save the new the handler and argument */
+
+ g_ajoyhandler = handler;
+ g_ajoyarg = arg;
+
+ /* Check each GPIO. */
+
+ for (i = 0; i < AJOY_NGPIOS; i++)
+ {
+ /* Enable interrupts on each pin that has either a press or
+ * release event associated with it.
+ */
+
+ bit = (1 << i);
+ if ((either & bit) != 0)
+ {
+ /* REVISIT: It would be better if we reconfigured for
+ * the edges of interest so that we do not get spurious
+ * interrupts.
+ */
+
+ sam_pioirqenable(g_joyirq[i]);
+ }
+ }
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: ajoy_disable
+ *
+ * Description:
+ * Disable all joystick interrupts
+ *
+ ****************************************************************************/
+
+static void ajoy_disable(void)
+{
+ irqstate_t flags;
+ int i;
+
+ /* Disable each joystick interrupt */
+
+ flags = enter_critical_section();
+ for (i = 0; i < AJOY_NGPIOS; i++)
+ {
+ sam_pioirqdisable(g_joyirq[i]);
+ }
+
+ leave_critical_section(flags);
+
+ /* Nullify the handler and argument */
+
+ g_ajoyhandler = NULL;
+ g_ajoyarg = NULL;
+}
+
+/****************************************************************************
+ * Name: ajoy_interrupt
+ *
+ * Description:
+ * Discrete joystick interrupt handler
+ *
+ ****************************************************************************/
+
+static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg)
+{
+ DEBUGASSERT(g_ajoyhandler);
+ if (g_ajoyhandler)
+ {
+ g_ajoyhandler(&g_ajoylower, g_ajoyarg);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_ajoy_initialization
+ *
+ * Description:
+ * Initialize and register the button joystick driver
+ *
+ ****************************************************************************/
+
+int sam_ajoy_initialization(void)
+{
+ int ret;
+ int i;
+
+ /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */
+
+ /* Open the ADC driver for reading. */
+
+ ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY);
+ if (ret < 0)
+ {
+ ierr("ERROR: Failed to open /dev/adc0: %d\n", ret);
+ return ret;
+ }
+
+ /* Configure the GPIO pins as interrupting inputs. */
+
+ for (i = 0; i < AJOY_NGPIOS; i++)
+ {
+ /* Configure the PIO as an input */
+
+ sam_configpio(g_joypio[i]);
+
+ /* Configure PIO interrupts, attach the interrupt handler, but leave
+ * the interrupt disabled.
+ */
+
+ sam_pioirq(g_joypio[i]);
+ irq_attach(g_joyirq[i], ajoy_interrupt, NULL);
+ sam_pioirqdisable(g_joyirq[i]);
+ }
+
+ /* Register the joystick device as /dev/ajoy0 */
+
+ ret = ajoy_register("/dev/ajoy0", &g_ajoylower);
+ if (ret < 0)
+ {
+ ierr("ERROR: ajoy_register failed: %d\n", ret);
+ file_close(&g_adcfile);
+ }
+
+ return ret;
+}
+
+#endif /* CONFIG_AJOYSTICK */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_appinit.c b/boards/arm/sama5/sama5d2-xult/src/sam_appinit.c
index 88e9e12..6426617 100644
--- a/boards/arm/sama5/sama5d2-xult/src/sam_appinit.c
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_appinit.c
@@ -1,35 +1,20 @@
/****************************************************************************
- * boards/arm/sama5/sama5d2-xult/src/sam_appinit.c
+ * boards/arm/sama5/sama5d2-xult/src/sam_appinit.c
*
- * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_at25.c b/boards/arm/sama5/sama5d2-xult/src/sam_at25.c
new file mode 100644
index 0000000..4827b69
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_at25.c
@@ -0,0 +1,128 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_at25.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/mount.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/spi/spi.h>
+#include <nuttx/mtd/mtd.h>
+#include <nuttx/fs/nxffs.h>
+
+#include "sam_spi.h"
+#include "sama5d2-xult.h"
+
+#ifdef HAVE_AT25
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_at25_automount
+ *
+ * Description:
+ * Initialize and configure the AT25 serial FLASH
+ *
+ ****************************************************************************/
+
+int sam_at25_automount(int minor)
+{
+ FAR struct spi_dev_s *spi;
+ FAR struct mtd_dev_s *mtd;
+ static bool initialized = false;
+ int ret;
+
+ /* Have we already initialized? */
+
+ if (!initialized)
+ {
+ /* No.. Get the SPI port driver */
+
+ spi = sam_spibus_initialize(AT25_PORT);
+ if (!spi)
+ {
+ ferr("ERROR: Failed to initialize SPI port %d\n", AT25_PORT);
+ return -ENODEV;
+ }
+
+ /* Now bind the SPI interface to the AT25 SPI FLASH driver */
+
+ mtd = at25_initialize(spi);
+ if (!mtd)
+ {
+ ferr("ERROR: Failed to bind SPI port %d to the AT25 FLASH driver\n");
+ return -ENODEV;
+ }
+
+#if defined(CONFIG_SAMA5D3XPLAINED_AT25_FTL)
+
+ /* And finally, use the FTL layer to wrap the MTD driver as a block driver */
+
+ ret = ftl_initialize(AT25_MINOR, mtd);
+ if (ret < 0)
+ {
+ ferr("ERROR: Failed to initialize the FTL layer: %d\n", ret);
+ return ret;
+ }
+
+#elif defined(CONFIG_SAMA5D3XPLAINED_AT25_NXFFS)
+
+ /* Initialize to provide NXFFS on the MTD interface */
+
+ ret = nxffs_initialize(mtd);
+ if (ret < 0)
+ {
+ ferr("ERROR: NXFFS initialization failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Mount the file system at /mnt/at25 */
+
+ ret = mount(NULL, "/mnt/at25", "nxffs", 0, NULL);
+ if (ret < 0)
+ {
+ ferr("ERROR: Failed to mount the NXFFS volume: %d\n", errno);
+ return ret;
+ }
+#endif
+
+ /* Now we are initializeed */
+
+ initialized = true;
+ }
+
+ return OK;
+}
+
+#endif /* HAVE_AT25 */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c b/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c
index 0d7311f..2441f38 100644
--- a/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c
@@ -1,35 +1,20 @@
/****************************************************************************
- * boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c
+ * boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_boot.c b/boards/arm/sama5/sama5d2-xult/src/sam_boot.c
index 86335a7..7936101 100644
--- a/boards/arm/sama5/sama5d2-xult/src/sam_boot.c
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_boot.c
@@ -1,35 +1,20 @@
/****************************************************************************
- * boards/arm/sama5/sama5d2-xult/src/sam_boot.c
+ * boards/arm/sama5/sama5d2-xult/src/sam_boot.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
@@ -70,6 +55,19 @@
void sam_boardinitialize(void)
{
+ /* Initialize USB if the 1) the HS host or device controller is in the
+ * configuration and 2) the weak function sam_usbinitialize() has been
+ * brought into the build.
+ * Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also selected.
+ */
+
+#if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS)
+ if (sam_usbinitialize)
+ {
+ sam_usbinitialize();
+ }
+#endif
+
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_bringup.c b/boards/arm/sama5/sama5d2-xult/src/sam_bringup.c
index 6d683cf..e961baf 100644
--- a/boards/arm/sama5/sama5d2-xult/src/sam_bringup.c
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_bringup.c
@@ -1,35 +1,20 @@
/****************************************************************************
- * boards/arm/sama5/sama5d2-xult/src/sam_bringup.c
+ * boards/arm/sama5/sama5d2-xult/src/sam_bringup.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
@@ -43,9 +28,103 @@
#include <syslog.h>
#include <debug.h>
+#include <nuttx/irq.h>
+#include <nuttx/kthread.h>
+#include <nuttx/usb/usbdev.h>
+#include <nuttx/usb/usbhost.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#ifdef CONFIG_CDCACM
+# include <nuttx/usb/cdcacm.h>
+#endif
+
+#ifdef CONFIG_NET_CDCECM
+# include <nuttx/usb/cdcecm.h>
+# include <net/if.h>
+#endif
+
+#ifdef CONFIG_USBMONITOR
+# include <nuttx/usb/usbmonitor.h>
+#endif
+
+#ifdef CONFIG_RNDIS
+# include <nuttx/usb/rndis.h>
+#endif
+
#include "sama5d2-xult.h"
/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define NSECTORS(n) \
+ (((n)+CONFIG_SAMA5D4EK_ROMFS_ROMDISK_SECTSIZE-1) / \
+ CONFIG_SAMA5D4EK_ROMFS_ROMDISK_SECTSIZE)
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_i2c_register
+ *
+ * Description:
+ * Register one I2C drivers for the I2C tool.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_I2CTOOL
+static void sam_i2c_register(int bus)
+{
+ FAR struct i2c_master_s *i2c;
+ int ret;
+
+ i2c = sam_i2cbus_initialize(bus);
+ if (i2c == NULL)
+ {
+ _err("ERROR: Failed to get I2C%d interface\n", bus);
+ }
+ else
+ {
+ ret = i2c_register(i2c, bus);
+ if (ret < 0)
+ {
+ _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret);
+ sam_i2cbus_uninitialize(i2c);
+ }
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: sam_i2ctool
+ *
+ * Description:
+ * Register I2C drivers for the I2C tool.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_I2CTOOL
+static void sam_i2ctool(void)
+{
+#ifdef CONFIG_SAMA5_TWI0
+ sam_i2c_register(0);
+#endif
+#ifdef CONFIG_SAMA5_TWI1
+ sam_i2c_register(1);
+#endif
+#ifdef CONFIG_SAMA5_TWI2
+ sam_i2c_register(2);
+#endif
+#ifdef CONFIG_SAMA5_TWI3
+ sam_i2c_register(3);
+#endif
+}
+#else
+# define sam_i2ctool()
+#endif
+
+/****************************************************************************
* Public Functions
****************************************************************************/
@@ -59,9 +138,183 @@
int sam_bringup(void)
{
-#ifdef CONFIG_FS_PROCFS
int ret;
+ /* Register I2C drivers on behalf of the I2C tool */
+
+ sam_i2ctool();
+
+#ifdef HAVE_HSMCI
+#ifdef CONFIG_SAMA5_HSMCI0
+ /* Initialize the HSMCI0 driver */
+
+ ret = sam_hsmci_initialize(HSMCI0_SLOTNO, HSMCI0_MINOR);
+ if (ret < 0)
+ {
+ _err("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
+ HSMCI0_SLOTNO, HSMCI0_MINOR, ret);
+ }
+
+#ifdef CONFIG_SAMA5D4EK_HSMCI0_MOUNT
+ else
+ {
+ /* REVISIT:
+ * A delay seems to be required here or the mount will fail.
+ */
+
+ /* Mount the volume on HSMCI0 */
+
+ ret = mount(CONFIG_SAMA5D4EK_HSMCI0_MOUNT_BLKDEV,
+ CONFIG_SAMA5D4EK_HSMCI0_MOUNT_MOUNTPOINT,
+ CONFIG_SAMA5D4EK_HSMCI0_MOUNT_FSTYPE,
+ 0, NULL);
+
+ if (ret < 0)
+ {
+ _err("ERROR: Failed to mount %s: %d\n",
+ CONFIG_SAMA5D4EK_HSMCI0_MOUNT_MOUNTPOINT, errno);
+ }
+ }
+#endif
+#endif
+
+#ifdef CONFIG_SAMA5_HSMCI1
+ /* Initialize the HSMCI1 driver */
+
+ ret = sam_hsmci_initialize(HSMCI1_SLOTNO, HSMCI1_MINOR);
+ if (ret < 0)
+ {
+ _err("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n",
+ HSMCI1_SLOTNO, HSMCI1_MINOR, ret);
+ }
+
+#ifdef CONFIG_SAMA5D4EK_HSMCI1_MOUNT
+ else
+ {
+ /* REVISIT: A delay seems to be required here or the mount will fail. */
+
+ /* Mount the volume on HSMCI1 */
+
+ ret = mount(CONFIG_SAMA5D4EK_HSMCI1_MOUNT_BLKDEV,
+ CONFIG_SAMA5D4EK_HSMCI1_MOUNT_MOUNTPOINT,
+ CONFIG_SAMA5D4EK_HSMCI1_MOUNT_FSTYPE,
+ 0, NULL);
+
+ if (ret < 0)
+ {
+ _err("ERROR: Failed to mount %s: %d\n",
+ CONFIG_SAMA5D4EK_HSMCI1_MOUNT_MOUNTPOINT, errno);
+ }
+ }
+#endif
+#endif
+#endif
+
+#ifdef HAVE_AUTOMOUNTER
+ /* Initialize the auto-mounter */
+
+ sam_automount_initialize();
+#endif
+
+#ifdef HAVE_ROMFS
+ /* Create a ROM disk for the /etc filesystem */
+
+ ret = romdisk_register(CONFIG_SAMA5D4EK_ROMFS_ROMDISK_MINOR, romfs_img,
+ NSECTORS(romfs_img_len),
+ CONFIG_SAMA5D4EK_ROMFS_ROMDISK_SECTSIZE);
+ if (ret < 0)
+ {
+ _err("ERROR: romdisk_register failed: %d\n", -ret);
+ }
+ else
+ {
+ /* Mount the file system */
+
+ ret = mount(CONFIG_SAMA5D4EK_ROMFS_ROMDISK_DEVNAME,
+ CONFIG_SAMA5D4EK_ROMFS_MOUNT_MOUNTPOINT,
+ "romfs", MS_RDONLY, NULL);
+ if (ret < 0)
+ {
+ _err("ERROR: mount(%s,%s,romfs) failed: %d\n",
+ CONFIG_SAMA5D4EK_ROMFS_ROMDISK_DEVNAME,
+ CONFIG_SAMA5D4EK_ROMFS_MOUNT_MOUNTPOINT, errno);
+ }
+ }
+#endif
+
+#ifdef HAVE_USBHOST
+ /* Initialize USB host operation. sam_usbhost_initialize() starts a thread
+ * will monitor for USB connection and disconnection events.
+ */
+
+ ret = sam_usbhost_initialize();
+ if (ret != OK)
+ {
+ _err("ERROR: Failed to initialize USB host: %d\n", ret);
+ }
+#endif
+
+#ifdef HAVE_USBMONITOR
+ /* Start the USB Monitor */
+
+ ret = usbmonitor_start();
+ if (ret != OK)
+ {
+ _err("ERROR: Failed to start the USB monitor: %d\n", ret);
+ }
+#endif
+
+#ifdef HAVE_MAXTOUCH
+ /* Initialize the touchscreen */
+
+ ret = sam_tsc_setup(0);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: sam_tsc_setup failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_PWM
+ /* Initialize PWM and register the PWM device. */
+
+ ret = sam_pwm_setup();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: sam_pwm_setup() failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_ADC
+ /* Initialize ADC and register the ADC driver. */
+
+ ret = sam_adc_setup();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: sam_adc_setup failed: %d\n", ret);
+ }
+#endif
+
+#ifdef HAVE_WM8904
+ /* Configure WM8904 audio */
+
+ ret = sam_wm8904_initialize(0);
+ if (ret != OK)
+ {
+ _err("ERROR: Failed to initialize WM8904 audio: %d\n", ret);
+ }
+#endif
+
+#ifdef HAVE_AUDIO_NULL
+ /* Configure the NULL audio device */
+
+ ret = sam_audio_null_initialize(0);
+ if (ret != OK)
+ {
+ _err("ERROR: Failed to initialize the NULL audio device: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_FS_PROCFS
/* Mount the procfs file system */
ret = mount(NULL, SAMA5_PROCFS_MOUNTPOINT, "procfs", 0, NULL);
@@ -72,5 +325,32 @@ int sam_bringup(void)
}
#endif
+#if defined(CONFIG_RNDIS)
+ /* Set up a MAC address for the RNDIS device. */
+
+ uint8_t mac[6];
+ mac[0] = 0xa0; /* TODO */
+ mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff;
+ mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff;
+ mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff;
+ mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff;
+ mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff;
+ usbdev_rndis_initialize(mac);
+#endif
+
+#ifdef CONFIG_NET_CDCECM
+ ret = cdcecm_initialize(0, NULL);
+ if (ret < 0)
+ {
+ _err("ERROR: cdcecm_initialize() failed: %d\n", ret);
+ }
+#endif
+
+ /* If we got here then perhaps not all initialization was successful, but
+ * at least enough succeeded to bring-up NSH with perhaps reduced
+ * capabilities.
+ */
+
+ UNUSED(ret);
return OK;
}
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_buttons.c b/boards/arm/sama5/sama5d2-xult/src/sam_buttons.c
index afe1d92..e2b72c7 100644
--- a/boards/arm/sama5/sama5d2-xult/src/sam_buttons.c
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_buttons.c
@@ -1,35 +1,20 @@
/****************************************************************************
- * boards/arm/sama5/sama5d2-xult/src/sam_buttons.c
+ * boards/arm/sama5/sama5d2-xult/src/sam_buttons.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_can.c b/boards/arm/sama5/sama5d2-xult/src/sam_can.c
new file mode 100644
index 0000000..c0ea545
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_can.c
@@ -0,0 +1,100 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_can.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/can/can.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "sam_can.h"
+#include "sama5d2-xult.h"
+
+#ifdef CONFIG_CAN
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#if defined(CONFIG_SAMA5_CAN0) && defined(CONFIG_SAMA5_CAN1)
+# warning "Both CAN0 and CAN1 are enabled. Assuming only CAN0."
+# undef CONFIG_SAMA5_CAN1
+#endif
+
+#ifdef CONFIG_SAMA5_CAN0
+# define CAN_PORT 0
+#else
+# define CAN_PORT 1
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_can_setup
+ *
+ * Description:
+ * Initialize CAN and register the CAN device
+ *
+ ****************************************************************************/
+
+int sam_can_setup(void)
+{
+#if defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1)
+ struct can_dev_s *can;
+ int ret;
+
+ /* Call stm32_caninitialize() to get an instance of the CAN interface */
+
+ can = sam_caninitialize(CAN_PORT);
+ if (can == NULL)
+ {
+ canerr("ERROR: Failed to get CAN interface\n");
+ return -ENODEV;
+ }
+
+ /* Register the CAN driver at "/dev/can0" */
+
+ ret = can_register("/dev/can0", can);
+ if (ret < 0)
+ {
+ canerr("ERROR: can_register failed: %d\n", ret);
+ return ret;
+ }
+
+ return OK;
+#else
+ return -ENODEV;
+#endif
+}
+
+#endif /* CONFIG_CAN */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_ethernet.c b/boards/arm/sama5/sama5d2-xult/src/sam_ethernet.c
new file mode 100644
index 0000000..6452440
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_ethernet.c
@@ -0,0 +1,328 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_ethernet.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Force verbose debug on in this file only to support unit-level testing. */
+
+#ifdef CONFIG_NETDEV_PHY_DEBUG
+# undef CONFIG_DEBUG_INFO
+# define CONFIG_DEBUG_INFO 1
+# undef CONFIG_DEBUG_NET
+# define CONFIG_DEBUG_NET 1
+#endif
+
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "sam_pio.h"
+#include "sam_ethernet.h"
+
+#include "sama5d2-xult.h"
+
+#ifdef HAVE_NETWORK
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_SAMA5_EMACA
+# undef CONFIG_SAMA5_EMAC_ISETH0
+#endif
+
+#ifdef CONFIG_SAMA5_EMAC_ISETH0
+# define SAMA5_EMAC_DEVNAME "eth0"
+# define SAMA5_GMAC_DEVNAME "eth1"
+#else
+# define SAMA5_GMAC_DEVNAME "eth0"
+# define SAMA5_EMAC_DEVNAME "eth1"
+#endif
+
+/* Debug ********************************************************************/
+
+/* Extra, in-depth debug output that is only available if
+ * CONFIG_NETDEV_PHY_DEBUG us defined.
+ */
+
+#ifdef CONFIG_NETDEV_PHY_DEBUG
+# define phyerr _err
+# define phywarn _warn
+# define phyinfo _info
+#else
+# define phyerr(x...)
+# define phywarn(x...)
+# define phyinfo(x...)
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_emac_phy_enable and sam_gmac_enable
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMA5_PIOE_IRQ
+#ifdef CONFIG_SAMA5_EMACA
+static void sam_emac_phy_enable(bool enable)
+{
+ phyinfo("IRQ%d: enable=%d\n", IRQ_INT_ETH1, enable);
+ if (enable)
+ {
+ sam_pioirqenable(IRQ_INT_ETH1);
+ }
+ else
+ {
+ sam_pioirqdisable(IRQ_INT_ETH1);
+ }
+}
+
+#endif
+
+#ifdef CONFIG_SAMA5_GMAC
+static void sam_gmac_phy_enable(bool enable)
+{
+ phyinfo("IRQ%d: enable=%d\n", IRQ_INT_ETH0, enable);
+ if (enable)
+ {
+ sam_pioirqenable(IRQ_INT_ETH0);
+ }
+ else
+ {
+ sam_pioirqdisable(IRQ_INT_ETH0);
+ }
+}
+#endif
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_netinitialize
+ *
+ * Description:
+ * Configure board resources to support networking.
+ *
+ ****************************************************************************/
+
+void weak_function sam_netinitialize(void)
+{
+#ifdef CONFIG_SAMA5_EMACA
+ /* Ethernet 10/100 (EMAC A) Port
+ *
+ * The main board contains a MICREL PHY device (KSZ8051) operating at
+ * 10/100 Mbps. The board supports MII and RMII interface modes.
+ *
+ * The two independent PHY devices embedded on CM and MB boards are
+ * connected to independent RJ-45 connectors with built-in magnetic
+ * and status LEDs.
+ *
+ * At the De-Assertion of Reset:
+ * PHY ADD[2:0]:001
+ * CONFIG[2:0]:001,Mode:RMII
+ * Duplex Mode:Half Duplex
+ * Isolate Mode:Disable
+ * Speed Mode:100Mbps
+ * Nway Auto-Negotiation:Enable
+ *
+ * The KSZ8051 PHY interrupt is available on PE30 INT_ETH1
+ */
+
+ phyinfo("Configuring %08x\n", PIO_INT_ETH1);
+ sam_configpio(PIO_INT_ETH1);
+#endif
+
+#ifdef CONFIG_SAMA5_GMAC
+ /* Tri-Speed Ethernet PHY
+ *
+ * The SAMA5D3 series-CM board is equipped with a MICREL PHY devices
+ * (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
+ * The board supports RGMII interface mode.
+ * The Ethernet interface consists of 4 pairs of low voltage differential
+ * pair signals designated from GRX� and GTx� plus control signals for
+ * link activity indicators. These signals can be used to connect to a
+ * 10/100/1000 BaseT RJ45 connector integrated on the main board.
+ *
+ * The KSZ9021/31 interrupt is available on PB35 INT_GETH0
+ */
+
+ phyinfo("Configuring %08x\n", PIO_INT_ETH0);
+ sam_configpio(PIO_INT_ETH0);
+#endif
+}
+
+/****************************************************************************
+ * Name: arch_phy_irq
+ *
+ * Description:
+ * This function may be called to register an interrupt handler that will
+ * be called when a PHY interrupt occurs. This function both attaches
+ * the interrupt handler and enables the interrupt if 'handler' is non-
+ * NULL. If handler is NULL, then the interrupt is detached and disabled
+ * instead.
+ *
+ * The PHY interrupt is always disabled upon return. The caller must
+ * call back through the enable function point to control the state of
+ * the interrupt.
+ *
+ * This interrupt may or may not be available on a given platform depending
+ * on how the network hardware architecture is implemented. In a typical
+ * case, the PHY interrupt is provided to board-level logic as a GPIO
+ * interrupt (in which case this is a board-specific interface and really
+ * should be called board_phy_irq()); In other cases, the PHY interrupt
+ * may be cause by the chip's MAC logic (in which case arch_phy_irq()) is
+ * an appropriate name. Other other boards, there may be no PHY interrupts
+ * available at all. If client attachable PHY interrupts are available
+ * from the board or from the chip, then CONFIG_ARCH_PHY_INTERRUPT should
+ * be defined to indicate that fact.
+ *
+ * Typical usage:
+ * a. OS service logic (not application logic*) attaches to the PHY
+ * PHY interrupt and enables the PHY interrupt.
+ * b. When the PHY interrupt occurs: (1) the interrupt should be
+ * disabled and () work should be scheduled on the worker thread (or
+ * perhaps a dedicated application thread).
+ * c. That worker thread should use the SIOCGMIIPHY, SIOCGMIIREG,
+ * and SIOCSMIIREG ioctl calls** to communicate with the PHY,
+ * determine what network event took place (Link Up/Down?), and
+ * take the appropriate actions.
+ * d. It should then interact the PHY to clear any pending
+ * interrupts, then re-enable the PHY interrupt.
+ *
+ * * This is an OS internal interface and should not be used from
+ * application space. Rather applications should use the SIOCMIISIG
+ * ioctl to receive a signal when a PHY event occurs.
+ * ** This interrupt is really of no use if the Ethernet MAC driver
+ * does not support these ioctl calls.
+ *
+ * Input Parameters:
+ * intf - Identifies the network interface. For example "eth0". Only
+ * useful on platforms that support multiple Ethernet interfaces
+ * and, hence, multiple PHYs and PHY interrupts.
+ * handler - The client interrupt handler to be invoked when the PHY
+ * asserts an interrupt. Must reside in OS space, but can
+ * signal tasks in user space. A value of NULL can be passed
+ * in order to detach and disable the PHY interrupt.
+ * arg - The argument that will accompany the interrupt
+ * enable - A function pointer that be unused to enable or disable the
+ * PHY interrupt.
+ *
+ * Returned Value:
+ * Zero (OK) returned on success; a negated errno value is returned on
+ * failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMA5_PIOE_IRQ
+int arch_phy_irq(FAR const char *intf, xcpt_t handler, void *arg,
+ phy_enable_t *enable)
+{
+ irqstate_t flags;
+ pio_pinset_t pinset;
+ phy_enable_t enabler;
+ int irq;
+
+ DEBUGASSERT(intf);
+
+ ninfo("%s: handler=%p\n", intf, handler);
+#ifdef CONFIG_SAMA5_EMACA
+ phyinfo("EMAC: devname=%s\n", SAMA5_EMAC_DEVNAME);
+#endif
+#ifdef CONFIG_SAMA5_GMAC
+ phyinfo("GMAC: devname=%s\n", SAMA5_GMAC_DEVNAME);
+#endif
+
+#ifdef CONFIG_SAMA5_EMACA
+ if (strcmp(intf, SAMA5_EMAC_DEVNAME) == 0)
+ {
+ phyinfo("Select EMAC\n");
+ pinset = PIO_INT_ETH1;
+ irq = IRQ_INT_ETH1;
+ enabler = sam_emac_phy_enable;
+ }
+ else
+#endif
+#ifdef CONFIG_SAMA5_GMAC
+ if (strcmp(intf, SAMA5_GMAC_DEVNAME) == 0)
+ {
+ phyinfo("Select GMAC\n");
+ pinset = PIO_INT_ETH0;
+ irq = IRQ_INT_ETH0;
+ enabler = sam_gmac_phy_enable;
+ }
+ else
+#endif
+ {
+ nerr("ERROR: Unsupported interface: %s\n", intf);
+ return NULL;
+ }
+
+ /* Disable interrupts until we are done. This guarantees that the
+ * following operations are atomic.
+ */
+
+ flags = enter_critical_section();
+
+ /* Configure the interrupt */
+
+ if (handler)
+ {
+ phyinfo("Configure pin: %08x\n", pinset);
+ sam_pioirq(pinset);
+
+ phyinfo("Attach IRQ%d\n", irq);
+ irq_attach(irq, handler, arg);
+ }
+ else
+ {
+ phyinfo("Detach IRQ%d\n", irq);
+ irq_detach(irq);
+ enabler = NULL;
+ }
+
+ /* Return with the interrupt disabled in either case */
+
+ sam_pioirqdisable(irq);
+
+ /* Return the enabling function pointer */
+
+ if (enable)
+ {
+ *enable = enabler;
+ }
+
+ /* Return the old handler (so that it can be restored) */
+
+ leave_critical_section(flags);
+ return OK;
+}
+#endif /* CONFIG_SAMA5_PIOE_IRQ */
+
+#endif /* HAVE_NETWORK */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_hsmci.c b/boards/arm/sama5/sama5d2-xult/src/sam_hsmci.c
new file mode 100644
index 0000000..4ae952f
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_hsmci.c
@@ -0,0 +1,329 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_hsmci.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* The SAMA5D3-Xplained provides a two SD memory card slots:
+ * (1) a full size SD card slot (J10), and
+ * (2) a microSD memory card slot (J11).
+ *
+ * The full size SD card slot connects via HSMCI0. The card detect discrete
+ * is available on PB17 (pulled high). The write protect descrete is tied to
+ * ground (via PP6) and not available to software. The slot supports 8-bit
+ * wide transfer mode, but the NuttX driver currently uses only the 4-bit
+ * wide transfer mode
+ *
+ * PD17 MCI0_CD
+ * PD1 MCI0_DA0
+ * PD2 MCI0_DA1
+ * PD3 MCI0_DA2
+ * PD4 MCI0_DA3
+ * PD5 MCI0_DA4
+ * PD6 MCI0_DA5
+ * PD7 MCI0_DA6
+ * PD8 MCI0_DA7
+ * PD9 MCI0_CK
+ * PD0 MCI0_CDA
+ *
+ * The microSD connects vi HSMCI1. The card detect discrete is available on
+ * PB18 (pulled high):
+ *
+ * PD18 MCI1_CD
+ * PB20 MCI1_DA0
+ * PB21 MCI1_DA1
+ * PB22 MCI1_DA2
+ * PB23 MCI1_DA3
+ * PB24 MCI1_CK
+ * PB19 MCI1_CDA
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/sdio.h>
+#include <nuttx/mmcsd.h>
+
+#include "sam_pio.h"
+#include "sam_hsmci.h"
+
+#include "sama5d3-xplained.h"
+
+#ifdef HAVE_HSMCI
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure holds static information unique to one HSMCI peripheral */
+
+struct sam_hsmci_state_s
+{
+ struct sdio_dev_s *hsmci; /* R/W device handle */
+ pio_pinset_t pincfg; /* Card detect PIO pin configuration */
+ uint8_t irq; /* Interrupt number (same as pid) */
+ uint8_t slotno; /* Slot number */
+ bool cd; /* TRUE: card is inserted */
+ xcpt_t handler; /* Interrupt handler */
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* HSCMI device state */
+
+#ifdef CONFIG_SAMA5_HSMCI0
+static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg);
+
+static struct sam_hsmci_state_s g_hsmci0 =
+{
+ .pincfg = PIO_MCI0_CD,
+ .irq = IRQ_MCI0_CD,
+ .slotno = 0,
+ .handler = sam_hsmci0_cardetect,
+};
+#endif
+
+#ifdef CONFIG_SAMA5_HSMCI1
+static int sam_hsmci1_cardetect(int irq, void *regs, FAR void *arg);
+
+static struct sam_hsmci_state_s g_hsmci1 =
+{
+ .pincfg = PIO_MCI1_CD,
+ .irq = IRQ_MCI1_CD,
+ .slotno = 1,
+ .handler = sam_hsmci1_cardetect,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_cardinserted_internal
+ *
+ * Description:
+ * Check if a card is inserted into the selected HSMCI slot
+ *
+ ****************************************************************************/
+
+bool sam_cardinserted_internal(struct sam_hsmci_state_s *state)
+{
+ bool inserted;
+
+ /* Get the state of the PIO pin */
+
+ inserted = sam_pioread(state->pincfg);
+ finfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
+ return !inserted;
+}
+
+/****************************************************************************
+ * Name: sam_hsmci_cardetect, sam_hsmci0_cardetect, and sam_hsmci1_cardetect
+ *
+ * Description:
+ * Card detect interrupt handlers
+ *
+ ****************************************************************************/
+
+static int sam_hsmci_cardetect(struct sam_hsmci_state_s *state)
+{
+ /* Get the current card insertion state */
+
+ bool cd = sam_cardinserted_internal(state);
+
+ /* Has the card detect state changed? */
+
+ if (cd != state->cd)
+ {
+ /* Yes... remember that new state and inform the HSMCI driver */
+
+ state->cd = cd;
+
+ /* Report the new state to the SDIO driver */
+
+ sdio_mediachange(state->hsmci, cd);
+ }
+
+ return OK;
+}
+
+#ifdef CONFIG_SAMA5_HSMCI0
+static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg)
+{
+ return sam_hsmci_cardetect(&g_hsmci0);
+}
+#endif
+
+#ifdef CONFIG_SAMA5_HSMCI1
+static int sam_hsmci1_cardetect(int irq, void *regs, FAR void *arg)
+{
+ return sam_hsmci_cardetect(&g_hsmci1);
+}
+#endif
+
+/****************************************************************************
+ * Name: sam_hsmci_state
+ *
+ * Description:
+ * Initialize HSMCI PIOs.
+ *
+ ****************************************************************************/
+
+static struct sam_hsmci_state_s *sam_hsmci_state(int slotno)
+{
+ struct sam_hsmci_state_s *state = NULL;
+
+#ifdef CONFIG_SAMA5_HSMCI0
+#ifdef CONFIG_SAMA5_HSMCI1
+ if (slotno == 0)
+#endif
+ {
+ state = &g_hsmci0;
+ }
+#ifdef CONFIG_SAMA5_HSMCI1
+ else
+#endif
+#endif
+
+#ifdef CONFIG_SAMA5_HSMCI1
+ {
+ state = &g_hsmci1;
+ }
+#endif
+
+ return state;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_hsmci_initialize
+ *
+ * Description:
+ * Perform architecture specific initialization
+ *
+ ****************************************************************************/
+
+int sam_hsmci_initialize(int slotno, int minor)
+{
+ struct sam_hsmci_state_s *state;
+ int ret;
+
+ /* Get the static HSMI description */
+
+ state = sam_hsmci_state(slotno);
+ if (!state)
+ {
+ ferr("ERROR: No state for slotno %d\n", slotno);
+ return -EINVAL;
+ }
+
+ /* Initialize card-detect and write-protect PIOs */
+
+ sam_configpio(state->pincfg);
+
+ /* Mount the SDIO-based MMC/SD block driver */
+
+ /* First, get an instance of the SDIO interface */
+
+ state->hsmci = sdio_initialize(slotno);
+ if (!state->hsmci)
+ {
+ ferr("ERROR: Failed to initialize SDIO slot %d\n", slotno);
+ return -ENODEV;
+ }
+
+ /* Now bind the SDIO interface to the MMC/SD driver */
+
+ ret = mmcsd_slotinitialize(minor, state->hsmci);
+ if (ret != OK)
+ {
+ ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
+ return ret;
+ }
+
+ /* Configure card detect interrupts */
+
+ sam_pioirq(state->pincfg);
+ irq_attach(state->irq, state->handler, NULL);
+
+ /* Then inform the HSMCI driver if there is or is not a card in the slot. */
+
+ state->cd = sam_cardinserted_internal(state);
+ sdio_mediachange(state->hsmci, state->cd);
+
+ /* Enable card detect interrupts */
+
+ sam_pioirqenable(state->irq);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sam_cardinserted
+ *
+ * Description:
+ * Check if a card is inserted into the selected HSMCI slot
+ *
+ ****************************************************************************/
+
+bool sam_cardinserted(int slotno)
+{
+ struct sam_hsmci_state_s *state;
+
+ /* Get the HSMI description */
+
+ state = sam_hsmci_state(slotno);
+ if (!state)
+ {
+ ferr("ERROR: No state for slotno %d\n", slotno);
+ return false;
+ }
+
+ /* Return the state of the PIO pin */
+
+ return sam_cardinserted_internal(state);
+}
+
+/****************************************************************************
+ * Name: sam_writeprotected
+ *
+ * Description:
+ * Check if a card is inserted into the selected HSMCI slot
+ *
+ ****************************************************************************/
+
+bool sam_writeprotected(int slotno)
+{
+ /* There are no write protect pins */
+
+ return false;
+}
+
+#endif /* HAVE_HSMCI */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_i2schar.c b/boards/arm/sama5/sama5d2-xult/src/sam_i2schar.c
new file mode 100644
index 0000000..bf04186
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_i2schar.c
@@ -0,0 +1,111 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_i2schar.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/audio/i2s.h>
+
+#include "sam_ssc.h"
+#include "sama5d2-xult.h"
+
+#if defined(CONFIG_AUDIO_I2SCHAR) && \
+ (defined(CONFIG_SAMA5_SSC0) || defined(CONFIG_SAMA5_SSC1))
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_SAMA5D3XPLAINED_SSC_PORT
+# if defined(CONFIG_SAMA5_SSC0)
+# define CONFIG_SAMA5D3XPLAINED_SSC_PORT 0
+# elif defined(CONFIG_SAMA5_SSC1)
+# define CONFIG_SAMA5D3XPLAINED_SSC_PORT 1
+# endif
+#endif
+
+#ifndef CONFIG_SAMA5D3XPLAINED_I2SCHAR_MINOR
+# define CONFIG_SAMA5D3XPLAINED_I2SCHAR_MINOR 0
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: i2schar_devinit
+ *
+ * Description:
+ * All architectures must provide the following interface in order to work
+ * with apps/examples/i2schar.
+ *
+ ****************************************************************************/
+
+int i2schar_devinit(void)
+{
+ static bool initialized = false;
+ struct i2s_dev_s *i2s;
+ int ret;
+
+ /* Have we already initialized? */
+
+ if (!initialized)
+ {
+ /* Call sam_ssc_initialize() to get an instance of the SSC/I2S
+ * interface
+ */
+
+ i2s = sam_ssc_initialize(CONFIG_SAMA5D3XPLAINED_SSC_PORT);
+ if (!i2s)
+ {
+ _err("ERROR: Failed to get the SAMA5 SSC/I2S driver for SSC%d\n",
+ CONFIG_SAMA5D3XPLAINED_SSC_PORT);
+ return -ENODEV;
+ }
+
+ /* Register the I2S character driver at "/dev/i2schar0" */
+
+ ret = i2schar_register(i2s, CONFIG_SAMA5D3XPLAINED_I2SCHAR_MINOR);
+ if (ret < 0)
+ {
+ aerr("ERROR: i2schar_register failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Now we are initialized */
+
+ initialized = true;
+ }
+
+ return OK;
+}
+
+#endif /* CONFIG_AUDIO_I2SCHAR && (CONFIG_SAMA5_SSC0 || CONFIG_SAMA5_SSC1) */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_nandflash.c b/boards/arm/sama5/sama5d2-xult/src/sam_nandflash.c
new file mode 100644
index 0000000..c5dceaa
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_nandflash.c
@@ -0,0 +1,212 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_nandflash.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/mount.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/mtd/mtd.h>
+#include <nuttx/fs/nxffs.h>
+
+#include "up_arch.h"
+#include "sam_periphclks.h"
+#include "sam_pio.h"
+#include "sam_nand.h"
+#include "hardware/sam_hsmc.h"
+#include "hardware/sam_pinmap.h"
+
+#include "sama5d2-xult.h"
+
+#ifdef CONFIG_SAMA5_EBICS3_NAND
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_nandflash_config
+ *
+ * Description:
+ * If CONFIG_SAMA5_EBICS3_NAND is defined, then NAND FLASH support is
+ * enabled. This function provides the board-specific implementation of
+ * the logic to reprogram the SMC to support NAND FLASH on the specified
+ * CS.
+ *
+ * Input Parameters:
+ * cs - Chip select number (in the event that multiple NAND devices
+ * are connected on-board).
+ *
+ * Returned Value:
+ * OK if the HSMC was successfully configured for this CS. A negated
+ * errno value is returned on a failure. This would fail with -ENODEV,
+ * for example, if the board does not support NAND FLASH on the requested
+ * CS.
+ *
+ ****************************************************************************/
+
+int board_nandflash_config(int cs)
+{
+ uint32_t regval;
+
+ /* The Embest and Ronetix CM boards and one Hynix NAND HY27UF(08/16)2G2B
+ * Series NAND (MT29F2G08ABAEAWP).
+ * This part has a capacity of 256Mx8bit () with spare 8Mx8 bit capacity.
+ * The device contains 2048 blocks, composed by 64 x 2112 byte pages.
+ * The effective size is approximately 256MiB.
+ *
+ * NAND is available on CS3.
+ */
+
+ if (cs == HSMC_CS3)
+ {
+ /* Make sure that the SMC peripheral is enabled. */
+
+ sam_hsmc_enableclk();
+
+ /* Configure the SMC */
+
+ regval = HSMC_SETUP_NWE_SETUP(1) | HSMC_SETUP_NCS_WRSETUP(1) |
+ HSMC_SETUP_NRD_SETUP(2) | HSMC_SETUP_NCS_RDSETUP(1);
+ putreg32(regval, SAM_HSMC_SETUP(HSMC_CS3));
+
+ regval = HSMC_PULSE_NWE_PULSE(5) | HSMC_PULSE_NCS_WRPULSE(7) |
+ HSMC_PULSE_NRD_PULSE(5) | HSMC_PULSE_NCS_RDPULSE(7);
+ putreg32(regval, SAM_HSMC_PULSE(HSMC_CS3));
+
+ regval = HSMC_CYCLE_NWE_CYCLE(8) | HSMC_CYCLE_NRD_CYCLE(9);
+ putreg32(regval, SAM_HSMC_CYCLE(HSMC_CS3));
+
+ regval = HSMC_TIMINGS_TCLR(3) | HSMC_TIMINGS_TADL(10) |
+ HSMC_TIMINGS_TAR(3) | HSMC_TIMINGS_TRR(4) |
+ HSMC_TIMINGS_TWB(5) | HSMC_TIMINGS_RBNSEL(3) |
+ HSMC_TIMINGS_NFSEL;
+ putreg32(regval, SAM_HSMC_TIMINGS(HSMC_CS3));
+
+ regval = HSMC_MODE_READMODE | HSMC_MODE_WRITEMODE |
+ HSMC_MODE_BIT_8 | HSMC_MODE_TDFCYCLES(1);
+ putreg32(regval, SAM_HSMC_MODE(HSMC_CS3));
+
+ /* Configure NAND PIO pins
+ *
+ * NAND Interface:
+ *
+ * NCS3/NANDCE - Dedicated pin; no configuration needed
+ * NANDCLE - PE21
+ * NANDALE - PE22
+ * NRD/NANDOE - Dedicated pin; no configuration needed
+ * NWE/NANDWE - Dedicated pin; no configuration needed
+ * NANDRDY - Dedicated pin; no configuration needed
+ * M_EBI_D0-7 - Dedicated pins; no configuration needed
+ */
+
+ sam_configpio(PIO_HSMC_NANDALE);
+ sam_configpio(PIO_HSMC_NANDCLE);
+
+ return OK;
+ }
+
+ return -ENODEV;
+}
+
+/****************************************************************************
+ * Name: sam_nand_automount
+ *
+ * Description:
+ * Initialize and configure the NAND on CS3
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_NAND
+int sam_nand_automount(int minor)
+{
+ FAR struct mtd_dev_s *mtd;
+ static bool initialized = false;
+ int ret;
+
+ /* Have we already initialized? */
+
+ if (!initialized)
+ {
+ /* Create and initialize an NAND MATD device */
+
+ mtd = sam_nand_initialize(HSMC_CS3);
+ if (!mtd)
+ {
+ ferr("ERROR: Failed to create the NAND driver on CS%d\n",
+ HSMC_CS3);
+ return -ENODEV;
+ }
+
+#if defined(CONFIG_SAMA5D3XPLAINED_NAND_FTL)
+ /* Use the FTL layer to wrap the MTD driver as a block driver */
+
+ ret = ftl_initialize(NAND_MINOR, mtd);
+ if (ret < 0)
+ {
+ ferr("ERROR: Failed to initialize the FTL layer: %d\n", ret);
+ return ret;
+ }
+
+#elif defined(CONFIG_SAMA5D3XPLAINED_NAND_NXFFS)
+ /* Initialize to provide NXFFS on the MTD interface */
+
+ ret = nxffs_initialize(mtd);
+ if (ret < 0)
+ {
+ ferr("ERROR: NXFFS initialization failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Mount the file system at /mnt/nand */
+
+ ret = mount(NULL, "/mnt/nand", "nxffs", 0, NULL);
+ if (ret < 0)
+ {
+ ferr("ERROR: Failed to mount the NXFFS volume: %d\n", errno);
+ return ret;
+ }
+#endif
+
+ /* Now we are initialized */
+
+ initialized = true;
+ }
+
+ return OK;
+}
+#endif
+
+#endif /* CONFIG_SAMA5_EBICS3_NAND */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_ostest.c b/boards/arm/sama5/sama5d2-xult/src/sam_ostest.c
new file mode 100644
index 0000000..e998ee2
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_ostest.c
@@ -0,0 +1,99 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_ostest.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "sama5d2-xult.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#undef HAVE_FPU
+#if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \
+ defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID)
+# define HAVE_FPU 1
+#endif
+
+#ifdef HAVE_FPU
+
+#if CONFIG_TESTING_OSTEST_FPUSIZE != (4*FPU_CONTEXT_REGS)
+# error "CONFIG_TESTING_OSTEST_FPUSIZE has the wrong size"
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint32_t g_saveregs[XCPTCONTEXT_REGS];
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/* Given an array of size CONFIG_TESTING_OSTEST_FPUSIZE, this function will
+ * return the current FPU registers.
+ */
+
+void arch_getfpu(FAR uint32_t *fpusave)
+{
+ irqstate_t flags;
+
+ /* Take a snapshot of the thread context right now */
+
+ flags = enter_critical_section();
+ up_saveusercontext(g_saveregs);
+
+ /* Return only the floating register values */
+
+ memcpy(fpusave, &g_saveregs[REG_S0], (4*FPU_CONTEXT_REGS));
+ leave_critical_section(flags);
+}
+
+/* Given two arrays of size CONFIG_TESTING_OSTEST_FPUSIZE this function
+ * will compare them and return true if they are identical.
+ */
+
+bool arch_cmpfpu(FAR const uint32_t *fpusave1, FAR const uint32_t *fpusave2)
+{
+ return memcmp(fpusave1, fpusave2, (4*FPU_CONTEXT_REGS)) == 0;
+}
+
+#endif /* HAVE_FPU */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_pwm.c b/boards/arm/sama5/sama5d2-xult/src/sam_pwm.c
new file mode 100644
index 0000000..f3608f8
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_pwm.c
@@ -0,0 +1,147 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_pwm.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <nuttx/timers/pwm.h>
+
+#include <arch/board/board.h>
+
+#include "sam_pwm.h"
+#include "sama5d2-xult.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* PWM.
+ * There are no dedicated PWM output pins available to the user for PWM
+ * testing.
+ * Care must be taken because all PWM output pins conflict with some other
+ * usage of the pin by other devices:
+ *
+ * -----+---+---+----+--------------------
+ * PWM PIN PER PIO CONFLICTS
+ * -----+---+---+----+--------------------
+ * PWM0 FI B PC28 SPI1, ISI
+ * H B PB0 GMAC
+ * B PA20 LCDC, ISI
+ * L B PB1 GMAC
+ * B PA21 LCDC, ISI
+ * -----+---+---+----+--------------------
+ * PWM1 FI B PC31 HDMI
+ * H B PB4 GMAC
+ * B PA22 LCDC, ISI
+ * L B PB5 GMAC
+ * B PE31 ISI, HDMI
+ * B PA23 LCDC, ISI
+ * -----+---+---+----+--------------------
+ * PWM2 FI B PC29 UART0, ISI, HDMI
+ * H C PD5 HSMCI0
+ * B PB8 GMAC
+ * L C PD6 HSMCI0
+ * B PB9 GMAC
+ * -----+---+---+----+--------------------
+ * PWM3 FI C PD16 SPI0, Audio
+ * H C PD7 HSMCI0
+ * B PB12 GMAC
+ * L C PD8 HSMCI0
+ * B PB13 GMAC
+ * -----+---+---+----+--------------------
+ */
+
+#ifndef CONFIG_SAMA5D3XPLAINED_CHANNEL
+# if defined(CONFIG_SAMA5_PWM_CHAN0)
+# warning Assuming PWM channel 0
+# define CONFIG_SAMA5D3XPLAINED_CHANNEL 0
+# elif defined(CONFIG_SAMA5_PWM_CHAN1)
+# warning Assuming PWM channel 1
+# define CONFIG_SAMA5D3XPLAINED_CHANNEL 1
+# elif defined(CONFIG_SAMA5_PWM_CHAN2)
+# warning Assuming PWM channel 2
+# define CONFIG_SAMA5D3XPLAINED_CHANNEL 2
+# elif defined(CONFIG_SAMA5_PWM_CHAN3)
+# warning Assuming PWM channel 3
+# define CONFIG_SAMA5D3XPLAINED_CHANNEL 3
+# endif
+#endif
+
+#if defined(CONFIG_PWM) && defined(CONFIG_SAMA5_PWM)
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_pwm_setup
+ *
+ * Description:
+ * Initialize PWM and register the PWM device.
+ *
+ ****************************************************************************/
+
+int sam_pwm_setup(void)
+{
+ static bool initialized = false;
+ struct pwm_lowerhalf_s *pwm;
+ int ret;
+
+ /* Have we already initialized? */
+
+ if (!initialized)
+ {
+ /* Call sam_pwminitialize() to get an instance of the PWM interface */
+
+ pwm = sam_pwminitialize(CONFIG_SAMA5D3XPLAINED_CHANNEL);
+ if (!pwm)
+ {
+ _err("ERROR: Failed to get the SAMA5 PWM lower half\n");
+ return -ENODEV;
+ }
+
+ /* Register the PWM driver at "/dev/pwm0" */
+
+ ret = pwm_register("/dev/pwm0", pwm);
+ if (ret < 0)
+ {
+ aerr("ERROR: pwm_register failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Now we are initialized */
+
+ initialized = true;
+ }
+
+ return OK;
+}
+
+#endif /* CONFIG_PWM */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_sdram.c b/boards/arm/sama5/sama5d2-xult/src/sam_sdram.c
new file mode 100644
index 0000000..9dcb1c6
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_sdram.c
@@ -0,0 +1,615 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_sdram.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include "up_arch.h"
+
+#include "sam_periphclks.h"
+#include "hardware/sam_memorymap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_sfr.h"
+#include "hardware/sam_mpddrc.h"
+
+#include "sama5d2-xult.h"
+
+/* This file requires:
+ *
+ * CONFIG_SAMA5_DDRCS -- DRAM support is enabled, and
+ * !CONFIG_SAMA5_BOOT_SDRAM - We did not boot into SRAM.
+ */
+
+#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* SDRAM differences */
+
+#if defined(CONFIG_SAMA5D3XPLAINED_MT47H128M16RT)
+
+ /* Used for SDRAM command handshaking */
+
+# define DDR2_BA0 (1 << 26)
+# define DDR2_BA1 (1 << 27)
+
+#elif defined(CONFIG_SAMA5D3XPLAINED_MT47H64M16HR)
+
+ /* Used for SDRAM command handshaking */
+
+# define DDR2_BA0 (1 << 25)
+# define DDR2_BA1 (1 << 26)
+
+#else
+# error Unknown SDRAM type
+#endif
+
+/* The delay loop in sam_sdram_delay requires 6 core cycles per iteration.
+ *
+ * At 384MHz:
+ *
+ * (6 cycles/iteration) / (0.384 cycles/nanosecond) =
+ * 15.6250 nanoseconds per iteration
+ *
+ * At 396MHz:
+ *
+ * (6 cycles/iteration) / (0.396 cycles/nanosecond) =
+ * 15.1515 nanoseconds per iteration
+ *
+ * At 528MHz:
+ *
+ * (6 cycles/iteration) / (0.528 cycles/nanosecond) =
+ * 11.3636 nanoseconds per iteration
+ */
+
+#define LOOP_GUARD 100
+# define CYCLES_TO_COUNT(cycles) (((cycles) / 6) + LOOP_GUARD)
+
+#if defined(CONFIG_SAMA5D3XPLAINED_384MHZ)
+# define NSEC_TO_COUNT(nsec) ((((nsec) * 1000) / 15625) + LOOP_GUARD)
+# define USEC_TO_COUNT(usec) ((((usec) * 1000000) / 15625) + LOOP_GUARD)
+#elif defined(CONFIG_SAMA5D3XPLAINED_528MHZ)
+# define NSEC_TO_COUNT(nsec) ((((nsec) * 1000) / 11364) + LOOP_GUARD)
+# define USEC_TO_COUNT(usec) ((((usec) * 1000000) / 11364) + LOOP_GUARD)
+#else /* #elif defined(CONFIG_SAMA5D3XPLAINED_396MHZ) */
+# define NSEC_TO_COUNT(nsec) ((((nsec) * 1000) / 15152) + LOOP_GUARD)
+# define USEC_TO_COUNT(usec) ((((usec) * 1000000) / 15152) + LOOP_GUARD)
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_sdram_delay
+ *
+ * Description:
+ * Precision delay function for SDRAM configuration.
+ *
+ * This delay loop requires 6 core cycles per iteration. The actual
+ * amount of time delayed will then vary with PCK.
+ *
+ ****************************************************************************/
+
+static inline void sam_sdram_delay(unsigned int loops)
+{
+ volatile unsigned int i;
+
+ for (i = 0; i < loops; i++)
+ {
+ asm("nop");
+ }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_sdram_config
+ *
+ * Description:
+ * Configures DDR2 (MT47H128M16RT 128MB or, optionally, MT47H64M16HR)
+ *
+ * Per the SAMA5D3-Xplained User guide:
+ * "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte).
+ * The board includes 2 Gbits of on-board soldered DDR2 (double data rate)
+ * SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from Micron
+ * for a total of 512 MBytes of DDR2 memory.
+ * The memory bus is 32 bits wide and operates with a frequency of up
+ * to 166 MHz."
+ *
+ * From the Atmel Code Example:
+ * MT47H64M16HR : 8 Meg x 16 x 8 banks
+ * Refresh count: 8K
+ * Row address: A[12:0] (8K)
+ * Column address A[9:0] (1K)
+ * Bank address BA[2:0] a(24,25) (8)
+ *
+ * This logic was taken from Atmel sample code for the SAMA5D3x-EK.
+ *
+ * Input Parameters:
+ * devtype - Either DDRAM_MT47H128M16RT or DDRAM_MT47H64M16HR
+ *
+ * Assumptions:
+ * The DDR memory regions is configured as strongly ordered memory. When
+ * we complete initialization of SDRAM and it is ready for use, we will
+ * make DRAM into normal memory.
+ *
+ ****************************************************************************/
+
+void sam_sdram_config(void)
+{
+ volatile uint8_t *ddr = (uint8_t *)SAM_DDRCS_VSECTION;
+ uint32_t regval;
+
+ /* Enable x2 clocking to the MPDDRC */
+
+ sam_mpddrc_enableclk();
+
+ /* Enable DDR clocking */
+
+ regval = getreg32(SAM_PMC_SCER);
+ regval |= PMC_DDRCK;
+ putreg32(regval, SAM_PMC_SCER);
+
+ /* Clear the low power register */
+
+ putreg32(0, SAM_MPDDRC_LPR);
+
+ /* Enable autofresh during calibration (undocumented) */
+
+ regval = getreg32(SAM_MPDDRC_HS);
+ regval |= MPDDRC_HS_AUTOREFRESH_CAL;
+ putreg32(regval, SAM_MPDDRC_HS);
+
+ /* Force DDR_DQ and DDR_DQS input buffer always on */
+
+ regval = getreg32(SAM_SFR_DDRCFG);
+ regval |= SFR_FDQIEN | SFR_FDQSIEN;
+ putreg32(regval, SAM_SFR_DDRCFG);
+
+ /* Configure the slave offset register */
+
+ regval = MPDDRC_DLL_SOR_S0OFF(1) | /* DLL Slave 0 Delay Line Offset */
+ MPDDRC_DLL_SOR_S1OFF(0) | /* DLL Slave 1 Delay Line Offset */
+ MPDDRC_DLL_SOR_S2OFF(1) | /* DLL Slave 2 Delay Line Offset */
+ MPDDRC_DLL_SOR_S3OFF(1); /* DLL Slave 3 Delay Line Offset */
+ putreg32(regval, SAM_MPDDRC_DLL_SOR);
+
+ /* Configure the master offset register (including upper mystery bits) */
+
+ regval = MPDDRC_DLL_MOR_MOFF(7) | /* DLL Master Delay Line Offset */
+ MPDDRC_DLL_MOR_CLK90OFF(31) | /* DLL CLK90 Delay Line Offset */
+ MPDDRC_DLL_MOR_SELOFF | /* DLL Offset Selection */
+ MPDDRC_DLL_MOR_KEY; /* Undocumented key */
+ putreg32(regval, SAM_MPDDRC_DLL_MOR);
+
+ /* Configure the I/O calibration register */
+
+ regval = getreg32(SAM_MPDDRC_IO_CALIBR);
+ regval &= ~(MPDDRC_IO_CALIBR_RDIV_MASK | MPDDRC_IO_CALIBR_TZQIO_MASK);
+ regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3));
+ putreg32(regval, SAM_MPDDRC_IO_CALIBR);
+
+ /* Force DDR_DQ and DDR_DQS input buffer always on */
+
+ putreg32(SFR_FDQIEN | SFR_FDQSIEN, SAM_SFR_DDRCFG);
+
+ /* Step 1: Program the memory device type
+ *
+ * DBW = 0 (32-bit bus wide)
+ * Memory Device = DDR2-SDRAM
+ */
+
+ putreg32(MPDDRC_MD_DDR2_SDRAM, SAM_MPDDRC_MD);
+
+ /* Step 2: Program the features of DDR2-SDRAM device into the Timing
+ * Register
+ */
+
+#if defined(CONFIG_SAMA5D3XPLAINED_MT47H128M16RT)
+
+ /* For MT47H128M16RT
+ *
+ * NC = 10 DDR column bits
+ * NR = 14 DDR row bits
+ * CAS = DDR2/LPDDR2 CAS Latency 4
+ * DLL = Disable reset (0)
+ * DIC_DS = 0
+ * DIS_DLL = Enable PLL (0)
+ * ZQ = Calibration command after initialization (0)
+ * OCD = OCD calibration mode exit, maintain setting (0)
+ * DQMS = Not shared (0)
+ * ENDRM = Disable read measure (0)
+ * NB = 8 banks
+ * NDQS = Not DQS disabled
+ * DECODE = Sequential decoding (0)
+ * UNAL = Unaliged access supported
+ */
+
+ regval = MPDDRC_CR_NC_10 | /* Number of Column Bits */
+ MPDDRC_CR_NR_14 | /* Number of Row Bits */
+ MPDDRC_CR_CAS_4 | /* CAS Latency */
+ MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */
+ MPDDRC_CR_8BANKS | /* Number of Banks */
+ MPDDRC_CR_NDQS | /* Not DQS */
+ MPDDRC_CR_UNAL; /* upport Unaligned Access */
+
+#elif defined(CONFIG_SAMA5D3XPLAINED_MT47H64M16HR)
+ /* For MT47H64M16HR
+ *
+ * NC = 10 DDR column bits
+ * NR = 13 DDR row bits
+ * CAS = DDR2/LPDDR2 CAS Latency 3
+ * DLL = Disable reset (0)
+ * DIC_DS = 0
+ * DIS_DLL = Enable PLL (0)
+ * ZQ = Calibration command after initialization (0)
+ * OCD = OCD calibration mode exit, maintain setting (0)
+ * DQMS = Not shared (0)
+ * ENDRM = Disable read measure (0)
+ * NB = 8 banks
+ * NDQS = Not DQS disabled
+ * DECODE = Sequential decoding (0)
+ * UNAL = Unaliged access supported
+ */
+
+ regval = MPDDRC_CR_NC_10 | /* Number of Column Bits */
+ MPDDRC_CR_NR_13 | /* Number of Row Bits */
+ MPDDRC_CR_CAS_3 | /* CAS Latency */
+ MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */
+ MPDDRC_CR_8BANKS | /* Number of Banks */
+ MPDDRC_CR_NDQS | /* Not DQS */
+ MPDDRC_CR_UNAL; /* upport Unaligned Access */
+
+#else
+# error Unknown SDRAM type
+#endif
+
+ putreg32(regval, SAM_MPDDRC_CR);
+
+ /* Configure the Timing Parameter 0 Register */
+
+ regval = MPDDRC_TPR0_TRAS(6) | /* Active to Precharge Delay: 6 * 7.5 = 45 ns */
+ MPDDRC_TPR0_TRCD(2) | /* Row to Column Delay: 2 * 7.5 = 15 ns */
+ MPDDRC_TPR0_TWR(2) | /* Write Recovery Delay: 3 * 7.5 = 22.5 ns */
+ MPDDRC_TPR0_TRC(8) | /* Row Cycle Delay: 8 * 7.5 = 60 ns */
+ MPDDRC_TPR0_TRP(2) | /* Row Precharge Delay: 2 * 7.5 = 15 ns */
+ MPDDRC_TPR0_TRRD(1) | /* Active BankA to Active BankB: 2 * 7.5 = 15 ns */
+ MPDDRC_TPR0_TWTR(2) | /* Internal Write to Read Delay: 2 clock cycle */
+ MPDDRC_TPR0_TMRD(2); /* Load Mode Register Command to
+ * Activate or Refresh Command: 2 clock
+ * cycles
+ */
+ putreg32(regval, SAM_MPDDRC_TPR0);
+
+ /* Configure the Timing Parameter 1 Register */
+
+ regval = MPDDRC_TPR1_TRFC(14) | /* Row Cycle Delay:
+ * 18 * 7.5 = 135 ns
+ * (min 127.5 ns for 1Gb DDR)
+ */
+ MPDDRC_TPR1_TXSNR(16) | /* Exit Self Refresh Delay to Non Read
+ * Command:
+ * 20 * 7.5 > 142.5ns TXSNR: Exit self
+ * refresh delay to Non Read command
+ */
+ MPDDRC_TPR1_TXSRD(208) | /* Exit Self Refresh Delay to Read
+ * Command:
+ * min 200 clock cycles, TXSRD: Exit
+ * self refresh delay to Read command
+ */
+ MPDDRC_TPR1_TXP(2); /* Exit Power-down Delay to First
+ * Command:
+ * 2 * 7.5 = 15 ns
+ */
+ putreg32(regval, SAM_MPDDRC_TPR1);
+
+ /* Configure the Timing Parameter 2 Register */
+
+ regval = MPDDRC_TPR2_TXARD(7) | /* Exit Active Power Down Delay to
+ * Read Command in Mode 'Fast Exit':
+ * min 2 clock cycles
+ */
+ MPDDRC_TPR2_TXARDS(7) | /* Exit Active Power Down Delay to
+ * Read Command in Mode 'Slow Exit':
+ * min 7 clock cycles
+ */
+ MPDDRC_TPR2_TRPA(2) | /* Row Precharge All Delay:
+ * min 18ns
+ */
+ MPDDRC_TPR2_TRTP(2) | /* Four Active Windows:
+ * 2 * 7.5 = 15 ns
+ * (min 7.5ns)
+ */
+ MPDDRC_TPR2_TFAW(10);
+ putreg32(regval, SAM_MPDDRC_TPR2);
+
+ /* DDRSDRC Low-power Register */
+
+ sam_sdram_delay(USEC_TO_COUNT(200));
+
+ regval = MPDDRC_LPR_LPCB_DISABLED | /* Low-power Feature is inhibited */
+ MPDDRC_LPR_TIMEOUT_0CLKS | /* Activates low-power mode after the end of transfer */
+ MPDDRC_LPR_APDE_FAST; /* Active Power Down Exit Time */
+ putreg32(regval, SAM_MPDDRC_LPR);
+
+ /* Step 3: An NOP command is issued to the DDR2-SDRAM. Program the NOP
+ * command into the Mode Register, the application must set MODE to 1 in
+ * the Mode Register.
+ */
+
+ putreg32(MPDDRC_MR_MODE_NOP, SAM_MPDDRC_MR);
+
+ /* Perform a write access to any DDR2-SDRAM address to acknowledge this
+ * command.
+ */
+
+ *ddr = 0;
+
+ /* Now clocks which drive DDR2-SDRAM device are enabled.
+ *
+ * A minimum pause of 200 usec is provided to precede any signal toggle.
+ * (6 core cycles per iteration, core is at 396MHz: min 13200 loops)
+ */
+
+ sam_sdram_delay(USEC_TO_COUNT(200));
+
+ /* Step 4: An NOP command is issued to the DDR2-SDRAM */
+
+ putreg32(MPDDRC_MR_MODE_NOP, SAM_MPDDRC_MR);
+
+ /* Perform a write access to any DDR2-SDRAM address to
+ * acknowledge this command.
+ */
+
+ *ddr = 0;
+
+ /* Now CKE is driven high. */
+
+ /* Wait 400 ns min */
+
+ sam_sdram_delay(NSEC_TO_COUNT(400));
+
+ /* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */
+
+ putreg32(MPDDRC_MR_MODE_PRCGALL, SAM_MPDDRC_MR);
+
+ /* Perform a write access to any DDR2-SDRAM address to
+ * acknowledge this command.
+ */
+
+ *ddr = 0;
+
+ /* Wait 400 ns min */
+
+ sam_sdram_delay(NSEC_TO_COUNT(400));
+
+ /* Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose
+ * between commercialor high temperature operations.
+ *
+ * The write address must be chosen so that BA[1] is set to 1 and BA[0] is
+ * set to 0.
+ */
+
+ putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR);
+ *((volatile uint8_t *)(ddr + DDR2_BA1)) = 0;
+
+ /* Wait 2 cycles min */
+
+ sam_sdram_delay(100); /* CYCLES_TO_COUNT(2) */
+
+ /* Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set
+ * all registers to 0.
+ *
+ * The write address must be chosen so that BA[1] is set to 1 and BA[0] is
+ * set to 1.
+ */
+
+ putreg32(MPDDRC_MR_MODE_LMR, SAM_MPDDRC_MR);
+ *((volatile uint8_t *)(ddr + DDR2_BA1 + DDR2_BA0)) = 0;
+
+ /* Wait 2 cycles min */
+
+ sam_sdram_delay(100); /* CYCLES_TO_COUNT(2) */
+
+ /* Step 8: An Extended Mode Register set (EMRS1) cycle
+ * is issued to enable DLL.
+ *
+ * The write address must be chosen so that BA[1] is set to
+ * 0 and BA[0] is set to 1.
+ */
+
+ putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR);
+ *((volatile uint8_t *)(ddr + DDR2_BA0)) = 0;
+
+ /* An additional 200 cycles of clock are required for locking DLL */
+
+ sam_sdram_delay(10000); /* CYCLES_TO_COUNT(200) */
+
+ /* Step 9: Program DLL field into the Configuration Register. */
+
+ regval = getreg32(SAM_MPDDRC_CR);
+ regval |= MPDDRC_CR_DLL;
+ putreg32(regval, SAM_MPDDRC_CR);
+
+ /* Step 10: A Mode Register set (MRS) cycle is issued to reset DLL.
+ *
+ * The write address must be chosen so that BA[1:0] bits are set to 0.
+ */
+
+ putreg32(MPDDRC_MR_MODE_LMR, SAM_MPDDRC_MR);
+ *ddr = 0;
+
+ /* Wait 2 cycles min */
+
+ sam_sdram_delay(100); /* CYCLES_TO_COUNT(2) */
+
+ /* Step 11: An all banks precharge command is issued to the DDR2-SDRAM.
+ *
+ * Perform a write access to any DDR2-SDRAM address to acknowledge this
+ * command
+ */
+
+ putreg32(MPDDRC_MR_MODE_PRCGALL, SAM_MPDDRC_MR);
+ *ddr = 0;
+
+ /* Wait 2 cycles min */
+
+ sam_sdram_delay(100); /* CYCLES_TO_COUNT(2) */
+
+ /* Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto
+ * refresh command (CBR) into the Mode Register.
+ *
+ * Perform a write access to any DDR2-SDRAM address to acknowledge this
+ * command.
+ */
+
+ putreg32(MPDDRC_MR_MODE_RFSH, SAM_MPDDRC_MR);
+ *ddr = 0;
+
+ /* Wait 2 cycles min */
+
+ sam_sdram_delay(100); /* CYCLES_TO_COUNT(2) */
+
+ /* Configure 2nd CBR.
+ *
+ * Perform a write access to any DDR2-SDRAM address to
+ * acknowledge this command.
+ */
+
+ putreg32(MPDDRC_MR_MODE_RFSH, SAM_MPDDRC_MR);
+ *ddr = 0;
+
+ /* Wait 2 cycles min */
+
+ sam_sdram_delay(100); /* CYCLES_TO_COUNT(2) */
+
+ /* Step 13: Program DLL field into the Configuration Register to low
+ * (Disable DLL reset).
+ */
+
+ regval = getreg32(SAM_MPDDRC_CR);
+ regval &= ~MPDDRC_CR_DLL;
+ putreg32(regval, SAM_MPDDRC_CR);
+
+ /* Step 14: A Mode Register set (MRS) cycle is issued to program the
+ * parameters of the DDR2-SDRAM devices.
+ *
+ * The write address must be chosen so that BA[1:0] are set to 0.
+ */
+
+ putreg32(MPDDRC_MR_MODE_LMR, SAM_MPDDRC_MR);
+ *ddr = 0;
+
+ /* Wait 2 cycles min */
+
+ sam_sdram_delay(100); /* CYCLES_TO_COUNT(2) */
+
+ /* Step 15: Program OCD field into the Configuration Register to high (OCD
+ * calibration default).
+ */
+
+ regval = getreg32(SAM_MPDDRC_CR);
+ regval |= MPDDRC_CR_OCD_DEFAULT;
+ putreg32(regval, SAM_MPDDRC_CR);
+
+ /* Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD
+ * default value.
+ *
+ * The write address must be chosen so that BA[1] is set to 0 and BA[0] is
+ * set to 1.
+ */
+
+ putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR);
+ *((volatile uint8_t *)(ddr + DDR2_BA0)) = 0;
+
+ /* Wait 2 cycles min */
+
+ sam_sdram_delay(100); /* CYCLES_TO_COUNT(2) */
+
+ /* Step 17: Program OCD field into the Configuration Register to low (OCD
+ * calibration mode exit).
+ */
+
+#if 0
+ regval = getreg32(SAM_MPDDRC_CR);
+ regval &= ~MPDDRC_CR_OCD_MASK;
+ putreg32(regval, SAM_MPDDRC_CR);
+#endif
+
+ /* Step 18: An Extended Mode Register set (EMRS1) cycle is issued to
+ * enable OCD exit.
+ *
+ * The write address must be chosen so that BA[1] is set to 0 and BA[0] is
+ * set to 1.
+ */
+
+ putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR);
+ *((volatile uint8_t *)(ddr + DDR2_BA0)) = 0;
+
+ /* Wait 2 cycles min */
+
+ sam_sdram_delay(100); /* CYCLES_TO_COUNT(2) */
+
+ /* Step 19,20: A mode Normal command is provided. Program the Normal mode
+ * into Mode Register.
+ */
+
+ putreg32(MPDDRC_MR_MODE_NORMAL, SAM_MPDDRC_MR);
+ *ddr = 0;
+
+ /* Step 21: Write the refresh rate into the count field in the Refresh
+ * Timer register. The DDR2-SDRAM device requires a refresh every 15.625
+ * usec or 7.81 usec.
+ *
+ * With a 100MHz frequency, the refresh timer count register must to be
+ * set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781
+ * i.e. 0x030d.
+ */
+
+ /* For MT47H64M16HR, The refresh period is 64ms (commercial), This equates
+ * to an average refresh rate of 7.8125usec (commercial), To ensure all
+ * rows of all banks are properly refreshed, 8192 REFRESH commands must be
+ * issued every 64ms (commercial)
+ */
+
+ /* ((64 x 10(^-3))/8192) x133 x (10^6) */
+
+ /* Set Refresh timer 7.8125 us */
+
+ putreg32(MPDDRC_RTR_COUNT(300), SAM_MPDDRC_RTR);
+
+ /* OK now we are ready to work on the DDRSDR */
+
+ /* Wait for end of calibration */
+
+ sam_sdram_delay(500);
+}
+
+#endif /* CONFIG_SAMA5_DDRCS && !CONFIG_SAMA5_BOOT_SDRAM */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_spi.c b/boards/arm/sama5/sama5d2-xult/src/sam_spi.c
new file mode 100644
index 0000000..88bf7f6
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_spi.c
@@ -0,0 +1,179 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_spi.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/spi/spi.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "sam_pio.h"
+#include "sam_spi.h"
+#include "sama5d2-xult.h"
+
+#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_spidev_initialize
+ *
+ * Description:
+ * Called to configure SPI chip select PIO pins for the SAMA5D3-Xplained
+ * board.
+ *
+ ****************************************************************************/
+
+void weak_function sam_spidev_initialize(void)
+{
+#ifdef CONFIG_SAMA5_SPI0
+#ifdef CONFIG_MTD_AT25
+ /* The AT25 serial FLASH connects using NPCS0 */
+
+ sam_configpio(PIO_AT25_NPCS0);
+#endif
+#endif
+
+#ifdef CONFIG_SAMA5_SPI1
+#endif
+}
+
+/****************************************************************************
+ * Name: sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata
+ *
+ * Description:
+ * These external functions must be provided by board-specific logic.
+ * They include:
+ *
+ * o sam_spi[0|1]select is a functions tomanage the board-specific chip
+ * selects
+ * o sam_spi[0|1]status and sam_spi[0|1]cmddata:
+ * Implementations of the status and cmddata methods of the SPI interface
+ * defined by struct spi_ops_(see include/nuttx/spi/spi.h).
+ * All other methods including sam_spibus_initialize()) are provided by
+ * common SAM3/4 logic.
+ *
+ * To use this common SPI logic on your board:
+ *
+ * 1. Provide logic in sam_boardinitialize() to configure SPI chip select
+ * pins.
+ * 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in
+ * your board-specific logic.
+ * These functions will perform chip selection and status operations
+ * using PIOs in the way your board is configured.
+ * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
+ * sam_spi[0|1]cmddata() functions in your board-specific logic. This
+ * function will perform cmd/data selection operations using PIOs in
+ * the way your board is configured.
+ * 3. Add a call to sam_spibus_initialize() in your low level application
+ * initialization logic
+ * 4. The handle returned by sam_spibus_initialize() may then be used to
+ * bind the SPI driver to higher level logic (e.g., calling
+ * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ * the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_spi[0|1]select
+ *
+ * Description:
+ * PIO chip select pins may be programmed by the board specific logic in
+ * one of two different ways. First, the pins may be programmed as SPI
+ * peripherals. In that case, the pins are completely controlled by the
+ * SPI driver. This method still needs to be provided, but it may be only
+ * a stub.
+ *
+ * An alternative way to program the PIO chip select pins is as a normal
+ * PIO output. In that case, the automatic control of the CS pins is
+ * bypassed and this function must provide control of the chip select.
+ * NOTE: In this case, the PIO output pin does *not* have to be the
+ * same as the NPCS pin normal associated with the chip select number.
+ *
+ * Input Parameters:
+ * devid - Identifies the (logical) device
+ * selected - TRUE:Select the device, FALSE:De-select the device
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMA5_SPI0
+void sam_spi0select(uint32_t devid, bool selected)
+{
+#ifdef CONFIG_MTD_AT25
+ /* The AT25 serial FLASH connects using NPCS0 */
+
+ if (devid == SPIDEV_FLASH(0))
+ {
+ sam_piowrite(PIO_AT25_NPCS0, !selected);
+ }
+#endif
+}
+#endif
+
+#ifdef CONFIG_SAMA5_SPI1
+void sam_spi1select(uint32_t devid, bool selected)
+{
+}
+#endif
+
+/****************************************************************************
+ * Name: sam_spi[0|1]status
+ *
+ * Description:
+ * Return status information associated with the SPI device.
+ *
+ * Input Parameters:
+ * devid - Identifies the (logical) device
+ *
+ * Returned Value:
+ * Bit-encoded SPI status (see include/nuttx/spi/spi.h.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMA5_SPI0
+uint8_t sam_spi0status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SAMA5_SPI0
+uint8_t sam_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif
+
+#endif /* CONFIG_SAMA5_SPI0 || CONFIG_SAMA5_SPI1 */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_usb.c b/boards/arm/sama5/sama5d2-xult/src/sam_usb.c
new file mode 100644
index 0000000..9434fb1
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_usb.c
@@ -0,0 +1,527 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_usb.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <sched.h>
+#include <errno.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/kthread.h>
+#include <nuttx/usb/usbdev.h>
+#include <nuttx/usb/usbhost.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include "up_arch.h"
+#include "sam_pio.h"
+#include "sam_usbhost.h"
+#include "hardware/sam_ohci.h"
+#include "sama5d2-xult.h"
+
+#if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_SAMA5D3XPLAINED_USBHOST_PRIO
+# define CONFIG_SAMA5D3XPLAINED_USBHOST_PRIO 50
+#endif
+
+#ifndef CONFIG_SAMA5D3XPLAINED_USBHOST_STACKSIZE
+# define CONFIG_SAMA5D3XPLAINED_USBHOST_STACKSIZE 1024
+#endif
+
+#ifdef HAVE_USBDEV
+# undef CONFIG_SAMA5_UHPHS_RHPORT1
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Retained device driver handles */
+
+#ifdef CONFIG_SAMA5_OHCI
+static struct usbhost_connection_s *g_ohciconn;
+#endif
+#ifdef CONFIG_SAMA5_EHCI
+static struct usbhost_connection_s *g_ehciconn;
+#endif
+
+/* Overcurrent interrupt handler */
+
+#if defined(HAVE_USBHOST) && defined(CONFIG_SAMA5_PIOD_IRQ)
+static xcpt_t g_ochandler;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: usbhost_waiter
+ *
+ * Description:
+ * Wait for USB devices to be connected to either the OHCI or EHCI hub.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_USBHOST
+#ifdef CONFIG_DEBUG_USB
+static int usbhost_waiter(struct usbhost_connection_s *dev,
+ const char *hcistr)
+#else
+static int usbhost_waiter(struct usbhost_connection_s *dev)
+#endif
+{
+ struct usbhost_hubport_s *hport;
+
+ uinfo("Running\n");
+ for (; ; )
+ {
+ /* Wait for the device to change state */
+
+ DEBUGVERIFY(CONN_WAIT(dev, &hport));
+ uinfo("%s\n", hport->connected ? "connected" : "disconnected");
+
+ /* Did we just become connected? */
+
+ if (hport->connected)
+ {
+ /* Yes.. enumerate the newly connected device */
+
+ CONN_ENUMERATE(dev, hport);
+ }
+ }
+
+ /* Keep the compiler from complaining */
+
+ return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: ohci_waiter
+ *
+ * Description:
+ * Wait for USB devices to be connected to the OHCI hub.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMA5_OHCI
+static int ohci_waiter(int argc, char *argv[])
+{
+#ifdef CONFIG_DEBUG_USB
+ return usbhost_waiter(g_ohciconn, "OHCI");
+#else
+ return usbhost_waiter(g_ohciconn);
+#endif
+}
+#endif
+
+/****************************************************************************
+ * Name: ehci_waiter
+ *
+ * Description:
+ * Wait for USB devices to be connected to the EHCI hub.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMA5_EHCI
+static int ehci_waiter(int argc, char *argv[])
+{
+#ifdef CONFIG_DEBUG_USB
+ return usbhost_waiter(g_ehciconn, "EHCI");
+#else
+ return usbhost_waiter(g_ehciconn);
+#endif
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_usbinitialize
+ *
+ * Description:
+ * Called from sam_usbinitialize very early in inialization to setup
+ * USB-related GPIO pins for the SAMA5D3-Xplained board.
+ *
+ * USB Ports
+ * The SAMA5D3 series-MB features three USB communication ports:
+ *
+ * 1. Port A Host High Speed (EHCI) and Full Speed (OHCI) multiplexed
+ * with USB Device High Speed Micro AB connector, J20
+ *
+ * 2. Port B Host High Speed (EHCI) and Full Speed (OHCI) standard type A
+ * connector, J19 upper port
+ *
+ * 3. Port C Host Full Speed (OHCI) only standard type A connector, J19
+ * lower port
+ *
+ * The two USB host ports (only) are equipped with 500-mA high-side power
+ * switch for self-powered and bus-powered applications.
+ *
+ * The USB device port A (J6) features a VBUS insert detection function.
+ *
+ * Port A
+ *
+ * PIO Signal Name Function
+ * ---- ----------- -----------------------------------------------------
+ * PE9 VBUS_SENSE VBus detection
+ *
+ * Note: No VBus power switch enable on port A. I think that this limits
+ * this port to a device port or as a host port for self-powered devices
+ * only.
+ *
+ * Port B
+ *
+ * PIO Signal Name Function
+ * ---- ----------- -----------------------------------------------------
+ * PE4 EN5V_USBB VBus power enable (via MN3 power switch). To the A1
+ * pin of J19 Dual USB A connector
+ *
+ * Port C
+ *
+ * PIO Signal Name Function
+ * ---- ----------- -----------------------------------------------------
+ * PE3 EN5V_USBC VBus power enable (via MN3 power switch). To the B1
+ * pin of J19 Dual USB A connector
+ *
+ * Both Ports B and C
+ *
+ * PIO Signal Name Function
+ * ---- ----------- -----------------------------------------------------
+ * PE5 OVCUR_USB Combined over-current indication from port A and B
+ *
+ * That offers a lot of flexibility. However, here we enable the ports only
+ * as follows:
+ *
+ * Port A -- USB device
+ * Port B -- EHCI host
+ * Port C -- OHCI host
+ *
+ ****************************************************************************/
+
+void weak_function sam_usbinitialize(void)
+{
+#ifdef HAVE_USBDEV
+ /* Configure Port A to support the USB device function */
+
+ sam_configpio(PIO_USBA_VBUS_SENSE); /* VBUS sense */
+
+ /* TODO: Configure an interrupt on VBUS sense */
+
+#endif
+
+#ifdef HAVE_USBHOST
+#ifdef CONFIG_SAMA5_UHPHS_RHPORT1
+ /* Configure Port A to support the USB OHCI/EHCI function */
+
+#ifdef PIO_USBA_VBUS_ENABLE /* SAMA5D3-Xplained has no port A VBUS enable */
+ sam_configpio(PIO_USBA_VBUS_ENABLE); /* VBUS enable, initially OFF */
+#endif
+#endif
+
+#ifdef CONFIG_SAMA5_UHPHS_RHPORT2
+ /* Configure Port B to support the USB OHCI/EHCI function */
+
+ sam_configpio(PIO_USBB_VBUS_ENABLE); /* VBUS enable, initially OFF */
+
+ /* Configure Port B VBUS overrcurrent detection */
+
+ sam_configpio(PIO_USBB_VBUS_OVERCURRENT); /* VBUS overcurrent */
+#endif
+#endif /* HAVE_USBHOST */
+}
+
+/****************************************************************************
+ * Name: sam_usbhost_initialize
+ *
+ * Description:
+ * Called at application startup time to initialize the USB host
+ * functionality.
+ * This function will start a thread that will monitor for device
+ * connection/disconnection events.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_USBHOST
+int sam_usbhost_initialize(void)
+{
+ pid_t pid;
+ int ret;
+
+ /* First, register all of the class drivers needed to support the drivers
+ * that we care about
+ */
+
+#ifdef CONFIG_USBHOST_HUB
+ /* Initialize USB hub class support */
+
+ ret = usbhost_hub_initialize();
+ if (ret < 0)
+ {
+ uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_USBHOST_MSC
+ /* Register theUSB host Mass Storage Class */
+
+ ret = usbhost_msc_initialize();
+ if (ret != OK)
+ {
+ uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_USBHOST_CDCACM
+ /* Register the CDC/ACM serial class */
+
+ ret = usbhost_cdcacm_initialize();
+ if (ret != OK)
+ {
+ uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_USBHOST_HIDKBD
+ /* Register the USB host HID keyboard class driver */
+
+ ret = usbhost_kbdinit();
+ if (ret != OK)
+ {
+ uerr("ERROR: Failed to register the KBD class\n");
+ }
+#endif
+
+ /* Then get an instance of the USB host interface. */
+
+#ifdef CONFIG_SAMA5_OHCI
+ /* Get an instance of the USB OHCI interface */
+
+ g_ohciconn = sam_ohci_initialize(0);
+ if (!g_ohciconn)
+ {
+ uerr("ERROR: sam_ohci_initialize failed\n");
+ return -ENODEV;
+ }
+
+ /* Start a thread to handle device connection. */
+
+ pid = kthread_create("OHCI Monitor", CONFIG_SAMA5D2XULT_USBHOST_PRIO,
+ CONFIG_SAMA5D2XULT_USBHOST_STACKSIZE,
+ (main_t)ohci_waiter, (FAR char * const *)NULL);
+ if (pid < 0)
+ {
+ uerr("ERROR: Failed to create ohci_waiter task: %d\n", ret);
+ return -ENODEV;
+ }
+#endif
+
+#ifdef CONFIG_SAMA5_EHCI
+ /* Get an instance of the USB EHCI interface */
+
+ g_ehciconn = sam_ehci_initialize(0);
+ if (!g_ehciconn)
+ {
+ uerr("ERROR: sam_ehci_initialize failed\n");
+ return -ENODEV;
+ }
+
+ /* Start a thread to handle device connection. */
+
+ pid = kthread_create("EHCI Monitor", CONFIG_SAMA5D2XULT_USBHOST_PRIO,
+ CONFIG_SAMA5D2XULT_USBHOST_STACKSIZE,
+ (main_t)ehci_waiter, (FAR char * const *)NULL);
+ if (pid < 0)
+ {
+ uerr("ERROR: Failed to create ehci_waiter task: %d\n", ret);
+ return -ENODEV;
+ }
+#endif
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: sam_usbhost_vbusdrive
+ *
+ * Description:
+ * Enable/disable driving of VBUS 5V output.
+ * This function must be provided by each platform that implements the
+ * OHCI or EHCI host interface
+ *
+ * Input Parameters:
+ * rhport - Selects root hub port to be powered host interface.
+ * See SAM_RHPORT_* definitions above.
+ * enable - true: enable VBUS power; false: disable VBUS power
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_USBHOST
+void sam_usbhost_vbusdrive(int rhport, bool enable)
+{
+ pio_pinset_t pinset = 0;
+
+ uinfo("RHPort%d: enable=%d\n", rhport + 1, enable);
+
+ /* Pick the PIO configuration associated with the selected root hub port */
+
+ switch (rhport)
+ {
+ case SAM_RHPORT1:
+#if !defined(CONFIG_SAMA5_UHPHS_RHPORT1)
+ uerr("ERROR: RHPort1 is not available in this configuration\n");
+ return;
+
+#elif !defined(PIO_USBA_VBUS_ENABLE)
+ /* SAMA5D2-XULT has no port A VBUS enable */
+
+ uerr("ERROR: RHPort1 has no VBUS enable\n");
+ return;
+#else
+ pinset = PIO_USBA_VBUS_ENABLE;
+ break;
+#endif
+
+ case SAM_RHPORT2:
+#ifndef CONFIG_SAMA5_UHPHS_RHPORT2
+ uerr("ERROR: RHPort2 is not available in this configuration\n");
+ return;
+#else
+ pinset = PIO_USBB_VBUS_ENABLE;
+ break;
+#endif
+
+ default:
+ uerr("ERROR: RHPort%d is not supported\n", rhport + 1);
+ return;
+ }
+
+ /* Then enable or disable VBUS power (active high) */
+
+ if (enable)
+ {
+ /* Enable the Power Switch by driving the enable pin high */
+
+ sam_piowrite(pinset, true);
+ }
+ else
+ {
+ /* Disable the Power Switch by driving the enable pin low */
+
+ sam_piowrite(pinset, false);
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: sam_setup_overcurrent
+ *
+ * Description:
+ * Setup to receive an interrupt-level callback if an overcurrent condition
+ * is detected on port B or C.
+ *
+ * REVISIT: Since this is a common signal, we will need to come up with
+ * some way to inform both EHCI and OHCI drivers when this error occurs.
+ *
+ * Input Parameters:
+ * handler - New overcurrent interrupt handler
+ *
+ * Returned Value:
+ * Old overcurrent interrupt handler
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_USBHOST
+xcpt_t sam_setup_overcurrent(xcpt_t handler)
+{
+#if defined(CONFIG_SAMA5_PIOD_IRQ) && (defined(CONFIG_SAMA5_UHPHS_RHPORT2) || \
+ defined(CONFIG_SAMA5_UHPHS_RHPORT3))
+
+ xcpt_t oldhandler;
+ irqstate_t flags;
+
+ /* Disable interrupts until we are done. This guarantees that the
+ * following operations are atomic.
+ */
+
+ flags = enter_critical_section();
+
+ /* Get the old interrupt handler and save the new one */
+
+ oldhandler = g_ochandler;
+ g_ochandler = handler;
+
+ /* Configure the interrupt */
+
+ sam_pioirq(PIO_USBBC_VBUS_OVERCURRENT);
+ irq_attach(IRQ_USBBC_VBUS_OVERCURRENT, handler, NULL);
+ sam_pioirqenable(IRQ_USBBC_VBUS_OVERCURRENT);
+
+ /* Return the old handler (so that it can be restored) */
+
+ leave_critical_section(flags);
+ return oldhandler;
+
+#else
+ return NULL;
+
+#endif
+}
+#endif /* CONFIG_SAMA5_PIOD_IRQ ... */
+
+/****************************************************************************
+ * Name: sam_usbsuspend
+ *
+ * Description:
+ * Board logic must provide the sam_usbsuspend logic if the USBDEV driver
+ * is used.
+ * This function is called whenever the USB enters or leaves suspend mode.
+ * This is an opportunity for the board logic to shutdown clocks, power,
+ * etc. while the USB is suspended.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBDEV
+void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume)
+{
+ uinfo("resume: %d\n", resume);
+}
+#endif
+#endif /* CONFIG_SAMA5_UHPHS || CONFIG_SAMA5_UDPHS */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_usbmsc.c b/boards/arm/sama5/sama5d2-xult/src/sam_usbmsc.c
new file mode 100644
index 0000000..5b83657
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_usbmsc.c
@@ -0,0 +1,91 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_usbmsc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <syslog.h>
+#include <errno.h>
+
+#include <nuttx/board.h>
+
+#include "sama5d2-xult.h"
+
+#ifdef CONFIG_USBMSC
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#ifndef HAVE_AT25
+# error AT25 Serial FLASH not supported
+#endif
+
+#ifndef CONFIG_SAMA5D3XPLAINED_AT25_FTL
+# error AT25 FTL support required (CONFIG_SAMA5D3XPLAINED_AT25_FTL)
+# undef HAVE_AT25
+#endif
+
+#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1
+# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0
+#endif
+
+#if CONFIG_SYSTEM_USBMSC_DEVMINOR1 != AT25_MINOR
+# error Confusion in the assignment of minor device numbers
+# undef HAVE_AT25
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_usbmsc_initialize
+ *
+ * Description:
+ * Perform architecture specific initialization as needed to establish
+ * the mass storage device that will be exported by the USB MSC device.
+ *
+ ****************************************************************************/
+
+int board_usbmsc_initialize(int port)
+{
+ /* Initialize the AT25 MTD driver */
+
+#ifdef HAVE_AT25
+ int ret = sam_at25_automount(AT25_MINOR);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: sam_at25_automount failed: %d\n", ret);
+ }
+
+ return ret;
+#else
+ return -ENODEV;
+#endif
+}
+
+#endif /* CONFIG_USBMSC */
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_userleds.c b/boards/arm/sama5/sama5d2-xult/src/sam_userleds.c
index 548df63..8da3692 100644
--- a/boards/arm/sama5/sama5d2-xult/src/sam_userleds.c
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_userleds.c
@@ -1,35 +1,20 @@
/****************************************************************************
- * boards/arm/sama5/sama5d2-xult/src/sam_userleds.c
+ * boards/arm/sama5/sama5d2-xult/src/sam_userleds.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
diff --git a/boards/arm/sama5/sama5d2-xult/src/sama5d2-xult.h b/boards/arm/sama5/sama5d2-xult/src/sama5d2-xult.h
index 8d944fe..43da228 100644
--- a/boards/arm/sama5/sama5d2-xult/src/sama5d2-xult.h
+++ b/boards/arm/sama5/sama5d2-xult/src/sama5d2-xult.h
@@ -1,35 +1,20 @@
/****************************************************************************
- * boards/arm/sama5/sama5d2-xult/src/sama5d2-xult.h
- *
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * boards/arm/sama5/sama5d2-xult/src/sama5d2-xult.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
@@ -57,6 +42,214 @@
/* Configuration ************************************************************/
+#define HAVE_HSMCI 1
+#define HAVE_AT25 1
+#define HAVE_NAND 1
+#define HAVE_USBHOST 1
+#define HAVE_USBDEV 1
+#define HAVE_USBMONITOR 1
+#define HAVE_NETWORK 1
+
+/* HSMCI */
+
+/* Can't support MMC/SD if the card interface(s) are not enable */
+
+#if !defined(CONFIG_SAMA5_HSMCI0) && !defined(CONFIG_SAMA5_HSMCI1)
+# undef HAVE_HSMCI
+#endif
+
+/* Can't support MMC/SD features if mountpoints are disabled */
+
+#if defined(HAVE_HSMCI) && defined(CONFIG_DISABLE_MOUNTPOINT)
+# warning Mountpoints disabled. No MMC/SD support
+# undef HAVE_HSMCI
+#endif
+
+/* We need PIO interrupts on PIOD to support card detect interrupts */
+
+#if defined(HAVE_HSMCI) && !defined(CONFIG_SAMA5_PIOD_IRQ)
+# warning PIOD interrupts not enabled. No MMC/SD support.
+# undef HAVE_HSMCI
+#endif
+
+/* NAND FLASH */
+
+/* Can't support the NAND device if NAND flash is not configured on EBI CS3 */
+
+#ifndef CONFIG_SAMA5_EBICS3_NAND
+# undef HAVE_NAND
+#endif
+
+/* Can't support NAND features if mountpoints are disabled or if we were not
+ * asked to mount the NAND part
+ */
+
+#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_SAMA5D3XPLAINED_NAND_BLOCKMOUNT)
+# undef HAVE_NAND
+#endif
+
+/* Can't support NAND if the MTD feature is not enabled */
+
+#if !defined(CONFIG_MTD) || !defined(CONFIG_MTD_NAND)
+# undef HAVE_NAND
+#endif
+
+/* If we are going to mount the NAND, then they user must also have told
+ * us what to do with it by setting one of CONFIG_SAMA5D3XPLAINED_NAND_FTL or
+ * CONFIG_SAMA5D3XPLAINED_NAND_NXFFS.
+ */
+
+#ifndef CONFIG_MTD
+# undef CONFIG_SAMA5D3XPLAINED_NAND_NXFFS
+# undef CONFIG_SAMA5D3XPLAINED_NAND_FTL
+#endif
+
+#if !defined(CONFIG_FS_NXFFS) || !defined(CONFIG_NXFFS_NAND)
+# undef CONFIG_SAMA5D3XPLAINED_NAND_NXFFS
+#endif
+
+#if !defined(CONFIG_SAMA5D3XPLAINED_NAND_FTL) && !defined(CONFIG_SAMA5D3XPLAINED_NAND_NXFFS)
+# undef HAVE_NAND
+#endif
+
+#if defined(CONFIG_SAMA5D3XPLAINED_NAND_FTL) && defined(CONFIG_SAMA5D3XPLAINED_NAND_NXFFS)
+# warning Both CONFIG_SAMA5D3XPLAINED_NAND_FTL and CONFIG_SAMA5D3XPLAINED_NAND_NXFFS are set
+# warning Ignoring CONFIG_SAMA5D3XPLAINED_NAND_NXFFS
+# undef CONFIG_SAMA5D3XPLAINED_NAND_NXFFS
+#endif
+
+/* AT25 Serial FLASH */
+
+/* Can't support the AT25 device if it SPI0 or AT25 support are not enabled */
+
+#if !defined(CONFIG_SAMA5_SPI0) || !defined(CONFIG_MTD_AT25)
+# undef HAVE_AT25
+#endif
+
+/* Can't support AT25 features if mountpoints are disabled or if we were not
+ * asked to mount the AT25 part
+ */
+
+#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_SAMA5D3XPLAINED_AT25_AUTOMOUNT)
+# undef HAVE_AT25
+#endif
+
+/* If we are going to mount the AT25, then they user must also have told
+ * us what to do with it by setting one of these.
+ */
+
+#ifndef CONFIG_FS_NXFFS
+# undef CONFIG_SAMA5D3XPLAINED_AT25_NXFFS
+#endif
+
+#if !defined(CONFIG_SAMA5D3XPLAINED_AT25_FTL) && !defined(CONFIG_SAMA5D3XPLAINED_AT25_NXFFS)
+# undef HAVE_AT25
+#endif
+
+#if defined(CONFIG_SAMA5D3XPLAINED_AT25_FTL) && defined(CONFIG_SAMA5D3XPLAINED_AT25_NXFFS)
+# warning Both CONFIG_SAMA5D3XPLAINED_AT25_FTL and CONFIG_SAMA5D3XPLAINED_AT25_NXFFS are set
+# warning Ignoring CONFIG_SAMA5D3XPLAINED_AT25_NXFFS
+# undef CONFIG_SAMA5D3XPLAINED_AT25_NXFFS
+#endif
+
+/* Assign minor device numbers. For example, if we also use MINOR number 0
+ * for the AT25, it should appear as /dev/mtdblock0
+ */
+
+#define _NAND_MINOR 0
+
+#ifdef HAVE_NAND
+# define NAND_MINOR _NAND_MINOR
+# define _AT25_MINOR (_NAND_MINOR+1)
+#else
+# define _AT25_MINOR _NAND_MINOR
+#endif
+
+#ifdef HAVE_AT25
+# define AT25_MINOR _AT25_MINOR
+#endif
+
+/* MMC/SD minor numbers: The NSH device minor extended is extended to
+ * support two devices. If CONFIG_NSH_MMCSDMINOR is zero, these will be:
+ * /dev/mmcsd0 and /dev/mmcsd1.
+ */
+
+#ifndef CONFIG_NSH_MMCSDMINOR
+# define CONFIG_NSH_MMCSDMINOR 0
+#endif
+
+#ifdef HAVE_HSMCI
+
+# define HSMCI0_SLOTNO 0
+# define HSMCI1_SLOTNO 1
+
+# ifdef CONFIG_SAMA5_HSMCI0
+# define HSMCI0_MINOR CONFIG_NSH_MMCSDMINOR
+# define HSMCI1_MINOR (CONFIG_NSH_MMCSDMINOR+1)
+# else
+# define HSMCI1_MINOR CONFIG_NSH_MMCSDMINOR
+# endif
+#else
+#endif
+
+/* USB Host / USB Device */
+
+/* Either CONFIG_SAMA5_UHPHS or CONFIG_SAMA5_UDPHS must be defined,
+ * or there is no USB of any kind.
+ */
+
+#if !defined(CONFIG_SAMA5_UHPHS)
+# undef CONFIG_SAMA5_OHCI
+# undef CONFIG_SAMA5_EHCI
+#endif
+
+#if !defined(CONFIG_SAMA5_UDPHS)
+# undef HAVE_USBDEV
+#endif
+
+/* CONFIG_USBDEV and CONFIG_USBHOST must also be defined */
+
+#if !defined(CONFIG_USBDEV)
+# undef HAVE_USBDEV
+#endif
+
+#if defined(CONFIG_USBHOST)
+# if !defined(CONFIG_SAMA5_OHCI) && !defined(CONFIG_SAMA5_EHCI)
+# warning CONFIG_USBHOST is defined, but neither CONFIG_SAMA5_OHCI nor CONFIG_SAMA5_EHCI are defined
+# endif
+#else
+# undef CONFIG_SAMA5_OHCI
+# undef CONFIG_SAMA5_EHCI
+#endif
+
+#if !defined(CONFIG_SAMA5_OHCI) && !defined(CONFIG_SAMA5_EHCI)
+# undef HAVE_USBHOST
+#endif
+
+/* Check if we should enable the USB monitor before starting NSH */
+
+#ifndef CONFIG_USBMONITOR
+# undef HAVE_USBMONITOR
+#endif
+
+#ifndef HAVE_USBDEV
+# undef CONFIG_USBDEV_TRACE
+#endif
+
+#ifndef HAVE_USBHOST
+# undef CONFIG_USBHOST_TRACE
+#endif
+
+#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE)
+# undef HAVE_USBMONITOR
+#endif
+
+/* Networking */
+
+#if !defined(CONFIG_NET) || (!defined(CONFIG_SAMA5_EMACA) && !defined(CONFIG_SAMA5_GMAC))
+# undef HAVE_NETWORK
+#endif
+
/* procfs File System */
#ifdef CONFIG_FS_PROCFS
@@ -107,6 +300,96 @@
PIO_INT_BOTHEDGES | PIO_PORT_PIOB | PIO_PIN6)
#define IRQ_BTN_USER SAM_IRQ_PB6
+/* HSMCI Card Slots *********************************************************/
+
+/* The SAMA5D2-XULT provides a SD memory card slots:
+ * a full size SD card slot (J19)
+ *
+ * The full size SD card slot connects via HSMCI0. The card detect discrete
+ * is available on PD17 (pulled high). The write protect discrete is tied to
+ * ground (via PP6) and not available to software. The slot supports 8-bit
+ * wide transfer mode, but the NuttX driver currently uses only the 4-bit
+ * wide transfer mode
+ *
+ * PD17 MCI0_CD
+ * PD1 MCI0_DA0
+ * PD2 MCI0_DA1
+ * PD3 MCI0_DA2
+ * PD4 MCI0_DA3
+ * PD5 MCI0_DA4
+ * PD6 MCI0_DA5
+ * PD7 MCI0_DA6
+ * PD8 MCI0_DA7
+ * PD9 MCI0_CK
+ * PD0 MCI0_CDA
+ */
+
+#define PIO_MCI0_CD (PIO_INPUT | PIO_CFG_DEFAULT | PIO_CFG_DEGLITCH | \
+ PIO_INT_BOTHEDGES | PIO_PORT_PIOA | PIO_PIN11)
+#define IRQ_MCI0_CD SAM_IRQ_PA11
+
+/* USB Ports ****************************************************************/
+
+/* The SAMA5D2-XULT features two USB communication ports:
+ *
+ * 1. Port A Host High Speed (EHCI) and Full Speed (OHCI) multiplexed with
+ * USB Device High Speed Micro AB connector, J23
+ *
+ * 2. Port B Host High Speed (EHCI) and Full Speed (OHCI) standard type A
+ * connector, J13
+ *
+ * The USB host port (only) is equipped with 500-mA high-side power
+ * switch for self-powered and bus-powered applications.
+ *
+ * The USB device port A (J6) features a VBUS insert detection function.
+ *
+ *
+ * Port A
+ *
+ * PIO Signal Name Function
+ * ---- ----------- -------------------------------------------------------
+ * PE9 VBUS_SENSE VBus detection
+ *
+ * Note: No VBus power switch enable on port A. I think that this limits
+ * this port to a device port or as a host port for self-powered devices
+ * only.
+ */
+
+#define PIO_USBA_VBUS_SENSE \
+ (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
+ PIO_INT_BOTHEDGES | PIO_PORT_PIOA | PIO_PIN31)
+#define IRQ_USBA_VBUS_SENSE \
+ SAM_IRQ_PA31
+
+/* Port B
+ *
+ * PIO Signal Name Function
+ * ---- ----------- -------------------------------------------------------
+ * PE3 EN5V_USBB VBus power enable via MN3 SP2526A-2E dual power
+ * switch. PE3 (EN5V_USBB)connects to ENB pin of MN3.
+ * MN3 OUTB (5V_USBB) is provided to pin 1 of J13 USB
+ * A connector
+ *
+ * Active high for SP2526A-1; active low for SP2526A-2
+ */
+
+#define PIO_USBB_VBUS_ENABLE \
+ (PIO_OUTPUT | PIO_CFG_DEFAULT | PIO_OUTPUT_SET | \
+ PIO_PORT_PIOB | PIO_PIN10)
+
+/* Ports B
+ *
+ * PIO Signal Name Function
+ * ---- ----------- -------------------------------------------------------
+ * PE5 OVCUR_USB Over-current indication from B
+ */
+
+#define PIO_USBB_VBUS_OVERCURRENT \
+ (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
+ PIO_INT_BOTHEDGES | PIO_PORT_PIOA | PIO_PIN29)
+#define IRQ_USBB_VBUS_OVERCURRENT \
+ SAM_IRQ_PA29
+
/****************************************************************************
* Public Types
****************************************************************************/
@@ -118,7 +401,7 @@
#ifndef __ASSEMBLY__
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
/****************************************************************************
@@ -131,5 +414,33 @@
int sam_bringup(void);
+/****************************************************************************
+ * Name: sam_usbinitialize
+ *
+ * Description:
+ * Called from sam_usbinitialize very early in initialization to setup
+ * USB-related PIO pins for the SAMA5D2-XULT board.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS)
+void weak_function sam_usbinitialize(void);
+#endif
+
+/****************************************************************************
+ * Name: stm32_usbhost_initialize
+ *
+ * Description:
+ * Called at application startup time to initialize the USB host
+ * functionality.
+ * This function will start a thread that will monitor for device
+ * connection/disconnection events.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_USBHOST
+int sam_usbhost_initialize(void);
+#endif
+
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM__SAMA5SAMA5D2_XULT_SRC_SAMA5D2_XULT_H */
diff --git a/boards/arm/sama5/sama5d3-xplained/src/sama5d3-xplained.h b/boards/arm/sama5/sama5d3-xplained/src/sama5d3-xplained.h
index b0cf5a6..180fcba 100644
--- a/boards/arm/sama5/sama5d3-xplained/src/sama5d3-xplained.h
+++ b/boards/arm/sama5/sama5d3-xplained/src/sama5d3-xplained.h
@@ -183,9 +183,9 @@
# define AT25_MINOR _AT25_MINOR
#endif
-/* MMC/SD minor numbers: The NSH device minor extended is extended to support
- * two devices. If CONFIG_NSH_MMCSDMINOR is zero, these will be: /dev/mmcsd0
- * and /dev/mmcsd1.
+/* MMC/SD minor numbers: The NSH device minor extended is extended to
+ * support two devices. If CONFIG_NSH_MMCSDMINOR is zero, these will be:
+ * /dev/mmcsd0 and /dev/mmcsd1.
*/
#ifndef CONFIG_NSH_MMCSDMINOR
@@ -319,12 +319,12 @@
/* HSMCI Card Slots *********************************************************/
-/* The SAMA5D3-Xplained provides a two SD memory card slots:
+/* The SAMA5D3-Xplained provides two SD memory card slots:
* (1) a full size SD card slot (J10), and
* (2) a microSD memory card slot (J11).
*
* The full size SD card slot connects via HSMCI0. The card detect discrete
- * is available on PD17 (pulled high). The write protect descrete is tied to
+ * is available on PD17 (pulled high). The write protect discrete is tied to
* ground (via PP6) and not available to software. The slot supports 8-bit
* wide transfer mode, but the NuttX driver currently uses only the 4-bit
* wide transfer mode
@@ -476,13 +476,14 @@
#ifdef CONFIG_SAMA5_GMAC
/* ETH0: Tri-Speed Ethernet PHY
*
- * The SAMA5D3 series-CM board is equipped with a MICREL PHY devices (MICREL
- * KSZ9021/31) operating at 10/100/1000 Mbps.
+ * The SAMA5D3 series-CM board is equipped with a MICREL PHY devices
+ * (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
* The board supports RGMII interface mode.
* The Ethernet interface consists of 4 pairs of low voltage differential
- * pair signals designated from TXRXP_A/TXRXM_A to TXRXP_D/TXRXM_D plus control
- * signals for link activity indicators. These signals can be used to connect
- * to a 10/100/1000 BaseT RJ45 connector integrated on the main board.
+ * pair signals designated from TXRXP_A/TXRXM_A to TXRXP_D/TXRXM_D plus
+ * control signals for link activity indicators. These signals can be used
+ * to connect to a 10/100/1000 BaseT RJ45 connector integrated on the main
+ * board.
*
* The KSZ9021/31 interrupt is available on PB35 INT_GETH0. The sense of
* the interrupt is configurable but is, by default, active low.
@@ -614,7 +615,7 @@
#ifndef __ASSEMBLY__
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
/****************************************************************************